Linear voltage regulator circuit

Abstract

The invention discloses a linear voltage regulator circuit, which comprises a first operational amplifier, a first transistor, an adjusting unit, a current mirror image unit and a sampling feedback unit, and is characterized in that the adjusting unit samples a first current according to a first sampling proportion to obtain a first sampling current, samples a second current according to a second sampling proportion to obtain a second sampling current, and the current of the branch where the first transistor is located is adjusted based on the first sampling current and the second sampling current. According to the linear voltage regulator circuit disclosed by the invention, the first current and the second current are sampled through the adjusting unit, so that the quiescent current of the driving stage of the power tube of the linear voltage regulator circuit can be directly limited in light load and no load based on the first sampling current and the second sampling current; nonlinearity is introduced into the sampling unit of the adjusting unit, so that quiescent current of a driving stage is not limited during heavy load, and dropout voltage of the linear voltage regulator circuit is guaranteed under the condition that the size of a power tube is not increased.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a linear voltage regulator circuit. Background Technology

[0002] The quiescent current and dropout voltage (the minimum dropout threshold required for the linear regulator to operate normally) are important parameters for linear regulators, especially in low-power system applications, as they determine the static power consumption and conversion efficiency of the linear regulator chip. However, in linear regulator chips, these two parameters are often mutually exclusive because the dropout voltage of a linear regulator is related to the size and turn-on degree of the power transistor. For the same power transistor size, a lower dropout voltage requires a larger turn-on degree (VGS voltage), which in turn requires a larger current to drive the power transistor, thus increasing the quiescent current.

[0003] To balance these two performance metrics, most linear regulator chips require circuit designers to add a loop to the driver stage of the power transistor. This loop limits the quiescent current of the driver stage by limiting the drain-source voltage of the power transistor, while increasing the size of the power transistor to ensure the dropout voltage. The disadvantage of this approach is that it consumes more area, and for chips with high dropout voltage requirements, this method requires an extremely large power transistor area, making it practically impossible to implement.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a linear regulator circuit that can limit the quiescent current of the linear regulator when it is operating in the dropout region and ensure a low dropout voltage under heavy load without increasing the area of ​​the power transistor.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution: a linear regulator circuit, comprising: a first operational amplifier, a first transistor, an adjustment unit, a current mirror unit, and a sampling feedback unit;

[0007] The current mirror unit has an input terminal, a current control terminal, and an output terminal. The output terminal of the first operational amplifier is connected to the control terminal of the first transistor to drive the first transistor. The adjustment unit is connected to the current control terminal and the second terminal of the first transistor. The input terminal of the current mirror unit is connected to the input voltage. The current mirror unit generates a first current based on the current on the first transistor and mirrors the first current to generate a second current. The sampling feedback unit is connected to the output terminal of the current mirror unit to form the voltage output terminal of the linear regulator circuit and generates a feedback voltage based on the second current. The first input terminal of the first operational amplifier is used to receive a first reference voltage, and the second input terminal of the first operational amplifier is used to receive the feedback voltage.

[0008] The adjustment unit is simultaneously connected to the current control terminal of the input voltage and current mirror unit and the output terminal of the current mirror unit. It samples the first current at a first sampling ratio to obtain a first sampled current and samples the second current at a second sampling ratio to obtain a second sampled current. The first sampling ratio changes with the magnitude of the first current and / or the second sampling ratio changes with the second current. The adjustment unit adjusts the current of the branch where the first transistor is located based on the first sampled current and the second sampled current.

[0009] In one or more embodiments of the present invention, the current mirror unit includes a second transistor and a third transistor. The first terminal of the second transistor and the first terminal of the third transistor form the input terminal of the current mirror unit and are connected to the input voltage. The control terminal of the second transistor is connected to the second terminal of the second transistor and the control terminal of the third transistor to form a current control terminal and is connected to the adjustment unit. The second terminal of the third transistor forms the output terminal of the current mirror unit and is connected to the sampling feedback unit to form a voltage output terminal.

[0010] In one or more embodiments of the present invention, the adjustment unit includes an adjustment transistor, a first sampling unit, and a second sampling unit. The first sampling unit is connected to a current control terminal and an input voltage to sample a first current according to a first sampling ratio to obtain a first sampling current. The second sampling unit is connected to a current control terminal, an input voltage, and a voltage output terminal to sample a second current according to a second sampling ratio to obtain a second sampling current. The control terminal of the adjustment transistor is connected to the first sampling unit and the second sampling unit. The second end of the adjustment transistor is connected to the current control terminal. The first end of the adjustment transistor is connected to the second end of a first transistor. The adjustment transistor adjusts the current in the branch where the first transistor is located based on the magnitude between the first sampling current and the second sampling current.

[0011] In one or more embodiments of the present invention, the current mirror unit includes a second transistor and a third transistor. The first terminals of the second transistor and the third transistor form the input terminals of the current mirror unit and are connected to the input voltage. The control terminal of the second transistor is connected to the second terminals of the second transistor and the control terminals of the third transistor to form a current control terminal and is connected to the adjustment unit. The second terminal of the third transistor forms the output terminal of the current mirror unit and is connected to the sampling feedback unit to form a voltage output terminal.

[0012] The first sampling unit includes a fourth transistor, a first resistor unit, and a first clamping mirror unit. The first terminal of the fourth transistor receives the input voltage. The control terminal of the fourth transistor is connected to a current control terminal. The second terminal of the fourth transistor is connected to the first terminal of the first resistor unit. The second terminal of the first resistor unit is connected to the first clamping mirror unit. The first clamping mirror unit is simultaneously connected to both the current control terminal and the control terminal of the regulating transistor. The first clamping mirror unit is used to clamp the voltage at the second terminal of the resistor unit based on the voltage at the current control terminal to generate a first sampling current on the fourth transistor, and to adjust the voltage at the control terminal of the regulating transistor based on the first sampling current. I1 / I1a = N = N0 (1 + λ(VIN - VG)) / (1 + λ(VIN - VD1)), where VD1 is the voltage at the second terminal of the fourth transistor, VG is the voltage at the current control terminal, N is the first sampling ratio, N0 is the width-to-length ratio of the second transistor to the fourth transistor, λ is the channel length modulation coefficient, and VIN is the input voltage. The first sampling ratio changes non-linearly with the magnitude of the first current; and / or

[0013] The second sampling unit includes a fifth transistor, a second resistor unit, and a second clamping mirror unit. The first terminal of the fifth transistor is used to receive the input voltage. The control terminal of the fifth transistor is connected to the current control terminal. The second terminal of the fifth transistor is connected to the second clamping mirror unit. The second clamping mirror unit is simultaneously connected to the voltage output terminal, the second resistor unit, and the control terminal of the regulating transistor. The second clamping mirror unit is used to clamp the voltage at the second terminal of the fifth transistor based on the voltage at the voltage output terminal to generate a sampling current on the fifth transistor, and to mirror the sampling current to generate a second sampling current to adjust the voltage at the control terminal of the regulating transistor. The second clamping mirror unit adjusts its own mirror ratio based on the second resistor unit, and mirrors the sampling current based on the mirror ratio to generate a second sampling current. The second sampling current is I2b = I2 / M, where I2 is the second current and M is the second sampling ratio. The second sampling ratio of the second current of the second sampling unit changes non-linearly with the magnitude of the second current.

[0014] In one or more embodiments of the present invention, the first sampling unit includes a fourth transistor, a first resistor unit, and a first clamping mirror unit. A first terminal of the fourth transistor is used to receive an input voltage. The control terminal of the fourth transistor is connected to a current control terminal. A second terminal of the fourth transistor is connected to a first terminal of the first resistor unit. The second terminal of the first resistor unit is connected to the first clamping mirror unit. The first clamping mirror unit is simultaneously connected to both the current control terminal and the control terminal of the regulating transistor. The first clamping mirror unit is used to clamp the voltage at the second terminal of the resistor unit based on the voltage at the current control terminal to generate a first sampling current on the fourth transistor, and to adjust the voltage at the control terminal of the regulating transistor based on the first sampling current; or

[0015] The first sampling unit includes a fourth transistor and a first clamping mirror unit. The first terminal of the fourth transistor is used to receive the input voltage. The control terminal of the fourth transistor is connected to the current control terminal. The first clamping mirror unit is connected to the current control terminal, the second terminal of the fourth transistor, and the control terminal of the regulating transistor. The first clamping mirror unit is used to clamp the voltage of the second terminal of the fourth transistor based on the voltage of the current control terminal to generate a first sampling current on the fourth transistor, and to adjust the voltage of the control terminal of the regulating transistor based on the first sampling current.

[0016] In one or more embodiments of the present invention, the second sampling unit includes a fifth transistor and a second clamping mirror unit. A first terminal of the fifth transistor is used to receive an input voltage. The control terminal of the fifth transistor is connected to a current control terminal. A second terminal of the fifth transistor is connected to the second clamping mirror unit. The second clamping mirror unit is simultaneously connected to a voltage output terminal and the control terminal of a regulating transistor. The second clamping mirror unit is used to clamp the voltage at the second terminal of the fifth transistor based on the voltage at the voltage output terminal to generate a second sampling current on the fifth transistor, and to adjust the voltage at the control terminal of the regulating transistor based on the second sampling current; or

[0017] The second sampling unit includes a fifth transistor, a second resistor unit, and a second clamping mirror unit. The first terminal of the fifth transistor is used to receive the input voltage. The control terminal of the fifth transistor is connected to the current control terminal. The second terminal of the fifth transistor is connected to the second clamping mirror unit. The second clamping mirror unit is simultaneously connected to the voltage output terminal, the second resistor unit, and the control terminal of the regulating transistor. The second clamping mirror unit is used to clamp the voltage at the second terminal of the fifth transistor based on the voltage at the voltage output terminal to generate a sampling current on the fifth transistor, and to mirror the sampling current to generate a second sampling current to adjust the voltage at the control terminal of the regulating transistor.

[0018] In one or more embodiments of the present invention, the first sampling unit includes a fourth transistor, a first resistor unit, and a first clamping mirror unit. A first terminal of the fourth transistor is used to receive an input voltage. The control terminal of the fourth transistor is connected to a current control terminal. A second terminal of the fourth transistor is connected to a first terminal of the first resistor unit. The second terminal of the first resistor unit is connected to the first clamping mirror unit. The first clamping mirror unit is simultaneously connected to both the current control terminal and the control terminal of the regulating transistor. The first clamping mirror unit is used to clamp the voltage at the second terminal of the resistor unit based on the voltage at the current control terminal to generate a first sampling current on the fourth transistor and to adjust the voltage at the control terminal of the regulating transistor based on the first sampling current. The first clamping mirror unit includes a first current mirror, a second current mirror, and a second current source. The first current mirror is connected to the second terminal of the first resistor unit, the current control terminal, the second current source, and the second current mirror. The first current mirror is used to clamp the voltage at the second terminal of the resistor unit based on the voltage at the current control terminal to generate a first sampling current on the fourth transistor and to transmit the first sampling current to the second current mirror. The second current mirror is simultaneously connected to the control terminal of the regulating transistor to adjust the voltage at the control terminal of the regulating transistor based on the first sampling current. Or

[0019] The first sampling unit includes a fourth transistor and a first clamping mirror unit. The first terminal of the fourth transistor is used to receive an input voltage. The control terminal of the fourth transistor is connected to a current control terminal. The first clamping mirror unit is connected to the current control terminal, the second terminal of the fourth transistor, and the control terminal of the regulating transistor. The first clamping mirror unit is used to clamp the voltage of the second terminal of the fourth transistor based on the voltage of the current control terminal to generate a first sampling current on the fourth transistor, and to adjust the voltage of the control terminal of the regulating transistor based on the first sampling current. The first clamping mirror unit includes a first current mirror, a second current mirror, and a second current source. The first current mirror is connected to the second terminal of the fourth transistor, the current control terminal, the second current source, and the second current mirror. The first current mirror is used to clamp the voltage of the second terminal of the fourth transistor based on the voltage of the current control terminal to generate a first sampling current on the fourth transistor and to send the first sampling current to the second current mirror. The second current mirror is also connected to the control terminal of the regulating transistor to adjust the voltage of the control terminal of the regulating transistor based on the first sampling current.

[0020] In one or more embodiments of the present invention, the second sampling unit includes a fifth transistor and a second clamping mirror unit. The first terminal of the fifth transistor is used to receive an input voltage. The control terminal of the fifth transistor is connected to a current control terminal. The second terminal of the fifth transistor is connected to the second clamping mirror unit. The second clamping mirror unit is simultaneously connected to a voltage output terminal and the control terminal of a regulating transistor. The second clamping mirror unit is used to clamp the voltage at the second terminal of the fifth transistor based on the voltage at the voltage output terminal to generate a second sampling current on the fifth transistor, and to adjust the voltage at the control terminal of the regulating transistor based on the second sampling current. The second clamping mirror unit includes a third current mirror and a third current source. The third current mirror is connected to the second terminal of the fifth transistor, the voltage output terminal, the third current source, and the control terminal of the regulating transistor. The third current mirror is used to clamp the voltage at the second terminal of the fifth transistor based on the voltage at the voltage output terminal to generate a second sampling current on the fifth transistor, and to adjust the voltage at the control terminal of the regulating transistor based on the second sampling current. Or

[0021] The second sampling unit includes a fifth transistor, a second resistor unit, and a second clamping mirror unit. The first terminal of the fifth transistor receives the input voltage. The control terminal of the fifth transistor is connected to a current control terminal. The second terminal of the fifth transistor is connected to the second clamping mirror unit. The second clamping mirror unit is simultaneously connected to the voltage output terminal, the second resistor unit, and the control terminal of the regulating transistor. The second clamping mirror unit is used to clamp the voltage at the second terminal of the fifth transistor based on the voltage at the voltage output terminal to generate a sampling current on the fifth transistor, and to mirror this sampling current to generate a second sampling current to adjust the voltage at the control terminal of the regulating transistor. The mirror unit includes a third current mirror, a third current source, and a fourth current mirror. The third current mirror is connected to the second terminal, voltage output terminal, third current source, and fourth current mirror of the fifth transistor. The third current mirror is used to clamp the voltage at the second terminal of the fifth transistor based on the voltage output terminal to generate a sampling current on the fifth transistor and to supply the sampling current to the fourth current mirror. The fourth current mirror is connected to the second resistor unit and the control terminal of the regulating transistor. The fourth current mirror is used to mirror the sampling current based on the mirror ratio generated by the second resistor unit to generate a second sampling current and to adjust the voltage at the control terminal of the regulating transistor based on the second sampling current; or

[0022] The second sampling unit includes a fifth transistor and a second clamping mirror unit. The first terminal of the fifth transistor is used to receive the input voltage. The control terminal of the fifth transistor is connected to the current control terminal. The second terminal of the fifth transistor is connected to the second clamping mirror unit. The second clamping mirror unit is simultaneously connected to the voltage output terminal and the control terminal of the regulating transistor. The second clamping mirror unit is used to clamp the voltage of the second terminal of the fifth transistor based on the voltage of the voltage output terminal to generate a second sampling current on the fifth transistor, and to adjust the voltage of the control terminal of the regulating transistor based on the second sampling current. The second clamping mirror unit includes a third current mirror and a seventh sampling unit. The seventh sampling unit is connected to the current mirror unit to sample the second current to obtain an eighth sampling current. The third current mirror is connected to the second terminal of the fifth transistor, the voltage output terminal, the seventh sampling unit, and the control terminal of the regulating transistor. The third current mirror is used to clamp the voltage of the second terminal of the fifth transistor based on the voltage of the voltage output terminal and the eighth sampling current that varies with the second current to generate a second sampling current on the fifth transistor, and to adjust the voltage of the control terminal of the regulating transistor based on the second sampling current.

[0023] In one or more embodiments of the present invention, the linear regulator circuit further includes a first adjustment unit, which is simultaneously connected to the output terminal of the first operational amplifier, the input voltage, the current control terminal of the current mirror unit, and the output terminal of the current mirror unit, to sample the first current to obtain a fourth sampling current and sample the second current to obtain a fifth sampling current. The first adjustment unit adjusts the voltage at the output terminal of the first operational amplifier based on the fourth sampling current and the fifth sampling current; and / or

[0024] The linear regulator circuit further includes a second adjustment unit, which is connected to both the current control terminal of the input voltage and current mirror unit and the output terminal of the current mirror unit. The second adjustment unit samples the first current to obtain a sixth sampled current and samples the second current to obtain a seventh sampled current. The first adjustment unit adjusts the voltage at the current control terminal of the current mirror unit based on the sixth sampled current and the seventh sampled current.

[0025] In one or more embodiments of the present invention, the regulating unit further includes a first current source, a first end of which is connected to the control terminal of the regulating tube, and a second end of which is connected to a reference voltage.

[0026] Compared with the prior art, the linear regulator circuit of the present invention samples the first current and the second current through the adjustment unit. Based on the first sampled current and the second sampled current, the static current of the driving stage of the power transistor of the linear regulator circuit can be directly limited under light load and no load. By introducing nonlinearity into the sampling unit of the adjustment unit, the static current of the driving stage is not limited under heavy load, thereby ensuring the dropout voltage of the linear regulator circuit without increasing the size of the power transistor. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a circuit diagram of the linear regulator circuit in Embodiment 1 of the present invention.

[0029] Figure 2 This is a circuit diagram of the adjustment unit in Embodiment 1 of the present invention.

[0030] Figure 3 This is a circuit diagram of the first adjustment unit in Embodiment 1 of the present invention.

[0031] Figure 4 This is a circuit diagram of the second adjustment unit in Embodiment 1 of the present invention.

[0032] Figure 5 This is a circuit diagram of the second sampling unit in Embodiment 2 of the present invention.

[0033] Figure 6 This is a circuit diagram of the second clamping mirror unit in Embodiment 3 of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0035] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0036] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0037] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0038] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0039] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0040] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0041] Example 1

[0042] like Figure 1 and Figure 2As shown, a linear regulator circuit includes: an operational amplifier op, a first transistor M1, an adjustment unit 10, a current mirror unit, and a sampling feedback unit 20.

[0043] The current mirror unit has an input terminal, a current control terminal VG, and an output terminal. The output terminal EA_OUT of the operational amplifier op is connected to the control terminal of the first transistor M1 to drive the first transistor M1. The adjustment unit 10 is connected to the current control terminal VG and the second terminal of the first transistor M1. The first terminal of the first transistor M1 is connected to a reference voltage. The input terminal of the current mirror unit is connected to the input voltage VIN. The current mirror unit generates a first current I1 based on the current on the first transistor M1 and mirrors the first current I1 to generate a second current I2. The sampling feedback unit 20 is connected to the output terminal of the current mirror unit to form the voltage output terminal VOUT of the linear regulator circuit and generates a feedback voltage VFB based on the second current I2. The first input terminal of the operational amplifier op is used to receive the reference voltage VREF, and the second input terminal of the operational amplifier op is used to receive the feedback voltage VFB. In one embodiment, the first input terminal of the operational amplifier op is a positive input terminal, and the second input terminal of the operational amplifier op is a negative input terminal. In other embodiments, the first input terminal of the operational amplifier op is a negative input terminal, and the second input terminal of the operational amplifier op is a positive input terminal.

[0044] The adjustment unit 10 is simultaneously connected to the input voltage VIN, the current control terminal VG of the current mirror unit, and the output terminal (voltage output terminal VOUT) of the current mirror unit. It samples the first current I1 at a first sampling ratio to obtain a first sampling current I1a, and samples the second current I2 at a second sampling ratio to obtain a second sampling current I2a. The first sampling ratio varies with the magnitude of the first current I1. In one embodiment, the first sampling ratio changes non-linearly with the magnitude of the first current I1. The adjustment unit 10 adjusts the current in the branch where the first transistor M1 is located based on the first sampling current I1a and the second sampling current I2a. In other embodiments, the second sampling ratio varies with the magnitude of the second current I2; specifically, the second sampling ratio changes non-linearly with the magnitude of the second current I2.

[0045] The current mirror unit includes a second transistor M2 and a third transistor M3. The first terminals of the second transistor M2 and the third transistor M3 form the input terminals of the current mirror unit and are connected to the input voltage VIN. The control terminal of the second transistor M2 is connected to the second terminals of the second transistor M2 and the control terminals of the third transistor M3 to form the current control terminal VG, which is connected to the adjustment unit 10. The second terminal of the third transistor M3 forms the output terminal of the current mirror unit and is connected to the sampling feedback unit 20 to form the voltage output terminal VOUT. The third transistor M3 is a power transistor, and the second transistor M2 is the driver stage of the power transistor. The quiescent current of the driver stage is adjusted by the adjustment unit.

[0046] In one embodiment, the sampling feedback unit 10 includes a first feedback resistor Ra and a second feedback resistor Rb. The first terminal of the first feedback resistor Ra is connected to the second terminal of the third transistor M3 to form a voltage output terminal VOUT. The second terminal of the first feedback resistor Ra is connected to the first terminal of the second feedback resistor Rb to generate a feedback voltage VFB. The second terminal of the second feedback resistor Rb is connected to a reference voltage, which is ground voltage.

[0047] like Figure 1 and 2 As shown, the adjustment unit 10 includes an adjustment transistor MT, a first current source A1, a first sampling unit 11, and a second sampling unit 12. The first sampling unit 11 is connected to the current control terminal VG and the input voltage VIN to sample the first current I1 according to a first sampling ratio to obtain a first sampling current I1a. The second sampling unit 12 is connected to the current control terminal VG, the input voltage VIN, and the voltage output terminal VOUT to sample the second current I2 according to a second sampling ratio to obtain a second sampling current I2a. The first terminal of the first current source A1 is connected to the control terminal of the adjustment transistor MT, and the second terminal of the first current source A1 is connected to the input voltage VIN. The control terminal of the adjustment transistor MT is connected to the first sampling unit 11 and the second sampling unit 12. The second terminal of the adjustment transistor MT is connected to the current control terminal VG, and the first terminal of the adjustment transistor MT is connected to the second terminal of the first transistor M1. The adjustment transistor MT adjusts the current (first current I1) in the branch where the first transistor M1 is located based on the magnitude between the first sampling current I1a and the second sampling current I2a. The first current source A1 is used to provide a fixed bias current so that the regulating transistor MT can be turned on even when the current on the third transistor M3 is 0, thereby providing a base current to the branch where the second transistor M2 is located, ensuring that the linear regulator is still in operation.

[0048] In one embodiment, the sum of the second sampling current I2a and the current generated by the first current source A1 is compared with the first sampling current I1a. If the sum of the second sampling current I2a and the current generated by the first current source A1 is greater than the first sampling current I1a, the voltage at the control terminal of the regulating transistor MT is pulled down; if the sum of the second sampling current I2a and the current generated by the first current source A1 is less than the first sampling current I1a, the voltage at the control terminal of the regulating transistor MT is pulled up. In other embodiments, the first current source A1 may not be provided.

[0049] like Figure 2As shown, the first sampling unit 11 includes a fourth transistor M4, a first resistor unit, and a first clamping mirror unit 111. The first terminal of the fourth transistor M4 receives the input voltage VIN. The control terminal of the fourth transistor M4 is connected to the current control terminal VG. The second terminal of the fourth transistor M4 is connected to the first terminal of the first resistor unit. The second terminal of the first resistor unit is connected to the first clamping mirror unit 111. The first clamping mirror unit 111 is simultaneously connected to the current control terminal VG and the control terminal of the regulating transistor MT. The first clamping mirror unit 111 is used to clamp the voltage at the second terminal of the resistor unit based on the voltage at the current control terminal VG to generate a first sampling current I1a on the fourth transistor M4, and to adjust the voltage at the control terminal of the regulating transistor MT based on the first sampling current I1a. In one embodiment, the first resistor unit includes a first resistor R1. The first terminal of the first resistor R1 is connected to the second terminal of the fourth transistor M4, and the second terminal of the first resistor R1 is connected to the first clamping mirror unit 111. In other embodiments, the first resistor unit can be other resistive module units.

[0050] like Figure 2 As shown, the first clamping mirror unit 111 includes a first current mirror, a second current mirror, and a second current source A2. The first current mirror is connected to the second terminal of the first resistor unit, the current control terminal VG, the second current source A2, and the second current mirror. The first current mirror is used to clamp the voltage at the second terminal of the resistor unit based on the voltage of the current control terminal VG to generate a first sampling current I1a on the fourth transistor M4 and to send the first sampling current I1a to the second current mirror. The second current mirror is also connected to the control terminal of the regulating transistor MT to adjust the voltage at the control terminal of the regulating transistor MT based on the first sampling current I1a. For ease of description, the first current mirror and the second current mirror are separated, but the first current mirror and the second current mirror connected together can also be regarded as a single current mirror.

[0051] In one embodiment, the first current mirror includes a sixth transistor M6 and a seventh transistor M7. The first terminal of the sixth transistor M6 is connected to the second terminal of the first resistor R1 of the first resistor unit. The first terminal of the seventh transistor M7 is connected to the current control terminal VG. The control terminal of the sixth transistor M6 is connected to the control terminal of the seventh transistor M7, the second terminal of the seventh transistor M7, and the first terminal of the second current source A2. The second terminal of the second current source A2 is connected to the reference voltage. The second terminal of the sixth transistor M6 is connected to the second current mirror. The width-to-length ratio of the sixth transistor M6 and the seventh transistor M7 is equal.

[0052] The first terminal of the fourth transistor M4 receives the input voltage VIN. The control terminal of the fourth transistor M4 is connected to the current control terminal VG, so that a current proportional to the current on the second transistor M2 can be obtained on the fourth transistor M4. At the same time, since the first terminal of the seventh transistor M7 is connected to the current control terminal VG, based on the characteristics of the current mirror, the first terminal of the sixth transistor M6 can also obtain a voltage equal to the voltage on the current control terminal VG. At this time, the current on the second transistor M2 is sampled through the fourth transistor M4.

[0053] In one embodiment, the second current mirror includes an eighth transistor M8 and a ninth transistor M9. The control terminal of the eighth transistor M8 is connected to the second terminal of the eighth transistor M8, the second terminal of the sixth transistor M6, and the control terminal of the ninth transistor M9. The second terminal of the ninth transistor M9 is connected to the control terminal of the regulating transistor MT. The first terminals of the eighth transistor M8 and the first terminals of the ninth transistor M9 are connected to a reference voltage.

[0054] like Figure 2 As shown, the second sampling unit 12 includes a fifth transistor M5 and a second clamping mirror unit 121. The first terminal of the fifth transistor M5 is used to receive the input voltage VIN. The control terminal of the fifth transistor M5 is connected to the current control terminal VG. The second terminal of the fifth transistor M5 is connected to the second clamping mirror unit 121. The second clamping mirror unit 121 is simultaneously connected to the voltage output terminal VOUT and the control terminal of the regulating transistor MT. The second clamping mirror unit 121 is used to clamp the voltage of the second terminal of the fifth transistor M5 based on the voltage of the voltage output terminal VOUT to generate a second sampling current I2a on the fifth transistor M5, and to adjust the voltage of the control terminal of the regulating transistor MT based on the second sampling current I2a.

[0055] The second clamping mirror unit 121 includes a third current mirror and a third current source A3. The third current mirror is connected to the second terminal of the fifth transistor M5, the voltage output terminal VOUT, the third current source A3, and the control terminal of the regulating transistor MT. The third current mirror is used to clamp the voltage of the second terminal of the fifth transistor M5 based on the voltage of the voltage output terminal VOUT to generate a second sampling current I2a on the fifth transistor M5, and to adjust the voltage of the control terminal of the regulating transistor MT based on the second sampling current I2a.

[0056] In one embodiment, the third current mirror includes a tenth transistor M10 and an eleventh transistor M11. The first terminal of the tenth transistor M10 is connected to the second terminal of the fifth transistor M5. The control terminal of the tenth transistor M10 is connected to the control terminal of the eleventh transistor M11, the second terminal of the eleventh transistor M11, and the first terminal of the third current source A3. The second terminal of the third current source A3 is connected to a reference voltage. The first terminal of the eleventh transistor M11 is connected to the voltage output terminal VOUT. The second terminal of the tenth transistor M10 is connected to the control terminal of the regulating transistor MT.

[0057] The first terminal of the fifth transistor M5 is used to receive the input voltage VIN. The control terminal of the fifth transistor M5 is connected to the current control terminal VG, so that a current proportional to the current on the third transistor M3 can be obtained on the fifth transistor M5. At the same time, since the first terminal of the eleventh transistor M11 is connected to the voltage output terminal VOUT, based on the characteristics of the current mirror, the first terminal of the tenth transistor M10 can also obtain a voltage equal to the voltage output terminal VOUT. At this time, the fifth transistor M5 can ensure more accurate acquisition of the current on the third transistor M3.

[0058] like Figure 1 As shown, the linear regulator circuit also includes a first adjustment unit 30 and a second adjustment unit 40. The first adjustment unit 30 is simultaneously connected to the output terminal EA_OUT of the operational amplifier op, the input voltage VIN, the current control terminal VG of the current mirror unit, and the output terminal of the current mirror unit. It samples the first current I1 to obtain a fourth sampling current and samples the second current I2 to obtain a fifth sampling current. Based on the fourth and fifth sampling currents, the first adjustment unit 30 adjusts (limits) the voltage at the output terminal EA_OUT of the operational amplifier op, thereby adjusting (limiting) the drain-source voltage of the third transistor M3. The second adjustment unit 40 is simultaneously connected to the input voltage VIN, the current control terminal VG of the current mirror unit, and the output terminal of the current mirror unit. It samples the first current I1 to obtain a sixth sampling current and samples the second current I2 to obtain a seventh sampling current. Based on the sixth and seventh sampling currents, the first adjustment unit 30 adjusts (limits) the voltage at the current control terminal VG of the current mirror unit, thereby adjusting (limiting) the drain-source voltage of the third transistor M3.

[0059] like Figure 3As shown, the first adjustment unit 30 includes a first adjustment transistor MT1, a first bias current source A31, a third sampling unit, and a fourth sampling unit. The third sampling unit is connected to the current control terminal VG and the input voltage VIN to sample the first current I1 to obtain a third sampling current I32a. The fourth sampling unit is connected to the current control terminal VG, the input voltage VIN, and the voltage output terminal VOUT to sample the second current I2 to obtain a fourth sampling current I33a. The first terminal of the first bias current source A31 is connected to the control terminal of the first adjustment transistor MT1, and the second terminal of the first bias current source A31 is connected to a reference voltage. The control terminal of the first adjustment transistor MT1 is connected to the third and fourth sampling units. The second terminal of the first adjustment transistor MT1 is connected to the output terminal EA_OUT of the operational amplifier op. The first terminal of the first adjustment transistor MT1 is connected to the reference voltage. The first adjustment transistor MT1 adjusts the voltage at the output terminal EA_OUT of the operational amplifier op based on the magnitude between the third sampling current I32a and the fourth sampling current I33a. The first bias current source A31 is used to provide a fixed bias current.

[0060] The third sampling unit includes a twelfth transistor M12 and a third clamping mirror unit 321. The first terminal of the twelfth transistor M12 is used to receive the input voltage VIN. The control terminal of the twelfth transistor M12 is connected to the current control terminal VG. The second terminal of the twelfth transistor M12 is connected to the third clamping mirror unit 321. The third clamping mirror unit 321 is simultaneously connected to the current control terminal VG and the control terminal of the first regulating transistor MT1. The third clamping mirror unit 321 is used to clamp the voltage of the second terminal of the twelfth transistor M12 based on the voltage of the current control terminal VG to generate a third sampling current I32a on the twelfth transistor M12, and to adjust the voltage of the control terminal of the first regulating transistor MT1 based on the third sampling current I32a.

[0061] The third clamping mirror unit 321 includes a fifth current mirror and a fourth current source A4. The fifth current mirror is connected to the second terminal of the twelfth transistor M12, the current control terminal VG, the fourth current source A4, and the control terminal of the first regulating transistor MT1. The fifth current mirror is used to clamp the voltage of the second terminal of the twelfth transistor M12 based on the voltage of the current control terminal VG to generate a third sampling current I32a on the twelfth transistor M12, and to adjust the voltage of the control terminal of the first regulating transistor MT1 based on the third sampling current I32a.

[0062] The fifth current mirror includes a thirteenth transistor M13 and a fourteenth transistor M14. The first terminal of the thirteenth transistor M13 is connected to the second terminal of the twelfth transistor M12. The control terminal of the thirteenth transistor M13 is connected to the control terminal of the fourteenth transistor M14, the second terminal of the fourteenth transistor M14, and the first terminal of the fourth current source A4. The second terminal of the fourth current source A4 is connected to the reference voltage. The first terminal of the fourteenth transistor M14 is connected to the current control terminal VG. The second terminal of the thirteenth transistor M13 is connected to the control terminal of the first regulating transistor MT1.

[0063] The fourth sampling unit includes a fifteenth transistor M15 and a fourth clamping mirror unit 331. The first terminal of the fifteenth transistor M15 receives the input voltage VIN. The control terminal of the fifteenth transistor M15 is connected to the current control terminal VG. The second terminal of the fifteenth transistor M15 is connected to the fourth clamping mirror unit 331. The fourth clamping mirror unit 331 is simultaneously connected to the voltage output terminal VOUT and the control terminal of the first regulating transistor MT1. The fourth clamping mirror unit 331 clamps the voltage at the second terminal of the fifteenth transistor M15 based on the voltage at the voltage output terminal VOUT to generate a fourth sampling current I33a on the fifteenth transistor M15, and adjusts the voltage at the control terminal of the first regulating transistor MT1 based on the fourth sampling current I33a. In other embodiments, a resistor unit may be connected between the second terminal of the fifteenth transistor M15 and the fourth clamping mirror unit 331.

[0064] like Figure 3 As shown, the fourth clamping mirror unit 331 includes a sixth current mirror, a seventh current mirror, and a fifth current source A5. The sixth current mirror is connected to the second terminal of the fifteenth transistor M15, the voltage output terminal VOUT, the fifth current source A5, and the seventh current mirror. The sixth current mirror is used to clamp the voltage at the second terminal of the fifteenth transistor M15 based on the voltage at the voltage output terminal VOUT to generate a fourth sampling current I33a on the fifteenth transistor M15 and to send the fourth sampling current I33a to the seventh current mirror. The seventh current mirror is also connected to the control terminal of the first regulating transistor MT1 to adjust the voltage at the control terminal of the first regulating transistor MT1 based on the fourth sampling current I33a. For ease of description, the sixth and seventh current mirrors are separated, but the connected sixth and seventh current mirrors can also be regarded as a single current mirror.

[0065] In one embodiment, the sixth current mirror includes a sixteenth transistor M16 and a seventeenth transistor M17. The first terminal of the sixteenth transistor M16 is connected to the second terminal of the fifteenth transistor M15. The first terminal of the seventeenth transistor M17 is connected to the voltage output terminal VOUT. The control terminal of the sixteenth transistor M16 is connected to the control terminal of the seventeenth transistor M17, the second terminal of the seventeenth transistor M17, and the first terminal of the fifth current source A5. The second terminal of the fifth current source A5 is connected to the reference voltage. The second terminal of the sixteenth transistor M16 is connected to the seventh current mirror.

[0066] In one embodiment, the seventh current mirror includes an eighteenth transistor M18 and a nineteenth transistor M19. The control terminal of the eighteenth transistor M18 is connected to the second terminal of the eighteenth transistor M18, the second terminal of the sixteenth transistor M16, and the control terminal of the nineteenth transistor M19. The second terminal of the nineteenth transistor M19 is connected to the control terminal of the first regulating transistor MT1. The first terminals of the eighteenth transistor M18 and the nineteenth transistor M19 are connected to a reference voltage.

[0067] like Figure 4 As shown, the second regulation unit 40 includes a second regulation transistor MT2, a second bias current source A41, a fifth sampling unit, and a sixth sampling unit. The fifth sampling unit is connected to the current control terminal VG and the input voltage VIN to sample the first current I1 to obtain a fifth sampling current I42a. The sixth sampling unit is connected to the current control terminal VG, the input voltage VIN, and the voltage output terminal VOUT to sample the second current I2 to obtain a sixth sampling current I43a. The first terminal of the second bias current source A41 is connected to the control terminal of the second regulation transistor MT2, and the second terminal of the second bias current source A41 is connected to the input voltage VIN. The control terminal of the second regulation transistor MT2 is connected to the fifth and sixth sampling units. The second terminal of the second regulation transistor MT2 is connected to the current control terminal VG, and the first terminal of the second regulation transistor MT2 is connected to the input voltage VIN. The second regulation transistor MT2 adjusts the voltage of the current control terminal VG based on the magnitude between the fifth sampling current I42a and the sixth sampling current I43a. The second bias current source A41 is used to provide a fixed bias current.

[0068] like Figure 4As shown, the fifth sampling unit includes a twentieth transistor M20 and a fifth clamping mirror unit 421. The first terminal of the twentieth transistor M20 receives the input voltage VIN. The control terminal of the twentieth transistor M20 is connected to the current control terminal VG. The second terminal of the twentieth transistor M20 is connected to the first terminal of the first resistor unit. The second terminal of the first resistor unit is connected to the fifth clamping mirror unit 421. The fifth clamping mirror unit 421 is simultaneously connected to the current control terminal VG and the control terminal of the second regulating transistor MT2. The fifth clamping mirror unit 421 is used to clamp the voltage at the second terminal of the twentieth transistor M20 based on the voltage at the current control terminal VG to generate a fifth sampling current I42a on the twentieth transistor M20, and to adjust the voltage at the control terminal of the second regulating transistor MT2 based on the fifth sampling current I42a. In other embodiments, a resistor unit may be provided between the second terminal of the twentieth transistor M20 and the fifth clamping mirror unit 421.

[0069] like Figure 4 As shown, the fifth clamping mirror unit 421 includes an eighth current mirror, a ninth current mirror, and a sixth current source A6. The eighth current mirror is connected to the second terminal of the twentieth transistor M20, the current control terminal VG, the sixth current source A6, and the ninth current mirror. The eighth current mirror is used to clamp the voltage of the second terminal of the twentieth transistor M20 based on the voltage of the current control terminal VG to generate a fifth sampling current I42a on the twentieth transistor M20 and to send the fifth sampling current I42a to the ninth current mirror. The ninth current mirror is also connected to the control terminal of the second regulating transistor MT2 to adjust the voltage of the control terminal of the second regulating transistor MT2 based on the fifth sampling current I42a. For ease of description, the eighth and ninth current mirrors are separated, but the connected eighth and ninth current mirrors can also be regarded as a single current mirror.

[0070] In one embodiment, the eighth current mirror includes a twenty-first transistor M21 and a twenty-second transistor M22. The first terminal of the twenty-first transistor M21 is connected to the second terminal of the twenty-second transistor M20. The first terminal of the twenty-second transistor M22 is connected to the current control terminal VG. The control terminal of the twenty-first transistor M21 is connected to the control terminal of the twenty-second transistor M22, the second terminal of the twenty-second transistor M22, and the first terminal of the sixth current source A6. The second terminal of the sixth current source A6 is connected to the reference voltage. The second terminal of the twenty-first transistor M21 is connected to the ninth current mirror.

[0071] In one embodiment, the ninth current mirror includes a twenty-third transistor M23 and a twenty-fourth transistor M24. The control terminal of the twenty-third transistor M23 is connected to the second terminal of the twenty-third transistor M23, the second terminal of the twenty-first transistor M21, and the control terminal of the twenty-fourth transistor M24. The second terminal of the twenty-fourth transistor M24 is connected to the control terminal of the second regulating transistor MT2. The first terminal of the twenty-third transistor M23 and the first terminal of the twenty-fourth transistor M24 are connected to a reference voltage.

[0072] like Figure 4 As shown, the sixth sampling unit includes a twenty-fifth transistor M25 and a sixth clamping mirror unit 431. The first terminal of the twenty-fifth transistor M25 is used to receive the input voltage VIN. The control terminal of the twenty-fifth transistor M25 is connected to the current control terminal VG. The second terminal of the twenty-fifth transistor M25 is connected to the sixth clamping mirror unit 431. The sixth clamping mirror unit 431 is simultaneously connected to the voltage output terminal VOUT and the control terminal of the second regulating transistor MT2. The sixth clamping mirror unit 431 is used to clamp the voltage of the second terminal of the twenty-fifth transistor M25 based on the voltage of the voltage output terminal VOUT to generate a sixth sampling current I43a on the twenty-fifth transistor M25, and to adjust the voltage of the control terminal of the second regulating transistor MT2 based on the sixth sampling current I43a.

[0073] The sixth clamping mirror unit 431 includes a tenth current mirror and a seventh current source A7. The tenth current mirror is connected to the second terminal of the twenty-fifth transistor M25, the voltage output terminal VOUT, the seventh current source A7, and the control terminal of the second regulating transistor MT2. The tenth current mirror is used to clamp the voltage of the second terminal of the twenty-fifth transistor M25 based on the voltage of the voltage output terminal VOUT to generate a sixth sampling current I43a on the twenty-fifth transistor M25, and to adjust the voltage of the control terminal of the second regulating transistor MT2 based on the sixth sampling current I43a.

[0074] In one embodiment, the tenth current mirror includes a twenty-sixth transistor M26 and a twenty-seventh transistor M27. The first terminal of the twenty-sixth transistor M26 is connected to the second terminal of the twenty-fifth transistor M25. The control terminal of the twenty-sixth transistor M26 is connected to the control terminal of the twenty-seventh transistor M27, the second terminal of the twenty-seventh transistor M27, and the first terminal of the seventh current source A7. The second terminal of the seventh current source A7 is connected to a reference voltage. The first terminal of the twenty-seventh transistor M27 is connected to the voltage output terminal VOUT. The second terminal of the twenty-sixth transistor M26 is connected to the control terminal of the second regulating transistor MT2.

[0075] In other embodiments, the first adjustment unit 30 and / or the second adjustment unit 40 may not be provided.

[0076] The linear regulator circuit also includes an RC filter circuit connected to the control terminal of the first transistor M1, and a protection resistor Rp connected to the input voltage VIN and the current control terminal VG. The RC filter circuit is used for frequency compensation to ensure the stability of the entire circuit loop and prevent oscillations. The protection resistor Rp is used to limit the voltage difference between the input voltage VIN and the voltage at the current control terminal VG.

[0077] Transistor M1, regulating transistor MT, regulating transistor MT1, eighth transistor M8, ninth transistor M9, eighteenth transistor M18, nineteenth transistor M19, twenty-third transistor M23, and twenty-fourth transistor M24 are N-channel MOSFETs. Transistor M2, regulating transistor MT2, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, seventh transistor M7, tenth transistor M10, eleventh transistor M11, twelfth transistor M12, thirteenth transistor M13, fourteenth transistor M14, fifteenth transistor M15, sixteenth transistor M16, seventeenth transistor M17, twentieth transistor M20, twenty-first transistor M21, twenty-second transistor M22, twenty-fifth transistor M25, twenty-sixth transistor M26, and twenty-seventh transistor M27 are P-channel MOSFETs. In other embodiments, the first transistor M1, the regulating transistor MT, the eighth transistor M8, the ninth transistor M9, the eighteenth transistor M18, the nineteenth transistor M19, the twenty-third transistor M23, and the twenty-fourth transistor M24 are P-channel MOSFETs. The second regulating transistor MT2, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the twentieth transistor M20, the twenty-first transistor M21, the twenty-second transistor M22, the twenty-fifth transistor M25, the twenty-sixth transistor M26, and the twenty-seventh transistor M27 are N-channel MOSFETs.

[0078] The first terminal of the first transistor M1, the first terminal of the regulating transistor MT, the first terminal of the first regulating transistor MT1, the first terminal of the eighth transistor M8, the first terminal of the ninth transistor M9, the first terminal of the eighteenth transistor M18, the first terminal of the nineteenth transistor M19, the first terminal of the twenty-third transistor M23, the first terminal of the twenty-fourth transistor M24, the first terminal of the second regulating transistor MT2, the first terminal of the second transistor M2, the first terminal of the third transistor M3, the first terminal of the fourth transistor M4, the first terminal of the fifth transistor M5, the first terminal of the sixth transistor M6, and the first terminal of the seventh transistor M7. The first terminal of the tenth transistor M10, the first terminal of the eleventh transistor M11, the first terminal of the twelfth transistor M12, the first terminal of the thirteenth transistor M13, the first terminal of the fourteenth transistor M14, the first terminal of the fifteenth transistor M15, the first terminal of the sixteenth transistor M16, the first terminal of the seventeenth transistor M17, the first terminal of the twentieth transistor M20, the first terminal of the twenty-first transistor M21, the first terminal of the twenty-second transistor M22, the first terminal of the twenty-fifth transistor M25, the first terminal of the twenty-sixth transistor M26, and the first terminal of the twenty-seventh transistor M27 are the sources.

[0079] The second terminal of the first transistor M1, the second terminal of the regulating transistor MT, the second terminal of the first regulating transistor MT1, the second terminal of the eighth transistor M8, the second terminal of the ninth transistor M9, the second terminal of the eighteenth transistor M18, the second terminal of the nineteenth transistor M19, the second terminal of the twenty-third transistor M23, the second terminal of the twenty-fourth transistor M24, the second terminal of the second regulating transistor MT2, the second terminal of the second transistor M2, the second terminal of the third transistor M3, the second terminal of the fourth transistor M4, the second terminal of the fifth transistor M5, the second terminal of the sixth transistor M6, and the second terminal of the seventh transistor M7. The second terminals of the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the twentieth transistor M20, the twenty-first transistor M21, the twenty-second transistor M22, the twenty-fifth transistor M25, the twenty-sixth transistor M26, and the twenty-seventh transistor M27 are drains.

[0080] The control terminals of the first transistor M1, the regulating transistor MT, the first regulating transistor MT1, the eighth transistor M8, the ninth transistor M9, the eighteenth transistor M18, the nineteenth transistor M19, the twenty-third transistor M23, the twenty-fourth transistor M24, the second regulating transistor MT2, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7. The control terminals of the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the twentieth transistor M20, the twenty-first transistor M21, the twenty-second transistor M22, the twenty-fifth transistor M25, the twenty-sixth transistor M26, and the twenty-seventh transistor M27 are the gates.

[0081] In one embodiment, after the adjustment unit 10 is provided, the first current I1 is limited to:

[0082]

[0083] N is the sampling ratio of the first sampling unit 11 (fourth transistor M4) for the first current I1, M is the sampling ratio of the second sampling unit for the second current I2, IA1 is the current generated by the first current source A1, and the current formula at the control terminal of the regulating transistor MT is: I2a+IA1=I1a, where I2a=I2 / M, I1a=I1 / N.

[0084] Based on the saturation current of any MOSFET formula:

[0085]

[0086] in, For electron mobility, The capacitance per unit area of ​​the gate oxide layer, This is the ratio of the channel width W to the channel length L of the MOSFET. This represents the source-gate voltage of the MOSFET. This is the threshold voltage of the MOSFET. The channel length modulation coefficient, This represents the source-drain voltage of the MOSFET.

[0087] The corresponding first current I1 and first sampling current I1a can be obtained. If the random error of the tube is ignored, we can obtain:

[0088]

[0089] Where VD1 is Figure 2 The voltage at the second terminal of the fourth transistor M4, This refers to the voltage at the current control terminal. N is the sampling ratio of the first sampling unit 11 (fourth transistor M4) for the first current I1, and N0 is the ratio of the width to the length of the second transistor M2 and the fourth transistor M4. VD1 is the channel length modulation coefficient, VIN is the input voltage, and due to the clamping effect of the sixth transistor M6 and the seventh transistor M7, VD1 can be expressed as:

[0090]

[0091] in, This is the source-gate voltage of the seventh transistor M7. The source-gate voltage of the sixth transistor M6 is... Substituting the formula for N into the formula for I1a, we can see that as I1a decreases, N decreases non-linearly. When I2 is small, N is even smaller, and I1 is also restricted to a very small value. As I1a increases, N increases non-linearly. When the value is large, N is larger, and thus the first current I1 is also larger.

[0092] in addition When the voltage is very high, the fourth transistor M4 will be pushed into the linear region, and the nonlinearity of N will be more obvious. The formula can be derived from the formula of the linear region of the MOSFET. When the fourth transistor M4 enters the linear region, the actual sampled first sampling current I1a will be too small. The regulating transistor MT will be fully turned on and will not be able to limit the voltage of the current control terminal VG, thus failing to limit the drain-source voltage of the third transistor M3.

[0093] Example 2

[0094] In this embodiment, based on Embodiment 1, the first resistor unit may not be provided in the first sampling unit 11. In this case, the second terminal of the fourth transistor M4 is directly connected to the first terminal of the sixth transistor M6 of the first clamping mirror unit 111. The structure of the second sampling unit 12 is modified, such as... Figure 5As shown, the second sampling unit 12 includes a fifth transistor M5, a second resistor unit, and a second clamping mirror unit 121. The first terminal of the fifth transistor M5 is used to receive the input voltage VIN. The control terminal of the fifth transistor M5 is connected to the current control terminal VG. The second terminal of the fifth transistor M5 is connected to the second clamping mirror unit 121. The second clamping mirror unit 121 is simultaneously connected to the voltage output terminal VOUT, the second resistor unit, and the control terminal of the regulating transistor MT. The second clamping mirror unit 121 is used to clamp the voltage of the second terminal of the fifth transistor M5 based on the voltage of the voltage output terminal VOUT to generate a sampling current I2a on the fifth transistor M5, and to mirror the sampling current I2a to generate a second sampling current I2b to adjust the voltage of the control terminal of the regulating transistor MT. The second resistor unit includes a second resistor R2.

[0095] like Figure 5 As shown, the second clamping mirror unit 121 includes a third current mirror, a third current source A3, and a fourth current mirror. The third current mirror is connected to the second terminal of the fifth transistor M5, the voltage output terminal VOUT, the third current source A3, and the fourth current mirror. The third current mirror is used to clamp the voltage of the second terminal of the fifth transistor M5 based on the voltage of the voltage output terminal VOUT to generate a sampling current I2a on the fifth transistor M5 and to send the sampling current I2a to the fourth current mirror. The fourth current mirror is connected to the second resistor unit and the control terminal of the regulating transistor MT. The fourth current mirror is used to mirror the sampling current I2a based on the mirror ratio generated by the second resistor unit to generate a second sampling current I2b and to adjust the voltage of the control terminal of the regulating transistor MT based on the second sampling current I2b.

[0096] The third current mirror includes the twenty-eighth transistor M28 and the twenty-ninth transistor M29. The first terminal of the twenty-eighth transistor M28 is connected to the second terminal of the fifth transistor M5. The control terminal of the twenty-eighth transistor M28 is connected to the control terminal of the twenty-ninth transistor M29, the second terminal of the twenty-ninth transistor M29, and the first terminal of the third current source A3. The second terminal of the third current source A3 is connected to the reference voltage. The first terminal of the twenty-ninth transistor M29 is connected to the voltage output terminal VOUT. The second terminal of the twenty-eighth transistor M28 is connected to the fourth current mirror.

[0097] The fourth current mirror includes the 30th transistor M30, the 31st transistor M31, the 32nd transistor M32, and the 33rd transistor M33. The control terminal of the 30th transistor M30 is connected to the control terminal of the 31st transistor M31, the second terminal of the 30th transistor M30, and the second terminal of the 28th transistor M28. The first terminal of the 30th transistor M30 is connected to the first terminal of the second resistor R2 of the second resistor unit. The first terminal of the 31st transistor M31 and the second terminal of the second resistor R2 of the second resistor unit are connected to the reference voltage. The second terminal of the 31st transistor M31 is connected to the second terminal of the 32nd transistor M32, the control terminal of the 32nd transistor M32, and the control terminal of the 33rd transistor M33. The first terminals of the 33rd transistor M33 and the 32nd transistor M32 are connected to the input voltage VIN. The second terminal of the 33rd transistor M33 is connected to the control terminal of the regulating transistor MT.

[0098] Transistor M5 (5th), M28 (28th), M29 (29th), M32 (32nd), and M33 (33rd) are P-channel MOSFETs; transistors M30 (30th) and M31 (31st) are N-channel MOSFETs. In other embodiments, transistors M5 (5th), M28 (28th), M29 (29th), M32 (32nd), and M33 (33rd) are N-channel MOSFETs; transistors M30 (30th) and M31 (31st) are P-channel MOSFETs.

[0099] The first terminals of transistors M5 (5th), M28 (28th), M29 (29th), M32 (32nd), M33 (33rd), M30 (30th), and M31 (31st) are the sources. The second terminals of transistors M5, M28, M29, M32, M33, M30, and M31 are the drains. The control terminals of transistors M5, M28, M29, M32, M33, M30, and M31 are the gates.

[0100] M= , Let M be the second current and M be the second sampling ratio of the second sampling unit 12. By adding a second resistor unit to the second sampling unit 12 that samples the second current I2, a nonlinearity is introduced, similar to Embodiment 1. Adding the second resistor unit increases the mirror ratio between the thirtieth transistor M30 and the thirty-first transistor M31 of the fourth current mirror. When the second current I2 increases, the current on the thirty-first transistor M31 and the second sampling current I2b injected into the control terminal of the regulating transistor MT become larger, exhibiting a nonlinear relationship. This is equivalent to the second sampling ratio M decreasing instead; that is, the second sampling ratio M for the second current I2 ultimately decreases as the second current I2 increases.

[0101] Example 3

[0102] In this embodiment, based on Embodiment 1, the first resistor unit may not be provided in the first sampling unit 11. In this case, the second terminal of the fourth transistor M4 is directly connected to the first terminal of the sixth transistor M6 of the first clamping mirror unit 111. The structure of the second clamping mirror unit 121 is modified, such as... Figure 6 As shown, the second clamping mirror unit 121 includes a third current mirror and a seventh sampling unit 1211. The seventh sampling unit 1211 is connected to the current mirror unit to sample the second current I2 to obtain an eighth sampling current. The third current mirror is connected to the second terminal of the fifth transistor M5, the voltage output terminal VOUT, the seventh sampling unit 1211, and the control terminal of the regulating transistor MT. The third current mirror is used to clamp the voltage of the second terminal of the fifth transistor M5 based on the voltage of the voltage output terminal VOUT and the eighth sampling current that varies with the second current I2 to generate a second sampling current I2a on the fifth transistor M5, and to adjust the voltage of the control terminal of the regulating transistor MT based on the second sampling current I2a.

[0103] The third current mirror includes the thirty-fourth transistor M34 and the thirty-fifth transistor M35. The first terminal of the thirty-fourth transistor M34 is connected to the second terminal of the fifth transistor M5. The control terminal of the thirty-fourth transistor M34 is connected to the control terminal and the second terminal of the thirty-fifth transistor M35. The first terminal of the thirty-fifth transistor M35 is connected to the voltage output terminal VOUT. The second terminal of the thirty-fourth transistor M34 is connected to the control terminal of the regulating transistor MT.

[0104] The fifth transistor M5, the thirty-fourth transistor M34, and the thirty-fifth transistor M35 are P-channel MOSFETs. In other embodiments, the fifth transistor M5, the thirty-fourth transistor M34, and the thirty-fifth transistor M35 are N-channel MOSFETs.

[0105] The first terminal of the fifth transistor M5, the first terminal of the thirty-fourth transistor M34, and the first terminal of the thirty-fifth transistor M35 are the sources; the second terminal of the fifth transistor M5, the second terminal of the thirty-fourth transistor M34, and the second terminal of the thirty-fifth transistor M35 are the drains; the control terminal of the fifth transistor M5, the control terminal of the thirty-fourth transistor M34, and the control terminal of the thirty-fifth transistor M35 are the gates.

[0106] By introducing the seventh sampling unit 1211 with a sampling ratio of K, the eighth sampling current is I2 / K, and the source-gate voltage of the thirty-fifth transistor M35 is... The voltage at the second terminal of the fifth transistor M5 increases as the second current I2 increases. ( In the formula for the source-gate voltage of the thirty-fourth transistor M34, ≈ Not valid. It decreases as the second current I2 increases.

[0107] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0108] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A linear voltage regulator circuit, characterized by, The application relates to a linear voltage regulator circuit. The current mirror unit has an input end, a current control end and an output end, the output end of the first operational amplifier is connected with the control end of the first transistor to drive the first transistor, the regulating unit is connected with the current control end and the second end of the first transistor, the input end of the current mirror unit is connected with an input voltage, the current mirror unit generates a first current based on the current on the first transistor and mirrors the first current to generate a second current, the sampling feedback unit is connected with the output end of the current mirror unit to form a voltage output end of the linear voltage regulator circuit and generates a feedback voltage based on the second current, the first input end of the first operational amplifier is used for receiving a first reference voltage, and the second input end of the first operational amplifier is used for receiving the feedback voltage. The regulating unit is connected with the input voltage, the current control end of the current mirror unit and the output end of the current mirror unit to sample the first current to obtain a first sampling current at a first sampling ratio and sample the second current to obtain a second sampling current at a second sampling ratio, the first sampling ratio changes with the size of the first current and / or the second sampling ratio changes with the size of the second current, and the regulating unit adjusts the current of the branch where the first transistor is located based on the first sampling current and the second sampling current. The current mirror unit comprises a second transistor and a third transistor, the first end of the second transistor and the first end of the third transistor form the input end of the current mirror unit and are connected with the input voltage, the control end of the second transistor is connected with the second end of the second transistor and the control end of the third transistor to form the current control end and is connected with the regulating unit, and the second end of the third transistor forms the output end of the current mirror unit and is connected with the sampling feedback unit to form the voltage output end.

2. The linear voltage regulator circuit of claim 1, wherein, The regulating unit comprises a regulating tube, a first sampling unit and a second sampling unit, the first sampling unit is connected with the current control end and the input voltage to sample the first current to obtain the first sampling current at the first sampling ratio, the second sampling unit is connected with the current control end, the input voltage and the voltage output end to sample the second current to obtain the second sampling current at the second sampling ratio, the control end of the regulating tube is connected with the first sampling unit and the second sampling unit, the second end of the regulating tube is connected with the current control end, the first end of the regulating tube is connected with the second end of the first transistor, and the regulating tube adjusts the current of the branch where the first transistor is located based on the size between the first sampling current and the second sampling current.

3. The linear voltage regulator circuit of claim 1, wherein, The current mirror unit comprises a second transistor and a third transistor, the first end of the second transistor and the first end of the third transistor form the input end of the current mirror unit and are connected with the input voltage, the control end of the second transistor is connected with the second end of the second transistor and the control end of the third transistor to form the current control end and is connected with the regulating unit, and the second end of the third transistor forms the output end of the current mirror unit and is connected with the sampling feedback unit to form the voltage output end.

4. The linear voltage regulator circuit of claim 3, wherein, ​ The first sampling unit comprises a fourth transistor, a first resistance unit and a first clamping mirror unit, a first end of the fourth transistor is configured to receive an input voltage, a control end of the fourth transistor is connected with a current control end, a second end of the fourth transistor is connected with a first end of the first resistance unit, a second end of the first resistance unit is connected with the first clamping mirror unit, the first clamping mirror unit is connected with the current control end and a control end of an adjusting tube at the same time, the first clamping mirror unit is configured to clamp a voltage of the second end of the first resistance unit based on a voltage of the current control end to generate a first sampling current on the fourth transistor, and adjust the voltage of the control end of the adjusting tube based on the first sampling current, VD1 is a voltage of the second end of the fourth transistor, is a voltage of the current control end, N is a first sampling ratio, N0 is a ratio of width-length ratios of the second transistor and the fourth transistor, is a channel length modulation coefficient, VIN is an input voltage, the first sampling ratio changes nonlinearly with a first current size; and / or The second sampling unit comprises a fifth transistor, a second resistance unit and a second clamping mirror unit, the first end of the fifth transistor is configured to receive an input voltage, the control end of the fifth transistor is connected with the current control end, the second end of the fifth transistor is connected with the second clamping mirror unit, the second clamping mirror unit is connected with the voltage output end, the second resistance unit and the control end of the adjusting tube at the same time, the second clamping mirror unit is configured to clamp the voltage of the second end of the fifth transistor based on the voltage of the voltage output end to generate a sampling current on the fifth transistor, and mirror the sampling current to generate a second sampling current to adjust the voltage of the control end of the adjusting tube, the second clamping mirror unit adjusts the mirror ratio of itself based on the second resistance unit, and mirrors the sampling current to generate the second sampling current based on the mirror ratio, the second sampling current is I2b= , is a second current, M is a second sampling ratio, and the second sampling ratio of the second sampling unit to the second current changes nonlinearly with the size of the second current.

5. The linear voltage regulator circuit of claim 3, wherein, The first sampling unit comprises a fourth transistor, a first resistance unit and a first clamping mirror unit, a first end of the fourth transistor is configured to receive an input voltage, a control end of the fourth transistor is connected with a current control end, a second end of the fourth transistor is connected with a first end of the first resistance unit, a second end of the first resistance unit is connected with the first clamping mirror unit, the first clamping mirror unit is connected with the current control end and a control end of the regulating tube at the same time, the first clamping mirror unit is configured to clamp a voltage of the second end of the resistance unit based on a voltage of the current control end to generate a first sampling current on the fourth transistor, and adjust the voltage of the control end of the regulating tube based on the first sampling current. Or The first sampling unit comprises a fourth transistor and a first clamping mirror unit, a first end of the fourth transistor is configured to receive an input voltage, a control end of the fourth transistor is connected with a current control end, the first clamping mirror unit is connected with the current control end, a second end of the fourth transistor and a control end of the regulating tube, the first clamping mirror unit is configured to clamp a voltage of the second end of the fourth transistor based on a voltage of the current control end to generate a first sampling current on the fourth transistor, and adjust the voltage of the control end of the regulating tube based on the first sampling current.

6. The linear voltage regulator circuit of claim 3, wherein, The second sampling unit comprises a fifth transistor and a second clamping mirror unit, a first end of the fifth transistor is configured to receive an input voltage, a control end of the fifth transistor is connected with a current control end, a second end of the fifth transistor is connected with the second clamping mirror unit, the second clamping mirror unit is connected with a voltage output end and a control end of the regulating tube at the same time, the second clamping mirror unit is configured to clamp a voltage of the second end of the fifth transistor based on a voltage of the voltage output end to generate a second sampling current on the fifth transistor, and adjust the voltage of the control end of the regulating tube based on the second sampling current. Or The second sampling unit comprises a fifth transistor, a second resistance unit and a second clamping mirror unit, a first end of the fifth transistor is configured to receive an input voltage, a control end of the fifth transistor is connected with a current control end, a second end of the fifth transistor is connected with the second clamping mirror unit, the second clamping mirror unit is connected with a voltage output end, a second resistance unit and a control end of the regulating tube at the same time, the second clamping mirror unit is configured to clamp a voltage of the second end of the fifth transistor based on a voltage of the voltage output end to generate a sampling current on the fifth transistor, and generate a second sampling current by mirroring the sampling current to adjust the voltage of the control end of the regulating tube.

7. The linear voltage regulator circuit of claim 3, wherein, The first sampling unit comprises a fourth transistor, a first resistance unit and a first clamping mirror unit, a first end of the fourth transistor is configured to receive an input voltage, a control end of the fourth transistor is connected with a current control end, a second end of the fourth transistor is connected with a first end of the first resistance unit, a second end of the first resistance unit is connected with the first clamping mirror unit, the first clamping mirror unit is connected with the current control end and a control end of the regulating tube at the same time, and the first clamping mirror unit is configured to clamp a voltage of the second end of the resistance unit based on a voltage of the current control end to generate a first sampling current on the fourth transistor and adjust the voltage of the control end of the regulating tube based on the first sampling current. The first clamping mirror unit comprises a first current mirror, a second current mirror and a second current source, the first current mirror is connected with the second end of the first resistance unit, the current control end, the second current source and the second current mirror, the first current mirror is configured to clamp the voltage of the second end of the resistance unit based on the voltage of the current control end to generate the first sampling current on the fourth transistor and transmit the first sampling current to the second current mirror, and the second current mirror is connected with the control end of the regulating tube at the same time to adjust the voltage of the control end of the regulating tube based on the first sampling current. The first sampling unit comprises a fourth transistor and a first clamping mirror unit, a first end of the fourth transistor is configured to receive an input voltage, a control end of the fourth transistor is connected with a current control end, the first clamping mirror unit is connected with the current control end, a second end of the fourth transistor and a control end of the regulating tube, and the first clamping mirror unit is configured to clamp a voltage of the second end of the fourth transistor based on a voltage of the current control end to generate a first sampling current on the fourth transistor and adjust the voltage of the control end of the regulating tube based on the first sampling current.

8. The linear voltage regulator circuit of claim 6, wherein, The second sampling unit comprises a fifth transistor and a second clamping mirror unit, a first end of the fifth transistor is configured to receive an input voltage, a control end of the fifth transistor is connected with a current control end, a second end of the fifth transistor is connected with the second clamping mirror unit, the second clamping mirror unit is connected with a voltage output end and a control end of the regulating tube at the same time, and the second clamping mirror unit is configured to clamp a voltage of the second end of the fifth transistor based on a voltage of the voltage output end to generate a second sampling current on the fifth transistor and adjust the voltage of the control end of the regulating tube based on the second sampling current. The second clamping mirror unit comprises a third current mirror and a third current source, the third current mirror is connected with the second end of the fifth transistor, the voltage output end, the third current source and the control end of the adjusting tube, and the third current mirror is used for clamping the voltage of the second end of the fifth transistor based on the voltage of the voltage output end to generate the second sampling current on the fifth transistor and adjust the voltage of the control end of the adjusting tube based on the second sampling current; Or The second sampling unit comprises the fifth transistor, the second resistance unit and the second clamping mirror unit, the first end of the fifth transistor is used for receiving the input voltage, the control end of the fifth transistor is connected with the current control end, the second end of the fifth transistor is connected with the second clamping mirror unit, the second clamping mirror unit is connected with the voltage output end, the second resistance unit and the control end of the adjusting tube at the same time, and the second clamping mirror unit is used for clamping the voltage of the second end of the fifth transistor based on the voltage of the voltage output end to generate the sampling current on the fifth transistor and mirror the sampling current to generate the second sampling current to adjust the voltage of the control end of the adjusting tube; The second clamping mirror unit comprises a third current mirror, a third current source and a fourth current mirror, the third current mirror is connected with the second end of the fifth transistor, the voltage output end, the third current source and the fourth current mirror, the third current mirror is used for clamping the voltage of the second end of the fifth transistor based on the voltage of the voltage output end to generate the sampling current on the fifth transistor and transmit the sampling current to the fourth current mirror, the fourth current mirror is connected with the second resistance unit and the control end of the adjusting tube, and the fourth current mirror is used for mirroring the sampling current to generate the second sampling current by the mirror ratio generated based on the second resistance unit and adjusting the voltage of the control end of the adjusting tube based on the second sampling current; Or The second sampling unit comprises the fifth transistor and the second clamping mirror unit, the first end of the fifth transistor is used for receiving the input voltage, the control end of the fifth transistor is connected with the current control end, the second end of the fifth transistor is connected with the second clamping mirror unit, the second clamping mirror unit is connected with the voltage output end and the control end of the adjusting tube at the same time, and the second clamping mirror unit is used for clamping the voltage of the second end of the fifth transistor based on the voltage of the voltage output end to generate the second sampling current on the fifth transistor and adjust the voltage of the control end of the adjusting tube based on the second sampling current; The second clamping mirror unit comprises a third current mirror and a seventh sampling unit, the seventh sampling unit is connected with the current mirror unit to sample the second current to obtain the eighth sampling current, the third current mirror is connected with the second end of the fifth transistor, the voltage output end, the seventh sampling unit and the control end of the adjusting tube, and the third current mirror is used for clamping the voltage of the second end of the fifth transistor based on the voltage of the voltage output end, the eighth sampling current which changes with the second current to generate the second sampling current on the fifth transistor and adjust the voltage of the control end of the adjusting tube based on the second sampling current.

9. The linear voltage regulator circuit of claim 1, wherein, The linear voltage regulator circuit further comprises a first regulating unit connected to the output of the first operational amplifier, the input voltage, the current control end of the current mirror unit and the output of the current mirror unit to sample the first current to obtain a fourth sampling current and sample the second current to obtain a fifth sampling current, and the first regulating unit regulates the voltage at the output of the first operational amplifier based on the fourth sampling current and the fifth sampling current; and / or The linear voltage regulator circuit further comprises a second regulating unit connected to the input voltage, the current control end of the current mirror unit and the output of the current mirror unit to sample the first current to obtain a sixth sampling current and sample the second current to obtain a seventh sampling current, and the first regulating unit regulates the voltage at the current control end of the current mirror unit based on the sixth sampling current and the seventh sampling current.

10. The linear voltage regulator circuit of claim 1, wherein, The regulating unit further comprises a first current source, a first end of the first current source being connected to the control end of the regulating tube, and a second end of the first current source being connected to the reference voltage.

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