Netlist subgraph matching method based on enhanced VF3 algorithm, storage medium and device

Abstract

The application belongs to the field of circuit design, and particularly relates to a subgraph matching method based on an enhanced VF3 algorithm, a storage medium and equipment. The method first generates a type of graph structure data of a pattern circuit and type II graph structure data of the pattern circuit and a target circuit according to a netlist file, and establishes a mapping between nodes in different graph structure data. The type II graph structure data takes element ports as nodes, and takes electrical connection relationships between nodes, signal transmission directions and control logic as edges. Then, key nodes in the pattern circuit are identified and the priority of the remaining nodes is calculated. A priority queue is generated in which the key nodes are in front and sorted by priority. Finally, the priority queue is taken as a node search sequence, and a subgraph matching algorithm is used to match nodes in the pattern circuit and the target circuit in the type II graph structure data, so as to determine the pattern circuit contained in the target circuit. The application solves the problem of low search efficiency and error identification of the existing subgraph matching scheme.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of circuit design, and particularly relates to a netlist subgraph matching method based on an enhanced VF3 algorithm, a corresponding computer program product, a storage medium, and a netlist analysis device for integrated circuit design. BACKGROUND

[0002] With the development of semiconductor technology, the market's demand for chip performance and integration continues to increase, which drives the industry's urgent need for efficiency improvement of integrated circuit design. Compared with the highly mature self-design process in digital circuits, analog layout design still heavily relies on the experience and knowledge of designers, with great design freedom, various constraint conditions, and performance sensitivity to physical implementation, which leads to significant challenges in the automation process. Analog subcircuit identification to realize netlist labeling is a key step in the front-end of layout design, aiming to identify device types and interconnection relationships from the circuit netlist, and then extract substructure modules with clear circuit functions such as current mirrors and differential pairs, and generate design constraints to guide subsequent placement and routing, to ensure the electrical characteristics and performance indicators of the circuit.

[0003] Traditional labeling methods are mostly based on graph matching algorithms, which realize the identification of functional structures by performing subgraph isomorphism search between predefined module templates and the circuit to be labeled. However, such methods usually have high computational complexity, and due to the use of exhaustive matching strategies, there is a lot of repeated search and redundant calculation, which restricts their application efficiency in large-scale circuits. For example, the time complexity of the traditional VF3 algorithm is O(N! x M), where N is the number of pattern graph nodes and M is the state verification complexity. In large-scale circuit netlists, this exponential complexity leads to unacceptable matching time. Traditional algorithms only consider the topological structure of the graph, lacking understanding of the specific semantics of the circuit. For example, it leads to incorrect identification due to the inability to distinguish the functional differences of the drain (D), gate (G), and source (S) ports of MOSFET. Existing pruning mechanisms are mainly based on simple topological constraints, lacking intelligent pruning strategies specific to the characteristics of circuit netlists. In complex circuits, the search state space grows exponentially, and the traditional backtracking mechanism is inefficient. SUMMARY

[0004] To solve the problem of low search efficiency and incorrect identification of existing subgraph matching algorithms in large-scale integrated circuit netlist files, the present application provides a netlist subgraph matching method based on an enhanced VF3 algorithm, a corresponding computer program product, a storage medium, and a netlist analysis device for integrated circuit design.

[0005] The present application adopts the following technical solutions:

[0006] A netlist subgraph matching method based on an enhanced VF3 algorithm, comprising:

[0007] According to the netlist files of the mode circuit and the target circuit, a kind of graph structure data G1 of mode circuit and the second kind of graph structure data G2 and G3 of mode circuit and target circuit are generated;And the mapping relationship between the nodes belonging to the same device in G1 and G2 is established.

[0008] Among them, the first kind of graph structure data takes each element contained in the circuit as a node, and takes the electrical connection relationship between the elements as an edge.

[0009] The second kind of graph structure data takes each port of the element as a node, and adds a label representing the port category to each node. Then, according to the element type, a directed edge representing the signal transmission direction or control logic is established between each port of each element, and according to the electrical connection relationship, an undirected edge is established between the ports of different elements.

[0010] From all the nodes contained in G2, the MOSFET gate connection point, the core node of the differential pair tube and the mirror node of the current mirror are identified as key nodes;The node degree, rarity and connection tightness of each node remaining in G2 are obtained, and the priority of each node is calculated;Each key node is randomly arranged in front, and the remaining nodes are arranged in order from large to small according to the priority, to obtain a priority queue.

[0011] Taking the priority queue as the node search order, the subgraph matching algorithm (VF3) is used to match the nodes of G3 and G2, and then the mode circuit contained in the target circuit is determined.

[0012] In node matching, if the labels of any candidate node and its parent node are consistent and the direction of the edge between the parent and child nodes is also consistent, it is determined that the two constitute a pending node, and when the two subgraphs composed of the pending node and the matched node satisfy the isomorphism constraint, it is determined that the two belong to the matched node.

[0013] As a further improvement of the application, the method for generating the first kind of graph structure data according to the netlist file of any circuit is:

[0014] According to the element list in the netlist file, all elements contained in the circuit are determined, and they are encoded into nodes in order to form a node set.

[0015] According to the connection information in the netlist file, the connection relationship between the elements is determined, and an undirected edge is generated between any two connected nodes;Further, a edge set is formed.

[0016] As a further improvement of the application, the method for generating the second kind of graph structure data according to the netlist file of any circuit is:

[0017] According to the port and connection point information in the netlist file, the external ports of all elements contained in the circuit are determined, and are encoded in sequence as respective nodes to form a node set.

[0018] According to the element type to which the node belongs, a category code is added to each node as a label; wherein different category codes are used for the respective ports of active devices, and the same category codes are used for the ports on both sides of passive devices; the category codes of the respective ports in the same type of element remain uniform.

[0019] According to the connection information in the netlist file, the connection relationship between the respective ports is determined, and a directed edge is generated for any two nodes belonging to different elements; to form a directed edge set.

[0020] According to the element type to which the node belongs, a directed edge is generated for any two nodes within each element; to form a directed edge set; wherein bidirectional edges are used between the ports of passive devices, and unidirectional edges are set according to the signal flow direction and control relationship between the ports of active devices.

[0021] As a further improvement of the present application, in the active device, if v i The port corresponding to the node can be used to control v j The port corresponding to the node, the directed edge between them is recorded as i → j .

[0022] Alternatively, if v i The signal flow direction of the port corresponding to the node v j The port corresponding to the node, the directed edge between them is recorded as i → j .

[0023] As a further improvement of the present application, for any node in the two-class graph structure data, the number of its neighbor nodes is recorded as the node degree U1; the reciprocal of the proportion of the number of the element to which the port corresponding to the node belongs in the entire netlist file is recorded as the rarity U2; the number of edges between it and the matched nodes is recorded as the connection tightness U3.

[0024] As a further improvement of the present application, the priority Pr of any node in the two-class graph structure data is calculated according to the following formula:

[0025] Pr=α·U1+β·U2+γ·U3

[0026] In the above formula, α, β and γ respectively represent the preset weights of U1, U2 and U3 in Pr.

[0027] As a further improvement of the present application, the key node identification method is:

[0028] (1) According to the port and connection point information in the netlist file, the gate connection point of the MOSFET is identified, and the corresponding node in G2 is taken as the key node.

[0029] (2) The mode subgraph of the differential pair tube and the current mirror is generated in advance, the mode subgraph is matched with G2, and the core node of the differential pair tube and the mirror node of the current mirror contained in G2 are identified after successful matching.

[0030] As a further improvement of the present application, the node matching method of G3 and G2 by subgraph matching algorithm is as follows:

[0031] S1: Take the first node in the priority queue and any node in G3 as the node pair to be matched, and judge whether the node labels of the two are consistent:

[0032] If not, replace the next node in G3 to form a new node pair to be matched.

[0033] If yes, continue to judge whether the labels of the parent nodes of the two nodes and the directions of the edges of the parent and child nodes are consistent.

[0034] S2: Judge whether the two subgraphs composed of the pending node and the matched node satisfy the isomorphism constraint:

[0035] If yes, add the pending node to the matched node set; otherwise, prune G2 and G3, and take the next node in the updated priority queue and any node remaining in G3 as the node pair to be matched for the next round of matching.

[0036] S3: When traversing the priority queue, complete the matching task of all nodes, and perform the de-duplication operation on the matched node set; finally output the element list and the matching number of the target circuit matched with the mode circuit.

[0037] As a further improvement of the present application, to judge whether any two subgraphs G01 and G02 satisfy the isomorphism constraint, the following criteria must be met:

[0038] Each node in G01 has a unique corresponding node in G02.

[0039] The corresponding nodes of different nodes in G01 are also different in G02.

[0040] The edges existing between any two nodes in G01 also exist between the corresponding two nodes in G02.

[0041] The edges between the corresponding nodes in G02 cannot exceed the edge range of G02.

[0042] The label of any node in G01 is completely consistent with the label of the corresponding node in G02.

[0043] The direction of any edge in G01 is completely consistent with the direction of the corresponding edge in G02.

[0044] The application also includes a computer program product comprising a computer program which, when executed by a processor, implements the enhanced VF3 algorithm-based netlist subgraph matching method as described above, and further identifies the isomorphic pattern circuit in the target circuit.

[0045] The application also includes a storage medium having stored therein a computer program which, when executed by a processor, implements the enhanced VF3 algorithm-based netlist subgraph matching method as described above, and further identifies the isomorphic pattern circuit in the target circuit.

[0046] The application also includes a netlist analysis device for integrated circuit design, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the enhanced VF3 algorithm-based netlist subgraph matching method as described above, and further identifies the isomorphic pattern circuit in the target circuit.

[0047] The technical solution provided by the application has the following beneficial effects:

[0048] The application develops a semantic coding framework specially for circuit netlists, which can model the topological information of circuit functions contained in the netlist file in detail based on the port characteristics of circuit elements. The scheme takes the ports of elements as nodes, differentiates the ports of different types of electronic elements, and designs different types of edges between the nodes inside and outside the element ports in combination with circuit functions and topological relationships. In this way, the limitations of traditional subgraph isomorphism algorithms that cannot distinguish the connection semantics specific to circuits are overcome.

[0049] The scheme also introduces an improved depth-first search strategy, designs a pruning mechanism in combination with circuit topological characteristics, and realizes progressive optimization from lightweight attributes to deep semantics. An adaptive heuristic node selection algorithm is innovatively proposed, and the selection order of candidate nodes is optimized through a dynamic weight calculation model. The proposed system ensures matching accuracy while optimizing algorithm complexity from exponential to approximately polynomial, providing a feasible technical path for efficient processing of large-scale circuit netlists.

[0050] The scheme can greatly improve the search efficiency of the mode circuit under the premise of ensuring the recognition accuracy. Further, accurate structure information is provided for subsequent layout design, performance optimization and verification. The technology can significantly improve the automation level of large-scale integrated circuit design, reduce the workload of manual labeling, avoid abnormal circuit functions caused by manual recognition errors, and provide an efficient and reliable solution for the increasingly complex analog circuit module recognition in modern chip design. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1 A step flow chart of the netlist subgraph matching method based on the enhanced VF3 algorithm provided in embodiment 1 of the present application.

[0052] Figure 2 A typical circuit introduced in embodiment 1 of the present application.

[0053] Figure 3 A topological graph corresponding to a class of graph structure data of the circuit graph. Figure 2

[0054] A topological graph corresponding to a class of graph structure data of the circuit graph. Figure 4 Figure 2 A principle diagram of the subgraph matching based on the second class of graph structure data by using the enhanced VF3 algorithm in embodiment 1 of the present application.

[0055] DETAILED DESCRIPTION Figure 5 In order to make the purpose, technical scheme and advantages of the present application clearer and more apparent, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0056] Embodiment 1

[0057] Embodiment 1

[0058] ​The existing subgraph matching algorithm has time complexity and state space explosion when applied to large-scale integrated circuits, which leads to a decrease in search efficiency. Moreover, the conventional algorithm cannot identify the semantics of circuit connections, so it is easy to have a mismatch phenomenon of the identified isomorphic subgraphs with similar topologies but different circuit functions. The application provides a netlist subgraph matching method based on an enhanced VF3 algorithm. The method redesigns the data format of the graph structure data generated by the netlist file, introduces a new type of two-class graph structure data containing circuit characteristic semantic information, and then reconstructs the logic of the subgraph search algorithm based on the new two-class graph structure data, thereby solving the circuit function mismatch problem. At the same time, the application also optimizes the search direction of the subgraph matching algorithm combined with the landmark of different nodes in the circuit function, thereby greatly reducing the complexity of the algorithm while ensuring the accuracy of the matching, optimizing the algorithm complexity from exponential level to approximate polynomial level, and providing a feasible technical path for efficient processing of large-scale circuit netlists.

[0059] In detail, as shown in Figure 1 The netlist subgraph matching method based on the enhanced VF3 algorithm provided by the embodiment includes the following processes:

[0060] Generate one-class graph structure data G1 of the pattern circuit and two-class graph structure data G2 and G3 of the pattern circuit and the target circuit from the netlist files of the pattern circuit and the target circuit, and establish a mapping relationship between the nodes belonging to the same device in G1 and G2.

[0061] The netlist file is the core input file of circuit simulation and synthesis, which is used to describe the structure of the circuit, the components and their connection relationship, and specify the control information of simulation or synthesis. The netlist file is usually presented in text format and serves as an intermediate file for circuit design and implementation. The main contents in the netlist file include: component list, connection information, port and connection point, attribute and parameter, and network description, etc. The component list includes the unique identifier of each component (such as R1, C2, etc.) and the component type (such as resistor, capacitor, etc.). The connection information lists which pins of each component are connected to each other, and each network has a unique name to identify the connected pins. The port and connection point information contains which interface is the port of each component, and the network is composed of multiple ports of components. The attributes and parameters include voltage, frequency, load, etc. information to help designers simulate and analyze. The network description information is used to describe all electronic components and their connection relationship in the circuit, which is an important part of circuit design.

[0062] In order to utilize the information in the netlist file to realize the identification and positioning of the pattern circuit (search object) contained therein by the subgraph matching algorithm in the target circuit (search space), the embodiment first needs to convert the netlist files of the target circuit and the pattern circuit into graph structure data recognizable by the subgraph matching algorithm. In the traditional scheme, each element contained in the circuit is usually taken as a node, and the electrical connection relationship between the elements is taken as an edge, and the netlist file is converted into a kind of graph structure data (denoted as G001). And the subgraph matching task is performed by using the graph structure data. And this is also the main reason why the existing subgraph matching algorithm has low search efficiency and accuracy in large-scale integrated circuits.

[0063] In the embodiment, a new graph structure data is designed, which takes each port of an element as a node, and takes the connection relationship between the ports outside each element and the signal transmission direction and control logic between the ports inside each element as an edge. Specifically, a directed edge representing the signal transmission direction or control logic is established between each port of each element according to the element type, and an undirected edge is established between the ports of different elements according to the electrical connection relationship. The graph structure data is named as two kinds of graph structure data (denoted as G002) in the embodiment. The subsequent subgraph matching task is also mainly based on the two kinds of graph structure data. Specifically, in actual application, for the target circuit, the embodiment only needs to convert it into the corresponding two kinds of graph structure data G3. For the pattern circuit, the embodiment needs to convert it into the corresponding two kinds of graph structure data G2, and also needs to convert it into the one kind of graph structure data G1, and establish a mapping relationship between the nodes contained in G1 and G2, so as to realize the quick query of the related attributes of the elements corresponding to each node in G2.

[0064] In the embodiment, the method for generating one kind of graph structure data from the netlist file of an arbitrary circuit is as follows:

[0065] Determine all elements contained in the circuit according to the element list in the netlist file, and encode them into nodes in sequence , to form a node set V1: ∈V1; i =1… n , n , wherein N represents the total number of electronic elements contained in the circuit. Determine the connection relationship between the elements according to the connection information in the netlist file, and generate an undirected edge and for any two connected nodes ; to form an edge set E1: ∈E1; ∈V1 and i ≠ jFinally, a class of graph structure data can be represented as G001: G001={V1, E1}.

[0066] In this embodiment, the second class of graph structure data takes each port of an element as a node. Each element in the original circuit diagram is generally represented as a node cluster composed of multiple nodes corresponding to each port of the element in this graph structure data. For example, passive elements such as capacitors, capacitors and inductors, and active elements such as diodes generally include two external ports, so the element is converted to a node cluster composed of two nodes in the circuit diagram, and the port number of active elements such as MOS tubes and BJTs is 3, so it is represented as a node cluster composed of three nodes. In order to distinguish different ports of the element, this embodiment also adds a label representing the port category to each node in the node cluster of each element. For example, the drain, gate and source of the PMOS tube correspond to the codes 11, 12 and 13 respectively; the drain, gate and source of the NMOS tube correspond to the codes 21, 22 and 23 respectively; the base, collector and emitter of the NPN type BJT correspond to the codes 51, 52 and 53 respectively; the base, collector and emitter of the PNP type BJT correspond to the codes 61, 62 and 63 respectively; the two ports of the diode have a polarity difference, so the corresponding codes are 71 and 72 respectively; and the two ports of the resistor have no direction difference, so the corresponding code is 31; the two ports of the capacitor also have no direction difference, so the corresponding code is 41; and so on. It needs to be emphasized that in the second class of graph structure data of this embodiment, the power supply VDD and the ground GND are also an independent node, and the corresponding codes are 0 and 99 respectively. The various signal input or output ports and intermediate nodes contained in the netlist file are not independent nodes, and these ports will be excluded in advance when preprocessing the netlist file.

[0067] In detail, in this embodiment, the method for generating the second class of graph structure data according to the netlist file of any circuit includes the following processes:

[0068] First, determine the external ports of all elements contained in the circuit according to the port and connection point information in the netlist file, and encode them as nodes in order , to form a node set V2: ∈V2; i =1… m , m represent the external ports of all elements contained in the circuit. Second, add a category code as a label to each node according to the element type to which the node belongs (which can be determined by the mapping relationship between nodes in G2 and G3). Among them, the ports of active devices use different category codes, and the ports on both sides of passive devices use the same category code; the category codes of each port in the same class of elements remain the same.

[0069] Next, the connection relationships between each port are determined based on the connection information in the netlist file, which represents any two nodes belonging to different components. and Generate an undirected edge ; Forms the edge set E2: ∈E2; ∈V2 and i ≠ j Then, based on the component type to which each node belongs, any two nodes within each component are considered. and Generate a directed edge ; This forms the edge set E3: ∈E3; ∈V2 and i ≠ j In passive devices (such as resistors and capacitors), bidirectional edges are used between the ports, while active devices have unidirectional edges based on the signal flow direction and control relationship between the ports. In active devices, if... The port corresponding to the node can be used for control in the circuit. The directed edge between the ports corresponding to the nodes (such as between the ports of a MOSFET) is denoted as . i → j Or, if Signal flow direction of the port corresponding to the node The directed edge between the ports corresponding to the nodes (such as between the ports of a diode) is denoted as... i → j Finally, the binary graph structure data is represented as G002: G002={V2,E2,E3}.

[0070] Specifically, as Figure 2 Taking the circuit diagram as an example, A and B are the two signal input ports of the circuit, and OUT is the signal output port of the circuit. Based on its netlist file, it can be converted to... Figure 3 The aforementioned graph structure file contains 8 nodes, corresponding to VDD, P1, P2, P3, N1, N2, N3, and GND. It is further converted into... Figure 4 The second type of graph structure file shown is then expanded to 20 nodes, namely 1 node corresponding to VDD and GND, and 3 nodes corresponding to each element in P1, P2, P3, N1, N2, and N3.

[0071] The MOSFET gate connection point, the core node of the differential pair tube and the mirror node of the current mirror are identified from all the nodes included in G2 as key nodes; the node degree, the rarity and the connection tightness of each node in G2 are obtained, and the priority of each node is calculated; each key node is randomly arranged in front, and the remaining nodes are arranged in the order from large to small according to the priority, to obtain a priority queue.

[0072] In the embodiment, in order to avoid the efficiency problem caused by the unordered search of the traditional subgraph matching algorithm, the priority of each node in the two-class graph structure data of the mode circuit is sorted to obtain a priority queue, and then the queue is taken as a search direction to perform a subsequent subgraph matching task.

[0073] In the embodiment, the principle of the priority sorting of each node in the two-class graph structure data can be summarized as follows: the key nodes with high integration are preferentially processed, and the node degree, the rarity of the device type and the connection tightness with the matched nodes are comprehensively considered. This is because the MOSFET gate connection point, the core node of the differential pair tube and the mirror node of the current mirror are the landmark nodes in part of the mode circuit, and locating these nodes first will help to quickly find other nodes around them, and then efficiently complete the search task of the mode circuit.

[0074] In actual application, the identification method of the key nodes is as follows:

[0075] (1) The MOSFET gate connection point is identified according to the port and connection point information in the netlist file, and the corresponding node in G2 is taken as a key node. (2) The mode subgraph of the differential pair tube and the current mirror is generated in advance, the node matching between the mode subgraph and G2 is performed, and the core node of the differential pair tube and the mirror node of the current mirror included in G2 are identified after the matching is successful.

[0076] Among the comprehensive indexes of the remaining nodes, the node with high node degree is connected to more nodes, which means that the node is more critical in the circuit (for example, the Gate port of the MOS tube is connected to multiple devices), and the preferential matching can exclude invalid branches earlier. The node with high device type rarity (such as a specific type of MOSFET) has fewer candidates in the target graph, and the preferential matching can improve the success rate. The node with high connection tightness with the matched nodes means that the current matching state is more constrained, and the preferential processing helps to maintain the topological consistency.

[0077] In the embodiment, for any node in the two-class graph structure data, the number of neighbor nodes is denoted as the node degree U1. The node degree U1 of any node in G2 can be directly obtained from G1, for example, a node is connected to three different nodes respectively, and the degree of the node is 3.

[0078] The reciprocal of the proportion of the number of elements to which the port corresponding to any node in the second graph structure data belongs in the entire netlist file is denoted as the rarity U2 of the node. In actual applications, the rarity U2 needs to be obtained in combination with G1 that is mapped with G2. For example, in a certain circuit, 10 elements are included, and the number of NMOS tubes is 2. After mapping, it is determined that a node in G2 is one of the ports of a certain NMOS tube, and the rarity of the node is 10 / 2=5.

[0079] The number of edges between any node and the matched nodes in the second graph structure data is denoted as the connection tightness U3. In actual applications, the initial value of the connection tightness U3 of each node is 0; as the subgraph matching task is executed, the number of matched nodes will increase, and therefore, after each round of node matching is completed, the connection tightness U3 of the remaining nodes will be updated. The more the number of edges between any node and the matched nodes, the higher the connection tightness U3, the closer to the center of the subgraph corresponding to the mode circuit, and the node should be preferentially matched.

[0080] In summary, in the embodiment, the calculation formula of the priority Pr of any node in the second graph structure data is as follows:

[0081] Pr=α·U1+β·U2+γ·U3

[0082] In the above formula, α, β and γ respectively represent the preset weights of U1, U2 and U3 in Pr. In actual applications, the values of α, β and γ can be dynamically adjusted according to actual scenarios. For example, the system can optimize these parameters in real time according to the current matching state and historical success rate, so that the algorithm has adaptability.

[0083] The priority queue is used as the node search order, the subgraph matching algorithm is used to match the nodes of G3 and G2, and then the mode circuit included in the target circuit is determined.

[0084] Unlike the VF3 algorithm, which performs subgraph matching in a single-type graph structure, this embodiment requires performing subgraph matching in a newly designed binary graph structure, which places new demands on the VF3 algorithm. Specifically, this embodiment refers to this modified algorithm as the enhanced VF3 algorithm. Firstly, this embodiment defines the search direction; the enhanced VF3 algorithm strictly follows a priority queue for node search order and backtracks based on the search results. Secondly, unlike the traditional VF3 algorithm, which considers two nodes to be undetermined simply because they have the same number of neighboring nodes, the enhanced VF3 algorithm in this embodiment requires that any set of candidate nodes and their parent nodes have identical labels and that the edges between parent and child nodes have identical directions before considering them as undetermined nodes. Finally, when the two subgraphs formed by the undetermined node and the matched node satisfy isomorphism constraints, they are considered matched nodes.

[0085] Accordingly, in this embodiment, based on the improved binary graph structure data, the criterion for determining whether two subgraphs are isomorphic is also more stringent. Specifically, in this embodiment, determining that any two subgraphs G01 and G02 satisfy the isomorphism constraint requires them to simultaneously satisfy the following criterion:

[0086] (1) Each node in G01 has a unique corresponding node in G02.

[0087] (2) Different nodes in G01 correspond to different nodes in G02.

[0088] (3) An edge between any two nodes in G01 also exists between the corresponding two nodes in G02.

[0089] (4) The edges between corresponding nodes in G02 cannot exceed the edge range of G02.

[0090] (5) The label of any node in G01 is exactly the same as the label of the corresponding node in G02.

[0091] (6) The direction of any edge in G01 is exactly the same as the direction of the corresponding edge in G02.

[0092] Specifically, such as Figure 5 As shown, in this embodiment, the enhanced subgraph matching algorithm is used to perform node matching on G3 and G2 as follows:

[0093] S1: Take the first node in the priority queue and any node in G3 as the node pair to be matched, and determine whether their node labels are the same:

[0094] Otherwise, replace the next node in G3 to form a new pair of nodes to be matched.

[0095] If yes, continue to determine whether the labels of the parent nodes of the two nodes and the directions of the edges between the parent and child nodes are consistent, and if yes, it is determined that the two belong to the pending nodes.

[0096] S2: Determine whether the two subgraphs formed by the pending nodes and the matched nodes satisfy the isomorphism constraint:

[0097] If yes, the pending node is added to the set of matched nodes; otherwise, the pruning operation is performed on G2 and G3, and the next node in the updated priority queue and any one of the remaining nodes in G3 are taken as a pair of nodes to be matched for the next round of matching.

[0098] S3: When the priority queue is traversed, the matching task of all nodes is completed, and the de-duplication operation is performed on the set of matched nodes (to avoid repeated matching of the same sub-circuit); finally, the element list and the matching number of the matched nodes in the target circuit are output.

[0099] In this embodiment, the node pairs to be matched are organized into a search tree, and the nodes at the same level in the tree correspond to the same node in the graph structure data. The search state s represents the updated result after each partial matching, and includes the set of matched nodes. For each group of pending nodes, it is verified whether the 6 constraints of subgraph isomorphism are satisfied: if not, the branch is directly pruned (eliminated) to avoid invalid search. If the constraints are satisfied, the corresponding node is added to the current state s to generate a new state, which is marked as a "consistent state". If the "consistent state" contains all nodes in the second type of graph structure data of the pattern circuit, it is determined to be a goal state (Goal State), that is, the subgraph of the pattern circuit to be matched is found in the target circuit.

[0100] Embodiment 2

[0101] The method provided in Embodiment 1 is essentially a data processing method. In order to better apply the scheme in Embodiment 1, this embodiment further provides a corresponding computer program product, a storage medium, and a netlist analysis device of integrated circuit design.

[0102] The computer program product provided in this embodiment includes a computer program, which is executed by a processor to implement the netlist subgraph matching method based on the enhanced VF3 algorithm as in Embodiment 1, and further identify the isomorphic pattern circuit in the target circuit.

[0103] The storage medium provided in this embodiment stores a computer program, which is executed by a processor to implement the netlist subgraph matching method based on the enhanced VF3 algorithm as in Embodiment 1, and further identify the isomorphic pattern circuit in the target circuit.

[0104] The integrated circuit design netlist analysis device provided in the embodiment includes a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, the method for matching a netlist subgraph based on an enhanced VF3 algorithm in the embodiment 1 is implemented, and then the isomorphic pattern circuit is identified in the target circuit.

[0105] The integrated circuit netlist analysis device provided in the embodiment is essentially a computer device. The computer device can be a smartphone, a tablet computer, a notebook computer, a desktop computer, a rack server, a blade server, a tower server, or a cabinet server (including a standalone server or a server cluster composed of multiple servers), etc. which can execute programs.

[0106] The computer device of the embodiment at least includes but is not limited to a memory and a processor which can be connected to each other in communication through a system bus. In the embodiment, the memory (i.e. a readable storage medium) includes a flash memory, a hard disk, a multimedia card, a card-type memory (e.g. an SD or DX memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory can be an internal storage unit of the computer device, such as a hard disk or a memory of the computer device. In other embodiments, the memory can also be an external storage device of the computer device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device. Of course, the memory can include both the internal storage unit and the external storage device of the computer device. In the embodiment, the memory is usually used to store an operating system and various application software installed on the computer device, etc. In addition, the memory can also be used to temporarily store various data which have been output or will be output.

[0107] The processor in some embodiments can be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chips. The processor is usually used to control the overall operation of the computer device.

[0108] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for matching sub-graphs of netlists based on an enhanced VF3 algorithm, characterized in that, It comprises: According to the netlist file of the mode circuit and the target circuit, the one-type graph structure data G1 of the mode circuit is generated, and the two-type graph structure data G2 and G3 of the mode circuit and the target circuit are generated; And the mapping relationship between the nodes belonging to the same device in G1 and G2 is established; The one-type graph structure data takes each element contained in the circuit as a node, and takes the electrical connection relationship between the elements as an edge; The two-type graph structure data takes each port of the element as a node, and adds a label representing the port category to each node; Then, according to the element type, a directed edge representing the signal transmission direction or control logic is established between each port of each element, and an undirected edge is established between the ports of different elements according to the electrical connection relationship; From all the nodes contained in G2, the MOSFET gate connection point, the core node of the differential pair tube, and the mirror node of the current mirror are identified as key nodes; the node degree, rarity, and connection tightness of each node remaining in G2 are obtained, and the priority of each node is calculated; each key node is randomly arranged in front, and the remaining nodes are arranged in order from large to small according to the priority, to obtain a priority queue; Taking the priority queue as the node search order, a subgraph matching algorithm is used to match the nodes of G3 and G2, and then the mode circuit contained in the target circuit is determined; In the node matching, if the labels of any candidate node and its parent node are consistent and the direction of the edge between the parent and child nodes is also consistent, it is determined that the two constitute a pending node, and when the two subgraphs composed of the pending node and the matched node meet the isomorphism constraint, it is determined that the two belong to the matched node.

2. The enhanced VF3 algorithm based netlist subgraph matching method of claim 1, wherein: The method for generating one-type graph structure data according to the netlist file of any circuit is: According to the element list in the netlist file, all elements contained in the circuit are determined, and they are sequentially encoded into nodes to form a node set; According to the connection information in the netlist file, the connection relationship between the elements is determined, and an undirected edge is generated between any two connected nodes; and then an edge set is formed.

3. The enhanced VF3 algorithm based netlist subgraph matching method of claim 1, wherein: The method for generating two-type graph structure data according to the netlist file of any circuit is: According to the port and connection point information in the netlist file, all external ports of the elements contained in the circuit are determined, and they are sequentially encoded into nodes to form a node set; According to the element type to which the node belongs, a category code is added to each node as a label; wherein the ports of active devices use different category codes, and the ports on both sides of passive devices use the same category code; the category codes of the ports in the same type of element remain the same; According to the connection information in the netlist file, the connection relationship between the ports is determined, and an undirected edge is generated between any two nodes belonging to different elements; and then an undirected edge set is formed; According to the element type to which the node belongs, a directed edge is generated between any two nodes in each element; a directed edge set is formed; wherein the ports of passive devices use bidirectional edges, and the ports of active devices use unidirectional edges.

4. The enhanced VF3 algorithm based netlist subgraph matching method of claim 3, wherein: In active devices, if v i The port corresponding to a node can be used to control v j The directed edge between two nodes is denoted by i → j ; Or, if v i Signal flow direction of the port corresponding to the node v j The directed edge between the port corresponding to the node and the port corresponding to the node is recorded as i → j .

5. The netlist subgraph matching method based on the enhanced VF3 algorithm according to claim 1, wherein: For any node in the second type of graph structure data, the number of its neighbor nodes is denoted as node degree U1; The reciprocal of the proportion of the number of elements to which the corresponding port belongs in the entire netlist file is denoted as rarity U2; The number of edges between the node and the matched node is denoted as connection closeness U3; And / or, the calculation formula of the priority Pr of any node in the second type of graph structure data is as follows: Pr = a U1 + β U2 + γ U3; In the above formula, a, β and γ respectively represent the preset weights of U1, U2 and U3 in Pr.

6. The enhanced VF3 algorithm based netlist subgraph matching method of claim 1, wherein: The identification method of the key node is: According to the port and connection point information in the netlist file, the gate connection point of the MOSFET is identified, and the corresponding node in G2 is taken as the key node; The mode subgraph of the differential pair transistor and the current mirror is generated in advance, the mode subgraph is matched with G2, and the core node of the differential pair transistor and the mirror node of the current mirror contained in G2 are identified after successful matching.

7. The enhanced VF3 algorithm based netlist subgraph matching method of claim 1, wherein, The node matching method of G3 and G2 by using the subgraph matching algorithm is as follows: S1: Take the first node in the priority queue and any node in G3 as a node pair to be matched, and judge whether the node labels of the two nodes are consistent: If not, replace the next node in G3 to form a new node pair to be matched; If yes, continue to judge whether the labels of the parent nodes of the two nodes and the directions of the edges of the parent and child nodes are consistent, and if yes, it is judged that the two belong to the pending node; S2: Judge whether the two subgraphs composed of the pending node and the matched node satisfy the isomorphism constraint: If yes, add the pending node to the set of matched nodes, otherwise, prune G2 and G3, and take the next node in the updated priority queue and any node remaining in G3 as a node pair to be matched for the next round of matching; S3: When the priority queue is traversed, the matching task of all nodes is completed, and the set of matched nodes is de-duplicated; finally, the element list and the matching number of the target circuit matched with the mode circuit are output; And / or, judging whether any two subgraphs G01 and G02 satisfy the isomorphism constraint needs to satisfy the following criteria at the same time: Each node in G01 has a unique corresponding node in G02; The corresponding nodes of different nodes in G01 are also different in G02; The edges between any two nodes in G01 also exist between the corresponding two nodes in G02; The edges between the corresponding nodes in G02 cannot exceed the edge range of G02; The label of any node in G01 is completely consistent with the label of the corresponding node in G02; The direction of any edge in G01 is completely consistent with the direction of the corresponding edge in G02.

8. A computer program product comprising a computer program, characterized in that, When the computer program is executed, the netlist subgraph matching method based on the enhanced VF3 algorithm is realized, and the isomorphic mode circuit in the target circuit is identified.

9. A storage medium having stored therein a computer program, characterized in that When the computer program is executed, the netlist subgraph matching method based on the enhanced VF3 algorithm is realized, and the isomorphic mode circuit in the target circuit is identified.

10. A device for analyzing a netlist of an integrated circuit design, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements the method for matching sub-graphs of a netlist based on an enhanced VF3 algorithm as claimed in any one of claims 1-7, thereby identifying isomorphic pattern circuits in a target circuit.

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