A 3D placer based die partition and hybrid bonding pad assignment method

Abstract

The present application relates to the technical field of electronic design automation, in particular to a kind of core grain division and mixed bonding pad distribution method based on 3D layouter, it is by obtaining netlist of user input and user specified constraint condition;Netlist and constraint condition are input 3D layouter, wherein, 3D layouter executes the following operation: under constraint condition, iteratively carry out multi-objective optimization, calculate the optimal position of each logic unit in multiple layout planes, and output at least one kind of core grain division result;Wherein, optimization target in multi-objective optimization includes: line length drive, timing drive, routability drive, heat distribution drive, reserved silicon through hole via and chip total area optimum;Wherein, each core grain division result includes the optimization result of multi-objective optimization, the core grain size of each core grain, the core grain where each logic unit of division is located, and corresponding coarse layout result.The method can achieve the purpose of considering interlayer routing, area distribution and core grain process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation, in particular to a die partitioning and mixed-bonding pad assignment method based on a 3D placer. BACKGROUND

[0002] The current mature 2D layout algorithm in the industry cannot be directly adapted to the 3D die structure. Currently, when performing 3D die structure partitioning, the commonly used method is to directly use the 2D layout algorithm for layout, and then map the 2D layout result to the 3D structure. However, since in the 2D layout stage, all modules are assumed to be in the same plane, and the connection only needs to consider the horizontal distance; when mapped to the 3D structure, the cells that are adjacent on the same plane may be assigned to different dies; at this time, even if the positions of the two cells in their respective layers are locally optimal, the connection between them must pass through the TSV to cross multiple layers, introducing an additional vertical path length; if the TSV position is limited, the signal may need to detour to the nearest TSV and then pass through the interlayer, resulting in an actual 3D line length much larger than the 2D estimated value, and further leading to problems such as timing constraints not being met, thereby causing the layout quality to decrease. In addition, since each layer in this method cannot perceive the wire position and cell distribution of other layers, this will affect the accuracy and reasonableness of the partitioning, leading to uneven die area of each layer, and making it impossible to achieve an efficient pad assignment and interconnection optimization method. In addition, if different processes are used for each layer die, the size and height of the standard cells in each layer are different, which will make the traditional 2D layout-based method even more difficult to apply. Therefore, there is an urgent need for a die partitioning method that can simultaneously consider interlayer routing, area distribution, and die process. SUMMARY

[0003] In view of the above technical problems, the technical solution adopted by the present application is as follows: a die partitioning method based on a 3D placer, the method comprising the following steps:

[0004] S100, obtaining a netlist input by a user, the netlist comprising a plurality of logic cells and their connection relationships.

[0005] S300, obtaining a constraint condition specified by the user, the constraint condition being: no constraint, or a combination of one or more constraint conditions selected from the layout layer number, the process version of each die candidate, the vertical interconnection method, the size of the reserved through-hole via, the pitch of the reserved through-hole via, the density of the reserved through-hole via, and the avoidance margin of the reserved through-hole via.

[0006] S500, input the netlist and the user-specified constraint conditions into a 3D placer, wherein the 3D placer performs the following operations: under the constraint conditions, iteratively performing multi-objective optimization, calculating the optimal position of each logic cell in multiple layout planes, and outputting at least one core particle partitioning result; wherein the optimization objectives in the multi-objective optimization include: wire length driving, timing driving, routability driving, thermal distribution driving, reserved through-silicon via (TSV) and chip total area optimization; wherein each core particle partitioning result includes the optimization result of multi-objective optimization, the core particle size of each core particle, the core particle where each partitioned logic cell is located, and the corresponding coarse layout result.

[0007] In addition, the application also provides a 3D placer-based hybrid bonding pad allocation method, which comprises the following steps:

[0008] P100, obtaining a user-input netlist, the netlist including multiple logic cells and their connection relationships;

[0009] P300, obtaining user-specified constraint conditions, the constraint conditions being one or more of the size, pitch, clearance margin, maximum density and threshold value of the hybrid bonding pad;

[0010] P500, inputting the netlist and the user-specified constraint conditions into a 3D placer, wherein the 3D placer performs the following operations: under the constraint conditions, iteratively performing multi-objective optimization; wherein the optimization objectives in the multi-objective optimization include: wire length driving, timing driving, routability driving, thermal distribution driving, reserved through-silicon via (TSV) and chip total area optimization; calculating the optimal position of hybrid bonding pad allocation based on the 3D layout result; wherein the steps of hybrid bonding pad allocation include:

[0011] According to the multiple target subsystems to be aligned in each layout plane and the multiple target regions associated with each target subsystem, the positions of the multiple target regions in different layout planes associated with each target subsystem are optimized, so that the overlapping area of the multiple target regions associated with the same target subsystem projected on the same layout plane is maximized;

[0012] For the multiple target regions associated with the same target subsystem, the cross-layer hybrid bonding pad pairs are preferentially configured based on the overlapping area, to obtain a hybrid bonding pad allocation result.

[0013] The application has at least the following beneficial effects:

[0014] The embodiment of the present application provides a kind of core grain division and hybrid bonding pad distribution method based on 3D layouter, which can carry out multi-objective optimization according to the space correlation of multi-layer layout plane, constraint condition and process difference in the process of layout and core grain division by 3D layouter for core grain division, to reduce long distance wiring across core grain, realize "system-interconnection-physical" collaborative 3D core grain division and hybrid bonding pad distribution, reduce later iteration, reach the purpose of giving consideration to interlayer wiring, area distribution and core grain process. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0016] Figure 1 A core grain division method based on 3D layouter is provided for the embodiment of the present application.

[0017] Figure 2 A hybrid bonding pad distribution method based on 3D layouter is provided for the embodiment of the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0019] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present application have the same meaning as commonly understood by those skilled in the art.

[0020] Embodiment one

[0021] Please refer to Figure 1 which shows a core grain division method based on 3D layouter, the method comprises the following steps:

[0022] S100, a netlist input by a user is obtained, and the netlist includes a plurality of logic units and their connection relationship.

[0023] The netlist is a file describing the logic units and their interconnection relationship in the circuit, and is the basis for core grain division.

[0024] S300, obtaining a constraint condition specified by a user, the constraint condition being a combination of one or more constraint conditions selected from a layout layer number, a process version of each core candidate, a vertical interconnection manner, a size of a reserved through-silicon via, a pitch of the reserved through-silicon via, a density of the reserved through-silicon via, and a clearance of the reserved through-silicon via.

[0025] The layout layer number includes two layout planes or a three-dimensional stacked structure of three or more layers, each layer being a layout plane.

[0026] Each layout plane is divided into one or more cores.

[0027] In an embodiment, if the layout layer number specified by the user is two, and the number of cores divided in each layer is one, the layout result is the division result, which is the simplest division result. For complex cases, each layer can be divided into multiple cores, and the combination of each layer results in a complex core division result.

[0028] The process version includes a complete set of design support files such as a standard cell library and a through-silicon via. The size, height, and other information of the standard cells may be different for different process versions.

[0029] In an embodiment, the 3D layouter supports configuring the same process for all cores, or configuring a suitable process for each layer of cores, or configuring the same process for some layers and different processes for other layers. Other process configuration methods also fall within the protection scope of the present application.

[0030] In an embodiment, the vertical interconnection manner is a through-silicon via (TSV) or direct hybrid bonding. Other types of vertical interconnection manners also fall within the protection scope of the present application.

[0031] In an embodiment, the density of the reserved through-silicon via is the maximum density.

[0032] The size of the reserved through-silicon via refers to the physical cross-sectional size of the through-silicon via (TSV) pre-made in a silicon wafer for vertical interconnection. The pitch of the reserved through-silicon via refers to the minimum distance between the centers or edges of adjacent through-silicon vias to avoid short circuit, process damage, or signal interference. The density of the reserved through-silicon via refers to the number of through-silicon vias arranged per unit area. The maximum density of the reserved through-silicon via refers to the maximum number of through-silicon vias arranged per unit area. The clearance of the reserved through-silicon via refers to the minimum safety distance that must be maintained around each TSV for passive devices, active circuits, or other sensitive structures.

[0033] In one embodiment, the constraints further include: user-specified groups of locations and / or groups of layers, and / or user-specified groups of logic cells to be configured in the same die. Wherein, for a user-specified group of locations, it has a determined number of layers in the layout plane and a coordinate position in the layout plane, its position remains unchanged during the layout process. For a user-specified group of layers, it only has a determined number of layers in the layout plane, and its specific position in the corresponding layout plane is not restricted, so its position in the corresponding layout plane can be optimized during the layout process. For a user-specified group of logic cells to be configured in the same die, it is constrained to belong to the same die, so it needs to be always configured in the same die during the layout process, and its specific position in the die can be optimized.

[0034] In one embodiment, the user configures the constraints through a visual interactive interface.

[0035] S500, input the netlist and user-specified constraints into a 3D placer, wherein the 3D placer performs the following operations: iteratively performs multi-objective optimization under the constraints, calculates the optimal position of each logic cell in multiple layout planes, and outputs at least one die partitioning result; wherein the optimization objectives in the multi-objective optimization include: wire length driving, timing driving, routability driving, thermal distribution driving, reserved through-hole and chip area optimization; wherein each die partitioning result includes the optimization result of multi-objective optimization, the size of each die, the die where each partitioned logic cell is located, and the corresponding coarse layout result.

[0036] Wherein, the 3D placer supports the collaborative layout of multi-layer standard cells / macros, provides hierarchical algorithms and inter-layer interconnection planning modules, minimizes intra-layer, inter-layer and global interconnection delays, and balances the area utilization of each layer.

[0037] In one embodiment, the 3D placer is a pseudo-3D placer or a true-3D placer. Other types of 3D placers also fall within the protection scope of the present application. Wherein, the pseudo-3D placer combines 2D layout with partitioning algorithms to optimize cell positions and partitioning in stages, and generates a 3D layout result. Wherein, the true-3D placer can realize the layout exploration of logic cells in real 3D space by 3D modeling of the layout space and logic cells, and uniformly optimize the position and partitioning, and has better partitioning quality.

[0038] Wherein, the optimization target of the routable wire is to improve the success rate of routing and reduce the congestion of routing. The optimization target of the reserved TSV is to optimize the number, position and distribution of the TSV. The optimization target of the total chip area is to minimize the total chip area under the premise of meeting all functional and physical constraints, so as to maximize the wafer utilization and reduce the manufacturing cost.

[0039] Wherein, the optimization target of the routable wire is to improve the success rate of routing and reduce the congestion of routing. The optimization target of the reserved TSV is to optimize the number, position and distribution of the TSV. The optimization target of the total chip area is to minimize the total chip area under the premise of meeting all functional and physical constraints, so as to maximize the wafer utilization and reduce the manufacturing cost.

[0040] In an embodiment, the step of multi-objective optimization includes: simultaneously optimizing each target in the process of iteration; and taking the violation items in the last round of optimization as the constraint input of the next round. For example, when the congestion degree exceeds the preset congestion threshold, redistribution is performed in the next round, and the total chip area and timing evaluation are updated. When the peak value of the thermal distribution exceeds the preset thermal threshold, the high-power module is migrated to the low-temperature region in the next round, while the total length of the interconnection between the modules after migration is constrained to be less than the preset total bus length threshold, and the like.

[0041] In an embodiment, the method further includes: S200, preprocessing the netlist, the preprocessing step including: inputting the netlist into a set abstraction model, the set abstraction model performing a merging operation on all gate standard cells in the netlist and updating the netlist; wherein the merging operation is to merge a plurality of gate standard cells satisfying a preset condition into one basic abstract module. Without affecting the accuracy of the layout, the number of units to be processed by the layout can be reduced from the order of magnitude of one billion gate standard cells or higher to the order of magnitude of one million set abstraction modules, thereby greatly improving the running speed and layout capability of the tool.

[0042] In an embodiment, the core particle size of the core particle is a core particle size specified by a user or an optimal core particle size generated in the 3D layout process, and other ways of obtaining the core particle size also fall within the protection scope of the present application.

[0043] In an embodiment, the step of generating the optimal core particle size in the 3D layout process includes: in S100, the constraint conditions further include a length-width ratio constraint and an area utilization constraint of each core particle. S500 further includes: the 3D layouter optimizes the size of each core particle according to the length-width ratio constraint and the area utilization constraint of each core particle to obtain the optimal core particle size.

[0044] In an embodiment, the method further comprises: based on the die size of all the dies, the step of mixed-technology bonding pad assignment in the process of multi-objective optimization by the iterative algorithm in S500 further comprises: according to the specified multiple target subsystems to be aligned in each layout plane and the multiple target regions associated with each target subsystem, optimizing the positions of the multiple target regions in different layout planes associated with each target subsystem so that the overlapping area of the multiple target regions associated with the same target subsystem projected on the same layout plane is maximized; and for the multiple target regions associated with the same target subsystem, based on the overlapping area, preferentially configuring the mixed-technology bonding pad pairs across layers to obtain the mixed-technology bonding pad assignment result. This can make the connection lines between vertically adjacent layout planes the shortest and does not require the insertion of buffers, thereby reducing the consumption of hardware resources. This avoids the prior art in which, due to the misalignment between the target regions in adjacent layout planes, the connection between the target regions in adjacent layout planes needs to be first connected through mixed-technology bonding pad pairs and then routed from the positions of the mixed-technology bonding pad pairs to the target regions in the corresponding layout planes, thereby resulting in the need to insert a large number of buffers on the routing within the layout plane, which not only results in long and complex wiring between the target regions but also consumes a large number of buffers and wastes hardware resources.

[0045] It should be noted that the bonding pad is also referred to as a bonding end, is made of copper, and has a surface that is subjected to a planarization process and is used to implement mixed-technology bonding.

[0046] In an embodiment, the target region is defined by its frame coordinates, and the frame coordinates are aligned in adjacent stacked layers to maximize the overlapping area.

[0047] In an embodiment, the target subsystem is a voltage domain, and the target region is a power supply region associated with the voltage domain. Other types of subsystems that need to be aligned in the layout process also fall within the protection scope of the present application.

[0048] In an embodiment, the target subsystem is a user-specified subsystem, a system-default-specified subsystem, or a subsystem that simultaneously includes a user-specified subsystem and a system-default-specified subsystem.

[0049] In an embodiment, in the step of mixed-technology bonding pad assignment, the constraint conditions are one or more of the size, pitch, clearance margin, maximum density, and threshold of the mixed-technology bonding pad, as well as the signal integrity constraint and / or the power integrity constraint. Other types of constraint conditions for the mixed-technology bonding pad assignment strategy also fall within the protection scope of the present application.

[0050] The size of the hybrid bonding pad refers to the physical size of the pad for realizing metal-metal direct bonding in the hybrid bonding structure. The pitch of the hybrid bonding pad refers to the distance between the centers of two adjacent bonding copper pads. The maximum density of the hybrid bonding pad refers to the maximum allowed number of hybrid bonding pads per unit area. The threshold constraint of the hybrid bonding pad refers to the maximum allowed number of hybrid bonding pads. The clearance margin of the hybrid bonding pad refers to the minimum distance that needs to be reserved around the hybrid bonding pad without other metal wires, devices or structures.

[0051] In summary, the core particle division method based on the 3D layout device provided by the embodiments of the present application can realize multi-objective optimization according to the spatial correlation of the multi-layer layout plane, the constraint condition and the process difference in the layout and core particle division process, so as to reduce the long-distance wiring across the core particles, realize the collaborative 3D core particle division and hybrid bonding pad allocation of "system-interconnection-physical", reduce the later iteration, and achieve the purpose of taking into account the interlayer wiring, area distribution and core particle process.

[0052] In fact, the 3D layout device based on the present application can not only realize the core particle division or the collaborative core particle division and hybrid bonding pad allocation, but also can only realize the separate hybrid bonding pad allocation. Therefore, the present application also provides Embodiment Two.

[0053] Embodiment Two

[0054] Please refer to Figure 2 which shows a hybrid bonding pad allocation method based on a 3D layout device, the method comprising the following steps:

[0055] P100, acquiring a netlist input by a user, the netlist comprising a plurality of logic units and the connection relationship thereof.

[0056] P300, acquiring a constraint condition specified by a user, the constraint condition being one or more of the size, the pitch, the clearance margin, the maximum density and the threshold of the hybrid bonding pad.

[0057] P500, input the netlist and user-specified constraints into a 3D placer, wherein the 3D placer performs the following operations: iteratively performing multi-objective optimization under the constraints; wherein the optimization objectives in the multi-objective optimization include: wire length driving, timing driving, routability driving, thermal distribution driving, reserved through-silicon via (TSV) and chip area optimization; calculating optimal positions of hybrid bonding pad allocation based on the 3D placement result; wherein the step of hybrid bonding pad allocation includes: optimizing the positions of the target regions in different layout planes associated with each target subsystem according to the specified target subsystems to be aligned in each layout plane and the target regions associated with each target subsystem, so that the overlapping area of the target regions associated with the same target subsystem projected on the same layout plane is maximized; for the target regions associated with the same target subsystem, preferentially configuring the cross-layer hybrid bonding pad pairs based on the overlapping area to obtain a hybrid bonding pad allocation result.

[0058] It should be noted that the related concepts, descriptions of steps and effects in Embodiment One are applicable to Embodiment Two, and will not be repeated.

[0059] Embodiments of the present application also provide a non-transitory computer-readable storage medium, which can be arranged in an electronic device to save at least one instruction or at least one program related to a method in the method embodiments, and the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided by the above embodiments.

[0060] Embodiments of the present application also provide an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0061] Embodiments of the present application also provide a computer program product, which includes program code for causing an electronic device to perform the steps of the methods according to various exemplary embodiments of the present application described above when the program product is run on the electronic device.

[0062] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the above-described functions.

[0063] While certain specific embodiments of the application have been described in detail herein for the purposes of exemplification, numerous other variations and modifications will be apparent to persons skilled in the art. Alterations and modifications of detail can be made by those skilled in the art, having the benefit of the above description, without departing from the spirit and scope of the application. It is intended that all such alterations and modifications be included within the scope of the application whose limits are to be determined only by the appended claims.

Claims

1. A 3D placer based core partitioning method, characterized in that, The method comprises the following steps: S100, acquiring a netlist input by a user, the netlist comprising a plurality of logic units and connection relationships thereof; S300, acquiring a constraint condition specified by the user, the constraint condition being a combination of one or more constraint conditions selected from a layout layer number, a process version of each die candidate, a vertical interconnection mode, a size of a reserved through via, a pitch of the reserved through via, a density of the reserved through via, and a clearance of the reserved through via; S500, inputting the netlist and the constraint condition specified by the user into a 3D placer, wherein the 3D placer performs the following operations: iteratively performing multi-objective optimization under the constraint condition, calculating an optimal position of each logic unit in a plurality of layout planes, and outputting at least one die partitioning result; wherein optimization objectives in the multi-objective optimization comprise: wire length driving, timing driving, routability driving, thermal distribution driving, reserved through via, and total chip area optimization; wherein each die partitioning result comprises an optimization result of multi-objective optimization, a die size of each die, a die in which each partitioned logic unit is located, and a corresponding coarse layout result; The method further comprises: based on the die size of all the dies, a step of mixed bond pad allocation is further included in the process of multi-objective optimization by the iterative algorithm in S500: According to the plurality of target subsystems to be aligned in each layout plane and the plurality of target regions associated with each target subsystem, the positions of the plurality of target regions in different layout planes associated with each target subsystem are optimized, so that the overlapping areas of the plurality of target regions associated with the same target subsystem projected on the same layout plane are maximized; For the plurality of target regions associated with the same target subsystem, a pair of cross-layer mixed bond pads is preferentially configured based on the overlapping areas, to obtain a mixed bond pad allocation result.

2. The method of claim 1, wherein, The method further comprises: S200, preprocessing the netlist, the preprocessing step comprising: inputting the netlist into a set abstraction model, the set abstraction model performing a merging operation on all gate circuit standard cells in the netlist and updating the netlist; wherein the merging operation is to merge a plurality of gate circuit standard cells satisfying a preset condition into one basic abstract cell.

3. The method of claim 1, wherein, The die size of the die is a user-specified die size or an optimal die size generated in the 3D layout process.

4. The method of claim 3, wherein, The step of generating the optimal die size in the 3D layout process comprises: In S100, the constraint condition further comprises a length-width ratio constraint and an area utilization ratio constraint of each die specified by the user; Then S500 further comprises: the 3D placer optimizes the size of each die according to the length-width ratio constraint and the area utilization ratio constraint of each die to obtain the optimal die size.

5. The method of claim 1, wherein, The target subsystem is a voltage domain, and the target region is a power supply region associated with the voltage domain.

6. The method of claim 1, wherein, When performing the mixed bond pad allocation strategy, the constraint condition is one or more of the size, pitch, clearance, maximum density, and threshold value of the mixed bond pad.

7. The method of claim 1, wherein, The 3D placer is a pseudo-3D placer or a true 3D placer.

8. The method of claim 1, wherein, S100, the constraint further comprises: a user-specified position and / or a user-specified layer number of a logic cell group, and / or a user-specified logic cell group to be configured in the same die.

9. The method of claim 1, wherein, The 3D placer supports the same process for all dies; or a respective appropriate process for each layer of the die; or the same process for some layers and different processes for other layers.

10. A 3D placer based hybrid bonding pad assignment method, characterized in that, The method comprises the following steps: P100, obtaining a user-input netlist, the netlist comprising a plurality of logic cells and their connection relationships; P300, obtaining a user-specified constraint, the constraint being one or more of: a size, a pitch, a clearance, a maximum density, and a threshold of a hybrid bonding pad; P500, inputting the netlist and the user-specified constraint into a 3D placer, wherein the 3D placer performs the following operations: iteratively performing multi-objective optimization under the constraint; wherein the optimization objectives in the multi-objective optimization comprise: a wire length drive, a timing drive, a routability drive, a thermal distribution drive, a reserved through-silicon via (TSV) and a total die area optimization; calculating an optimal position of a hybrid bonding pad assignment based on a 3D layout result; wherein the hybrid bonding pad assignment comprises: optimizing positions of a plurality of target regions in different layout planes associated with each target subsystem to be aligned in each layout plane based on the plurality of target subsystems and the plurality of target regions associated with each target subsystem, so as to maximize an overlapping area of the plurality of target regions associated with the same target subsystem projected on the same layout plane; For the plurality of target regions associated with the same target subsystem, a hybrid bonding pad pair across layers is preferentially configured based on the overlapping area to obtain a hybrid bonding pad assignment result.

11. The method of claim 10, wherein, The target subsystem is a voltage domain, and the target region is a power supply region associated with the voltage domain.

12. The method of claim 10, wherein, The 3D placer is a pseudo-3D placer or a true-3D placer.

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