Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a pixel circuit for receiving a light-emitting control signal and a compensation voltage write-in control signal. The first shift register is used for generating a light-emitting control signal and comprises a first pull-up transistor. The second shift register is used for generating a compensation voltage write-in control signal and comprises a second pull-up transistor. And one of the first shift register and the second shift register is located in the first shift register placement area, and the other one is located in the second shift register placement area, so that brightness compensation can be provided for light emitting devices electrically connected with a plurality of pixel circuits close to the first shift register and the second shift register. Moreover, the channel width of the first pull-up transistor is different from the channel width of the second pull-up transistor, so that the channel widths of the first pull-up transistor and the second pull-up transistor can be adaptively set, and the influence difference of the first shift register and the second shift register on the luminance can be balanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] The display panel includes a shift register and a pixel circuit, the shift register can be used to provide a driving signal for the pixel circuit to drive the working of the pixel circuit. Usually, the output end of one shift register is electrically connected with multiple pixel circuits located in the same row. However, due to the reasons such as wiring impedance and signal delay in the driving signal transmission process, the driving signals received by the pixel circuits close to the shift register and the pixel circuits far away from the shift register in the same row are different, which causes the luminance difference of multiple light emitting devices, and is not conducive to improving the display uniformity of the display panel. SUMMARY

[0003] Therefore, the present application provides a display panel and a display device to solve the above problems.

[0004] In a first aspect, an embodiment of the present application provides a display panel, which comprises: a pixel circuit, the pixel circuit comprising a driving transistor, a light emitting control transistor and a compensation voltage writing transistor, the first electrode of the light emitting control transistor being electrically connected with the first electrode of the driving transistor, the second electrode being electrically connected with a light emitting device, and the gate electrode receiving a light emitting control signal; the first electrode of the compensation voltage writing transistor receiving a compensation voltage, the second electrode being electrically connected with the second electrode of the driving transistor, and the gate electrode receiving a compensation voltage writing control signal; a first shift register for generating a light emitting control signal, the first shift register comprising a first gating circuit, the first gating circuit comprising a first pull-up transistor for outputting a light emitting control signal in a high level state; a second shift register for generating a compensation voltage writing control signal, the second shift register comprising a second gating circuit, the second gating circuit comprising a second pull-up transistor for outputting a compensation voltage writing control signal in a high level state; The display panel further comprises a display area, a first shift register placement area and a second shift register placement area, the first shift register placement area and the second shift register placement area are respectively located on the opposite sides of the display area in a first direction; the first direction is a row direction; one of the first shift register and the second shift register is located in the first shift register placement area, and the other is located in the second shift register placement area; The channel width of the first pull-up transistor is different from the channel width of the second pull-up transistor.

[0005] In a second aspect, an embodiment of the present application provides a display device comprising the display panel provided in the first aspect.

[0006] In the embodiments of the present application, the first shift register and the second shift register are respectively arranged on opposite sides of the display area in the first direction. The first shift register and the second shift register can be used to affect the multiple light emitting devices driven by the multiple pixel circuits arranged in the first direction, so that the light emitting devices electrically connected to the multiple pixel circuits close to the first shift register can be compensated by the first shift register, and the light emitting devices electrically connected to the multiple pixel circuits close to the second shift register can be compensated by the second shift register, thereby improving the light emitting brightness uniformity of the multiple light emitting devices. In addition, the channel width of the first pull-up transistor and the channel width of the second pull-up transistor are different, which is conducive to adjusting the influence of the first shift register and the second shift register on the light emitting brightness of the light emitting device by changing the channel width of the transistor, and is conducive to balancing the difference in the influence of the first shift register and the second shift register on the light emitting brightness by adaptively setting the channel width of the first pull-up transistor and the channel width of the second pull-up transistor, thereby further improving the light emitting uniformity of the light emitting device and further improving the display effect of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0008] Figure 1 A plan view of a display panel provided by the present application is provided. Figure 2 A schematic diagram of a pixel circuit provided by the present application is provided. Figure 3 A schematic diagram of a first shift register or the second shift register provided by the present application is provided. Figure 4 A plan view of another display panel provided by the embodiments of the present application is provided. Figure 5 A plan view of another display panel provided by the present application is provided. Figure 6 A plan view of another display panel provided by the present application is provided. Figure 7 A plan view of another display panel provided by the present application is provided. Figure 8 A plan view of another display panel provided by the present application is provided. Figure 9 A schematic diagram of a fourth shift register provided in this application; Figure 10 This is a schematic diagram of a display device provided in this application. Detailed Implementation

[0009] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0010] It should be understood that the described embodiments are merely some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort, including new embodiments obtained by combining the various embodiments mentioned in this application without technical conflict, are within the scope of protection of this application.

[0011] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0012] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0013] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0014] It should be understood that although the terms "first," "second," etc., may be used to describe shift registers, pull-up transistors, control signals, etc., in the embodiments of this application, these should not be limited to these terms. These terms are only used to distinguish shift registers, pull-up transistors, control signals, etc., from each other. For example, without departing from the scope of the embodiments of this application, a first control signal may also be referred to as a second control signal, and similarly, a second control signal may also be referred to as a first control signal. Through meticulous and in-depth research, the applicant of this application provides a solution to the problems existing in the prior art.

[0015] Figure 1 This is a plan view of a display panel provided in this application.Figure 2 This is a schematic diagram of a pixel circuit provided in this application. Figure 3 This is a schematic diagram of a first shift register or a second shift register provided in this application.

[0016] This application provides a display panel 100, such as Figure 1 As shown, the display panel 100 includes a pixel circuit 10, a first shift register 20, and a second shift register 30. Wherein, as... Figure 2 As shown, the pixel circuit 10 includes a driving transistor Md, a light-emitting control transistor M1, and a compensation voltage writing transistor M2. The first terminal of the light-emitting control transistor M1 is electrically connected to the first terminal of the driving transistor Md, the second terminal is electrically connected to the light-emitting device 200, and the gate receives the light-emitting control signal EM. When the light-emitting control signal EM transmits a valid turn-on signal to the light-emitting control transistor M1, the light-emitting control transistor M1 turns on and transmits the light-emitting driving current generated by the driving transistor Md to the light-emitting device 200, causing the light-emitting device 200 to emit light.

[0017] The first terminal of the compensation voltage writing transistor M2 receives the compensation voltage Vdh, its second terminal is electrically connected to the second terminal of the driving transistor Md, and its gate receives the compensation voltage writing control signal SPX. A frame in the display panel 100 includes a writing frame and a sustain frame, with the sustain frame following the writing frame. During the writing frame, the driving transistor Md receives a data voltage Vdata, which is used to control the magnitude of the light-emitting driving current generated by the light-emitting driving transistor Md. In the sustain frame, leakage current exists at the gate of the driving transistor Md, affecting the accuracy of the light-emitting driving current generated by the driving transistor Md. Therefore, the compensation voltage writing transistor M2 is set to turn on after receiving the on control signal transmitted by the compensation voltage writing control signal SPX, so that the gate of the driving transistor Md receives the compensation voltage Vdh, which is used to maintain the stability of the gate potential of the driving transistor Md, thereby improving the stability of the light-emitting driving current output by the driving transistor Md during a single frame.

[0018] like Figure 3As shown, the first shift register 20 can be used to generate a light-emitting control signal EM, which is a signal that switches between high and low levels. The first shift register 20 includes a first gating circuit 201, which includes a first pull-up transistor T1. The first pull-up transistor T1 is used to output the light-emitting control signal EM in a high-level state. The first gating circuit 201 also includes a first pull-down transistor L1. The first pull-up transistor T1 receives a high-level signal VGH, and the first pull-down transistor L1 receives a low-level signal VGL. The first pull-down transistor L1 is used to output the light-emitting control signal EM in a low-level state. The first shift register 20 also includes a first control circuit 202, which is used to control whether the first pull-up transistor T1 or the first pull-down transistor L1 in the first gating circuit 201 is turned on.

[0019] In one frame, the first shift register 20 generates the light emission control signal EM at a relatively high frequency, combined with Figure 2 As can be seen, the light-emitting control transistor M1 is electrically connected to the light-emitting device 200. Therefore, the light-emitting control signal EM, which is electrically connected to the gate of the light-emitting control transistor M1, couples with the first electrode 2001 of the light-emitting device 200 during transitions. Especially when the light-emitting control signal EM is pulled high, it raises the potential of the first electrode 2001 of the light-emitting device 200, thereby increasing the brightness of the light-emitting device 200. This effect is most pronounced when the light-emitting device 200 is displaying at low grayscale. At low grayscale, the light-emitting device 200 requires a smaller light-emitting drive current, making it more difficult to accurately control the magnitude of the light-emitting drive current generated by the drive transistor Md. Therefore, to a certain extent, the light-emitting device 200 emits light by utilizing the effect of the light-emitting control signal EM coupling to raise the potential of the first electrode 2001 of the light-emitting device 200.

[0020] Continue to refer to Figure 3As shown, the second shift register 30 can be used to generate a compensation voltage write control signal SPX. The second shift register 30 includes a second gating circuit 301, which includes a second pull-up transistor T2. The second pull-up transistor T2 is used to output a high-level compensation voltage write control signal SPX. The second gating circuit 301 also includes a second pull-down transistor L2. The second pull-up transistor T2 receives a high-level signal VGH, and the second pull-down transistor L2 receives a low-level signal VGL. The second pull-down transistor L2 is used to output a low-level compensation voltage write control signal SPX. The second shift register 30 also includes a second control circuit 302, which is used to control whether the second pull-up transistor T2 or the second pull-down transistor L2 in the second gating circuit 301 is turned on. It should be noted that the first shift register 20 and the second shift register 30 can be set to have the same circuit structure, but the first shift register 20 and the second shift register 30 are still set as two different circuits in the display panel 100, which are used to output the light emission control signal EM and the compensation voltage write control signal SPX, respectively.

[0021] In this embodiment, we will use a P-type transistor as an example to illustrate the concept. The compensation voltage write transistor M2 is turned off when its gate receives a high-level compensation voltage write control signal SPX, and turned on when its gate receives a low-level compensation voltage write control signal SPX.

[0022] However, research has found that the first shift register 20 is typically placed on one side of the display panel 100. Pixel circuits 10 located in the same row are usually electrically connected to the output of the same first shift register 20, resulting in a control signal line for transmitting the light emission control signal EM. This control signal line is electrically connected to multiple pixel circuits 10 located in the same row. Based on the above, when the light emission control signal EM is pulled high, it couples and raises the first electrode 2001 of the light-emitting device 200, thereby increasing the brightness of the light-emitting device 200. However, for a whole row of pixel circuits 10, the control signal line used to transmit the light emission control signal EM has trace impedance. Therefore, the pixel circuit 10 closer to the first shift register 20 receives a higher level of the light emission control signal EM when it is high, while the pixel circuit 10 farther from the first shift register 20 receives a higher level of the light emission control signal EM when it is high. Furthermore, the rising edge of the light emission control signal EM received by pixel circuits 10 that are farther away from the first shift register 20 will have a certain delay. Considering various factors, this will cause the first electrode 2001 of the light-emitting device 200 electrically connected to the pixel circuit 10 closer to the first shift register 20 to be coupled and raised to a greater extent than the first electrode 2001 of the light-emitting device 200 electrically connected to the pixel circuit 10 farther away from the first shift register 20. Thus, taking the location of the first shift register 20 as a reference, a "near bright, far dark" phenomenon will occur in the row of pixel circuits 10 electrically connected to the first shift register 20. "Near bright, far dark" can be explained as the brightness contribution ratio of the first shift register 20 to the light-emitting device 200 electrically connected to the pixel circuit 10 closer to it being greater than the brightness contribution ratio of the light-emitting device 200 electrically connected to the pixel circuit 10 farther away from it.

[0023] When a first shift register 20, which is electrically connected to multiple pixel circuits 10 in the same row, contributes differently to the brightness of the light-emitting devices 200 at the near and far ends, it will cause the multiple light-emitting devices 200 driven by the pixel circuits 10 in the same row to produce different brightness, thereby causing uneven display on the display panel 100.

[0024] For the second shift register 30, it includes a second pull-up transistor T2. The high-level signal transmitted by the second pull-up transistor T2 is used to control the compensation voltage writing transistor M2 to turn off. The longer the time from turn-on to turn-off of the compensation voltage writing transistor M2, the closer the gate potential of the driving transistor Md is to the target value; the shorter the time from turn-on to turn-off of the compensation voltage writing transistor M2, the further the gate potential of the driving transistor Md is from the target value. The output of the second shift register 30 can be electrically connected to a control signal line, which is simultaneously electrically connected to the gates of the compensation voltage writing transistors M2 of multiple pixel circuits 10. Due to the trace impedance of the control signal line and the certain delay in signal transmission, when the high-level compensation voltage writing control signal SPX is transmitted, the pixel circuit 10 closer to the second shift register 30 receives the control signal to turn off the compensation voltage writing transistor Md first, and the compensation voltage writing transistor M2 turns off and stops compensating the gate voltage of the driving transistor Md. The pixel circuit 10, which is farther away from the second shift register 30, receives the control signal to turn off the compensation voltage writing transistor Md later, and the compensation voltage writing transistor M2 is turned on for a longer time. As a result, the gate compensation voltage time of the driving transistor Md is longer, and the gate potential of the driving transistor Md is raised better.

[0025] Regarding the pattern of the light-emitting driving current generated by the driving transistor Md, taking a P-type transistor as an example, the higher the gate potential of the driving transistor Md, the smaller the light-emitting driving current it generates; the lower the gate potential of the driving transistor Md, the larger the light-emitting driving current it generates.

[0026] Therefore, considering the above-mentioned situation of receiving the compensation voltage writing control signal SPX for the same row of pixel circuits 10: the gate potential of the driving transistor Md in the pixel circuit 10 that is closer to the second shift register 30 is compensated for for a shorter time, resulting in a lower gate potential of the driving transistor Md in the pixel circuit 10 at that position. Consequently, the light-emitting driving current generated by the driving transistor Md in the pixel circuit 10 at that position is larger, resulting in a higher brightness contribution of the second shift register 30 to the light-emitting device 200 electrically connected to the pixel circuit 10 that is closer to it.

[0027] The gate potential of the driving transistor Md in the pixel circuit 10, which is farther away from the second shift register 30, is compensated for for a longer period of time. As a result, the gate potential of the driving transistor Md in the pixel circuit 10 at that location is higher, which in turn results in a smaller light-emitting driving current generated by the driving transistor Md in the pixel circuit 10 at that location. Consequently, the second shift register 30 contributes less to the brightness of the light-emitting device 200 electrically connected to the pixel circuit 10, which is farther away from it.

[0028] Therefore, taking a second shift register 30 as a reference, multiple light-emitting devices 200 driven by the same row of pixel circuits 10 electrically connected to the second shift register 30 also exhibit the phenomenon of "nearer brighter, farther darker". This "nearer brighter, farther darker" can be explained as the second shift register 30 contributing more brightness to the light-emitting devices 200 electrically connected to the pixel circuit 10 closer to it than to the light-emitting devices 200 electrically connected to the pixel circuit 10 farther away.

[0029] When a second shift register 30, which is electrically connected to multiple pixel circuits 10 in the same row, contributes differently to the brightness of the light-emitting devices 200 at the near and far ends, it will cause the multiple light-emitting devices 200 driven by the pixel circuits 10 in the same row to produce different brightness, thereby causing uneven display on the display panel 100.

[0030] In summary, the control signals output by the first shift register 20 and the second shift register 30 contribute approximately the same amount to the brightness of the multiple light-emitting devices 200 electrically connected to the same row of pixel circuits 10, exhibiting a "nearer brighter, farther darker" phenomenon. Considering the influence of the positions of the first shift register 20 and the second shift register 30 on the brightness of the light-emitting devices 200, and the resulting display unevenness, further measures are taken to improve the above-mentioned problems. (Continue to refer to...) Figure 1 As shown, this application proposes that the display panel 100 further includes a display area A1, a first shift register placement area A2, and a second shift register placement area A3. The first shift register placement area A2 and the second shift register placement area A3 are respectively located on opposite sides of the display area A1 in a first direction X1. The first direction X1 is a row direction, and multiple pixel circuits 10 located in the same row are arranged along the first direction X1. One of the first shift register 20 and the second shift register 30 is located in the first shift register 20 placement area, and the other is located in the second shift register 30 placement area. In this embodiment, the example is that the first shift register 20 is placed in the first shift register placement area A2, and the second shift register 30 is placed in the second shift register placement area A3.

[0031] Therefore, for the same row of pixel circuits 10, the multiple pixel circuits 10 near the first shift register placement area A2 are closer to the first shift register 20 and farther from the second shift register 30, while the multiple pixel circuits near the second shift register placement area A3 are closer to the second shift register 30 and farther from the first shift register 20. Thus, considering the brightness contribution ratio of the first shift register 20 and the second shift register 30 to the multiple light-emitting devices 200 electrically connected to the same row of pixel circuits 10, the multiple light-emitting devices 200 electrically connected to the multiple pixel circuits 10 closer to the first shift register 20 can receive a higher brightness contribution ratio from the first shift register 20 and a lower brightness contribution ratio from the second shift register 30, and vice versa. This facilitates a more balanced distribution of the brightness contribution formed by the first shift register 20 and the second shift register 30 among the multiple light-emitting devices 200 in the same row. This helps reduce the risk that some light-emitting devices 200 electrically connected to the pixel circuit 10 in the same row may have an excessively high brightness contribution ratio while others may have an excessively low brightness contribution ratio. Consequently, this improves the uniformity of the light emission brightness of the multiple light-emitting devices 200 driven by the pixel circuit 10 in the same row, and enhances the display uniformity of the display panel 100.

[0032] Furthermore, in this embodiment, an example is given using a circuit where the first shift register 20 and the second shift register 30 have the same structure. This helps to reduce the fabrication difficulty of the first shift register 20 and the second shift register 30. When the circuit structures of the first shift register 20 and the second shift register 30 are the same, it has been found that the effect of the light emission control signal EM generated by the first shift register 20 on the coupling height of the first electrode 2001 of the light emission device 200 on the light emission brightness is greater than the effect of the second shift register 30 on the light emission brightness.

[0033] Therefore, this application further considers that although placing the first shift register 20 and the second shift register 30 on opposite sides of the display area A1 in the first direction X1 improves the uneven brightness of the light emission on the side near the first shift register placement area A2 and the side near the second shift register placement area A3, the impact of the transition of the light emission control signal EM generated by the first shift register 20 on the light emission brightness is greater than the impact of the transition of the compensation voltage control signal SPX generated by the second shift register 30 on the light emission brightness. Therefore, it is further proposed to set the channel width of the first pull-up transistor T1 to be different from the channel width of the second pull-up transistor T2, so as to further improve the uniformity of light emission brightness on the side near the first shift register placement area A2 and the side near the second shift register placement area A3. It should be noted that the channel width of the transistor mentioned in this application refers to the width of the overlapping portion of the active layer and the gate of the transistor.

[0034] The channel width of a transistor has a significant impact on its conduction capability. Generally, increasing the channel width improves the transistor's conduction capability, while decreasing it decreases it. Increasing the channel width of the first pull-up transistor T1 enhances its conduction capability, thereby increasing the rate at which the first shift register 20 outputs the high-level light-emitting control signal EM. This further increases the contribution of the first shift register 20 to the brightness of the light-emitting device 200, especially providing a more significant brightness compensation effect for the light-emitting device 200 driven by the pixel circuit 10 located near the first shift register 20. If the channel width of the first pull-up transistor T1 is reduced, the conduction capability of the first pull-up transistor T1 will be reduced. This will reduce the influence of the first shift register 20 on the light emission brightness of the light-emitting device 200, and reduce the brightness enhancement effect on the light-emitting device 200 driven by the pixel circuit 10 near the first shift register 20. To a certain extent, this can reduce the difference in light emission brightness obtained by the light-emitting device 200 driven by the pixel circuit 10 near and far from the first shift register 20 due to the first shift register 20.

[0035] Increasing the channel width of the second pull-up transistor T2 improves its conduction capability, increasing the rate at which the compensation voltage control signal SPX, which is in a high-level state, is output by the second shift register 30. This further reduces the time it takes for the gate potential of the compensation driving transistor Md in the pixel circuit 10 near the second shift register 30 to be reached, resulting in a more significant brightness compensation effect on the light-emitting device 200 driven by the pixel circuit 10 near the second shift register 30. Conversely, decreasing the channel width of the first pull-up transistor T1 reduces the rate at which the compensation voltage control signal SPX, which is in a high-level state, increases the time it takes for the gate potential of the compensation driving transistor Md in the pixel circuit 10 near the second shift register 30. This further enhances the brightness of the light-emitting device 200 driven by the pixel circuit 10 near the second shift register 30, and to some extent reduces the difference in brightness obtained by the light-emitting device 200 driven by the first shift register 20 between the pixel circuit 10 near and far from the second shift register 30.

[0036] In summary, adjusting the channel width of the first pull-up transistor T1 and the second pull-up transistor T2 can adjust the influence of the first shift register 20 and the second shift register 30 on the brightness of the light-emitting device 200. Therefore, setting the channel widths of the first pull-up transistor T1 and the second pull-up transistor T2 to be different allows for adaptive setting of the channel widths of the first pull-up transistor T1 and the second pull-up transistor T2, thereby further improving the uniformity of light emission from the light-emitting device 200.

[0037] For example, based on the existing design where the channel widths of the first pull-up transistor T1 in the first shift register 20 and the second pull-up transistor T2 in the second shift register 30 are the same, the channel width of the second pull-up transistor T2 in the second shift register 30 is not modified, but the channel width of the first pull-up transistor T1 in the first shift register 20 is reduced. This makes the channel width of the first pull-up transistor T1 in the first shift register 20 located in the first shift register placement area A2 smaller than the channel width of the second pull-up transistor T2 in the second shift register 30 located in the second shift register placement area A3. This reduces the brightness compensation effect of the first shift register 20 on the light-emitting device 200 driven by the pixel circuit 10, which is closer to it, thereby balancing the difference in the influence of the first shift register 20 and the second shift register 30 on the light emission brightness and improving the display uniformity of the light-emitting device 200.

[0038] For example, based on the existing design where the channel widths of the first pull-up transistor T1 in the first shift register 20 and the second pull-up transistor T2 in the second shift register 30 are the same, the channel width of the first pull-up transistor T1 in the first shift register 20 is not modified, while the channel width of the second pull-up transistor T2 in the second shift register 30 is increased. This makes the channel width of the second pull-up transistor T2 in the second shift register 30 located in the second shift register placement area A3 greater than the channel width of the first pull-up transistor T1 in the first shift register placement area A2. This improves the brightness compensation effect of the second shift register 30 on the light-emitting device 200 driven by the pixel circuit 10, which is closer to it, thereby balancing the difference in the influence of the first shift register 20 and the second shift register 30 on the light emission brightness and improving the display uniformity of the light-emitting device 200.

[0039] For example, based on the existing design where the channel widths of the first pull-up transistor T1 in the first shift register 20 and the second pull-up transistor T2 in the second shift register 30 are the same, the channel widths of both the first pull-up transistor T1 in the first shift register 20 and the second pull-up transistor T2 in the second shift register 30 are modified, and the degree of modification can be different. The channel width data of the first pull-up transistor T1 and the second pull-up transistor T2, which have a better effect on improving the brightness uniformity of the light-emitting device 200, are obtained through brightness uniformity testing.

[0040] In this embodiment, the first shift register 20 and the second shift register 30 are respectively placed on opposite sides of the display area A1 in the first direction X1. The first shift register 20 and the second shift register 30 can be used to affect the multiple light-emitting devices 200 driven by the multiple pixel circuits 10 arranged along the first direction X1, which have a "near bright and far dark" effect. This allows the light-emitting devices 200 electrically connected to the multiple pixel circuits 10 near the first shift register placement area A2 to receive a higher brightness compensation effect from the first shift register 20, and the light-emitting devices 200 electrically connected to the multiple pixel circuits 10 near the second shift register placement area A3 to receive a higher brightness compensation effect from the second shift register 30, thereby improving the uniformity of the light emission brightness of the multiple light-emitting devices 200. Furthermore, it is proposed that the channel width of the first pull-up transistor T1 and the channel width of the second pull-up transistor T2 be different. This is beneficial to adjust the influence of the first shift register 20 and the second shift register 30 on the brightness of the light-emitting device 200 by changing the transistor channel width. It is also beneficial to balance the difference in the influence of the first shift register 20 and the second shift register 30 on the brightness by adaptively setting the channel width of the first pull-up transistor T1 and the second pull-up transistor T2, thereby further improving the uniformity of light emission of the light-emitting device 200 and further improving the display effect of the display panel 100.

[0041] Figure 4 This is a plan view of another display panel provided in an embodiment of this application.

[0042] In one embodiment of this application, reference continues to be made to... Figure 2 As shown, the pixel circuit 10 also includes a threshold compensation transistor M3. The first terminal of the threshold compensation transistor M3 is electrically connected to the first terminal of the driving transistor Md, and the second terminal is electrically connected to the gate of the driving transistor Md. The gate receives the threshold compensation control signal S1N. Taking the threshold compensation transistor M3 as an N-type transistor as an example, using an N-type transistor can increase the difficulty of turning on the threshold compensation transistor M3, thereby reducing the risk of leakage current from the first node N1 potential to the threshold compensation transistor M3.

[0043] When threshold compensation transistor M3 receives a high-level threshold compensation control signal S1N, threshold compensation transistor M3 turns on and compensates the threshold voltage of driving transistor Md to the gate of driving transistor Md. It also transmits the compensation voltage Vdh or data voltage Vdata received by the second terminal of driving transistor Md to the gate of driving transistor Md, thereby improving the gate potential stability of driving transistor Md.

[0044] like Figure 4As shown, the display panel 100 also includes a third shift register 40, which is used to generate a threshold compensation control signal S1N. Multiple cascaded third shift registers 40 are electrically connected to pixel circuits 10 in different rows, taking one third shift register 40 electrically connected to pixel circuits 10 in the same row as an example. From the perspective of the effect of the third shift register 40 on the luminous brightness of multiple light-emitting devices 200 electrically connected to the pixel circuits 10 in the same row: a control signal line transmitting the threshold compensation control signal S1N is electrically connected to the output terminal of the third shift register 40, and the control signal line transmits the threshold compensation control signal S1N to the pixel circuits 10 arranged in the first direction X1. Due to the inherent impedance of the control signal lines and the delay during transmission, the threshold compensation control signal S1N experiences a certain delay and a potential drop during its high-level state as it is transmitted. This results in better conduction of the threshold compensation transistor M3 in the pixel circuit 10 closer to the third shift register 40, and poorer conduction of the threshold compensation transistor M3 in the pixel circuit 10 farther from the third shift register 40. Consequently, the gate compensation effect on the driving transistor Md is better in the pixel circuit 10 closer to the third shift register 40, and the gate potential of the driving transistor Md in this location is compensated to be higher, resulting in a lower light-emitting driving current generated by the driving transistor Md. Conversely, the gate compensation effect on the driving transistor Md is poorer in the pixel circuit 10 farther from the third shift register 40, and the gate potential of the driving transistor Md in this location is compensated to be lower, resulting in a higher light-emitting driving current generated by the driving transistor Md.

[0045] In summary, for a single third shift register 40, a "near-dark, far-bright" phenomenon occurs among the multiple light-emitting devices 200 driven by the same row of pixel circuits 10 electrically connected to it. This "near-dark, far-bright" phenomenon can be explained as follows: the brightness contribution of the third shift register 40 to the light-emitting devices 200 electrically connected to the pixel circuit 10 closer to it is less than the brightness contribution to the light-emitting devices 200 electrically connected to the pixel circuit 10 farther away. This is the opposite of the "near-bright, far-dark" phenomenon caused by the first shift register 20 and the second shift register 30 mentioned above.

[0046] In this embodiment, the second shift register 30 and the third shift register 40 are both located in the first shift register placement area A2, and the first shift register 20 is located in the second shift register placement area A3. This will, to some extent, neutralize the difference in luminous intensity caused by the second shift register 30 and the third shift register 40, so that the luminous intensity of the light-emitting devices 200 electrically connected to the pixel circuit 10 is mainly considered in terms of the influence of the first shift register 20. Considering that the second shift register 30 and the third shift register 40 are both located in the first shift register placement area A2, and the first shift register 20 is located in the second shift register placement area A3, there will be instances where, due to the position of the first shift register 20, the luminous intensity of multiple light-emitting devices 200 electrically connected to the pixel circuit 10 closer to the second shift register placement area A3 is higher than that of multiple light-emitting devices 200 electrically connected to the pixel circuit 10 farther from the second shift register placement area A3.

[0047] Furthermore, setting the channel width of the second pull-up transistor T2 to be greater than that of the first pull-up transistor T1 improves the conduction capability of the second pull-up transistor T2, thereby increasing the rate at which the compensation voltage control signal SPX is output at a high level from the second shift register 30. This further reduces the time of the gate potential of the compensation driving transistor Md in the pixel circuit 10 near the second shift register 30, resulting in a more significant brightness compensation effect on the light-emitting device 200 driven by the pixel circuit 10 near the second shift register 30. Based on the existing design where the channel widths of the first pull-up transistor T1 in the first shift register 20 and the second pull-up transistor T2 in the second shift register 30 are the same, the channel width of the first pull-up transistor T1 in the first shift register 20 is not modified, while the channel width of the second pull-up transistor T2 in the second shift register 30 is increased. By making the channel width of the second pull-up transistor T2 of the second shift register 30 located in the first shift register placement area A2 greater than the channel width of the first pull-up transistor T1 of the first shift register 20 located in the second shift register placement area A3, the brightness of the light-emitting device 200 driven by the pixel circuit 10 which is closer to the first shift register placement area A2 can be increased, thereby balancing the difference in the influence of the first shift register 20 on the light emission brightness and improving the display uniformity of the light-emitting device 200.

[0048] Figure 5 A plan view of yet another display panel provided in this application.

[0049] In one embodiment of this application, reference continues to be made to... Figure 2As shown, the pixel circuit 10 also includes a threshold compensation transistor M3. The first terminal of the threshold compensation transistor M3 is electrically connected to the first terminal of the driving transistor Md, and the second terminal is electrically connected to the gate of the driving transistor Md. The gate receives the threshold compensation control signal S1N. Taking the threshold compensation transistor M3 as an N-type transistor as an example, using an N-type transistor can increase the difficulty of turning on the threshold compensation transistor M3, thereby reducing the risk of leakage current from the first node N1 potential to the threshold compensation transistor M3.

[0050] When threshold compensation transistor M3 receives a high-level threshold compensation control signal S1N, threshold compensation transistor M3 turns on and compensates the threshold voltage of driving transistor Md to the gate of driving transistor Md. It also transmits the compensation voltage Vdh or data voltage Vdata received by the second terminal of driving transistor Md to the gate of driving transistor Md, thereby improving the gate potential stability of driving transistor Md.

[0051] like Figure 4 As shown, the display panel 100 also includes a third shift register 40, which is used to generate a threshold compensation control signal S1N. In conjunction with the above embodiments, for a single third shift register 40, multiple light-emitting devices 200 driven by the same row of pixel circuits 10 electrically connected to the third shift register 40 exhibit a "near-dark, far-bright" phenomenon. This "near-dark, far-bright" phenomenon can be interpreted as the third shift register 40 contributing less brightness to the light-emitting devices 200 electrically connected to the closer pixel circuit 10, and less brightness to the light-emitting devices 200 electrically connected to the farther pixel circuit 10. This is the opposite of the "near-bright, far-dark" phenomenon caused by the improved first shift register 20 and second shift register 30.

[0052] Compared to the brightness effects of the second shift register 30 and the second shift register 40 on the light-emitting device 200, the brightness effect of the light-emitting driving signal EM generated by the first shift register 20 on the first electrode 2001 of the light-emitting device 200 is more significant. The contribution ratio of the first shift register 20 to the brightness of the light-emitting device 200 is greater than that of the second shift register 30 and the third shift register 40. Therefore, in this embodiment, it is proposed that the first shift register 20 and the third shift register 40 are both located in the first shift register placement area A2, and the second shift register 30 is located in the second shift register placement area A3. The third shift register 40 and the first shift register 20, which create a "near dark, far bright" effect on the brightness of multiple light-emitting devices 200 electrically connected to the same row of pixel circuits 10, are placed on the same side of the display panel 100. This allows the effect of the third shift register 40 reducing the brightness of the light-emitting devices 200 electrically connected to the nearest pixel circuit 10 to be offset by the effect of the first shift register 20 increasing the brightness of the light-emitting devices 200 electrically connected to the nearest pixel circuit 10. In this way, the light-emitting devices 200 electrically connected to the pixel circuit 10 that are closer to the first shift register placement area A2 will still receive brightness compensation from the first shift register 20, but will not receive excessive brightness compensation. The second shift register 30, located in the second shift register placement area A3, also has a certain brightness compensation effect on the light-emitting devices 200 electrically connected to the pixel circuit 10 that are close to the second shift register placement area A3. This helps to balance the brightness compensation received by multiple light-emitting devices 200 electrically connected to the same row of pixel circuit 10, improve the brightness uniformity of multiple light-emitting devices 200, and improve the display effect of the display panel 100.

[0053] In one embodiment of this application, the channel width of the first pull-up transistor T1 in the first shift register 20 is set to be greater than the channel width of the second pull-up transistor T2 in the second shift register 30, which is beneficial to improving the conduction capability of the first pull-up transistor T1. This increases the rate at which the first shift register 20 outputs the high-level light-emitting control signal EM, further increasing the contribution ratio of the first shift register 20 to the light-emitting brightness of the light-emitting device 200, especially resulting in a more significant brightness compensation effect for the light-emitting device 200 driven by the pixel circuit 10 close to the first shift register 20.

[0054] This approach helps to address the reduced brightness of the light-emitting device 200 driven by the pixel circuit 10 near the first shift register placement area A2 caused by the third shift register 40. It also avoids situations where the brightness compensation effect of the first shift register 20 cannot offset the brightness reduction caused by the third shift register 40, thereby improving the reliability of improving brightness uniformity using the scheme of placing the first shift register 20 and the third shift register 40 in the first shift register placement area A2 and the second shift register 30 in the second shift register placement area A3.

[0055] In one embodiment of this application, reference continues to be made to... Figure 2 As shown, the driving transistor Md and the compensation voltage writing transistor M2 are both P-type transistors, while the threshold compensation transistor M3 is an N-type transistor. This design facilitates the activation of both the driving transistor Md and the compensation voltage writing transistor M2 under low-level driving conditions, reducing the driving difficulty and thus lowering the power consumption of the pixel circuit 10. Since leakage current is prone to occur at the gate of the driving transistor Md, i.e., at the first node N1, setting the threshold compensation transistor M3, which is electrically connected to the first node N1, to be an N-type transistor increases the difficulty of turning on the threshold compensation transistor M3, thereby reducing the risk of leakage current from the first node N1 to the threshold compensation transistor M3 and improving the gate potential stability of the driving transistor Md.

[0056] Figure 6 A plan view of yet another display panel provided in this application.

[0057] In one embodiment of this application, the display area A1 is configured to include a first shift register placement area A2 and a second shift register placement area A3, so that the first shift register 20 and the second shift register 30 can be prepared within the display area A1, which helps to reduce the degree of occupation of the display panel 100 bezel when preparing the shift registers, thereby achieving a narrow bezel.

[0058] For example, a plurality of first shift registers 20 cascaded on the second direction X2 are alternately arranged in the first shift register placement area A2 with a plurality of pixel circuits 10 arranged on the second direction X2, and a plurality of second shift registers 30 cascaded on the second direction X2 are alternately arranged in the second shift register placement area A3 with a plurality of pixel circuits 10 arranged on the second direction X2.

[0059] In one embodiment of this application, reference continues to be made to... Figure 1 As shown, the display panel 100 also includes a border area A4, which at least partially surrounds the display area A1. Light emission from the display panel 100 is achieved in the display area A1.

[0060] In this embodiment, the first shift register placement area A2 and the second shift register placement area A3 are both located in the border area A4, which helps to avoid the first shift register 20 and the second shift register 30 squeezing the space in the display area A1 and reducing the line pressure in the display area A1.

[0061] In one embodiment of this application, reference continues to be made to... Figure 2 As shown, the pixel circuit 10 also includes: The power supply voltage is written to transistor M4. The first terminal of transistor M4 receives the power supply voltage PVDD, the second terminal is electrically connected to the second terminal of driving transistor Md, and the gate is electrically connected to the light-emitting control signal EM. Taking a P-type transistor as an example, the light-emitting control signal EM can simultaneously control both light-emitting control transistor M1 and power supply voltage writing transistor M4. When the light-emitting control signal EM is low, both power supply voltage writing transistor M4 and light-emitting control transistor M1 are turned on. Power supply voltage writing transistor M4 writes the power supply voltage PVDD to the second terminal of driving transistor Md, driving driving transistor Md to turn on and generate a light-emitting driving current. At this time, light-emitting control transistor M1 also turns on and transmits the light-emitting driving current to the first terminal 2001 of light-emitting device 200, causing light-emitting device 200 to emit light.

[0062] The data voltage writing transistor M5 receives the data voltage Vdata at its first terminal, is electrically connected to the second terminal of the driving transistor Md at its second terminal, and receives the first control signal SP at its gate. Taking a P-type transistor as an example, when the first control signal SP is low, the data voltage writing transistor M5 turns on and writes the data voltage Vdata to the second terminal of the driving transistor Md. It should be noted that in one frame of the display panel 100, the pixel circuit 10 first enters the write frame, causing the data voltage writing transistor M5 to transmit the data voltage Vdata. Then, the pixel circuit 10 enters the sustain frame, causing the compensation voltage writing transistor M2 to transmit the compensation voltage Vdh. The compensation voltage Vdh maintains a similar light-emitting driving current in the sustain frame as in the write frame, thereby ensuring the brightness stability of the light-emitting device 200 in one frame.

[0063] The first reset transistor M6 has a first terminal receiving a first reset voltage Vref1, a second terminal electrically connected to the gate of the driving transistor Md, and a gate receiving a second control signal S2N. The first reset transistor M6 is also electrically connected to the first node N1, posing a leakage risk to N1. Therefore, the first reset transistor M6 can be configured as an N-type transistor to increase the difficulty of its conduction, thereby reducing the risk of leakage from N1 to M6. When the second control signal S2N is high, the first reset transistor M65 turns on and transmits the first reset voltage Vref1 to the gate of the driving transistor Md, completing the gate reset of the driving transistor Md.

[0064] The second reset transistor M7 has a first terminal that receives the second reset voltage Vref2, a second terminal that is electrically connected to the first terminal 2001 of the light-emitting device 200, and a gate that receives the compensation voltage write control signal SPX. Taking a P-type transistor as an example, when the compensation voltage write control signal SPX is low, the second reset transistor M7 turns on and transmits the second reset voltage Vref2 to the first terminal 2001 of the light-emitting device 200, thus completing the reset of the first terminal 2001 of the light-emitting device 200.

[0065] Figure 7 This is a plan view of yet another display panel provided in this application. Figure 8 A plan view of yet another display panel provided in this application.

[0066] In one embodiment of this application, such as Figure 7 , Figure 8 As shown, the display panel 100 also includes a fourth shift register 50 and a fifth shift register 60. The fourth shift register 50 can be used to generate a first control signal SP. The fifth shift register 60 can be used to generate a second control signal S2N.

[0067] The display panel 100 also includes a first control signal line SL1, which is used to transmit a first control signal SP and is electrically connected to multiple pixel circuits 10 located in the same row. The first control signal line SL1 is electrically connected to the output terminal of the fourth shift register 50.

[0068] In this embodiment, the fourth shift register 50 includes a first sub-shift register 501 and a second sub-shift register 502. The first sub-shift register 501 is located in the first shift register placement area A2, and the second sub-shift register 502 is located in the second shift register placement area A3. The first control signal SP is used to control whether the data writing transistor M5 is turned on. The data writing transistor M5 is used to transmit data voltage. To reduce the influence of the trace impedance and transmission delay of the first control signal line SL1, a fourth shift register 50 capable of generating the first control signal SP is provided in both the first shift register placement area A2 and the second shift register placement area A3. One end of the first control signal line SL1 near the first shift register placement area A2 is electrically connected to the output terminal of the first sub-shift register 501, and the other end of the first control signal line SL1 near the second shift register placement area A3 is electrically connected to the output terminal of the second sub-shift register 502. That is, in the same row of pixel circuits 10, there are two first control signal lines SL1, one electrically connected to multiple pixel circuits 10 near the first shift register placement area A2, and the other electrically connected to multiple pixel circuits 10 near the second shift register placement area A3. This helps reduce the time and magnitude differences between the pixel circuits 10 near the first shift register placement area A2 and the pixel circuits 10 near the second shift register placement area A3 receiving the first control signal SP, improving the accuracy of the data voltage Vdata received by the pixel circuits 10, and improving the brightness uniformity of the light-emitting device 200 and the display uniformity of the display panel 100.

[0069] In one embodiment of this application, such as Figure 7 As shown, the fifth shift register 60 is located in the second shift register placement area A3. Since the second shift register 30 and the third shift register 40 are both located in the first shift register placement area A2, and the first shift register 20 is located in the second shift register placement area A3, the shift registers in the first shift register placement area A2 include three types: the second shift register 30, the third shift register 40, and the fourth shift register 50. Similarly, the shift registers in the second shift register placement area A3 also include three types: the first shift register 20, the fourth shift register 50, and the fifth shift register 60. This helps to balance the number and types of shift registers in the first shift register placement area A2 and the second shift register placement area A3, improving the circuit regularity of the display panel 100 and increasing the product yield of the display panel 100.

[0070] Or, such as Figure 8As shown, the fifth shift register 60 is located in the second shift register placement area A3. Since the first shift register 20 and the third shift register 40 are both located in the first shift register placement area A2, and the second shift register 30 is located in the second shift register placement area A3, the shift registers in the first shift register placement area A2 include three types: the first shift register 20, the third shift register 40, and the fourth shift register 50. Similarly, the shift registers in the second shift register placement area A3 also include three types: the second shift register 30, the fourth shift register 50, and the fifth shift register 60. This helps to balance the number and types of shift registers in the first shift register placement area A2 and the second shift register placement area A3, improving the circuit regularity of the display panel 100 and increasing the product yield of the display panel 100.

[0071] Figure 9 A schematic diagram of a fourth shift register provided in this application.

[0072] In one embodiment of this application, such as Figure 9 As shown, the fourth shift register 50 includes a third gating circuit 501, which includes a third pull-up transistor T3 and a first output transistor T4. The first terminal of the third pull-up transistor T3 receives a high-level signal VGH, and its second terminal is electrically connected to the output terminal of the fourth shift register 50. The first terminal of the first output transistor T4 receives a first clock signal XCK, and its second terminal is electrically connected to the output terminal of the fourth shift register 50. Exemplarily, the fourth shift register 50 also includes a third control circuit 502, which controls whether the third pull-up transistor T3 and the first output transistor T4 are turned on. The first clock signal XCK is a signal that switches between high and low levels. The fourth shift register 50 also receives a second clock signal CK, which is a signal with the same period and opposite potentials. A start signal STV is used to control whether the fourth shift register 50 starts working. When the first clock signal XCK transmits a high-level signal, the second clock signal CK transmits a low-level signal, causing the gate potential of the first output transistor T4 to be pulled low. The first output transistor T4 turns on and outputs the high-level state of the first clock signal XCK to the output terminal of the fourth shift register 50. At the same time, the gate of the third pull-up transistor T3 is also pulled low, causing the output high-level signal VGH to be output to the output terminal of the fourth shift register 50. This ensures the stability of the high-level signal output by the fourth shift register 50 and ensures the reliable shutdown of the first control signal SP controlling the data writing transistor M.

[0073] When the first clock signal XCK transmits a low-level signal, the second clock signal CK transmits a high-level signal. The transistors in the fourth shift register 50 controlled by the second clock signal CK remain off. The first capacitor C1 in the fourth shift register 50 is electrically connected to the second terminal and gate of the first output transistor T4. The first capacitor C1 stabilizes the gate potential of the first output transistor T4, thus keeping the gate of the first output transistor T4 pulled low. The first output transistor T4 then turns on and outputs the low-level state of the first clock signal XCK to the output terminal of the fourth shift register 50. From the above analysis of the operation of the fourth shift register 50, it can be concluded that the first output transistor T4 acts as the first control signal SP for outputting the high-level and low-level states of the fourth shift register 50, while the third pull-up transistor T3 outputs a high-level signal VGH to maintain the high-level state of the first control signal SP. Therefore, changing the channel width of the third pull-up transistor T3 has little impact on the circuit operation of the fourth shift register 50.

[0074] Continue to refer to Figure 7 As shown, the second shift register 30 is located in the second shift register placement area A3. Furthermore, if the channel width of the second pull-up transistor T2 of the second shift register 30, located in the first shift register placement area A2, is large, it will increase the space occupied by the second pull-up transistor T2 in the first shift register placement area A2. Therefore, it is easy to result in a high degree of space congestion in the first shift register placement area A2. (Continue to refer to...) Figure 8 As shown, the first shift register 20 is located in the first shift register placement area A2. Furthermore, when the channel width of the first pull-up transistor T1 of the first shift register 20 located in the first shift register placement area A2 is large, it is also easy to create a situation where the space in the first shift register placement area A2 is highly congested.

[0075] In shift registers, the two output transistors electrically connected to the shift register's output are typically made relatively large. For example, the channel widths of the first pull-up transistor T1, the first pull-down transistor L1, the second pull-up transistor T2, the second pull-down transistor L2, the third pull-up transistor T3, and the first output transistor T4 are significantly larger than the channel widths of other transistors in the shift register that are not directly electrically connected to the shift register's output. This improves the transistors' conduction capability, thereby enhancing the stability of the shift register's high-level or low-level control signals. Therefore, when it comes to improving the space occupied by the shift register, adjusting the channel width of the output transistors offers the best cost-effectiveness and produces the most significant effect. Thus, the size of some output transistors with less impact can be appropriately reduced to alleviate space constraints in the first shift register placement area A2.

[0076] In this embodiment, the channel width of the third pull-up transistor T3 in the first sub-shift register 501 located in the first shift register placement area A2 is set to be smaller than the channel width of the third pull-up transistor T3 in the second sub-shift register 502. This helps to reduce the space occupied by the third pull-up transistor T3 in the first shift register placement area A2, and to a certain extent, relieves the space pressure caused by the increased channel width of the second pull-up transistor T2 or the first pull-up transistor T1, thus reducing the circuit fabrication pressure of the first shift register placement area A2.

[0077] In one embodiment of this application, reference continues to be made to... Figure 2 As shown, the pixel circuit 10 also includes a threshold compensation transistor M3. The first terminal of the threshold compensation transistor M3 is electrically connected to the first terminal of the driving transistor Md, and the second terminal is electrically connected to the gate of the driving transistor Md. The gate receives the threshold compensation control signal S1N. Taking the threshold compensation transistor M3 as an N-type transistor as an example, using an N-type transistor can increase the difficulty of turning on the threshold compensation transistor M3, thereby reducing the risk of leakage current from the first node N1 potential to the threshold compensation transistor M3.

[0078] When threshold compensation transistor M3 receives a high-level threshold compensation control signal S1N, threshold compensation transistor M3 turns on and compensates the threshold voltage of driving transistor Md to the gate of driving transistor Md. It also transmits the compensation voltage Vdh or data voltage Vdata received by the second terminal of driving transistor Md to the gate of driving transistor Md, thereby improving the gate potential stability of driving transistor Md.

[0079] Continue to refer to Figure 4 As shown, the display panel 100 also includes a third shift register 40, which is used to generate a threshold compensation control signal S1N. In conjunction with the above embodiments, for a single third shift register 40, multiple light-emitting devices 200 driven by the same row of pixel circuits 10 electrically connected to the third shift register 40 exhibit a "near-dark, far-bright" phenomenon. This "near-dark, far-bright" phenomenon can be interpreted as the third shift register 40 contributing less brightness to the light-emitting devices 200 electrically connected to the closer pixel circuit 10, and less brightness to the light-emitting devices 200 electrically connected to the farther pixel circuit 10. This is the opposite of the "near-bright, far-dark" phenomenon caused by the improved first shift register 20 and second shift register 30.

[0080] Compared to the influence of the second shift register 30 and the second shift register 40 on the brightness of the light-emitting device 200, the influence of the light-emitting driving signal EM generated by the first shift register 20 on the brightness of the light-emitting device 200, resulting in a higher coupling height at the first electrode 2001 of the light-emitting device 200, is more significant. The contribution ratio of the first shift register 20 to the brightness of the light-emitting device 200 is greater than that of the second shift register 30 and the third shift register 40.

[0081] Therefore, in the embodiments of this application, such as Figure 4 As shown, both the second shift register 30 and the third shift register 40 are located in the first shift register placement area A2. For multiple light-emitting devices 200 driven by the same row of pixel circuits 10, the "near bright, far dark" effect brought by the second shift register 30 and the "near dark, far bright" effect brought by the third shift register 40 are somewhat offset, thus reducing the degree of change in the brightness of the light-emitting devices 200. Furthermore, the first shift register 20 is located in the second shift register placement area A3, reducing the channel width of the first pull-up transistor T1. For example, based on the existing design where the channel widths of the first pull-up transistor T1 in the first shift register 20 and the second pull-up transistor T2 in the second shift register 30 are the same, the channel width of the second pull-up transistor T2 in the second shift register 30 is not modified, but the channel width of the first pull-up transistor T1 in the first shift register 20 is reduced. This design ensures that the channel width of the first pull-up transistor T1 in the first shift register 20 located in the second shift register placement area A3 is smaller than the channel width of the second pull-up transistor T2 in the second shift register 30 located in the first shift register placement area A2. This helps to reduce the impact of the first shift register 20 on the brightness of the light-emitting device 200, and reduces the brightness boost effect on the light-emitting device 200 driven by the pixel circuit 10 near the first shift register 20. To a certain extent, it can reduce the difference in brightness impact between the light-emitting devices 200 driven by the pixel circuit 10 near and far from the first shift register 20 due to the first shift register 20, thereby improving the display uniformity of the display panel 100.

[0082] Figure 10 This is a schematic diagram of a display device provided in this application.

[0083] This application provides a display device 300, such as... Figure 10 As shown, the display device 300 includes the display panel 100 as provided in the above embodiment. Optionally, the display device 300 is a device for display such as a computer, television, or mobile phone.

[0084] In the display device 300, the first shift register 20 and the second shift register 30 are respectively placed on opposite sides of the display area A1 in the first direction X1. The first shift register 20 and the second shift register 30 can be used to affect the multiple light-emitting devices 200 driven by the multiple pixel circuits 10 arranged along the first direction X1, which are "brighter near and darker far". This allows the light-emitting devices 200 electrically connected to the multiple pixel circuits 10 near the first shift register placement area A2 to receive a higher brightness compensation effect from the first shift register 20, and the light-emitting devices 200 electrically connected to the multiple pixel circuits 10 near the second shift register placement area A3 to receive a higher brightness compensation effect from the second shift register 30, thereby improving the uniformity of the light emission brightness of the multiple light-emitting devices 200. Furthermore, it is proposed that the channel width of the first pull-up transistor T1 and the channel width of the second pull-up transistor T2 be different. This is beneficial to adjust the influence of the first shift register 20 and the second shift register 30 on the brightness of the light-emitting device 200 by changing the transistor channel width. It is also beneficial to balance the difference in the influence of the first shift register 20 and the second shift register 30 on the brightness by adaptively setting the channel width of the first pull-up transistor T1 and the second pull-up transistor T2, thereby further improving the uniformity of light emission of the light-emitting device 200 and further improving the display effect of the display panel 100.

[0085] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: A pixel circuit includes a driving transistor, a light-emitting control transistor, and a compensation voltage writing transistor. The first terminal of the light-emitting control transistor is electrically connected to the first terminal of the driving transistor, the second terminal is electrically connected to the light-emitting device, and the gate receives a light-emitting control signal. The first terminal of the compensation voltage writing transistor receives a compensation voltage, the second terminal is electrically connected to the second terminal of the driving transistor, and the gate receives a compensation voltage writing control signal. A first shift register is used to generate a light-emitting control signal. The first shift register includes a first gating circuit, which includes a first pull-up transistor. The first pull-up transistor is used to output a light-emitting control signal in a high-level state. The second shift register is used to generate a compensation voltage write control signal. The second shift register includes a second gating circuit, which includes a second pull-up transistor. The second pull-up transistor is used to output a high-level compensation voltage write control signal. The display panel further includes a display area, a first shift register placement area, and a second shift register placement area. The first shift register placement area and the second shift register placement area are respectively located on opposite sides of the display area in a first direction; the first direction is the row direction; one of the first shift register and the second shift register is located in the first shift register placement area, and the other is located in the second shift register placement area. The channel width of the first pull-up transistor is different from that of the second pull-up transistor.

2. The display panel according to claim 1, characterized in that, The pixel circuit further includes a threshold compensation transistor, wherein the first terminal of the threshold compensation transistor is electrically connected to the first terminal of the driving transistor, the second terminal is electrically connected to the gate of the driving transistor, and the gate receives a threshold compensation control signal. The display panel also includes a third shift register for generating a threshold compensation control signal; The second shift register and the third shift register are both located in the first shift register placement area, and the first shift register is located in the second shift register placement area; the channel width of the second pull-up transistor is greater than the channel width of the first pull-up transistor.

3. The display panel according to claim 1, characterized in that, The pixel circuit further includes a threshold compensation transistor, wherein the first terminal of the threshold compensation transistor is electrically connected to the first terminal of the driving transistor, the second terminal is electrically connected to the gate of the driving transistor, and the gate receives a threshold compensation control signal. The display panel also includes a third shift register for generating a threshold compensation control signal; The first shift register and the third shift register are both located in the first shift register placement area, and the second shift register is located in the second shift register placement area.

4. The display panel according to claim 3, characterized in that, The channel width of the first pull-up transistor is greater than the channel width of the second pull-up transistor.

5. The display panel according to claim 2 or 3, characterized in that, The driving transistor and the compensation voltage writing transistor are both P-type transistors, and the threshold compensation transistor is an N-type transistor.

6. The display panel according to claim 1, characterized in that, The display area includes the first shift register placement area and the second shift register placement area.

7. The display panel according to claim 1, characterized in that, The display panel further includes a border area, which at least partially surrounds the display area; Both the first shift register placement area and the second shift register placement area are located within the border area.

8. The display panel according to claim 2 or 4, characterized in that, The pixel circuit also includes: A power supply voltage writing transistor is used, wherein the first terminal of the power supply voltage writing transistor receives the power supply voltage, the second terminal is electrically connected to the second terminal of the driving transistor, and the gate is electrically connected to the light emission control signal. A data voltage writing transistor is used, wherein the first terminal of the data voltage writing transistor receives a data voltage, the second terminal is electrically connected to the second terminal of the driving transistor, and the gate receives a first control signal. The first reset transistor has a first terminal receiving a first reset voltage, a second terminal electrically connected to the gate of the driving transistor, and a gate receiving a second control signal. The second reset transistor has a first terminal that receives a second reset voltage, a second terminal that is electrically connected to the first terminal of the light-emitting device, and a gate that receives a compensation voltage write control signal.

9. The display panel according to claim 8, characterized in that, The display panel also includes: The fourth shift register is used to generate the first control signal; The fifth shift register is used to generate the second control signal; The display panel further includes a first control signal line, which is used to transmit the first control signal and is electrically connected to a plurality of pixel circuits located in the same row; the fourth shift register includes a first sub-shift register and a second sub-shift register, wherein the first sub-shift register is located in the first shift register placement area and the second sub-shift register is located in the second shift register placement area; The end of the first control signal line near the first shift register placement area is electrically connected to the output terminal of the first sub-shift register, and the end of the first control signal line near the second shift register placement area is electrically connected to the output terminal of the second sub-shift register.

10. The display panel according to claim 9, characterized in that, The fifth shift register is located in the second shift register placement area.

11. The display panel according to claim 9, characterized in that, The fourth shift register includes a third gating circuit, which includes a third pull-up transistor and a first output transistor. The first terminal of the third pull-up transistor receives a high-level signal, and the second terminal is electrically connected to the output terminal of the fourth shift register. The first terminal of the first output transistor receives a first clock signal, and the second terminal is electrically connected to the output terminal of the fourth shift register. Wherein, the channel width of the third pull-up transistor in the first sub-shift register is smaller than the channel width of the third pull-up transistor in the second sub-shift register.

12. The display panel according to claim 1, characterized in that, The pixel circuit further includes a threshold compensation transistor, wherein the first terminal of the threshold compensation transistor is electrically connected to the first terminal of the driving transistor, the second terminal is electrically connected to the gate of the driving transistor, and the gate receives a threshold compensation control signal. The display panel also includes a third shift register for generating a threshold compensation control signal; The second shift register and the third shift register are both located in the first shift register placement area, and the first shift register is located in the second shift register placement area, thereby reducing the channel width of the first pull-up transistor.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

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