Same-screen circuit, method, chip and equipment

Abstract

The invention relates to the technical field of chip design, and provides a same-screen circuit, method, chip and equipment, the circuit is applied to an FPGA, the circuit comprises a pixel processing module, an image optimization module and an input port group, and the pixel processing module comprises an acquisition unit and a processing unit; the input port group is used for receiving multiple paths of first original image signals; the acquisition unit is used for sampling multiple paths of first original image signals to obtain multiple paths of first image data; the image optimization module is used for scaling the multiple paths of first image data to obtain multiple paths of first scaled image data; and the processing unit is used for integrating the multiple paths of first zoomed image data into one path of same-screen image data. According to the input device and the display device, the resolution compatibility between the input device and the display device can be improved, and different requirements of different scenes on the number of input ports are met, so that tape-out customization for specific requirements does not need to be carried out like a traditional ASIC (Application Specific Integrated Circuit) chip, and better adaptability and lower development cost are achieved.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and in particular to a screen-on-screen circuit, method, chip, and device. Background Technology

[0002] Screen mirroring circuits typically use one or more ASIC (Application-Specific Integrated Circuit) chips to display multimedia content from multiple different input devices on another screen. In other words, they aggregate multiple inputs into a single output to achieve screen mirroring.

[0003] Currently, the design of screen mirroring circuits often encounters compatibility issues. These compatibility issues are mainly reflected in the following aspects: First, resolution incompatibility, for example, the resolution of the input source is incompatible with the resolution of the display device; Second, the number of interfaces in the screen mirroring circuit is fixed, and the same circuit cannot be compatible with the different requirements of the number of input ports in different scenarios.

[0004] To solve the above compatibility issues, it is often necessary to redesign different chip circuits. However, since ASIC chips are custom chips, once the number of input ports and resolution are determined, any changes to the circuit require re-fabrication. This makes it impossible to modify the existing screen-sharing circuit design in a timely manner, resulting in poor adaptability and high development costs. Summary of the Invention

[0005] This application provides a screen-sharing circuit, method, chip, and device to solve the problems of poor compatibility of existing screen-sharing circuits, which leads to poor adaptability and high development costs.

[0006] In a first aspect, this application provides a screen-sharing circuit for use in an FPGA, including a pixel processing module, an image optimization module, and an input port group, wherein the pixel processing module includes a data acquisition unit and a processing unit; The input port group is used to receive multiple first raw image signals; The acquisition unit is used to sample the multiple first original image signals to obtain multiple first image data; The image optimization module is used to scale the multiple first image data to obtain multiple scaled first image data. The processing unit is used to integrate the multiple first-scaled image data into a single on-screen image data.

[0007] In one embodiment, it further includes a first interface standard conversion module; the input terminal of the first interface standard conversion module is connected to some or all of the ports in the input port group, and the output terminal of the first interface standard conversion module is connected to the acquisition unit; The input port group is also used to receive multiple second raw image signals; The first interface standard conversion module is used to convert the multiple second original image signals into the multiple first original image signals.

[0008] In one embodiment, the acquisition unit is specifically used to acquire the multiple first original image signals according to a preset row length and a preset field length to obtain the multiple first image data. The image optimization module is specifically used to reduce the pixel size of each image data of the multiple first image data to a preset pixel size to obtain the multiple first scaled image data.

[0009] In one embodiment, the image optimization module is specifically used to interpolate the pixels of each image data in the multiple first image data using a bilinear interpolation algorithm to obtain the multiple first scaled image data.

[0010] In one embodiment, a storage module is also included; The storage module is connected to the image optimization module and is used to store the multi-channel first scaled image data output by the image optimization module; The storage module is also connected to the processing unit and is used to transmit the multiple first scaled image data to the processing unit. The processing unit is specifically used to integrate the row length and field length of the multiple first scaled image data to obtain the single-channel on-screen image data with the target resolution.

[0011] In one embodiment, it further includes an output port group and a second interface standard conversion module; the input of the second interface standard conversion module is connected to the output of the processing unit, and the output of the second interface standard conversion module is connected to the output port group. The output port group is used to receive the same channel of screen-on image data; or Used to receive second standard interface data, which is the data after the second interface standard conversion module converts the one-channel screen-sharing image data.

[0012] In one embodiment, an EDID module is further included; the EDID module is connected to the pixel processing module. The EDID module is used to read the resolution of the display device and output it to the pixel processing module, so that the pixel processing module adjusts the resolution of the same-screen image data according to the resolution of the display device; and / or The target resolution is used to read the target resolution of the simultaneous image data and output the target resolution to the display device so that the display device can display the signal according to the target resolution.

[0013] Secondly, this application provides a method for simultaneous display on the same screen, applied to an FPGA, comprising: Receive multiple channels of the first raw image signal; The multiple first original image signals are sampled to obtain multiple first image data; The multi-channel first image data is scaled to obtain multi-channel scaled first image data; The multiple first-scaled image data are integrated into a single on-screen image data.

[0014] Thirdly, this application provides a screen mirroring chip, including the screen mirroring circuit described in the first aspect.

[0015] Fourthly, this application provides a screen mirroring device, including the screen mirroring chip described in the third aspect.

[0016] The screen-sharing circuit, method, chip, and device provided in this application are applied to FPGA (Field-Programmable Gate Array). They include a pixel processing module, an image optimization module, and an input port group. The pixel processing module includes a data acquisition unit and a processing unit. The input port group receives multiple first raw image signals. The data acquisition unit samples the multiple first raw image signals to obtain multiple first image data. The image optimization module scales the multiple first image data to obtain multiple scaled first image data. The processing unit integrates the scaled first image data into a single screen-sharing image data. In this application, on the one hand, by scaling the received image data, the resolution of raw image data at different resolutions can be flexibly adjusted, allowing the resolution of the input source to flexibly adapt to the resolution of the display device, improving the resolution compatibility between the input device and the display device. On the other hand, by setting up an input port group, the number of ports within the group can be expanded or deactivated as needed, thus accommodating different requirements for the number of input ports in different scenarios. In summary, this application can improve the resolution compatibility between input devices and display devices, and is compatible with different requirements for the number of input ports in different scenarios. Therefore, unlike traditional ASIC chips, it does not require customized tape-out for specific needs, and has better adaptability and lower development costs. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the screen-sharing circuit provided in this application.

[0019] Figure 2 This is a flowchart illustrating the screen-sharing method provided in this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0022] In the description of this application, the terms "first," "second," etc., are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, in the description of this application, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects have an "or" relationship.

[0023] Figure 1 This is a schematic diagram of the screen-sharing circuit provided in this application; see reference. Figure 1The screen-sharing circuit is applied to an FPGA and includes a pixel processing module, an image optimization module, and an input port group. The pixel processing module includes an acquisition unit and a processing unit. The input port group is used to receive multiple first raw image signals; The acquisition unit is used to sample multiple channels of first raw image signals to obtain multiple channels of first image data; The image optimization module is used to scale multiple first image data to obtain multiple scaled first image data. The processing unit is used to integrate multiple first-scaled image data into one on-screen image data.

[0024] The input port group includes at least two input ports. Each input port receives one first raw image signal output from an input source, so at least two first raw signals can be received. The acquisition unit samples each channel of the first original image signal to obtain the first image data corresponding to each channel of the first original image signal; The image optimization module performs scaling processing on each channel of first image data to adapt the resolution of each channel of first image data to the resolution of the display device, thereby obtaining the first scaled image data corresponding to each channel of first image data.

[0025] After the processing unit integrates multiple first-scaled image data into one simultaneous image data, it can realize the synchronous display of multiple inputs on the same display device; wherein, the number of pixels of the simultaneous image data is equal to the number of pixels of any one first original image signal.

[0026] This embodiment, implemented using an FPGA, leverages the reprogrammable nature of the FPGA to sample the first original image signal at a preset scale and scale multiple first image data streams to a preset size. This allows it to receive any number of original image signals with uncommon resolutions, process them into signals of common resolutions, and then integrate them to obtain a single on-screen image data stream output to the display device. For example, for 1080p... 840, 1080 Raw image signals with uncommon resolutions like 960 are converted into on-screen image data with the target resolution to ensure compatibility with display device resolutions. For example, the target resolution could be 1080. It can accept common resolutions like 720; it can also receive raw image signals at any number of common resolutions, process them to a less common resolution, and output them in one channel, such as 1080. The original image signal with a common resolution like 720 is processed to a resolution of 1080. 840, 1080 It can output image data on the same screen at resolutions such as 960 that are not common. As for the input port group, the number of ports can be increased or decreased to improve the adaptability of the number of input ports in different scenarios.

[0027] It should be noted that applying the screen mirroring circuit to an FPGA means that the screen mirroring circuit is implemented through an FPGA board. Furthermore, since video is composed of multiple frames of images, the image signal processing method in this embodiment is also applicable to video signals. That is, this embodiment can process multiple image signals to output one screen mirroring image data, and it can also process multiple video signals to output one screen mirroring video data; see reference. Figure 1 This means that after processing four image signals, one output is a single image data stream on the same screen, or after processing four video signals, one output is a single video data stream on the same screen. Similarly, this embodiment is also suitable for displaying multiple images on the same screen.

[0028] The screen mirroring circuit provided in this embodiment is applied to an FPGA and includes a pixel processing module, an image optimization module, and an input port group. The pixel processing module includes a acquisition unit and a processing unit. The input port group is used to receive multiple first original image signals. The acquisition unit is used to sample the multiple first original image signals to obtain multiple first image data. The image optimization module is used to scale the multiple first image data to obtain multiple first scaled image data. The processing unit is used to integrate the multiple first scaled image data into one screen mirroring image data. In this embodiment, on the one hand, by scaling the received image data, distortion of subsequent screen mirroring image data can be avoided, protecting image quality. On the other hand, through the cooperation of the image optimization module and the pixel processing module, the resolution of original image data with different resolutions can be flexibly adjusted, so that the resolution of the input source can be flexibly adapted to the resolution of the display device, improving the resolution compatibility between the input device and the display device. Furthermore, by setting the input port group, the number of ports in the group can be expanded or deactivated as needed, thereby being compatible with different requirements for the number of input ports in different scenarios. In summary, this embodiment can improve the resolution compatibility between input devices and display devices, and is compatible with different requirements for the number of input ports in different scenarios. Therefore, unlike traditional ASIC chips, it does not require customized tape-out for specific needs, and has better adaptability and lower development costs.

[0029] Reference Figure 1 In one embodiment, the screen mirroring circuit further includes a first interface standard conversion module; the input terminal of the first interface standard conversion module is connected to some or all of the ports in the input port group, and the output terminal of the first interface standard conversion module is connected to the acquisition unit. The input port group is also used to receive multiple second raw image signals; The first interface standard conversion module is used to convert multiple second raw image signals into multiple first raw image signals.

[0030] Since the original image signal output from the input source may not necessarily be an image signal conforming to the same interface standard, in order to facilitate the subsequent processing unit in the pixel processing module to integrate and process the data to obtain the same-screen image data in the preset data format, it is necessary to convert the signal type of the original image signal output from the input source to a signal type that the pixel processing module can process when the signal type is inconsistent with the signal type that the pixel processing module can process.

[0031] In this embodiment, the pixel processing module can be a VGA (Video Graphics Array) pixel processing module. The signal type that the pixel processing module can process is VGA. If the received original image signal is not a VGA signal, then the signal type of the original image signal needs to be converted to a VGA signal.

[0032] Furthermore, if the signal type of the first original image signal is VGA, its corresponding receiving interface is a VGA interface, and the signal type of the second original image signal is HDIM (High Definition Multimedia Interface) signal, its corresponding receiving interface is HDIM. In this case, the signal type of the second original image signal needs to be converted to the signal type corresponding to the first original image signal before the second original image signal can be processed by the VGA pixel processing module. This conversion process is performed by the first interface standard conversion module, which is the HDIM to VGA module.

[0033] In this embodiment, the circuit is equipped with a first interface standard conversion module, which enables the circuit to adapt to the original image signals of different interface standards output by the input source, thereby improving the circuit's compatibility in terms of input signal types. This allows the screen-sharing circuit to adapt to original image signals of various signal types and realize the simultaneous display of multiple different original signals.

[0034] Reference Figure 1 In one embodiment, the acquisition unit is specifically used to acquire multiple first original image signals according to a preset row length and a preset field length to obtain multiple first image data; The image optimization module is specifically used to reduce the pixel size of each image data of the multiple first image data to a preset pixel size, thereby obtaining multiple first scaled image data.

[0035] The preset row length and preset field length are obtained based on FPGA programming. That is, given the target resolution of the display device, the row length and field length can be set based on the target resolution. The row length and field length correspond to the resolution size. Then, each channel of the first original image signal can be acquired according to the set row length and field length to obtain the corresponding first image data. Each first image data has the same resolution as the display device, which facilitates the subsequent acquisition of screen image data with the same resolution as the target resolution. It should be noted that, in 1080p... For a 720p resolution image, its row length is the number of effective pixels in its row, which is 1080 pixels, and its field length is the number of effective pixels in its column, which is 720 pixels; with 1080p... For a 720 resolution video, the line length is the number of clock cycles corresponding to the row pixels, that is, the effective number of rows is 1080 clock cycles. The field length is the number of clock cycles corresponding to the column pixels, that is, the effective duration of the field is 720 clock cycles. The line corresponds to the video line rate, and the field corresponds to the video frame rate.

[0036] Furthermore, for multiple channels of first image data, since they need to be displayed simultaneously on the target display device, each channel of image data also needs to be scaled, such as... Figure 1 As shown, for four input sources and one output source, the total number of pixels in each first image data stream needs to be reduced to 1 / 4 of its original size. For example, if the total number of pixels in the first image data is 1080... When there are 720, reduce them to 1 / 4 of their size, which is 540. 360, where the total number of pixels can be reduced in any way, without limitation. In this embodiment, points can be selected by alternating rows and columns. For example, half of the pixels in a row can be selected by selecting one pixel every other row, and half of the pixels in a column can be selected by selecting one pixel every other column. The total number of pixels is then 1 / 4 of the previous amount.

[0037] In this embodiment, the acquisition unit first samples multiple first original image signals according to the resolution of the display device to obtain multiple first image data with the same resolution as the display device. Then, each multiple first image data is scaled proportionally so that it can still meet the resolution requirements of the display device when integrated later, thereby realizing the same-screen display on the display device.

[0038] Reference Figure 1 In one embodiment, the image optimization module is specifically used to interpolate the pixels of each image data in the multiple first image data using a bilinear interpolation algorithm to obtain multiple first scaled image data.

[0039] For each channel of first image data, while reducing its size, it is also necessary to preserve the image quality as much as possible and avoid image distortion. Therefore, a bilinear interpolation algorithm can be used to reduce the size of each channel of first image data. This algorithm is also known as bilinear interpolation. Mathematically, bilinear interpolation is a linear interpolation extension of the interpolation function of two variables. Its core idea is to perform linear interpolation in the x-direction and y-direction of (x,y) respectively. Its specific application in this embodiment is as follows: The RGB values ​​R, G, and B represent the color depth of red, green, and blue, respectively. Taking a 24-bit wide RGB signal as an example, each color in R, G, and B is represented by an 8-bit width. For instance, when the R value of a pixel is 8'b1111_1111, the G value is 8'b0000_0000, and the B value is 8'b0000_0000, the color of that pixel is the reddest. Since the color depth of red, green, and blue can be described by the numerical value of a pixel, the average of the RGB values ​​of a pixel and its surrounding pixels can be taken as the RGB value of that pixel. For example, the average of the R values ​​of the pixel and its eight surrounding pixels can be taken as the R value of that pixel, the average of the G values ​​of the pixel and its eight surrounding pixels can be taken as the G value of that pixel, and the average of the B values ​​of the pixel and its eight surrounding pixels can be taken as the B value of that pixel. This ensures that the RGB value of the pixel will not deviate significantly from that of the surrounding pixels after being scaled down, thereby eliminating the feeling of image fragmentation and minimizing the distortion of image quality after image scaling.

[0040] By performing the above operations on each pixel in the first image data stream, the corresponding first scaled image data can be obtained.

[0041] This embodiment uses the principle of bilinear interpolation to regenerate an image with smoother pixel values ​​than the original image. Visually, this allows the image to retain the quality of the original image to the maximum extent even after being reduced in size.

[0042] Reference Figure 1 In one embodiment, a storage module is also included; The storage module is connected to the image optimization module and is used to store the multi-channel first-scaled image data output by the image optimization module. The storage module is also connected to the processing unit for transmitting multiple first-scaled image data to the processing unit; The processing unit is specifically used to integrate the row length and field length of multiple first scaled image data to obtain one on-screen image data with the target resolution.

[0043] The processing unit is specifically used to adjust the preset row length and preset field length according to the FPGA programming, and to integrate multiple first-scaled image data according to the adjusted preset row length and preset field length to obtain one on-screen image data with the target resolution.

[0044] When integrating multiple first-scaled image data, the processing unit can further adjust the preset line length and preset field length according to the resolution of the display device, i.e. the target resolution, so as to integrate the multiple first-scaled image data based on the adjusted line length and field length, so that it is consistent with the resolution of the display device and achieves simultaneous display.

[0045] Furthermore, the storage module includes a control unit and a storage unit. The control unit is connected to the image optimization module, the processing unit, and the storage unit, respectively. Multiple channels of first-scaled image data output by the image optimization module are stored in the storage unit via the control unit. The multiple channels of first-scaled image data in the storage unit are read by the control unit and transmitted to the processing unit at a preset rate. Specifically, the storage unit can be a DDR (Double Data Rate Synchronous Dynamic Random Access Memory), and the control unit can be a DDR control unit, which is connected to the image optimization module, the processing unit, and the DDR, respectively. Multiple channels of first-scaled image data output by the image optimization module are stored in the DDR via the DDR control unit. The multiple channels of first-scaled image data in the DDR are read by the DDR control unit and transmitted to the processing unit at a preset rate. The preset rate can be real-time reading or a reading rate adapted to the corresponding signal type to facilitate the processing unit's integration of the multiple channels of first-scaled image data.

[0046] In this design, the DDR memory cells within the storage module transmit data once on the rising edge and once on the falling edge of the clock signal, achieving a data transfer rate twice that of traditional SDRAM (Synchronous Dynamic Random Access Memory) at the same clock frequency. This design significantly improves memory bandwidth without increasing the clock frequency, and the memory cells can also be other types of memory; this implementation does not impose any restrictions on this.

[0047] It should be noted that the storage module can be connected to other modules or units wirelessly or via wired connection. There is no limitation here, as long as data transmission between the storage module and other modules or units can be achieved.

[0048] In this embodiment, the storage module stores the multiple first-scale data output by the image optimization module before outputting it to the processing unit for integration. This effectively preserves the multiple first-scale data output by the image optimization module, preventing integration failure due to accidental data loss when directly integrating the multiple first-scale data. Furthermore, by including the storage module, buffer pressure is reduced. Simultaneously, through the cooperation between the control unit, storage unit, and processing unit, and in conjunction with the integration rate of the processing unit, the final on-screen image data output by the processing unit conforms to the protocol specifications and the VGA signal output format.

[0049] Reference Figure 1 In one embodiment, it further includes an output port group and a second interface standard conversion module; the input of the second interface standard conversion module is connected to the output of the processing unit, and the output of the second interface standard conversion module is connected to the output port group. The output port group is used to receive one channel of screen-sharing image data; or to receive second standard interface data, which is the data after the second interface standard conversion module converts one channel of screen-sharing image data.

[0050] The signal type corresponding to the second standard interface data is the same as the signal type corresponding to the second original image signal.

[0051] The output port group includes at least two output ports. Each output port can receive one channel of screen mirroring image data and output it to a display device. Since the signal type corresponding to the screen mirroring image data output by the processing unit can be converted into the target signal type through the second interface standard conversion module, for example, converting the signal type corresponding to the screen mirroring image data to be consistent with the signal type of the second original image signal, the circuit can adapt to multiple input and output sources. Therefore, this embodiment does not limit the type of output port of the screen mirroring circuit. At the same time, the number of display devices and output ports is not limited. For example, it can be 1 output source or 2 output sources, while the screen mirroring circuit can have 4 input sources and 1 output source. Obviously, it can also have 8 input sources and 1 output source, 4 input sources and 2 output sources, etc. Therefore, the number of ports in the input port group and the output port group can be adaptively adjusted based on the number of input sources and output sources.

[0052] Since the interface standard of the interface type corresponding to one channel of screen-sharing image data output by the processing unit may not be consistent with the interface standard of the display device, it is necessary to convert the interface standard of the one channel of screen-sharing image data to the interface standard of the display device.

[0053] In this embodiment, the interface type corresponding to the display device can be HDIM, and the interface type corresponding to one channel of screen-sharing image data output by the processing unit is VGA. Therefore, the signal type corresponding to this channel of screen-sharing image data needs to be converted from VGA to HDIM, that is, converted into the second standard interface data, so that the channel of screen-sharing image data can be displayed normally by the display device in the future. This conversion process is executed by the second interface standard conversion module, which is the VGA to HDIM module.

[0054] This embodiment allows for the expansion or deactivation of the number of ports within a group by setting up an output port group, thereby ensuring compatibility with different requirements for the number of output ports in different scenarios. Furthermore, the inclusion of a second interface standard conversion module enables the circuit to adapt to the simultaneous display requirements of multiple interface standards from the output source, enhancing the circuit's compatibility in terms of output signal types.

[0055] Reference Figure 1 In one embodiment, it further includes an EDID module; the EDID module is connected to the pixel processing module; The EDID module is used to read the resolution of the display device and output it to the pixel processing module, so that the pixel processing module adjusts the resolution of one channel of on-screen image data according to the resolution of the display device; and / or This is used to read the target resolution of one channel of on-screen image data and output the target resolution to the display device so that the display device can display the signal according to the target resolution.

[0056] The EDID (Extended Display Identification Data) module is a standardized data module. EDID is a standard for display identification data established by VESA (Video Electronics Standards Association) when developing the DDC (Display Data Channel) communication protocol. It can be read using the DDC protocol, a protocol for bidirectional communication between a monitor and a computer or other devices. Through DDC, the monitor can transmit information to the computer, such as the monitor's name, available pixels, and maximum resolution, and this information is used to make correct settings when installing or configuring a new monitor.

[0057] The EDID module can be connected to an external display device to read the display parameters of the external display device, such as the resolution that the external display device can support, and then transmit the display parameters to the pixel processing module, so that the pixel processing module adjusts the resolution of the video image data to be output according to the display parameters; or it can read the resolution of the video image data to be output, and then transmit the resolution of the video image data to the display device. If the resolution is consistent with the resolution of the display device, the display device displays the signal of the video image data according to the resolution.

[0058] Furthermore, the display parameters (such as resolution) of the external display device can also be stored in an additional EEPROM to reduce the interface and logic resources of the FPGA.

[0059] In this embodiment, by setting an EDID module in the screen mirroring circuit, display parameters such as resolution can be transmitted between the external display device and the pixel processing module, which is beneficial for the pixel processing module to adjust the resolution of the screen mirroring image data to be output and for the display device to display the screen mirroring image data with its supported resolution.

[0060] Figure 2 This is a flowchart illustrating the screen-sharing method provided in this application; see reference. Figure 2 This simultaneous display method, applied to FPGA, may include: Step 201: Receive multiple channels of the first raw image signal; Step 202: Sample the multiple channels of the first original image signal to obtain multiple channels of first image data; Step 203: Scale the multiple first image data to obtain multiple scaled first image data; Step 204: Integrate the multiple first-scaled image data into one simultaneous image data.

[0061] In step 201, the multiple first original image signals are signals output from at least two external input sources. The resolution of each first original image signal may or may not be the same, and this is not limited here.

[0062] Furthermore, the multiple first original image signals can be received through the input port group of the FPGA screen-sharing circuit; the input port group includes at least two input ports, each input port receives one first original image signal output from an input source, so at least two first original signals can be received.

[0063] In step 202, each channel of the first original image signal can be sampled to obtain the first image data corresponding to each channel of the first original image signal; Furthermore, this step can be implemented using the sampling unit of the FPGA screen-sharing circuit.

[0064] In step 203, each channel of first image data can be scaled to adapt the resolution of each channel of first image data to the resolution of the display device, thereby obtaining the first scaled image data corresponding to each channel of first image data. Furthermore, this step can be implemented using the image optimization module of the FPGA screen-sharing circuit.

[0065] In step 204, after integrating multiple first scaled image data into one simultaneous image data, multiple inputs can be displayed synchronously on the same display device; wherein, the number of pixels of the simultaneous image data is equal to the number of pixels of any one first original image signal; Furthermore, this step can be implemented through the processing unit of the FPGA screen mirroring circuit.

[0066] The acquisition unit and processing unit can be integrated into the pixel processing module of the FPGA screen-sharing circuit.

[0067] This embodiment, implemented using an FPGA, leverages the reprogrammable nature of the FPGA to sample the first original image signal at a preset scale and scale multiple first image data streams to a preset size. This allows it to receive any number of original image signals with uncommon resolutions, process them into signals of common resolutions, and then integrate them to obtain a single on-screen image data stream output to the display device. For example, for 1080p... 840, 1080 The original image signal with an uncommon resolution like 960 is converted into on-screen image data with the target resolution, for example, the target resolution could be 1080. It can accept common resolutions like 720; it can also receive raw image signals at any number of common resolutions, process them to a less common resolution, and output them in one channel, such as 1080. Raw image signals with common resolutions like 720 are processed to 1080. 840, 1080 It can output image data on the same screen at resolutions such as 960 that are not common. As for the input port group, the number of ports can be increased or decreased to improve the adaptability of the number of input ports in different scenarios.

[0068] It should be noted that since video is composed of multiple frames, the image signal processing method in this embodiment is also applicable to video signals. That is, this embodiment can process multiple image signals to output one simultaneous image data stream, and it can also process multiple video signals to output one simultaneous video data stream; see reference... Figure 1This means that after processing four image signals, one output is a single image data stream on the same screen, or after processing four video signals, one output is a single video data stream on the same screen. Similarly, this embodiment is also suitable for displaying multiple images on the same screen.

[0069] The screen-sharing method provided in this embodiment, on the one hand, can flexibly adjust the resolution of original image data of different resolutions by scaling the received image data, thereby enabling the resolution of the input source to flexibly adapt to the resolution of the display device and improving the resolution compatibility between the input device and the display device; on the other hand, by setting up input port groups, the number of ports within a group can be expanded or deactivated as needed, thus accommodating different requirements for the number of input ports in different scenarios. In summary, this embodiment can improve the resolution compatibility between the input device and the display device and accommodate different requirements for the number of input ports in different scenarios. Therefore, unlike traditional ASIC chips, it does not require customized tape-out for specific needs, and has good adaptability and low development cost.

[0070] This application provides a screen mirroring chip, which may include the aforementioned screen mirroring circuit.

[0071] Since the screen mirroring chip is based on the aforementioned screen mirroring circuit, it possesses all the technical features and beneficial effects of the aforementioned screen mirroring circuit, which will not be elaborated here.

[0072] This application provides a screen mirroring device, which may include the aforementioned screen mirroring chip.

[0073] Since the screen mirroring device is based on the aforementioned screen mirroring chip, it possesses all the technical features and beneficial effects of the aforementioned screen mirroring chip, which will not be elaborated here.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A screen-sharing circuit, characterized in that, Applied to FPGA, it includes a pixel processing module, an image optimization module, and an input port group, wherein the pixel processing module includes an acquisition unit and a processing unit; The input port group is used to receive multiple first raw image signals; The acquisition unit is used to sample the multiple first original image signals to obtain multiple first image data; The image optimization module is used to scale the multiple first image data to obtain multiple scaled first image data. The processing unit is used to integrate the multiple first-scaled image data into a single on-screen image data.

2. The screen-sharing circuit according to claim 1, characterized in that, It also includes a first interface standard conversion module; the input end of the first interface standard conversion module is connected to some or all of the ports in the input port group, and the output end of the first interface standard conversion module is connected to the acquisition unit; The input port group is also used to receive multiple second raw image signals; The first interface standard conversion module is used to convert the multiple second original image signals into the multiple first original image signals.

3. The screen-sharing circuit according to claim 1, characterized in that, The acquisition unit is specifically used to acquire the multiple first original image signals according to the preset row length and preset field length to obtain the multiple first image data. The image optimization module is specifically used to reduce the pixel size of each image data of the multiple first image data to a preset pixel size to obtain the multiple first scaled image data.

4. The screen-sharing circuit according to claim 3, characterized in that, The image optimization module is specifically used to interpolate the pixels of each image data in the multiple first image data using a bilinear interpolation algorithm to obtain the multiple first scaled image data.

5. The screen-sharing circuit according to claim 1, characterized in that, It also includes a storage module; The storage module is connected to the image optimization module and is used to store the multi-channel first scaled image data output by the image optimization module; The storage module is also connected to the processing unit and is used to transmit the multiple first scaled image data to the processing unit. The processing unit is specifically used to integrate the row length and field length of the multiple first scaled image data to obtain the single-channel on-screen image data with the target resolution.

6. The screen-sharing circuit according to claim 1, characterized in that, It also includes an output port group and a second interface standard conversion module; the input of the second interface standard conversion module is connected to the output of the processing unit, and the output of the second interface standard conversion module is connected to the output port group. The output port group is used to receive the same channel of screen-on image data; or Used to receive second standard interface data, which is the data after the second interface standard conversion module converts the one-channel screen-sharing image data.

7. The screen-sharing circuit according to claim 1, characterized in that, It also includes an EDID module; the EDID module is connected to the pixel processing module; The EDID module is used to read the resolution of the display device and output it to the pixel processing module, so that the pixel processing module adjusts the resolution of the same-screen image data according to the resolution of the display device. and / or The target resolution is used to read the target resolution of the simultaneous image data and output the target resolution to the display device so that the display device can display the signal according to the target resolution.

8. A method for simultaneous display, characterized in that, Applied to FPGAs, including: Receive multiple channels of the first raw image signal; The multiple first original image signals are sampled to obtain multiple first image data; The multi-channel first image data is scaled to obtain multi-channel scaled first image data; The multiple first-scaled image data are integrated into a single on-screen image data.

9. A screen-sharing chip, characterized in that, Includes the screen-sharing circuit as described in any one of claims 1 to 7.

10. A same-screen device, characterized in that, Includes the screen-sharing chip as described in claim 9.

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