Operating method of non-volatile memory, storage device, and operating method of storage device

Abstract

The invention discloses an operating method of a nonvolatile memory, a storage device, and an operating method of the storage device. An operating method of a memory device including a memory controller and a non-volatile memory device includes: generating a plurality of pieces of transfer parity data corresponding to a plurality of data lines, respectively; transmitting a write command, data, and the plurality of pieces of transfer parity data to a first non-volatile memory through the plurality of data lines; performing a transmission error detection operation for each of the plurality of data lines based on each of the plurality of pieces of transmission parity data; determining that a retraining execution condition is satisfied based on an error detection result generated in the transmission error detection operation; and transmitting state information indicating a transmission error state to the memory controller when a retraining execution condition is satisfied in response to the state read command.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0108496, filed on August 13, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present disclosure relates to an operating method of a nonvolatile memory, a storage device, and an operating method of a storage device. BACKGROUND

[0003] Semiconductor memories are classified into volatile memory devices (such as static random access memory (SRAM) and dynamic random access memory (DRAM)) that lose stored data at power-off and nonvolatile memory devices (such as a flash memory device, a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), and a ferroelectric random access memory (FRAM)) that retain stored data even at power-off.

[0004] A storage device can include a nonvolatile memory and a controller for controlling the nonvolatile memory. Communication between the nonvolatile memory and the controller is performed at a low operating frequency compared to a memory system including a high-speed memory such as a DRAM or an SRAM. However, it is desired to perform communication between the nonvolatile memory and the controller at a high operating frequency. Accordingly, various methods for aligning communication signals between the nonvolatile memory and the controller are being introduced. SUMMARY

[0005] In general, the present disclosure relates to a storage controller, a storage device, and an operating method of a storage device.

[0006] According to some embodiments, the disclosure relates to an operating method of a storage device including a storage controller and a non-volatile memory device, the operating method including: generating, by the storage controller, a plurality of transmission parity data respectively corresponding to a plurality of data lines; transmitting, by the storage controller and through the plurality of data lines, a write command, data, and the plurality of transmission parity data to a first non-volatile memory among a plurality of non-volatile memories included in the non-volatile memory device; performing, by the first non-volatile memory, a transmission error detection operation for each of the plurality of data lines based on each of the plurality of transmission parity data; determining, by the first non-volatile memory, whether a retraining execution condition is satisfied based on an error detection result generated in the transmission error detection operation; transmitting, by the storage controller, a status read command to the first non-volatile memory; and in response to the status read command, transmitting, by the first non-volatile memory, status information indicating a transmission error state to the storage controller when the retraining execution condition is satisfied.

[0007] According to some embodiments, the disclosure relates to an operating method of a non-volatile memory, the operating method including: receiving a first sub-data and a first sub-transmission parity data through a first data line and a second sub-data and a second sub-transmission parity data through a second data line; performing a transmission error detection operation on the first sub-data based on the first sub-transmission parity data and performing a transmission error detection operation on the second sub-data based on the second sub-transmission parity data; determining whether a retraining execution condition is satisfied based on an error detection result generated in the transmission error detection operation; and in response to a status read command, outputting, through the first data line and the second data line, status information indicating a transmission error state when the retraining execution condition is satisfied.

[0008] According to some embodiments, the disclosure relates to a storage device including: a non-volatile memory device including a plurality of non-volatile memories; and a storage controller configured to: generate a plurality of transmission parity data respectively corresponding to a plurality of data lines, transmit a write command, data, and the plurality of transmission parity data to a first non-volatile memory among the plurality of non-volatile memories through the plurality of data lines, and transmit a status read command to the first non-volatile memory. The first non-volatile memory performs a transmission error detection operation for each of the plurality of data lines based on each of the plurality of transmission parity data, determines whether a retraining execution condition is satisfied based on an error detection result generated in the transmission error detection operation, and in response to the status read command, transmits status information indicating a transmission error state to the storage controller when the retraining execution condition is satisfied. BRIEF DESCRIPTION OF DRAWINGS

[0009] Example embodiments will be more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of an example of a storage device according to some embodiments.

[0011] Figure 2 is a block diagram of a storage device according to some embodiments. Figure 1

[0012] Figure 3 is a block diagram of an example of a storage controller according to some embodiments. Figure 1

[0013] Figure 4 is a block diagram of an example of a non-volatile memory according to some embodiments. Figure 1

[0014] Figure 5 is a block diagram of an example of error detection circuitry and retraining determination circuitry according to some embodiments. Figure 1

[0015] Figure 6 is a flowchart of an example of operation of a storage device according to some embodiments. Figure 1

[0016] and Figure 7A are diagrams for explaining an example of a transfer error detection operation of a first non-volatile memory according to some embodiments. Figure 7B Figure 2

[0017] Figure 8A and Figure 8B are diagrams for explaining an example of a transfer error detection operation of a first non-volatile memory according to some embodiments. Figure 2

[0018] Figure 9 is a flowchart of an example of operation of a first non-volatile memory according to some embodiments. Figure 2

[0019] Figure 10 is a flowchart of an example of operation of a storage controller according to some embodiments. Figure 1

[0020] Figure 11 is a flowchart of an example of operation S320 according to some embodiments. Figure 10

[0021] Figure 12 is a flowchart of an example of operation of a storage device according to some embodiments.​​​​​​​​​​Figure 2 a flowchart of an example of the operation of the storage controller of FIG. 1.

[0022] Figure 13 is an example of the operation of the storage controller of FIG. 1 according to some embodiments. Figure 2 a flowchart of an example of the operation of the storage controller of FIG. 1.

[0023] Figure 14 is an example of the operation of the storage controller of FIG. 1 according to some embodiments. Figure 2 a flowchart of an example of the operation of the storage controller of FIG. 1.

[0024] Figure 15 is an example of the operation of the storage controller of FIG. 1 according to some embodiments. Figure 2 a flowchart of an example of the operation of the storage controller of FIG. 1.

[0025] Figure 16 is an example of the operation of the storage controller of FIG. 1 according to some embodiments. Figure 2 a flowchart of an example of the operation of the storage controller of FIG. 1.

[0026] Figure 17A and Figure 17B is a diagram for explaining an example of a transfer error detection operation of the first nonvolatile memory of FIG. 1 according to some embodiments. Figure 2 DETAILED DESCRIPTION

[0027] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram of an example of a storage device according to some embodiments. In Figure 1 , the storage device 100 can include a storage controller 110 and a nonvolatile memory device 120. According to some embodiments, the storage device 100 can be a mass storage medium such as a solid state drive (SSD). The storage device 100 can be included in one of information processing devices configured to process pieces of information and store the processed information, such as a personal computer (PC), a laptop computer, a server, a workstation, a smart phone, a tablet PC, a digital camera, and a black box. However, the scope of the present disclosure is not limited thereto, and the storage device 100 can be implemented in various forms and can be included in various devices or various systems.

[0029] The storage controller 110 can be configured to control the nonvolatile memory device 120. For example, the storage controller 110 can store data in the nonvolatile memory device 120 or read data stored in the nonvolatile memory device 120 under the control of an external host. According to some embodiments, the storage controller 110 can perform various maintenance operations for improving the performance or reliability of the nonvolatile memory device 120 independently of the control of the external host. ​

[0030] According to some embodiments, the storage controller 110 can be configured to communicate with an external host based on a predetermined host interface. The predetermined host interface can include at least one of various host interfaces such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect (PCI), a PCI-express (PCI-E), an advanced technology attachment (ATA), a serial-ATA, a parallel-ATA, a small computer small interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a mobile industry processor interface (MIPI), a non-volatile memory-express (NVM-e), and a compute express link (CXL) interface.

[0031] According to some embodiments, the storage controller 110 can be configured to communicate with the non-volatile memory device 120 based on a predetermined memory interface. The predetermined memory interface can include at least one of various flash memory interfaces such as a ToggleNAND interface and an open NAND flash interface (ONFI).

[0032] For example, the storage controller 110 can transmit and receive various signals by a control signal CTRL of a control signal line, a signal of a data line DQ, and a signal of a data strobe line DQS, in order to control the non-volatile memory device 120.

[0033] For example, the control signal CTRL, the signal of the data strobe line DQS, and the signals of the plurality of data lines DQ can be provided to the non-volatile memory device 120 through different signal lines or different signal pins, respectively. The control signal CTRL and the signal of the data strobe line DQS can be signals for distinguishing signals (e.g., a command CMD, an address ADDR, or data DATA) provided to the non-volatile memory device 120 through the signals of the plurality of data lines DQ. For example, the signal of the data line DQ indicates a signal transmitted and received through a data pin (DQ pin), and the signal of the data strobe line DQS indicates a signal transmitted and received through a data strobe pin (DQS pin).

[0034] The non-volatile memory device 120 can operate under the control of the storage controller 110. For example, the non-volatile memory device 120 can store data or output stored data under the control of the storage controller 110. The non-volatile memory device 120 can include a plurality of non-volatile memories NVM.

[0035] For example, the non-volatile memory NVM can distinguish whether a signal provided through the plurality of data lines DQ is a command CMD, an address ADDR, or data DATA based on the control signal CTRL. According to some embodiments, various signals such as a command latch enable signal CLE, an address latch enable signal ALE, a read enable signal RE / or a write enable signal WE / can be provided to the non-volatile memory NVM via a control signal line.

[0036] The non-volatile memory NVM can be configured to identify (or capture) data DATA provided through the plurality of data lines DQ based on a signal of the data strobe line DQS. The non-volatile memory NVM can store the identified data DATA based on a received command CMD and an address ADDR.

[0037] For example, the non-volatile memory NVM can include a NAND flash. However, the scope of the present disclosure is not limited thereto, and the non-volatile memory device 120 can include at least one of volatile memory and non-volatile memory such as a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc.

[0038] The storage device 100 can perform training (e.g., read training or write training) to increase accuracy of communication when all functions are performed. The storage device 100 can determine alignment of signals of the plurality of data lines DQ and a target delay of a signal of the data strobe line DQS. As a data input / output speed between the storage controller 110 and the non-volatile memory NVM increases, a retraining operation is needed.

[0039] The non-volatile memory NVM and the storage controller 110 can transmit and receive data through the plurality of data lines DQ. Delays on paths of the plurality of data lines DQ and the data strobe line DQS can vary with temperature changes. When a sampling timing changes due to the delay variation, a setup / hold (S / H) margin can be reduced. The storage controller 110 can perform retraining to compensate for the delay variation with temperature changes. Accordingly, the storage controller 110 can adjust the delays on the paths. However, when the retraining is performed, resources for training can increase.

[0040] For example, the storage controller 110 can periodically collect temperature information or voltage information of the plurality of non-volatile memories NVM. In some embodiments, the storage controller 110 can periodically send an oscillator request command to the plurality of non-volatile memories NVM. The storage controller 110 can periodically request an oscillator value of a data strobe signal. The storage controller 110 can monitor each of the plurality of non-volatile memories NVM. The monitoring can indicate an operation of monitoring a delay change on a path of the plurality of data lines DQ and the data strobe line DQS. The storage controller 110 can determine a retraining time of the non-volatile memories NVM by the monitoring. Accordingly, the performance of the storage device 100 can be degraded.

[0041] The storage device 100 can determine the retraining time while performing a normal operation. The storage device 100 can determine when to perform the retraining by a write operation without a monitoring operation. In some embodiments, the storage device 100 can determine when to perform the retraining by a write operation as well as a monitoring operation.

[0042] The storage controller 110 can generate a plurality of transmission parity data for each of the plurality of data lines DQ. The storage controller 110 can transmit the plurality of transmission parity data to the non-volatile memories NVM together with the data. According to some embodiments, the storage controller 110 can transmit the data, the memory parity data, and the transmission parity data to the non-volatile memories NVM. The memory parity data can indicate parity data for improving memory cell reliability. The transmission parity data can indicate parity data for resolving transmission errors.

[0043] The non-volatile memories NVM can perform a transmission error detection operation based on the transmission parity data. The non-volatile memories NVM can determine a condition for performing the retraining based on a result of the transmission error detection operation. When the non-volatile memories NVM determine that the retraining is necessary based on the error detection result, the non-volatile memories NVM can provide a notification of the determination result to the storage controller 110.

[0044] The non-volatile memories NVM can include a transmission error detection circuit 121 and a retraining determination circuit 122. The transmission error detection circuit 121 can perform a transmission error detection operation for each of the plurality of data lines DQ based on the transmission parity data. The transmission error detection circuit 121 can determine whether there is an error in the sub-data received from each of the plurality of data lines DQ. The transmission error detection circuit 121 can generate an error detection result.

[0045] The retraining determination circuit 122 can determine whether the retraining condition is satisfied based on the error detection result. For example, the retraining determination circuit 122 can determine whether the retraining condition is satisfied by comparing the number of data lines from which a transmission error is detected with a threshold. In response to a status read command, the non-volatile memory NVM can transmit status information indicating a transmission error status to the storage controller 110.

[0046] Accordingly, the storage device 100 can not perform a monitoring operation of periodically monitoring temperature / voltage changes of the plurality of non-volatile memories NVM. The non-volatile memory NVM can detect an error based on transmission parity data. The non-volatile memory NVM can inform the storage controller 110 of a transmission error status through status information. The storage device 100 can perform retraining without performance degradation.

[0047] Figure 3 is a block diagram of a storage device 100 according to some embodiments. Figure 4 In the storage device 100, the storage controller 110 can determine whether a retraining condition is satisfied based on a result of detecting a transmission error. Figure 1 and Figure 4 In the storage device 100, the storage controller 110 can determine whether a retraining condition is satisfied based on a result of detecting a transmission error.

[0048] The non-volatile memory device 120 can include a plurality of non-volatile memories NVM11 to NVMmn. Each of the plurality of non-volatile memories NVM11 to NVMmn can correspond to a non-volatile memory NVM of Figure 2 The plurality of non-volatile memories NVM11 to NVMmn can be connected to one of the plurality of channels CH1 to CHm through a corresponding path. For example, the non-volatile memories NVM11 to NVM1n can be connected to the first channel CH1 through paths W11 to W1n, and the non-volatile memories NVM21 to NVM2n can be connected to the second channel CH2 through paths W21 to W2n. According to some embodiments, each of the non-volatile memories NVM11 to NVMmn can be implemented as an arbitrary memory unit that can be operated according to a separate command from the storage controller 110. For example, each of the non-volatile memories NVM11 to NVMmn can be implemented as a chip or a die, but the present disclosure is not limited thereto.

[0049] The storage controller 110 can transmit and receive signals to and from the nonvolatile memory device 120 through the plurality of channels CH1 to CHm. For example, the storage controller 110 can transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the nonvolatile memory device 120 through the plurality of channels CH1 to CHm, or can receive data DATAa to DATAm from the nonvolatile memory device 120.

[0050] The storage controller 110 can select one of the nonvolatile memory devices connected to each channel through each channel and can transmit and receive signals to and from the selected nonvolatile memory device. For example, the storage controller 110 can select the nonvolatile memory NVM11 from among the nonvolatile memories NVM11 to NVM1n connected to the first channel CH1. The storage controller 110 can transmit a command CMDa, an address ADDRa, and data DATAa to the selected nonvolatile memory NVM11 through the first channel CH1, or can receive data DATAa from the selected nonvolatile memory NVM11.

[0051] The storage controller 110 can transmit and receive signals to and from the nonvolatile memory device 120 through different channels in parallel. For example, the storage controller 110 can transmit a command CMDb to the nonvolatile memory device 120 through the second channel CH2 while transmitting a command CMDa to the nonvolatile memory device 120 through the first channel CH1. For example, the storage controller 110 can receive data DATAb from the nonvolatile memory device 120 through the second channel CH2 while receiving data DATAa from the nonvolatile memory device 120 through the first channel CH1.

[0052] According to some embodiments, the storage controller 110 can perform a read operation or a write operation on the second nonvolatile memory NVM21 connected to the second channel CH2 while performing a retraining operation on the first nonvolatile memory NVM11 connected to the first channel CH1.

[0053] The storage controller 110 can control overall operations of the nonvolatile memory device 120. The storage controller 110 can control each of the nonvolatile memories NVM11 to NVMmn connected to the channels CH1 to CHm by transmitting signals to the channels CH1 to CHm. For example, the storage controller 110 can control one nonvolatile memory selected from the nonvolatile memories NVM11 to NVM1n by transmitting a command CMDa and an address ADDRa to the first channel CH1.

[0054] Each of the non-volatile memories NVM11 to NVMmn can operate under the control of the memory controller 110. For example, the non-volatile memory NVM11 can program data DATAa according to the command CMDa, address ADDRa, and data DATAa provided to the first channel CH1. For example, the non-volatile memory NVM21 can read data DATAb according to the command CMDb and address ADDRb provided to the second channel CH2, and can send the read data DATAb to the memory controller 110.

[0055] exist Figure 1 In this embodiment, non-volatile memory device 120 is shown as communicating with memory controller 110 via m channels and including n non-volatile memory devices corresponding to each channel. However, the number of channels and the number of non-volatile memory devices connected to a channel may vary.

[0056] Figure 2 This illustrates according to some embodiments. Figure 3 A block diagram of the storage controller 110. Figure 1 and Figure 1 In this configuration, the storage controller 110 may include a central processing unit (CPU) 111, host interface circuitry 117, and NVM interface circuitry 118. The storage controller 110 may also include a flash translation layer (FTL) 112, a packet manager (PCK MNG) 113, a buffer memory (BUF MEM) 114, an error correction code (ECC) engine (ENG) 115, and an Advanced Encryption Standard (AES) engine 116. The storage controller 110 may also include a working memory (not shown), in which the FTL 112 is loaded, and the CPU 111 can control data write and read operations on the non-volatile memory device by executing the FTL 112.

[0057] According to some implementations, the host interface circuit 117 may include at least one of various interfaces, such as Double Data Rate (DDR), Low Power DDR (LPDDR), Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Mobile Industrial Processor Interface (MIPI), Non-Volatile Memory-Fast (NVM-e), and Universal Flash Memory (UFS)).

[0058] The host interface circuit 117 can transmit and receive packets to and from a host (not shown). Packets transmitted from the host to the host interface circuit 117 can include, for example, commands or data to be written to the non-volatile memory device 120, and packets transmitted from the host interface circuit 117 to the host can include, for example, responses to the commands or data read from the non-volatile memory device 120. The NVM interface circuit 118 can transmit data to be written to the non-volatile memory device 120 to the non-volatile memory device 120, or can receive data read from the non-volatile memory device 120. The NVM interface circuit 118 can be implemented to comply with a standard, such as Toggle or ONFI.

[0059] The FTL 112 can perform several functions, such as address mapping, wear leveling, and garbage collection. Address mapping is an operation of changing a logical address received from a host to a physical address used to actually store data in the non-volatile memory device 120. Wear leveling is a technique for preventing over-deterioration of a specific block by enabling blocks within the non-volatile memory device 120 to be used uniformly, and can be implemented, for example, by a firmware technique that equalizes erase counts of physical blocks. Garbage collection is a technique for securing available capacity within the non-volatile memory device 120 by using a method of copying valid data of an existing block to a new block and then erasing the existing block.

[0060] The packet manager 113 can create packets according to a protocol of an interface agreed with a host, or parse various types of information from packets received from the host. The buffer memory 114 can temporarily store data to be written to the non-volatile memory device 120 or data read from the non-volatile memory device 120. The buffer memory 114 can be configured to be disposed within the memory controller 110, but can also be placed outside the memory controller 110.

[0061] The ECC engine 115 can perform error detection and correction functions with respect to read data read from the non-volatile memory device 120. In more detail, the ECC engine 115 can generate parity bits for write data to be written to the non-volatile memory device 120, and the generated parity bits can be stored in the non-volatile memory device 120 together with the write data. When data is read from the non-volatile memory device 120, the ECC engine 115 can correct errors in the read data by using the parity bits read from the non-volatile memory device 120 together with the read data, and can output the read data in which the errors have been corrected.

[0062] According to some embodiments, the ECC engine 115 can generate memory parity data. The ECC engine 155 can generate memory parity data for detecting errors included in data read from the non-volatile memory NVM. The ECC engine 155 can use the memory parity data to supplement memory cell reliability.

[0063] According to some embodiments, the ECC engine 115 can generate transmission parity data. The ECC engine 115 can divide data (or user data or page data) by a number of data lines. The ECC engine 115 can divide the data into a plurality of sub-data. The ECC engine 115 can generate sub-transmission parity data for each of the plurality of sub-data. The transmission parity data can be used to compensate for lane errors or transmission errors.

[0064] The AES engine 116 can perform at least one of an encryption operation and a decryption operation on data input to the storage controller 110 by using a symmetric key algorithm.

[0065] As the input / output speed between the storage controller 110 and the non-volatile memory NVM increases, the range of the effective window can decrease. The lane error rate can increase during data transmission. During initialization, training can be performed to ensure maximum margin within the effective window. However, temperature changes and voltage changes of the non-volatile memory NVM can increase during the input / output operation. Accordingly, skewing can occur between signals of the plurality of data lines DQ and signals of the data strobe line DQS. Due to the skewing, the non-volatile memory NVM can store data including errors. Although the reliability of the memory cell is good (i.e., the memory cell maintains a normal distribution), due to lane transmission errors, data including errors can be stored in a pattern that causes uncorrectable error correction codes (UECCs) in a read operation. Thus, re-training is needed.

[0066] According to some embodiments, the storage controller 110 can monitor temperature changes and voltage changes of the non-volatile memory NVM in order to determine whether to perform re-training. The storage controller 110 can request an oscillator value of a data strobe signal from the non-volatile memory NVM. The storage controller 110 can request delay information of the data strobe signal from the non-volatile memory NVM. Alternatively, the storage controller 110 can request a DQS / DQ phase change from the non-volatile memory NVM.

[0067] According to some implementations, sufficient time may be required to increase the accuracy of the oscillator request commands. The storage controller 110 may also perform a monitoring operation (or polling operation) that periodically sends oscillator request commands, even to the non-volatile memory NVM, which does not require retraining. Therefore, the performance of the storage device 100 degrades. In other words, because the storage controller 110 periodically sends oscillator commands, input / output performance may be reduced. In other words, the sequential performance and quality of service (QoS) latency of the storage device 100 may be reduced.

[0068] According to some implementations, the storage controller 110 can determine the retraining time. The storage controller 110 can determine whether each of the plurality of non-volatile memory NVMs needs retraining. The storage controller 110 can determine whether retraining is needed based on status information indicating a transmission error state. The storage controller 110 can perform retraining on the non-volatile memory NVMs in response to the status information indicating a transmission error state. The storage controller 110 can determine, based on the status information, whether the programming failure is due to a memory cell error or a channel transmission error. Therefore, the storage device 100 can detect channel errors between the storage controller 110 and the non-volatile memory NVMs in real time without performance degradation.

[0069] Figure 3 This illustrates according to some embodiments. Figure 4 A block diagram of non-volatile memory (NVM). Figure 1 In this context, non-volatile memory (NVM) can correspond to... Figure 4 Multiple non-volatile memories NVM11 to NVMmn. Figure 2 and Figure 1 In this configuration, the non-volatile memory (NVM) may include a memory cell array 123, a row decoder 124, a page buffer unit 125, input / output circuitry 126, a voltage generator 127, and control logic circuitry 128. Additionally, the NVM may also include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc. According to some embodiments, the NVM may be a non-volatile memory device (such as NAND flash memory). However, the scope of this disclosure is not limited thereto.

[0070] For example, memory cell array 123 can be the core of a non-volatile memory (NVM). Row decoder 124, page buffer unit 125, input / output circuitry 126, and control logic circuitry 128 can be peripheral circuitry of the NVM. Peripheral circuitry can be configured to access the core.

[0071] The memory cell array 123 can include a plurality of memory blocks. Each of the plurality of memory blocks can include a plurality of memory cells. The memory cell array 123 can be connected to the page buffer unit 125 via bit lines BL and can be connected to the row decoder 124 via word lines WL, string selection lines SSL, and ground selection lines GSL.

[0072] According to some embodiments, the memory cell array 123 can include a three- dimensional (3D) memory cell array, and the 3D memory cell array can include a plurality of strings. Each of the plurality of strings can include memory cells connected to word lines vertically stacked on a base, respectively. U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587, and U.S. Patent No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are hereby incorporated by reference in their entirety.

[0073] The row decoder 124 can receive a row address X-ADDR from the control logic circuit 128. The row decoder 124 can decode the row address X-ADDR, and based on a result of the decoding, can control or drive voltages of the string selection lines SSL, the word lines WL, and the ground selection lines GSL. For example, based on the result of the decoding, the row decoder 124 can provide operating voltages corresponding to the string selection lines SSL, the word lines WL, and the ground selection lines GSL, respectively.

[0074] In response to the row address X-ADDR, the row decoder 124 can select one word line from the plurality of word lines WL and one string selection line from the plurality of string selection lines SSL. For example, the row decoder 360 can apply a program voltage and a program verify voltage to the selected word line during a program operation, and can apply a read voltage to the selected word line during a read operation.

[0075] The page buffer unit 125 can be connected to the memory cell array 123 via the bit lines BL. The page buffer unit 125 can select at least one bit line from the bit lines BL in response to a column address Y-ADDR. The page buffer unit 125 can operate as a write driver or a sense amplifier according to an operation mode. For example, the page buffer unit 125 can receive data DATA from the input / output circuit 126 (e.g., via a data line DL), and can temporarily store the received data DATA. The page buffer unit 125 can control a voltage of the bit line BL so that the temporarily stored data DATA is stored in the memory cell array 123. In some embodiments, the page buffer unit 125 can read data DATA from the memory cell array 123 by detecting a change in the voltage of the bit line BL. The page buffer unit 125 can transmit the read data DATA to the input / output circuit 126.

[0076] The input / output circuit 126 can exchange data DATA with an external device (e.g., a memory controller). According to some embodiments, the input / output circuit 126 can output or receive data DATA to or from the external device in synchronization with a data strobe signal.

[0077] The voltage generator 127 can generate various types of voltages for performing a program operation, a read operation, and an erase operation based on a voltage control signal CTRL_vol. For example, the voltage generator 127 can generate a program voltage, a read voltage, a program verify voltage, an erase voltage, etc. as a word line voltage VWL.

[0078] The control logic circuit 128 can provide overall control of various operations within the non-volatile memory NVM. The control logic circuit 128 can output various control signals in response to a command CMD and / or an address ADDR from the memory controller 110. For example, the control logic circuit 128 can output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0079] The control logic circuit 128 can include a transmission error detection circuit 121 and a retraining determination circuit 122. The transmission error detection circuit 121 can perform a transmission error detection operation. The transmission error detection circuit 121 can perform a decoding operation based on received transmission parity data. The transmission error detection circuit 121 can detect an error in each piece of sub-data by using the transmission parity data. The transmission error detection circuit 121 can detect an error for sub-data corresponding to each of the plurality of data lines DQ. The transmission error detection circuit 121 can determine the number of errors included in the sub-data.

[0080] For example, the transmission error detection circuit 121 can determine whether the sub-data includes a '1' bit error, a '2' bit error, or a '3' bit or more error. The transmission error detection circuit 121 can generate an error detection result. The transmission error detection circuit 121 can generate transmission error information based on the error detection result. The transmission error detection circuit 121 can generate the transmission error information by accumulating the error detection result. The transmission error detection circuit 121 can transmit information about whether an error has been detected for each of the plurality of data lines and information about the number of errors for each of the plurality of data lines to the memory controller 110 through the transmission error information.

[0081] The retraining determination circuit 122 can determine whether retraining of the non-volatile memory (NVM) is necessary based on error detection results. The retraining determination circuit 122 can also determine whether retraining conditions are met based on error detection results. For example, the retraining determination circuit 122 can determine that retraining conditions are met when the number of data lines from which errors have been detected is greater than or equal to a threshold. However, the scope of this disclosure is not limited thereto, and retraining conditions can be combined in various ways.

[0082] For example, the retraining determination circuit 122 can determine whether a retraining condition is met by integrating multiple error detection results. The retraining determination circuit 122 can determine whether a retraining condition is met based on the number of errors included in the sub-data. The retraining condition can correspond to the condition under which a UECC occurs.

[0083] According to some implementations, the non-volatile memory (NVM) can generate state information based on the determination made by the retraining determination circuit 122. For example, when retraining conditions are met, the NVM can notify the storage controller 110 that retraining is required by indicating a transmission error state.

[0084] As described above, the non-volatile memory (NVM) can detect errors during each write operation based on transmitted parity data. The NVM can notify the storage controller 110 of the transmission error status. Therefore, the NVM can avoid storing data including transmission errors and can recover the data immediately.

[0085] Figure 4 This illustrates according to some embodiments. Figure 5 A block diagram of an example error detection circuit and retraining determination circuit. Figure 1 In this embodiment, the non-volatile memory (NVM) may include a transmission error detection circuit 121 and a retraining determination circuit 122. The transmission error detection circuit 121 may include a first sub-error detection circuit 121_1, a second sub-error detection circuit 121_2, a third sub-error detection circuit 121_3, and a fourth sub-error detection circuit 121_4. However, the scope of this disclosure is not limited thereto, and the number of sub-error detection circuits included in the error detection circuit may be reduced or increased depending on the implementation.

[0086] Each of the first to fourth sub-error detection circuits 121_1-121_4 can receive data transmitted through a corresponding line. For example, the first sub-error detection circuit 121_1 can receive data transmitted through the first data line DQ1. The second sub-error detection circuit 121_2 can receive data transmitted through the second data line DQ2. The third sub-error detection circuit 121_3 can receive data transmitted through the third data line DQ3. The fourth sub-error detection circuit 121_4 can receive data transmitted through the fourth data line DQ4.

[0087] Each of the first to fourth sub-error detection circuits 121_1-121_4 can perform a transmission error detection. Each of the first to fourth sub-error detection circuits 121_1-121_4 can detect an error of the received data. Each of the first to fourth sub-error detection circuits 121_1-121_4 can detect an error in the sub-data based on the sub-transmission parity data.

[0088] For example, the first sub-error detection circuit 121_1 can detect an error of the data received through the first data line DQ1. The second sub-error detection circuit 121_2 can detect an error of the data received through the second data line DQ2. The third sub-error detection circuit 121_3 can detect an error of the data received through the third data line DQ3. The fourth sub-error detection circuit 121_4 can detect an error of the data received through the fourth data line DQ4.

[0089] The transmission error detection circuit 121 can generate an error detection result. The error detection result can include a first sub-result, a second sub-result, a third sub-result, and a fourth sub-result. The first sub-error detection circuit 121_1 can generate the first sub-result, the second sub-error detection circuit 121_2 can generate the second sub-result, the third sub-error detection circuit 121_3 can generate the third sub-result, and the fourth sub-error detection circuit 121_4 can generate the fourth sub-result. The transmission error detection circuit 121 can transmit the error detection result to the retraining determination circuit 122.

[0090] The retraining determination circuit 122 can receive the error detection result. The retraining determination circuit 122 can receive a threshold value. The storage controller 110 can set the threshold value through a threshold setting command. The threshold value can be a predetermined value. The retraining determination circuit 122 can store the threshold value. The retraining determination circuit 122 can determine whether a retraining condition is satisfied based on the error detection result and the threshold value. The retraining determination circuit 122 can generate a result of the determination. The retraining determination circuit 122 can transmit the result of the determination to the control logic circuit 128. The control logic circuit 128 can generate state information based on the result of the determination.

[0091] As described above, the non-volatile memory NVM can perform a transfer error detection operation. The non-volatile memory NVM can inform the storage controller 110 whether retraining is necessary. Accordingly, the storage device 100 can remove an overhead of periodically determining whether retraining is necessary. In other words, the storage controller 110 can not send a separate command for confirming a temperature / voltage change to each of the plurality of non-volatile memories NVM. The storage device 100 can prevent performance degradation.

[0092] The operation of the first non-volatile memory NVM 11 described below is applicable to the plurality of non-volatile memories NVM included in the non-volatile memory device 120 according to some embodiments. Figure 5 The plurality of non-volatile memories NVM can perform the operation of the first non-volatile memory NVM 11 described below. For example, each of the plurality of non-volatile memories NVM can perform a transfer error detection operation.

[0093] Figure 1 is a flowchart of an example of the operation of the storage device 100 according to some embodiments. Figure 6 Figure 1 and Figure 7A is a diagram for explaining an example of a transfer error detection operation of the first non-volatile memory NVM 11 according to some embodiments. Figure 7B

[0094] Figure 2 and Figure 7A shows a case where a retraining condition is satisfied. Referring to Figure 7B , Figure 2 , Figure 6 and Figure 7A , the storage controller 110 can communicate with the first non-volatile memory NVM 11 among the plurality of non-volatile memories NVM 11 to NVMmn. The storage controller 110 can perform a write operation with respect to the first non-volatile memory NVM 11. The storage controller 110 can store data in the first non-volatile memory NVM 11. For example, the storage controller 110 can perform a write operation with respect to the first non-volatile memory NVM 11 in response to a write request of an external host device (not shown).

[0095] The storage controller 110 can determine whether retraining with respect to the first non-volatile memory NVM 11 is necessary through the write operation. The storage controller 110 can determine whether to perform retraining with respect to the first non-volatile memory NVM 11 by performing a general write operation without a separate monitoring operation (or a polling operation). In some embodiments, the storage controller 110 can determine whether to perform retraining with respect to the first non-volatile memory NVM 11 by performing a general write operation as well as a monitoring operation.

[0096] ​​In operation S110, the storage controller 110 can generate transmission parity data TP1. The storage controller 110 can generate the transmission parity data TP1 based on the data DT1. The storage controller 110 can divide the data DT1 into a first sub-data DT1_S1, a second sub-data DT1_S2, a third sub-data DT1_S3, and a fourth sub-data DT1_S4. The data DT1 can include the first sub-data DT1_S1, the second sub-data DT1_S2, the third sub-data DT1_S3, and the fourth sub-data DT1_S4. The transmission parity data TP1 can include a first sub-transmission parity data TP1_S1, a second sub-transmission parity data TP1_S2, a third sub-transmission parity data TP1_S3, and a fourth sub-transmission parity data TP1_S4.

[0097] According to some embodiments, the storage controller 110 can divide the data DT1 in the number of data lines DQ. The storage controller 110 can divide the data DT1 into a plurality of sub-data having the same size in the number of data lines DQ. For example, the storage controller 110 can divide the data DT1 into the first sub-data DT1_S1, the second sub-data DT1_S2, the third sub-data DT1_S3, and the fourth sub-data DT1_S4. The first sub-data DT1_S1 to the fourth sub-data DT1_S4 can have the same size.

[0098] For example, the first sub-data DT1_S1 can correspond to the first data line DQ1, the second sub-data DT1_S2 can correspond to the second data line DQ2, the third sub-data DT1_S3 can correspond to the third data line DQ3, and the fourth sub-data DT1_D4 can correspond to the fourth data line DQ4. The first sub-data DT1_S1 can be a first portion of the data DT1, the second sub-data DT1_S2 can be a second portion of the data DT1, the third sub-data DT1_S3 can be a third portion of the data DT1, and the fourth sub-data DT1_S4 can be a fourth portion of the data DT1.

[0099] According to some embodiments, the storage controller 110 can generate the transmission parity data TP1 based on the data DT1. For example, the storage controller 110 can generate the first sub-transmission parity data TP1_S1 based on the first sub-data DT1_S1. The storage controller 110 can generate the second sub-transmission parity data TP1_S2 based on the second sub-data DT1_S2. The storage controller 110 can generate the third sub-transmission parity data TP1_S3 based on the third sub-data DT1_S3. The storage controller 110 can generate the fourth sub-transmission parity data TP1_S4 based on the fourth sub-data DT1_S4.

[0100] For example, the first sub-transfer parity data TP1_S1 can correspond to the first sub-data DT1_S1. The second sub-transfer parity data TP1_S2 can correspond to the second sub-data DT1_S2. The third sub-transfer parity data TP1_S3 can correspond to the third sub-data DT1_S3. The fourth sub-transfer parity data TP1_S4 can correspond to the fourth sub-data DT1_S4.

[0101] In operation S120, the storage controller 110 can send the write command, the data DT1, and the transfer parity data TP1 to the non-volatile memory NVM. The data DT1 can also be data corresponding to the write command. For example, the data DT1 can be user data.

[0102] The storage controller 110 can send the first sub-data DT1_S1 through the first data line DQ1 during the first time period T1. The storage controller 110 can send the second sub-data DT1_S2 through the second data line DQ2 during the first time period T1. The storage controller 110 can send the third sub-data DT1_S3 through the third data line DQ3 during the first time period T1. The storage controller 110 can send the fourth sub-data DT1_S4 through the fourth data line DQ4 during the first time period T1.

[0103] The storage controller 110 can send the first sub-transfer parity data TP1_S1 through the first data line DQ1 during the second time period T2. The storage controller 110 can send the second sub-transfer parity data TP1_S2 through the second data line DQ2 during the second time period T2. The storage controller 110 can send the third sub-transfer parity data TP1_S3 through the third data line DQ3 during the second time period T2. The storage controller 110 can send the fourth sub-transfer parity data TP1_S4 through the fourth data line DQ4 during the second time period T2.

[0104] The first non-volatile memory NVM 11 can receive the first sub-data DT1_S1 and the first sub-transfer parity data TP1_S1 through the first data line DQ1. The first non-volatile memory NVM 11 can receive the second sub-data DT1_S2 and the second sub-transfer parity data TP1_S2 through the second data line DQ2. The first non-volatile memory NVM 11 can receive the third sub-data DT1_S3 and the third sub-transfer parity data TP1_S3 through the third data line DQ3. The first non-volatile memory NVM 11 can receive the fourth sub-data DT1_S4 and the fourth sub-transfer parity data TP1_S4 through the fourth data line DQ4.

[0105] For example, the data received by the non-volatile memory NVM can include errors due to skew of signals of the data lines DQ and signals of the data strobe lines DQS. In other words, the data transmitted by the memory controller 110 and the data received by the first non-volatile memory NVM 11 can be different from each other due to transmission errors. For example, it is assumed that the first sub-data DT1_S1 to the third sub-data DT1_S3 received by the first non-volatile memory NVM 11 include errors and the fourth sub-data DT1_S4 received by the first non-volatile memory NVM 11 does not include errors.

[0106] In operation S130, the first non-volatile memory NVM 11 can perform a transmission error detection operation. The first non-volatile memory NVM 11 can detect errors of the data DT1 based on the transmission parity data TP1. The first non-volatile memory NVM 11 can detect transmission errors for each of the plurality of data lines DQ.

[0107] For example, the first sub-error detection circuit 121_1 can receive the first sub-data DT1_S1 and the first sub-transmission parity data TP1_S1. The second sub-error detection circuit 121_2 can receive the second sub-data DT1_S2 and the second sub-transmission parity data TP1_S2. The third sub-error detection circuit 121_3 can receive the third sub-data DT1_S3 and the third sub-transmission parity data TP1_S3. The fourth sub-error detection circuit 121_4 can receive the fourth sub-data DT1_S4 and the fourth sub-transmission parity data TP1_S4.

[0108] Each of the first sub-error detection circuit 121_1 to the fourth sub-error detection circuit 121_4 can perform a transmission error detection operation. The first sub-error detection circuit 121_1 can detect errors of the first sub-data DT1_S1 based on the first sub-transmission parity data TP1_S1. The second sub-error detection circuit 121_2 can detect errors of the second sub-data DT1_S2 based on the second sub-transmission parity data TP1_S2. The third sub-error detection circuit 121_3 can detect errors of the third sub-data DT1_S3 based on the third sub-transmission parity data TP1_S3. The fourth sub-error detection circuit 121_4 can detect errors of the fourth sub-data DT1_S4 based on the fourth sub-transmission parity data TP1_S4.

[0109] The transmission error detection circuit 121 can generate an error detection result. The transmission error detection circuit 121 can transmit the error detection result to the retraining determination circuit 122. The error detection result can include a first sub-result SR1, a second sub-result SR2, a third sub-result SR3, and a fourth sub-result SR4. The error detection result can include information about whether an error is detected, information about the number of errors included in the data, etc. The first sub-result SR1 can be generated by the first sub-error detection circuit 121_1, the second sub-result SR2 can be generated by the second sub-error detection circuit 121_2, the third sub-result SR3 can be generated by the third sub-error detection circuit 121_3, and the fourth sub-result SR4 can be generated by the fourth sub-error detection circuit 121_4. Each of the first sub-result SR1 to the fourth sub-result SR4 can indicate an error detection result for each corresponding sub-data. For example, the first sub-result SR1 can indicate an error detection result for the first sub-data DT1_S1.

[0110] Because the first sub-data DT1_S1 includes an error, the first sub-error detection circuit 121_1 can detect an error from the first sub-data DT1_S1 based on the first sub-transmission parity data TP1_S1. In other words, the first sub-error detection circuit 121_1 can determine that there is an error in the first sub-data DT1_S1. The first sub-error detection circuit 121_1 can generate the first sub-result SR1 indicating a first value (e.g., 'F'). For example, the first value can indicate that there is an error. A second value (e.g., 'P') can indicate that there is no error.

[0111] Because the second sub-data DT1_S2 includes an error, the second sub-error detection circuit 121_2 can determine that there is an error in the second sub-data DT1_S2 based on the second sub-transmission parity data TP1_S2. The second sub-error detection circuit 121_2 can generate the second sub-result SR2 indicating the first value (e.g., 'F'). Because the third sub-data DT1_S3 includes an error, the third sub-error detection circuit 121_3 can determine that there is an error in the third sub-data DT1_S3 based on the third sub-transmission parity data TP1_S3. The third sub-error detection circuit 121_3 can generate the third sub-result SR3 indicating the first value (e.g., 'F'). Because the fourth sub-data DT1_S4 does not include an error, the fourth sub-error detection circuit 121_4 can determine that there is no error in the fourth sub-data DT1_S4 based on the fourth sub-transmission parity data TP1_S4. The fourth sub-error detection circuit 121_4 can generate the fourth sub-result SR4 indicating the second value (e.g., 'P').

[0112] The transmission error detection circuit 121 can send the error detection results to the retraining determination circuit 122. The first sub error detection circuit 121_1 can send the first sub result SR1 to the retraining determination circuit 122. The second sub error detection circuit 121_2 can send the second sub result SR2 to the retraining determination circuit 122. The third sub error detection circuit 121_3 can send the third sub result SR3 to the retraining determination circuit 122. The fourth sub error detection circuit 121_4 can send the fourth sub result SR4 to the retraining determination circuit 122.

[0113] In operation S140, the first non-volatile memory NVM 11 can determine whether the retraining condition is satisfied based on the error detection results. The retraining determination circuit 122 can receive the error detection results. The retraining determination circuit 122 can determine whether the retraining of the non-volatile memory NVM is necessary based on the error detection results. The retraining determination circuit 122 can determine whether the retraining condition is satisfied based on the error detection results.

[0114] According to some embodiments, the retraining determination circuit 122 can count the number of data lines DQ from which errors are detected as the error detection line number LNUM based on the error detection results. For example, because the first sub result SR1 to the third sub result SR3 indicate the first value and the fourth sub result SR4 indicates the second value, the retraining determination circuit 122 can count the error detection line number LNUM as '3'.

[0115] According to some embodiments, the retraining determination circuit 122 can determine whether the retraining condition is satisfied. The retraining determination circuit 122 can compare the error detection line number LNUM with a predetermined threshold value VTH. The retraining determination circuit 122 can determine whether the error detection line number LNUM is equal to or greater than the threshold value VTH. It is assumed that the threshold value VTH is '3'. However, the scope of the present disclosure is not limited thereto.

[0116] According to some embodiments, the retraining determination circuit 122 can generate a determination result DR. The determination result DR can indicate whether the retraining is necessary. In some embodiments, the determination result DR can indicate whether the storage controller 110 is notified of the occurrence of the transmission error. In some embodiments, the determination result DR can indicate whether the uncorrectable error correction code (UECC) has occurred. The UECC can indicate a state including an error that is not corrected by the ECC engine 115 of the storage controller 110.

[0117] For example, because the number of error detection lines LNUM (e.g., '3') is equal to or greater than the threshold value VTH (e.g., '3'), the retraining determination circuit 122 can determine that the retraining condition is satisfied. The retraining determination circuit 122 can generate a determination result DR indicating a fourth value (e.g., 'Yes'). For example, the third value (e.g., 'No') can indicate that the retraining condition is not satisfied. The fourth value (e.g., 'Yes') can indicate that the retraining condition is satisfied.

[0118] According to some embodiments, when the retraining condition is satisfied, the first non-volatile memory NVM 11 can not perform a program operation to store data in the memory cell array 123. The first non-volatile memory NVM 11 can notify the storage controller 110 that a transfer error has occurred, without storing data including the error in the memory cell array 123.

[0119] According to some embodiments, when the retraining condition is not satisfied, the first non-volatile memory NVM 11 can store data in the memory cell array 123. The first non-volatile memory NVM 11 can perform a program operation in response to a write command. The first non-volatile memory NVM 11 can transmit state information indicating a normal state to the storage controller 110.

[0120] In operation S150, the storage controller 110 can transmit a state read command to the first non-volatile memory NVM 11. In operation S160, the first non-volatile memory NVM 11 can transmit a response to the storage controller 110. The first non-volatile memory NVM 11 can transmit state information (or a response to the state read command) to the storage controller 110.

[0121] According to some embodiments, the retraining determination circuit 122 can transmit the determination result DR to the control logic circuit 128. According to some embodiments, the control logic circuit 128 can generate a response to the state read command based on the determination result DR. For example, the response to the state read command can include a transfer error field. The transfer error field can indicate whether there is a transfer error of such a size that necessitates retraining.

[0122] According to some embodiments, the retraining determination circuit 122 can generate state information based on the determination result DR. The non-volatile memory NVM can notify the storage controller 110 that retraining needs to be performed through the state information. When it is determined that the retraining condition is satisfied, the non-volatile memory NVM can transmit state information indicating a transfer error state to the storage controller 110. When it is determined that the retraining condition is not satisfied, the non-volatile memory NVM can transmit state information indicating a normal state (or an error-free state) to the storage controller 110.

[0123] The storage controller 110 can perform retraining on the first nonvolatile memory NVM 11 in response to the state information indicating the transmission error state. The storage controller 110 can determine to perform retraining based on the state information indicating the transmission error state.

[0124] According to some embodiments, the storage controller 110 can perform retraining only for the first nonvolatile memory NVM 11 among the plurality of nonvolatile memories NVM 11 to NVM mn. However, the scope of the disclosure is not limited thereto. According to some embodiments, the storage controller 110 can perform retraining for the nonvolatile memories NVM 12 to NVM 1n sharing the first channel CH1 with the first nonvolatile memory NVM 11. In some embodiments, the storage controller 110 can perform retraining for all of the plurality of nonvolatile memories NVM 11 to NVM mn.

[0125] As described above, the storage controller 110 can generate a plurality of transmission parity data respectively corresponding to a plurality of data lines DQ. The storage controller 110 can transmit a write command, data, and the plurality of transmission parity data to the first nonvolatile memory NVM 11 through the plurality of data lines DQ. The first nonvolatile memory NVM 11 can perform a transmission error detection operation for each of the plurality of data lines DQ based on each of the plurality of transmission parity data. The first nonvolatile memory NVM 11 can determine whether a retraining execution condition is satisfied based on an error detection result generated in the transmission error detection operation. The storage controller 110 can transmit a state read command to the first nonvolatile memory NVM 11. In response to the state read command, when the retraining execution condition is satisfied, the first nonvolatile memory NVM 11 can transmit state information indicating a transmission error state to the storage controller 110. Accordingly, performance and reliability of the storage device 100 can be improved.

[0126] Figure 7B and Figure 8A is a diagram for explaining an example of a transmission error detection operation of the first nonvolatile memory NVM 11 according to some embodiments of Figure 8B . Figure 2 and Figure 8A shows a case where a retraining condition is not satisfied. For convenience of explanation, detailed descriptions of the first to fourth sub data DT1_S1 to DT1_S4 and the first to fourth transmission parity data TP1_S1 to TP1_S4 described above are omitted.

[0127] In Figure 8B , Figure 2 , Figure 7A , Figure 7B and Figure 8AIn this case, the storage controller 110 can transmit the data DT1 and the transmission parity data TP1 to the first nonvolatile memory NVM 11. Also, the storage controller 110 can transmit the memory parity data to the first nonvolatile memory NVM 11.

[0128] Assuming that the first sub-data DT1_S1 includes a transmission error, and the second sub-data DT1_S2 to the fourth sub-data DT1_S4 do not include transmission errors. The first nonvolatile memory NVM 11 can receive the first sub-data DT1_S1 and the first sub-transmission parity data TP1_S1 through the first data line DQ1. The first nonvolatile memory NVM 11 can receive the second sub-data DT1_S2 and the second sub-transmission parity data TP1_S2 through the second data line DQ2. The first nonvolatile memory NVM 11 can receive the third sub-data DT1_S3 and the third sub-transmission parity data TP1_S3 through the third data line DQ3. The first nonvolatile memory NVM 11 can receive the fourth sub-data DT1_S4 and the fourth sub-transmission parity data TP1_S4 through the fourth data line DQ4.

[0129] Because the first sub-data DT1_S1 includes an error, the first sub-error detection circuit 121_1 can detect an error from the first sub-data DT1_S1 based on the first sub-transmission parity data TP1_S1. In other words, the first sub-error detection circuit 121_1 can determine that there is an error in the first sub-data DT1_S1. The first sub-error detection circuit 121_1 can generate the first sub-result SR1 indicating a first value (e.g., ‘F’).

[0130] Because the second sub-data DT1_S2 does not include an error, the second sub-error detection circuit 121_2 can determine that there is no error in the second sub-data DT1_S2 based on the second sub-transmission parity data TP1_S2. The second sub-error detection circuit 121_2 can generate the second sub-result SR2 indicating a second value (e.g., ‘P’). Because the third sub-data DT1_S3 does not include an error, the third sub-error detection circuit 121_3 can determine that there is no error in the third sub-data DT1_S3 based on the third sub-transmission parity data TP1_S3. The third sub-error detection circuit 121_3 can generate the third sub-result SR3 indicating the second value (e.g., ‘P’). Because the fourth sub-data DT1_S4 does not include an error, the fourth sub-error detection circuit 121_4 can determine that there is no error in the fourth sub-data DT1_S4 based on the fourth sub-transmission parity data TP1_S4. The fourth sub-error detection circuit 121_4 can generate the fourth sub-result SR4 indicating the second value (e.g., ‘P’).

[0131] Because the first sub-result SR1 indicates the first value and the second sub-result SR2 to the fourth sub-result SR4 indicate the second value, the retraining determination circuit 122 can count the error detection line number LNUM as ‘1’. Because the error detection line number LNUM (e.g., ‘1’) is less than the threshold value VTH (e.g., ‘3’), the retraining determination circuit 122 can determine that the retraining condition is not satisfied. The retraining determination circuit 122 can generate the determination result DR indicating the third value (e.g., “No”).

[0132] The first non-volatile memory NVM 11 can generate the state information indicating the normal state based on the determination result DR indicating the third value. In response to the state read command, the first non-volatile memory NVM 11 can transmit the state information indicating the normal state to the storage controller 110.

[0133] Figure 8B is a flowchart of an example of an operation of a first non-volatile memory NVM 11 according to some embodiments. Figure 9 Figure 2 and Figure 2 In operation S210, the first non-volatile memory NVM 11 can receive a write command, data DT1, and transmission parity data TP1. As described above, the transmission parity data TP1 can include a plurality of sub-transmission parity data TP1_S1 to TP1_S4 (i.e., a first sub-transmission parity data TP1_S1, a second sub-transmission parity data TP1_S2, a third sub-transmission parity data TP1_S3, and a fourth sub-transmission parity data TP1_S4). The transmission parity data TP1 can be parity data for detecting a transmission error.

[0134] According to some embodiments, the first non-volatile memory NVM 11 can further receive memory parity data. In other words, the first non-volatile memory NVM 11 can receive a write command, data DT1, memory parity data, and transmission parity data TP1. The memory parity data can be parity data for detecting a memory cell error.

[0135] According to some embodiments, the first non-volatile memory NVM 11 can perform a decoding operation based on the transmission parity data TP1. The first non-volatile memory NVM 11 can detect an error of the data DT1 based on the transmission parity data TP1. The storage controller 110 can perform a decoding operation based on the memory parity data. The storage controller 110 can detect an error from the data DT1 based on the memory parity data.

[0136] ​According to some embodiments, the first non-volatile memory NVM 11 can detect an error of each of the plurality of data lines DQ1 to DQ4. In other words, the first non-volatile memory NVM 11 can detect an error of the first sub data DT1_S1 corresponding to the first data line DQ1 based on the first sub transmission parity data TP1_S1. The first non-volatile memory NVM 11 can detect an error of the second sub data DT1_S2 corresponding to the second data line DQ2 based on the second sub transmission parity data TP1_S2. The storage controller 110 can detect an error of the data DT1 based on the memory parity data. The storage controller 110 can detect an error from the overall data DT1 in addition to the error of each of the plurality of data lines DQ1 to DQ4. The storage controller 110 can detect an error of the overall data DT1 based on the overall memory parity data.

[0137] In operation S220, the first non-volatile memory NVM 11 can perform a transmission error detection operation. The first non-volatile memory NVM 11 can detect a transmission error of each of the plurality of data lines DQ1 to DQ4. The first non-volatile memory NVM 11 can generate an error detection result.

[0138] In operation S230, the first non-volatile memory NVM 11 can update transmission error information. The first non-volatile memory NVM 11 can update the transmission error information based on the error detection result. The first non-volatile memory NVM 11 can store the transmission error information in a memory circuit included in the first non-volatile memory NVM 11. For example, the memory circuit can include a plurality of latch circuits.

[0139] According to some embodiments, the transmission error information can include a history of the error detection result. The first non-volatile memory NVM 11 can accumulate the error detection result, and transmit the accumulated error detection result as the transmission error information. For example, the transmission error information can include at least one of identifier information of a data line from which a transmission error has been detected, a number of errors detected in data, and a time at which an error was detected. The transmission error information can include information required to analyze a transmission error. The transmission error information can additionally include a temperature when a transmission error is detected, a reference voltage when a transmission error is detected, and an oscillator value when a transmission error is detected.

[0140] In operation S240, the first non-volatile memory NVM 11 can determine whether a retraining condition has been satisfied. The retraining condition can be determined in advance. According to some embodiments, the retraining condition can include whether a UECC is likely to occur. By adjusting the retraining condition, a channel bit error rate (BER) tolerance range can be determined. The storage device 100 can optimize input / output power by determining a channel BER.

[0141] According to some embodiments, the first nonvolatile memory NVM 11 can determine the number of data lines from which errors have been detected. When the number of data lines from which errors have been detected is greater than or equal to a threshold value, the first nonvolatile memory NVM 11 can determine that the retraining condition has been satisfied. When the number of data lines from which errors have been detected is less than the threshold value, the first nonvolatile memory NVM 11 can determine whether the retraining condition is satisfied. The first nonvolatile memory NVM 11 can perform operation S260 when the retraining condition has been satisfied, and can perform operation S250 when the retraining condition has not been satisfied.

[0142] In operation S250, in response to the status read command, the first nonvolatile memory NVM 11 can transmit status information indicating a normal state to the memory controller 110. The first nonvolatile memory NVM 11 can store the received data in the memory cell array 123.

[0143] According to some embodiments, the first nonvolatile memory NVM 11 can store both data and transmission parity data in the memory cell array 123. According to some embodiments, the first nonvolatile memory NVM 11 can store only data in the memory cell array 123, and can not store the transmission parity data TP1 in the memory cell array 123. Because the first nonvolatile memory NVM 11 does not store the transmission parity data, the first nonvolatile memory NVM 11 can more efficiently use storage space. Because the first nonvolatile memory NVM 11 has used the transmission parity data in the transmission error detection operation, the first nonvolatile memory NVM 11 can not store the transmission parity data.

[0144] According to some embodiments, when the first nonvolatile memory NVM 11 receives data, memory parity data, and transmission parity data in operation S210, the first nonvolatile memory NVM 11 can store all of the data, the memory parity data, and the transmission parity data in the memory cell array 123. In this case, because the transmission parity data is additionally stored in the memory cell array 123, the size of the memory parity data can be smaller than when the transmission parity data is not stored.

[0145] According to some embodiments, the first non-volatile memory NVM 11 can store only the data and the memory parity data in the memory cell array 123, and can not store the transfer parity data in the memory cell array 123. The first non-volatile memory NVM 11 can store the memory parity data in the memory cell array 123, and then, in response to a read command, the first non-volatile memory NVM 11 can transmit both the data DT1 and the memory parity data to the memory controller 110. The memory parity data is used to resolve memory cell reliability issues. Thus, in order for the memory controller 110 to detect errors in the read data, the first non-volatile memory NVM 11 can store the memory parity data in the memory cell array 123, and then transmit the memory parity data to the memory controller 110 along with the read data.

[0146] After programming the data in the memory cell array 123, the first non-volatile memory NVM 11 can transmit state information indicating a normal state to the memory controller 110. According to some embodiments, when the first non-volatile memory NVM 11 has failed at programming time, the first non-volatile memory NVM 11 can transmit state information indicating a programming failure state to the memory controller 110.

[0147] In operation S260, in response to a state read command, the first non-volatile memory NVM 11 can transmit state information indicating a transfer error state to the memory controller 110. When the retraining condition has been satisfied, the first non-volatile memory NVM 11 can not perform a programming operation. The first non-volatile memory NVM 11 can not store data including an error in the memory cell array 123. The first non-volatile memory NVM 11 can receive a state read command. In response to the state read command, the first non-volatile memory NVM 11 can transmit state information indicating a transfer error state to the memory controller 110. For example, the first non-volatile memory NVM 11 can output the state information indicating the transfer error state through a plurality of data lines DQ.

[0148] Thus, the first non-volatile memory NVM 11 can inform the memory controller 110 that a transfer error has occurred. The first non-volatile memory NVM 11 can actively inform the memory controller 110 that retraining is to be performed. Thus, the memory device 100 can not perform monitoring of the plurality of non-volatile memories NVM11 to NVMnm of the memory controller 110. The memory device 100 can perform retraining triggered by each of the plurality of non-volatile memories NVM11 to NVM1n. The memory device 100 can selectively perform retraining for the first non-volatile memory NVM 11 that needs retraining. Thus, a memory device with improved performance and reliability is provided.

[0149] Figure 9 is an example of the operation of the storage controller 110 according to some embodiments. Figure 10 Figure 1 and Figure 1 In the storage controller 110, the retraining operation can be performed for at least one of the plurality of nonvolatile memories NVM11 to NVMmn.

[0150] In operation S310, the storage controller 110 can receive state information indicating a transfer error state from the first nonvolatile memory NVM11. The storage controller 110 can not transmit a separate command for determining a retraining time of the first nonvolatile memory NVM11. The storage controller 110 can determine the retraining time of the first nonvolatile memory NVM11 through a write operation of the first nonvolatile memory NVM11 as a normal operation.

[0151] In operation S320, the storage controller 110 can perform a retraining operation for the first nonvolatile memory NVM11. The retraining operation can include at least one of a reference voltage training operation, a duty cycle correction training operation, a read training operation, and a write training operation. The retraining operation will be described in detail with reference to Figure 10

[0152] As described above, the storage controller 110 can determine the retraining time of the first nonvolatile memory NVM11 through a general write operation without a monitoring operation. The storage controller 110 can determine whether to perform retraining based on the state information. The storage controller 110 can perform retraining in response to the state information indicating a transfer error state. The storage controller 110 can perform at least one of a reference voltage training operation, a double data rate (DCC) training operation, a read training operation, and a write training operation for the first nonvolatile memory NVM11.

[0153] Figure 11 is an example of the operation S320 of the storage controller 110 according to some embodiments. Figure 11 Figure 10 , Figure 2 and Figure 10 In the storage controller 110, the retraining operation can be performed for at least one of the plurality of nonvolatile memories NVM11 to NVMmn.

[0154] ​​​In operation S321, the storage controller 110 can perform a reference voltage training operation with respect to the first nonvolatile memory NVM 11. In operation S322, the storage controller 110 can perform a DCC training operation with respect to the first nonvolatile memory NVM 11.

[0155] In the DDR mode, each of the signals of the plurality of data lines DQ can be sequentially sampled in synchronization with rising and falling edges of a signal of a data strobe line DQS. Each of the signals of the plurality of data lines DQ can be divided into a logic high interval and a logic low interval based on a reference voltage level. For example, in each of the signals of the plurality of data lines DQ, an interval higher than the reference voltage level can be distinguished as a logic high interval, and an interval lower than the reference voltage level can be distinguished as a logic low interval. Based on the reference voltage level, a data window of the signals of the first and second data lines can be determined according to a ratio of the logic high interval to the logic low interval of first and second data sampled based on the signal of the data strobe line DQS.

[0156] When a "duty mismatch" occurs in each of the signals of the plurality of data lines DQ, the logic high interval and the logic low interval of each of the signals of the plurality of data lines DQ can have different lengths. In other words, the ratio between the logic high interval and the logic low interval can not be 1:1. At this time, the signals of the first and second data lines can have data windows of different lengths, and the effective data window of the signals of the first and second data lines can decrease, resulting in degradation of the performance of the storage device 100. Accordingly, a method of securing an effective data window by performing duty correction based on a reference voltage level is required to address the duty mismatch of each of the signals of the plurality of data lines DQ. The storage device 100 can perform a reference voltage training operation of determining a reference voltage level for addressing the duty mismatch.

[0157] According to some embodiments, the storage device 100 can perform a DCC training operation to address the duty mismatch of each of the signals of the plurality of data lines DQ. The storage device 100 can adjust the ratio between the logic high interval and the logic low interval to a desired ratio (e.g., 1:1) by using the DCC training.

[0158] In operation S323, the storage controller 110 can perform a read training operation with respect to the first nonvolatile memory NVM 11. In operation S324, the storage controller 110 can perform a write training operation with respect to the first nonvolatile memory NVM 11.

[0159] Even when the phases of the signals are aligned at the transmission time, skew can occur between the points in time when multiple signals arrive at the receiver due to noise during communication processing. For the receiving device to sample the signals on the data lines DQ to generate accurate data DATA, an optimal delay needs to be applied to the signal on the data gate line DQS. The delay required for the signal on the data gate line DQS to accurately sample each of the signals on the multiple data lines DQ is called the target delay. When the delay applied to the signal on the data gate line DQS is not the target delay or the data skew is not resolved, the likelihood of communication errors occurring in the storage device 100 can increase. The storage device 100 can perform a training operation to determine the alignment of the signals on the multiple data lines DQ between the storage controller 110 and each of the multiple non-volatile memories NVM11 to NVMnm, as well as the target delay of the signal on the data gate line DQS. The storage device 100 can perform training (e.g., read training or write training) to increase the accuracy of communication when performing all functions.

[0160] Figure 11 It is based on some implementation methods Figure 12 A flowchart illustrating an example of the operation of storage device 100. Figure 2 and Figure 2 In this device, storage device 100 can detect transmission errors by performing a transmission error detection operation. Storage device 100 can generate transmission error information based on the result of the transmission error detection. Storage device 100 can store the transmission error information.

[0161] In operation S410, the storage controller 110 may send a transmission error information request command to the first non-volatile memory NVM 11. According to some embodiments, the transmission error information request command may be a feature acquisition command or a vendor command. However, the scope of this disclosure is not limited thereto.

[0162] In operation S420, the first non-volatile memory NVM11 can send transmission error information to the memory controller 110. The first non-volatile memory NVM11 can receive transmission error information request commands. In response to the transmission error information request commands, the first non-volatile memory NVM11 can send stored transmission error information to the memory controller 110. For example, the first non-volatile memory NVM11 can output transmission error information via multiple data lines DQ.

[0163] Figure 12 It is based on some implementation methods Figure 13 A flowchart illustrating an example of the operation of the storage controller 110. Figure 2 and Figure 2In some embodiments, the storage controller 110 can perform a retraining based on the state information indicating a transfer error state and the transfer error information.

[0164] In operation S510, the storage controller 110 can receive state information indicating a transfer error state from the first nonvolatile memory NVM 11. In operation S520, the storage controller 110 can transmit a transfer error information request command to the first nonvolatile memory NVM 11. The storage controller 110 can transmit the transfer error information request command to the first nonvolatile memory NVM 11 in response to the state information indicating a transfer error state, instead of immediately performing a retraining on the first nonvolatile memory NVM 11. The storage controller 110 can request more information from the first nonvolatile memory NVM 11 in order to determine whether to perform a retraining. Accordingly, the storage controller 110 can transmit the transfer error information request command to the first nonvolatile memory NVM 11. In operation S530, the storage controller 110 can receive transfer error information from the first nonvolatile memory NVM 11.

[0165] In operation S540, the storage controller 110 can determine whether to perform a retraining. According to some embodiments, the storage controller 110 can determine whether to perform a retraining based on the transfer error information. The storage controller 110 can perform operation S550 upon determining to perform a retraining, and can not perform operation S550 upon determining not to perform a retraining. According to an embodiment, the storage controller 110 can determine a type of training or a range of training based on the transfer error information.

[0166] According to some embodiments, the storage controller 110 can determine what training operation to perform in a retraining operation based on the transfer error information. In other words, the storage controller 110 can determine a type of training based on the transfer error information. For example, the storage controller 110 can determine to perform at least one of a reference voltage training operation, a DCC training operation, a read training operation, and a write training operation. The storage controller 110 can determine to perform only a write operation for the first nonvolatile memory NVM 11.

[0167] According to some embodiments, the storage controller 110 can perform a training operation for all of the plurality of data lines DQ. In some embodiments, the storage controller 110 can determine a data line to undergo a training operation from all of the plurality of data lines DQ. In other words, the storage controller 110 can determine a range of training based on the transfer error information. The storage controller 110 can select at least one of the plurality of data lines DQ.

[0168] For example, the storage controller 110 can identify that a transmission error has been detected from the first to third data lines DQ1 to DQ3 through the transmission error information. For example, the storage controller 110 can identify that a transmission error has not been detected from the fourth data line DQ4 through the transmission error information. Accordingly, the storage controller 110 can determine to perform training for the first to third data lines DQ1 to DQ3 of the first nonvolatile memory NVM 11. The storage controller 110 can determine not to perform training for the fourth data line DQ4 of the first nonvolatile memory NVM 11.

[0169] In operation S550, the storage controller 110 can perform a re-training operation for the first nonvolatile memory NVM 11. The storage controller 110 can perform the re-training based on the determined type of training or the determined range of training. For example, the storage controller 110 can perform a write training for the first to third data lines DQ1 to DQ3 of the first nonvolatile memory NVM 11. The storage controller 110 can not perform training for the fourth data line DQ4 of the first nonvolatile memory NVM 11.

[0170] According to some embodiments, the storage controller 110 can perform a normal operation for the second nonvolatile memory NVM 21 while performing the re-training for the first nonvolatile memory NVM 11. The second nonvolatile memory NVM 21 can not share a channel with the first nonvolatile memory NVM 11. The channel of the first nonvolatile memory NVM 11 and the channel of the second nonvolatile memory NVM 21 can be different from each other. The storage controller 110 can perform a read operation or a write operation for the second nonvolatile memory NVM 21 while performing the re-training operation for the first nonvolatile memory NVM 11.

[0171] Figure 13 is a flowchart of an example of an operation of the storage device 100 according to some embodiments. Figure 14 In operation S550, the storage controller 110 can perform a re-training operation for the first nonvolatile memory NVM 11. The storage controller 110 can perform the re-training based on the determined type of training or the determined range of training. For example, the storage controller 110 can perform a write training for the first to third data lines DQ1 to DQ3 of the first nonvolatile memory NVM 11. The storage controller 110 can not perform training for the fourth data line DQ4 of the first nonvolatile memory NVM 11. Figure 2 and Figure 2 In operation S550, the storage controller 110 can perform a re-training operation for the first nonvolatile memory NVM 11. The storage controller 110 can perform the re-training based on the determined type of training or the determined range of training. For example, the storage controller 110 can perform a write training for the first to third data lines DQ1 to DQ3 of the first nonvolatile memory NVM 11. The storage controller 110 can not perform training for the fourth data line DQ4 of the first nonvolatile memory NVM 11.

[0172] In operation S610, the storage controller 110 can transmit a threshold setting command to the first nonvolatile memory NVM 11. According to some embodiments, the threshold setting command can be a set feature command or a vendor command. However, the scope of the present disclosure is not limited thereto. According to some embodiments, the threshold setting command can include information about a threshold value to be changed.

[0173] In operation S620, the first non-volatile memory NVM 11 can update the threshold value. The first non-volatile memory NVM 11 can receive a threshold value set command. The first non-volatile memory NVM 11 can update the threshold value in response to the threshold value set command. For example, the first non-volatile memory NVM 11 can store the threshold value in a register included in the first non-volatile memory NVM 11. The first non-volatile memory NVM 11 can store the threshold value included in the threshold value set command in the register. The first non-volatile memory NVM 11 can update the changed threshold value. For example, the first non-volatile memory NVM 11 can adjust the threshold value to '2'.

[0174] In operation S630, the storage controller 110 can transmit a write command, data, and transfer parity data to the first non-volatile memory NVM 11. In operation S640, the first non-volatile memory NVM 11 can perform a transfer error detection operation. In operation S650, the first non-volatile memory NVM 11 can determine whether a retraining condition has been satisfied based on the updated threshold value. The first non-volatile memory NVM 11 can count the number of data lines from which an error has been detected. The first non-volatile memory NVM 11 can compare the error detection line number LNUM with the threshold value. For example, the first non-volatile memory NVM 11 can compare the error detection line number LNUM with the changed threshold value (e.g., '2').

[0175] In operation S660, the storage controller 110 can transmit a status read command to the first non-volatile memory NVM 11. In operation S670, in response to the status read command, the first non-volatile memory NVM 11 can transmit status information to the storage controller 110. When the error detection line number LNUM is equal to or greater than the changed threshold value, the first non-volatile memory NVM 11 can transmit status information indicating a transfer error state to the storage controller 110. When the error detection line number LNUM is less than the changed threshold value, the first non-volatile memory NVM 11 can transmit status information indicating a normal state to the storage controller 110.

[0176] In operation S680, the storage controller 110 can perform retraining. The storage controller 110 can perform retraining on the first non-volatile memory NVM 11 in response to the status information indicating the transfer error state. Alternatively, the storage controller 110 can obtain transfer error information through a transfer error information request command. The storage controller 110 can perform retraining based on the transfer error information.

[0177] The storage controller 110 may refrain from performing the operation of operation S680 in response to status information indicating a normal state. In other words, the storage controller 110 may refrain from performing retraining in response to status information indicating a normal state.

[0178] Figure 14 It is based on some implementation methods Figure 15 A flowchart illustrating an example of the operation of storage device 100. Figure 2 and Figure 2 In this configuration, storage device 100 can activate or deactivate a transmission error detection operation. Storage controller 110 can send a transmission error detection activation command. Based on the transmission error detection activation command, first non-volatile memory NVM 11 can perform a transmission error detection operation in response to a subsequently received write command. Storage controller 110 can send a transmission error detection deactivation command. Based on the transmission error detection deactivation command, first non-volatile memory NVM 11 can not perform a transmission error detection operation in response to a subsequently received write command.

[0179] In operation S701, the storage controller 110 may send a transmission error detection activation command. The transmission error detection activation command may refer to a command used to activate transmission error detection operation within the first non-volatile memory NVM 11. The first non-volatile memory NVM 11 may receive the transmission error detection activation command. The first non-volatile memory NVM 11 may activate a transmission error detection flag in response to the transmission error detection activation command. The transmission error detection flag may be stored in a register included in the first non-volatile memory NVM 11.

[0180] In operation S702, the storage controller 110 can send write commands, data, and transfer parity data to the first non-volatile memory NVM 11. The storage controller 110 can generate transfer parity data based on the data. The storage controller 110 can also send memory parity data.

[0181] In operation S703, the first non-volatile memory NVM11 can perform a transmission error detection operation. The first non-volatile memory NVM11 can perform a transmission error detection operation in response to an activated transmission error detection flag. The first non-volatile memory NVM11 can detect errors on each of the multiple data lines DQ.

[0182] In operation S704, the first nonvolatile memory NVM 11 can determine whether a retraining condition is satisfied based on a result of the error detection. For example, the first nonvolatile memory NVM 11 can count a number of data lines from which an error has been detected. The first nonvolatile memory NVM 11 can compare the number of data lines from which an error has been detected with a threshold. The first nonvolatile memory NVM 11 can determine whether the number of data lines from which an error has been detected is equal to or greater than the threshold.

[0183] In operation S705, the first nonvolatile memory NVM 11 can perform a program operation. When the retraining condition has not been satisfied, the first nonvolatile memory NVM 11 can perform the program operation. The first nonvolatile memory NVM 11 can store data in the memory cell array. When the retraining condition has been satisfied, the first nonvolatile memory NVM 11 can not perform the operation of operation S705.

[0184] In operation S706, the first nonvolatile memory NVM 11 can transmit state information to the storage controller 110. When the retraining condition has been satisfied, in response to a state read command, the first nonvolatile memory NVM 11 can transmit state information indicating a transmission error state to the storage controller 110. When the retraining condition has not been satisfied, in response to the state read command, the first nonvolatile memory NVM 11 can transmit state information indicating a normal state to the storage controller 110. In response to the state information indicating the transmission error state, the storage controller 110 can perform retraining with respect to the first nonvolatile memory NVM 11.

[0185] In operation S707, the storage controller 110 can transmit a transmission error detection deactivation command to the first nonvolatile memory NVM 11. The transmission error detection deactivation command can refer to a command for deactivating a transmission error detection operation within the first nonvolatile memory NVM 11. The first nonvolatile memory NVM 11 can receive the transmission error detection deactivation command. The first nonvolatile memory NVM 11 can deactivate the transmission error detection flag in response to the transmission error detection deactivation command.

[0186] In operation S708, the storage controller 110 can transmit a write command and data to the first nonvolatile memory NVM 11. The storage controller 110 can also transmit memory parity data. The storage controller 110 can not generate transmission parity data based on the data. The storage controller 110 can not transmit the transmission parity data to the first nonvolatile memory NVM 11.

[0187] The first non-volatile memory NVM11 may not perform a transmission error detection operation. The first non-volatile memory NVM11 may not perform a transmission error detection operation in response to a deactivated transmission error detection flag.

[0188] In operation S709, the first non-volatile memory NVM11 can perform programming operations. The first non-volatile memory NVM11 can store data in the memory cell array. According to an embodiment, the first non-volatile memory NVM11 can store memory parity data in the memory cell array.

[0189] In operation S710, the first non-volatile memory NVM11 can send status information to the memory controller 110. In response to a status read command, the first non-volatile memory NVM11 can send status information indicating a normal state to the memory controller 110.

[0190] Figure 15 It is based on some implementation methods Figure 16 A flowchart illustrating an example of the operation of storage device 100. Figure 2 and Figure 2 In this process, the storage device 100 can determine the retraining time based on at least one of transmission error information, the oscillator value of the data strobe signal, temperature information, and voltage information.

[0191] According to some implementations, the storage controller 110 can monitor the temperature and voltage of each of the plurality of non-volatile memory (NVMs). The storage controller 110 can receive temperature or voltage information from the plurality of NVMs. The storage controller 110 can periodically request temperature or voltage information from each of the plurality of NVMs. The storage controller 110 can determine, based on the temperature or voltage information, whether to perform retraining on each of the plurality of NVMs.

[0192] In operation S810, the storage controller 110 may send a transmission error information request command to the first non-volatile memory NVM 11. For example, in response to status information indicating a transmission error state, the storage controller 110 may send a transmission error information request command to the first non-volatile memory NVM 11. In operation S820, the first non-volatile memory NVM 11 may send transmission error information to the storage controller 110. In response to the transmission error information request command, the first non-volatile memory NVM 11 may send stored transmission error information to the storage controller 110.

[0193] In operation S830, the memory controller 110 can transmit an oscillator activation command to the first nonvolatile memory NVM 11. In operation S840, the first nonvolatile memory NVM 11 can perform an oscillator monitoring operation. For example, the first nonvolatile memory NVM 11 can perform the oscillator monitoring operation in response to the oscillator activation command. That is, the first nonvolatile memory NVM 11 can monitor an oscillator value of a data strobe signal. For example, the oscillator value can indicate an oscillator count value. The oscillator monitoring operation can refer to an operation of counting a number of oscillations of a signal (or a data strobe signal) of the data strobe line DQS. The first nonvolatile memory NVM 11 can count the number of oscillations of the signal (or the data strobe signal) of the data strobe line DQS.

[0194] In operation S850, the memory controller 110 can transmit an oscillator request command to the first nonvolatile memory NVM 11. For example, the memory controller 110 can request an oscillator count value. In operation S860, the first nonvolatile memory NVM 11 can transmit an oscillator value to the memory controller 110. For example, the first nonvolatile memory NVM 11 can transmit the oscillator count value of the data strobe signal in response to the oscillator request command.

[0195] In operation S870, the memory controller 110 can determine whether to perform retraining based on the oscillator value and the transmission error information. However, the scope of the disclosure is not limited thereto, and the memory controller 110 can determine whether to perform retraining based on at least one of the transmission error information, the oscillator value of the data strobe signal, temperature information, and voltage information.

[0196] In operation S880, the memory controller 110 can perform retraining for the first nonvolatile memory NVM 11. The memory controller 110 can determine that retraining is needed based on the oscillator value and the transmission error information. In this case, the memory controller 110 can perform a retraining operation for the first nonvolatile memory NVM 11.

[0197] Figure 15 and Figure 17A is a diagram for explaining an example of a transmission error detection operation of the first nonvolatile memory NVM 11 according to some embodiments of the disclosure. Figure 17B , Figure 2 , Figure 2 and Figure 17A Figure 17BIn particular embodiments, the first non-volatile memory NVM 11 can determine whether a retraining condition has been satisfied based on accumulated error detection results. For example, the first non-volatile memory NVM 11 can receive first data DT1 during a first time period T1, and can receive first transmission parity data TP1 during a second time period T2. The first transmission parity data TP1 can correspond to the first data DT1. The first transmission parity data TP1 can be transmission parity data for the first data DT1.

[0198] The first non-volatile memory NVM 11 can receive second data DT2 during a third time period T3, and can receive second transmission parity data TP2 during a fourth time period T4. The second transmission parity data TP2 can correspond to the second data DT2. The first non-volatile memory NVM 11 can receive third data DT3 during a fifth time period T5, and can receive third transmission parity data TP3 during a sixth time period T6. The third transmission parity data TP3 can correspond to the third data DT3. The first non-volatile memory NVM 11 can receive fourth data DT4 during a seventh time period T7, and can receive fourth transmission parity data TP4 during an eighth time period T8. The fourth transmission parity data TP4 can correspond to the fourth data DT4.

[0199] For example, the first data DT1 can include first sub-data DT1_S1, second sub-data DT1_S2, third sub-data DT1_S3, and fourth sub-data DT1_S4, and the first transmission parity data TP1 can include first sub-transmission parity data TP1_S1, second sub-transmission parity data TP1_S2, third sub-transmission parity data TP1_S3, and fourth sub-transmission parity data TP1_S4. The first sub-transmission parity data TP1_S1 can correspond to the first sub-data DT1_S1, the second sub-transmission parity data TP1_S2 can correspond to the second sub-data DT1_S2, the third sub-transmission parity data TP1_S3 can correspond to the third sub-data DT1_S3, and the fourth sub-transmission parity data TP1_S4 can correspond to the fourth sub-data DT1_S4.

[0200] The second data DT2 can include first, second, third, and fourth sub data DT2_S1, DT2_S2, DT2_S3, and DT2_S4, and the second transmission parity data TP2 can include first, second, third, and fourth sub transmission parity data TP2_S1, TP2_S2, TP2_S3, and TP2_S4. The first sub transmission parity data TP2_S1 can correspond to the first sub data DT2_S1, the second sub transmission parity data TP2_S2 can correspond to the second sub data DT2_S2, the third sub transmission parity data TP2_S3 can correspond to the third sub data DT2_S3, and the fourth sub transmission parity data TP2_S4 can correspond to the fourth sub data DT2_S4.

[0201] The third data DT3 can include first, second, third, and fourth sub data DT3_S1, DT3_S2, DT3_S3, and DT3_S4, and the third transmission parity data TP3 can include first, second, third, and fourth sub transmission parity data TP3_S1, TP3_S2, TP3_S3, and TP3_S4. The first sub transmission parity data TP3_S1 can correspond to the first sub data DT3_S1, the second sub transmission parity data TP3_S2 can correspond to the second sub data DT3_S2, the third sub transmission parity data TP3_S3 can correspond to the third sub data DT3_S3, and the fourth sub transmission parity data TP3_S4 can correspond to the fourth sub data DT3_S4.

[0202] The fourth data DT4 can include first, second, third, and fourth sub data DT4_S1, DT4_S2, DT4_S3, and DT4_S4, and the fourth transmission parity data TP4 can include first, second, third, and fourth sub transmission parity data TP4_S1, TP4_S2, TP4_S3, and TP4_S4. The first sub transmission parity data TP4_S1 can correspond to the first sub data DT4_S1, the second sub transmission parity data TP4_S2 can correspond to the second sub data DT4_S2, the third sub transmission parity data TP4_S3 can correspond to the third sub data DT4_S3, and the fourth sub transmission parity data TP4_S4 can correspond to the fourth sub data DT4_S4.

[0203] The first non-volatile memory NVM 11 can receive the first sub-data DT1_S1, the first sub-transfer parity data TP1_S1, the first sub-data DT2_S1, the first sub-transfer parity data TP2_S1, the first sub-data DT3_S1, the first sub-transfer parity data TP3_S1, the first sub-data DT4_S1, and the first sub-transfer parity data TP4_S1 through the first data line DQ1. The first non-volatile memory NVM 11 can receive the second sub-data DT1_S2, the second sub-transfer parity data TP1_S2, the second sub-data DT2_S2, the second sub-transfer parity data TP2_S2, the second sub-data DT3_S2, the second sub-transfer parity data TP3_S2, the second sub-data DT4_S2, and the second sub-transfer parity data TP4_S2 through the second data line DQ2. The first non-volatile memory NVM 11 can receive the third sub-data DT1_S3, the third sub-transfer parity data TP1_S3, the third sub-data DT2_S3, the third sub-transfer parity data TP2_S3, the third sub-data DT3_S3, the third sub-transfer parity data TP3_S3, the third sub-data DT4_S3, and the third sub-transfer parity data TP4_S3 through the third data line DQ3. The first non-volatile memory NVM 11 can receive the fourth sub-data DT1_S4, the fourth sub-transfer parity data TP1_S4, the fourth sub-data DT2_S4, the fourth sub-transfer parity data TP2_S4, the fourth sub-data DT3_S4, the fourth sub-transfer parity data TP3_S4, the fourth sub-data DT4_S4, and the fourth sub-transfer parity data TP4_S4 through the fourth data line DQ4.

[0204] The transfer error detection circuit 121 can perform a transfer error detection operation for the first sub-data DT1_S1 based on the first sub-transfer parity data TP1_S1, can perform a transfer error detection operation for the second sub-data DT1_S2 based on the second sub-transfer parity data TP1_S2, can perform a transfer error detection operation for the third sub-data DT1_S3 based on the third sub-transfer parity data TP1_S3, and can perform a transfer error detection operation for the fourth sub-data DT1_S4 based on the fourth sub-transfer parity data TP1_S4.

[0205] The transmission error detection circuit 121 can perform a transmission error detection operation for the first sub-data DT2_S1 based on the first sub-transmission parity data TP2_S1, can perform a transmission error detection operation for the second sub-data DT2_S2 based on the second sub-transmission parity data TP2_S2, can perform a transmission error detection operation for the third sub-data DT2_S3 based on the third sub-transmission parity data TP2_S3, and can perform a transmission error detection operation for the fourth sub-data DT2_S4 based on the fourth sub-transmission parity data TP2_S4. Because the remaining sub-data DT3_S1 to DT3_S4 and DT4_S1 to DT4_S4 are similar to the sub-data DT1_S1 to DT1_S4 and DT2_S1 to DT2_S4, detailed descriptions thereof are omitted.

[0206] Assuming that the first sub-data DT1_S1, the first sub-data DT3_D1, the third sub-data DT3_S3, and the fourth sub-data DT4_S4 include transmission errors. The first non-volatile memory NVM 11 can generate a first error detection result based on the first data DT1 and the first transmission parity data TP1. For example, because the first sub-data DT1_S1 includes an error, a first sub-result of the first error detection result EDR1 can indicate a first value 'F'. Because the second sub-data DT1_S2 does not include an error, a second sub-result of the first error detection result EDR1 can indicate a second value 'P'. Because the third sub-data DT1_S3 does not include an error, a third sub-result of the first error detection result EDR1 can indicate the second value 'P'. Because the fourth sub-data DT1_S4 does not include an error, a fourth sub-result of the first error detection result EDR1 can indicate the second value 'P'.

[0207] For example, because the first sub-data DT2_S1 does not include an error, a first sub-result of the second error detection result EDR2 can indicate the second value 'P'. Because the second sub-data DT2_S2 does not include an error, a second sub-result of the second error detection result EDR2 can indicate the second value 'P'. Because the third sub-data DT2_S3 does not include an error, a third sub-result of the second error detection result EDR2 can indicate the second value 'P'. Because the fourth sub-data DT1_S4 does not include an error, a fourth sub-result of the second error detection result EDR2 can indicate the second value 'P'.

[0208] For example, because the first sub-data DT3_S1 includes an error, the first sub-result of the third error detection result EDR3 can indicate the first value 'F'. Because the second sub-data DT3_S2 does not include an error, the second sub-result of the third error detection result EDR3 can indicate the second value 'P'. Because the third sub-data DT3_S3 includes an error, the third sub-result of the third error detection result EDR3 can indicate the first value 'F'. Because the fourth sub-data DT3_S4 does not include an error, the fourth sub-result of the third error detection result EDR3 can indicate the second value 'P'.

[0209] For example, because the first sub-data DT4_S1 does not include an error, the first sub-result of the fourth error detection result EDR4 can indicate the second value 'P'. Because the second sub-data DT4_S2 does not include an error, the second sub-result of the fourth error detection result EDR4 can indicate the second value 'P'. Because the third sub-data DT4_S3 does not include an error, the third sub-result of the fourth error detection result EDR4 can indicate the second value 'P'. Because the fourth sub-data DT4_S4 includes an error, the fourth sub-result of the fourth error detection result EDR4 can indicate the first value 'F'.

[0210] The first non-volatile memory NVM 11 can determine whether a retraining condition has been satisfied based on the accumulated error detection results. For example, the first non-volatile memory NVM 11 can determine whether an error has been detected for the first data line DQ1 based on the respective first sub-results of the first error detection result EDR1 through the fourth error detection result EDR4. The first non-volatile memory NVM 11 can determine whether an error has been detected for the second data line DQ2 based on the respective second sub-results of the first error detection result EDR1 through the fourth error detection result EDR4. Because the remaining data lines DQ3 and D4 are similar thereto, detailed descriptions thereof are omitted.

[0211] For example, the first non-volatile memory NVM 11 can generate a final error detection result FEDR based on the accumulated error detection results. Because the first sub-result in the first error detection result EDR1 indicates the first value and the first sub-result in the third error detection result EDR3 indicates the first value, the first sub-result of the final error detection result FEDR can indicate the first value 'F'. Because all of the second sub-results in the first error detection result EDR1 through the fourth error detection result EDR4 indicate the second value, the second sub-result of the final error detection result FEDR can indicate the second value 'P'. Because the third sub-result in the third error detection result EDR3 indicates the first value, the third sub-result of the final error detection result FEDR can indicate the first value 'F'. Because the fourth sub-result in the fourth error detection result EDR4 indicates the first value 'F', the fourth sub-result of the final error detection result FEDR can indicate the first value 'F'.

[0212] The first non-volatile memory NVM 11 can count the error detection line number LNUM based on the final error detection result FEDR. Because the first non-volatile memory NVM 11 has detected errors from the first data line DQ1, the third data line DQ3, and the fourth data line DQ4, the error detection line number LNUM can be '3'. Because the error detection line number LNUM (e.g., '3') is equal to or greater than the threshold value (e.g., '3'), the first non-volatile memory NVM 11 can determine that the retraining condition has been satisfied. In response to the status read command, the first non-volatile memory NVM 11 can transmit the status information indicating the transmission error state to the memory controller 110.

[0213] While this disclosure contains many specifics, these should not be construed as limiting the scope of what can be claimed, but as merely providing illustrations of some of the embodiments of the present innovations. Certain features that are described in this disclosure in the context of separate embodiments can also be implemented in combination with each other. Conversely, various features that are described in the context of a single embodiment can also be implemented on other embodiments, alone or in any suitable subcombination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a subcombination or variation of a subcombination.

Claims

1. A method of operating a storage device, the storage device comprising a storage controller and a non-volatile memory device, the method comprising: The storage controller generates multiple parity check data lines, each corresponding to a different data line. The storage controller sends write commands, data, and the multiple transmission parity data to a first non-volatile memory among multiple non-volatile memories via the multiple data lines, the multiple non-volatile memories being included in a non-volatile memory device; Based on each of the multiple transmission parity check data lines, a transmission error detection operation is performed by the first non-volatile memory for each of the multiple data lines; Based on the error detection results generated in the transmission error detection operation, the first non-volatile memory determines that the retraining execution conditions are met; The storage controller sends the status read command to the first non-volatile memory; as well as In response to a status read command and based on the fulfillment of retraining execution conditions, the first non-volatile memory sends status information indicating a transmission error to the storage controller.

2. The operating method as described in claim 1, wherein, The steps to determine if the retraining execution conditions are met include: The number of data lines from which errors are detected is counted as the number of error detection lines; and If the number of error detection lines is greater than or equal to a predetermined threshold, it is determined that the conditions for retraining are met.

3. The operating method as described in claim 1, further comprising: In response to the status information indicating a transmission error, the storage controller performs a retraining operation on the first non-volatile memory.

4. The operating method as described in claim 3, further comprising: While performing a retraining operation on the first non-volatile memory connected to the first channel, the storage controller performs a read operation or a write operation on the second non-volatile memory connected to the second channel among the plurality of non-volatile memories.

5. The operating method as described in claim 3, wherein, The steps involved in performing a retraining operation include at least one of the following: Perform reference voltage training operation; Perform duty cycle correction training. Perform the read training operation; and Perform the write training operation.

6. The operating method as described in claim 1, further comprising: Based on the error detection results, the transmission error information is updated by the first non-volatile memory. The transmission error information includes at least one of the identifier information of the data line from which an error has been detected and the number of errors detected.

7. The operating method as described in claim 6, further comprising: The storage controller sends a transmission error information request command to the first non-volatile memory; as well as In response to a transmission error information request command, the first non-volatile memory sends the transmission error information to the memory controller.

8. The operating method as described in claim 7, further comprising: Based on the transmission error information, a retraining operation is performed on the data line where the error has been detected.

9. The operating method as described in claim 7, further comprising: The storage controller sends the oscillator request command of the data strobe signal to the first non-volatile memory; In response to an oscillator request command, the oscillator value is sent from the first non-volatile memory to the memory controller; Based on the transmission error information and the oscillator value, the memory controller determines whether to perform a retraining operation on the first non-volatile memory; as well as When it is determined that a retraining operation needs to be performed on the first non-volatile memory, a retraining operation is performed on the first non-volatile memory.

10. The operating method as described in claim 9, further comprising: The storage controller sends the oscillator activation command of the data strobe signal to the first non-volatile memory; as well as In response to the oscillator activation command, the oscillator value is monitored by the first non-volatile memory.

11. The operating method as described in claim 1, in, The steps of sending a write command, the data, and the multiple transfer parity data lines from the storage controller to a first non-volatile memory among the plurality of non-volatile memories include: First data and first transmission parity data are sent to a first non-volatile memory via a first data line among the plurality of data lines, and second data and second transmission parity data are sent to the first non-volatile memory via a second data line among the plurality of data lines; and The third data and the third transmission parity data are sent to the first non-volatile memory via the first data line, and the fourth data and the fourth transmission parity data are sent to the first non-volatile memory via the second data line. The steps for performing transmission error detection for each of the multiple data lines include: A first error detection operation is performed on the first data based on the first transmitted parity data, and a second error detection operation is performed on the second data based on the second transmitted parity data; and A third error detection operation is performed on the third data based on the third transmitted parity data, and a fourth error detection operation is performed on the fourth data based on the fourth transmitted parity data.

12. The operating method as described in claim 11, wherein, The steps to determine if the retraining execution conditions are met include: Based on the results of the first error detection operation and the third error detection operation, it is determined that an error was detected for the first data line. Based on the results of the second and fourth error detection operations, it is determined that an error was detected for the second data line. The number of data lines from which errors were detected among the plurality of data lines is counted as the number of error detection lines; and If the number of error detection lines is greater than or equal to a predetermined threshold, it is determined that the conditions for retraining are met.

13. The operating method as described in claim 1, further comprising: The parity check data is stored in a memory cell array included in the first non-volatile memory.

14. The operating method as described in claim 1, wherein, The steps of sending a write command, the data, and the multiple transfer parity data lines from the storage controller to a first non-volatile memory among the plurality of non-volatile memories include: The storage controller sends the write command, the data, the memory parity data, and the multiple transmission parity data lines to the first non-volatile memory via the multiple data lines; and The first non-volatile memory stores only the data and memory parity data in the memory cell array.

15. The operating method as described in claim 1, further comprising: The storage controller sends a transmission error detection activation command to the first non-volatile memory.

16. A method of operating a non-volatile memory, the method comprising: The system receives first sub-data and first sub-transmission parity data via the first data line, and receives second sub-data and second sub-transmission parity data via the second data line. The transmission error detection operation is performed on the first sub-data based on the parity check data of the first sub-transmission, and the transmission error detection operation is performed on the second sub-data based on the parity check data of the second sub-transmission. Based on the error detection results generated in the transmission error detection operation, it is determined that the conditions for retraining execution are met; as well as In response to a status read command and based on the fulfillment of retraining execution conditions, the error status information is transmitted via the first and second data lines.

17. The operating method as described in claim 16, wherein, The steps to determine if the retraining execution conditions are met include: The number of data lines from which errors are detected is counted as the number of error detection lines; and If the number of error detection lines is greater than or equal to a predetermined threshold, it is determined that the conditions for retraining are met.

18. The operating method as described in claim 16, further comprising: Based on the error detection results, update the transmission error information. The transmission error information includes at least one of the identifier information of the data line from which an error has been detected and the number of errors detected.

19. The operating method as described in claim 18, further comprising: In response to a transmission error information request command, the transmission error information is output via the first data line and the second data line.

20. A storage device, comprising: A non-volatile memory device, comprising multiple non-volatile memories; as well as The storage controller is configured as follows: Generate multiple transmission parity check data lines, each corresponding to a different data line. The write command, data, and parity check data are sent to the first non-volatile memory among the plurality of non-volatile memories via the plurality of data lines. Send the status read command to the first non-volatile memory. The first non-volatile memory is configured as follows: Based on each of the multiple transmission parity check data lines, a transmission error detection operation is performed for each of the multiple data lines. Based on the error detection results generated in the transmission error detection operation, it is determined that the conditions for retraining are met, and In response to the status read command and based on the fulfillment of the retraining execution conditions, status information indicating the transmission error status is sent to the storage controller.

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