Dynamic state machine control method and system for multi-chip flash memory test
By using a dynamic state machine control method, unified management and synchronous control of multi-chip flash memory testing are achieved, solving the problem of low testing efficiency, improving testing accuracy and compatibility, and making it suitable for various chip types and low-power scenarios.
Patent Information
- Application Number
- CN202511669656.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-14
- Publication Date
- 2026-02-13
AI Technical Summary
Existing multi-chip flash memory testing methods lack unified management and synchronous control, resulting in low testing efficiency and a high risk of data corruption or inaccurate testing.
A dynamic state machine control method is adopted, which enables synchronous stopping and resuming of multiple chips by sending pause and resume commands uniformly through the host. It supports Global mode and Local mode, ensures the consistency of the state of each chip during the state machine stop and resume process, and provides adapted commands for chip type and low power consumption scenarios.
It improves the efficiency of multi-chip testing, reduces testing time, ensures testing accuracy and data integrity, is applicable to various chip types, including 3D NAND Flash and NOR Flash, has strong compatibility, and supports low-power testing scenarios.
Smart Images
Figure CN121528285A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip testing technology, and specifically to a dynamic state machine control method and system for multi-chip flash memory testing. Background Technology
[0002] In modern semiconductor memory technology, testing multi-chip flash memory (such as 3D NAND Flash or multi-chip packages) is a complex and time-consuming process. Traditional testing methods typically require testing each chip individually, leading to low testing efficiency. To improve testing efficiency, multi-chip testing (MCT) technology is widely adopted, which involves testing multiple chips simultaneously. However, MCT technology may require pausing and resuming certain operations during testing. For each different IC, maintaining consistent functional parameters with the quality and results of individual chip testing under MCT conditions is crucial, and the time savings from multiple tests are beneficial, such as when a chip's state is abnormal or test parameters need to be reconfigured. Existing methods often lack unified management and synchronous control of multiple chips when stopping and resuming state machines, which can easily lead to data corruption or inaccurate testing. Summary of the Invention
[0003] The purpose of this invention is to provide a dynamic state machine control method and system for multi-chip flash memory testing, so as to solve the above-mentioned technical problems.
[0004] The objective of this invention can be achieved through the following technical solutions: A dynamic state machine control method for multi-chip flash memory testing includes two processes: stopping the state machine and resuming the state machine. The specific steps are as follows: Stop state machine: The host sends a unified pause command to all chips under test. After receiving the command, each chip saves the current operation status information and stops the current operation. The host confirms that all chips have been successfully paused by reading the status register of each chip. State machine recovery: The host sends a unified recovery command to all chips under test according to the test requirements. After receiving the command, each chip loads the previously saved state information and restores the previous operation. The host confirms that all chips have been successfully recovered by reading the state register of each chip.
[0005] As a further aspect of the present invention: both the stop state machine and the recovery state machine support Global mode and Local mode; wherein, in Global mode, the host sends a unified command to all chips under test to achieve synchronous stop or recovery, while in Local mode, the host sends a command to a single target chip, and the chip that does not receive the command continues to complete the current task.
[0006] As a further aspect of the present invention: In Local mode, after a single chip receives a stop command, it locks the current state through a state table to avoid over-erasure or over-programming exceptions; after a single chip receives a resume command, it continues to execute the operations before the pause from the state table information of the last pause.
[0007] As a further aspect of the present invention: when the chip under test is a 3D NAND Flash chip, the pause command is the PROGRAM_SUSPEND command, the resume command is the PROGRAM_RESUME command, and the host reads the chip status register through the READ_STATUS command to confirm the pause or resume status.
[0008] As a further aspect of the present invention: when the chip under test is a NOR Flash chip and is in a low-power test scenario, the pause command is the DEEP_POWER_DOWN command, and the resume command is the EXIT_DEEP_POWER_DOWN command; after receiving the DEEP_POWER_DOWN command, the chip automatically saves the current operation state information and enters the low-power mode, and after receiving the EXIT_DEEP_POWER_DOWN command, it resumes from the low-power mode and loads the saved state information.
[0009] As a further aspect of the present invention: the host establishes a communication connection with all chips under test through the SPI interface to enable command sending and status information reading.
[0010] A dynamic state machine control system for multi-chip flash memory testing includes a host controller and multiple chips under test (DUTs). The host controller sends pause and resume commands to the DUTs and monitors the status of each chip by reading its status register. The DUTs receive commands and execute pause, state saving, resume, and state loading operations of the state machine, and support 3D NAND Flash and NOR Flash types.
[0011] As a further aspect of the present invention: the chip under test has a built-in state storage module, which is used to save the current operation state information when a pause command is received, and to call the state information when a resume command is received.
[0012] As a further aspect of the present invention: the chip under test has a built-in status register, which is used to record the current working status of the chip in real time, so that the host controller can read it to confirm the operation result.
[0013] As a further aspect of the present invention: the host controller includes a pause command sending unit, a resume command sending unit, and a status reading unit; the pause command sending unit is used to send a pause command, the resume command sending unit is used to send a resume command, and the status reading unit is used to read chip status register information.
[0014] The beneficial effects of this invention are as follows: By uniformly sending commands from the host, the synchronous stopping and resuming of multiple chip state machines is achieved, solving the problem of lack of unified management and synchronous control in existing technologies. This significantly improves testing efficiency and reduces testing time in multi-chip testing environments. It supports both Global and Local control modes, meeting the needs of synchronous testing of all chips while allowing for individual operation on a single faulty chip, avoiding interruptions to the overall testing process. It also prevents chip over-erasure and over-programming anomalies, ensuring data integrity and testing accuracy. It is compatible with various chip types such as 3D NAND Flash and NOR Flash, and supports low-power testing scenarios. It has strong compatibility and a wide range of applications, meeting the functional requirements of IC development for stopping, resuming, and pausing chips at any time, and enabling the IC to reach the required functional state within a specific short time. Attached Figure Description
[0015] The invention will now be further described with reference to the accompanying drawings.
[0016] Figure 1 This is a schematic diagram of the overall structure of a dynamic state machine control method and system for multi-chip flash memory testing according to the present invention. Detailed Implementation
[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0018] Please see Figure 1 As shown, a dynamic state machine control method and system for multi-chip flash memory testing are disclosed. The invention will be described in detail below with reference to specific embodiments.
[0019] Example 1: Multi-chip flash memory test environment: Assume that multiple 3D NAND Flash chips are being tested simultaneously, and each chip supports the "PROGRAM_SUSPEND" and "PROGRAM_RESUME" commands; 1. Stopped state machine (Global mode): The host sends the "PROGRAM_SUSPEND" command to all chips via the SPI interface; After receiving a command, each chip saves the status information of the current programming operation (such as programming progress, target address, etc.) and stops the current programming operation; The host computer reads the status register of each chip using the "READ_STATUS" command to confirm that all chips have entered the pause state.
[0020] 2. Restore the state machine (Global mode): The host sends the "PROGRAM_RESUME" command to all chips according to the test requirements; After receiving a command, each chip loads the previously saved state information and resumes the programming operation from the paused position; The host computer reads the status register of each chip using the "READ_STATUS" command to confirm that all chips have been restored to normal working condition.
[0021] 3. Stopped state machine (Local mode): When a single chip receives a stop command, it will enter its status table to stop other chips that have not received this command from continuing to complete their tasks. This can prevent the chip from being over-erected or over-programmed.
[0022] 4. Restore the state machine (Local mode): When a single chip receives a reply command, it will change its status table from the last paused state to resume its operation from the last paused state.
[0023] Example 2: Stop and Resume in Low Power Mode: 1. Stopped state machine: The host sends a "DEEP_POWER_DOWN" command to all chips, causing each chip to enter a low-power mode; When each chip enters low-power mode, it automatically saves the current operation status information and stops the current operation; The host computer confirms through the status register that all chips have entered low-power mode.
[0024] 2. Restore the state machine: The host sends the "EXIT_DEEP_POWER_DOWN" command to all chips according to the test requirements; After receiving the command, each chip recovers from low-power mode to normal operating state and loads the previously saved state information; The host computer confirms through the status register that all chips have returned to normal working condition.
[0025] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.
Claims
1. A dynamic state machine control method for multi-chip flash memory testing, characterized in that, The process includes two parts: stopping the state machine and restoring the state machine. The specific steps are as follows: Stop state machine: The host sends a unified pause command to all chips under test. After receiving the command, each chip saves the current operation status information and stops the current operation. The host confirms that all chips have been successfully paused by reading the status register of each chip. State machine recovery: The host sends a unified recovery command to all chips under test according to the test requirements. After receiving the command, each chip loads the previously saved state information and restores the previous operation. The host confirms that all chips have been successfully recovered by reading the state register of each chip.
2. The dynamic state machine control method for multi-chip flash memory testing according to claim 1, characterized in that, Both the stop state machine and the recovery state machine support Global mode and Local mode. In Global mode, the host sends a unified command to all chips under test to achieve synchronous stop or recovery. In Local mode, the host sends a command to a single target chip, and the chip that does not receive the command continues to complete the current task.
3. The dynamic state machine control method for multi-chip flash memory testing according to claim 2, characterized in that, In Local mode, after a single chip receives a stop command, it locks its current state through a status table to avoid over-erase or over-programming exceptions. After receiving the recovery command, the single chip resumes the operation that was performed before the pause, starting from the status table information of the last pause.
4. The dynamic state machine control method for multi-chip flash memory testing according to claim 1, characterized in that, When the chip under test is a 3D NAND Flash chip, the pause command is the PROGRAM_SUSPEND command, and the resume command is the PROGRAM_RESUME command. The host reads the chip status register through the READ_STATUS command to confirm the pause or resume status.
5. The dynamic state machine control method for multi-chip flash memory testing according to claim 1, characterized in that, When the chip under test is a NOR Flash chip and is in a low-power test scenario, the pause command is the DEEP_POWER_DOWN command, and the resume command is the EXIT_DEEP_POWER_DOWN command. After receiving the DEEP_POWER_DOWN command, the chip automatically saves the current operation status information and enters the low-power mode. After receiving the EXIT_DEEP_POWER_DOWN command, it resumes from the low-power mode and loads the saved status information.
6. The dynamic state machine control method for multi-chip flash memory testing according to claim 1, characterized in that, The host establishes a communication connection with all chips under test through the SPI interface to send commands and read status information.
7. A dynamic state machine control system for multi-chip flash memory testing, characterized in that, It includes a host controller and multiple chips under test (DUTs); the host controller is used to send pause and resume commands to the DUTs and monitor the status of each chip by reading the chip status register; the DUTs are used to receive commands and perform pause, state saving, resume, and state loading operations of the state machine, and support 3D NAND Flash and NOR Flash types.
8. A dynamic state machine control system for multi-chip flash memory testing according to claim 7, characterized in that, The chip under test has a built-in state storage module, which is used to save the current operation state information when a pause command is received, and to call up the state information when a resume command is received.
9. A dynamic state machine control system for multi-chip flash memory testing according to claim 7, characterized in that, The chip under test has a built-in status register, which is used to record the chip's current working status in real time, so that the host controller can read it to confirm the operation result.
10. A dynamic state machine control system for multi-chip flash memory testing according to claim 7, characterized in that, The host controller includes a pause command sending unit, a resume command sending unit, and a status reading unit; the pause command sending unit is used to send pause commands, the resume command sending unit is used to send resume commands, and the status reading unit is used to read chip status register information.