Clamping circuit for chip electrostatic protection

Abstract

The invention discloses a clamping circuit for chip electrostatic protection, which comprises a first MOS (Metal Oxide Semiconductor) tube, a second MOS tube, a third MOS tube and a fourth MOS tube, the drain electrode of the first MOS tube is connected with an IO (Input / Output) port, and the source electrode of the first MOS tube is connected with an ESD (Electro-Static Discharge) sampling line which is connected with a power supply; the RC trigger type power supply clamping unit comprises an RC network and a power supply clamping module, an intermediate node of the RC network is connected with a grid electrode of the first MOS tube, the RC network is connected between the ESD sampling line and the ground, and the power supply clamping module is connected among the ESD sampling line, a power supply and the ground. The RC network is used for keeping a low level at an intermediate node when external high-voltage static electricity is injected through the IO port or the power supply side, and the power supply clamping module is used for conducting a power supply-ground discharge path when electrostatic discharge at the IO port side or the power supply side is detected. According to the circuit, the voltage difference between the IO port and the ESD sampling line can be reduced, so that the clamping voltage of the IO port under a forward ESD event is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor integrated circuits, and particularly relates to a clamping circuit for chip electrostatic protection. BACKGROUND

[0002] Generally, the whole chip electrostatic protection takes the power supply and the ground as an ESD bus, connects the signal IO and the power supply / ground with a diode, and connects the power supply and the ground with a power clamp, as shown in the following figure. Figure 1 When the electrostatic occurs in the direction of IO->VDD / GND, the current discharge direction is shown by an arrow (1). When the electrostatic occurs in the direction of GND->IO / VDD, the current discharge direction is shown by an arrow (2). The power clamp is used to sense the voltage fluctuation between the power supply and the ground, and is turned on during the electrostatic event and is turned off in other working states. However, the circuit of the existing protection network either wastes the clamping capacity of the power clamp or causes the voltage drop of the diode between the IO and the ESD sampling line, and in the low-voltage IO protection scenario, the loss of a diode voltage drop is also difficult to bear. SUMMARY

[0003] In view of the above problems of the prior art, the present application aims to provide a clamping circuit for chip electrostatic protection, which can reduce the voltage difference between the IO port and the ESD sampling line, and further reduce the clamping voltage of the IO port under the forward ESD event.

[0004] To solve the above technical problems, the present application provides the following technical scheme. A clamping circuit for chip electrostatic protection, comprising: a first MOS tube, whose drain is connected with an IO port, and whose source is connected with an ESD sampling line, and the ESD sampling line is connected with a power supply; and an RC triggered power clamp unit, comprising an RC network and a power clamp module, wherein the middle node of the RC network is connected with the gate of the first MOS tube, the RC network is connected between the ESD sampling line and the ground, the power clamp module is connected between the ESD sampling line, the power supply and the ground, the RC network is used to keep the low level at the middle node when the external high-voltage electrostatic is injected through the IO port or the power supply side, and the power clamp module is used to turn on the power supply-ground discharge path when the electrostatic discharge on the IO port side or the power supply side is detected.

[0005] Preferably, the first MOS tube is a PMOS tube.

[0006] The RC network comprises a first resistor and a first capacitor, a node between the first resistor and the first capacitor is an intermediate node of the RC network, the other end of the first resistor is connected with an ESD sampling line, and the other end of the first capacitor is grounded.

[0007] The power supply clamping module comprises a second MOS tube, a third MOS tube, and a fourth MOS tube, the other end of the first resistor is also directly connected with the source electrode of the fourth MOS tube, the gate electrode of the fourth MOS tube is connected with the intermediate node of the RC network and the gate electrode of the second MOS tube, the drain electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube and then connected with the gate electrode of the third MOS tube, the drain electrode of the third MOS tube is connected with a power supply, the source electrode of the third MOS tube is grounded, and the source electrode of the second MOS tube is grounded.

[0008] The second MOS tube is an NMOS tube, the third MOS tube is an NMOS tube, and the fourth MOS tube is a PMOS tube.

[0009] The power supply clamping module comprises a second MOS tube, a third MOS tube, and a fourth MOS tube, the other end of the first resistor is also directly connected with the source electrode of the fourth MOS tube, the gate electrode of the fourth MOS tube is connected with the intermediate node of the RC network and the gate electrode of the second MOS tube, the drain electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube and then connected with the gate electrode of the third MOS tube, the drain electrode of the third MOS tube is connected with a power supply, the source electrode of the third MOS tube is grounded, and the source electrode of the second MOS tube is grounded.

[0010] The power supply clamping module comprises a second MOS tube, a third MOS tube, and a fourth MOS tube, the other end of the first resistor is also directly connected with the source electrode of the fourth MOS tube, the gate electrode of the fourth MOS tube is connected with the intermediate node of the RC network and the gate electrode of the second MOS tube, the drain electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube and then connected with the gate electrode of the third MOS tube, the drain electrode of the third MOS tube is connected with a power supply, the source electrode of the third MOS tube is grounded, and the source electrode of the second MOS tube is grounded.

[0011] The power supply clamping module comprises a second MOS tube, a third MOS tube, and a fourth MOS tube, the other end of the first resistor is also directly connected with the source electrode of the fourth MOS tube, the gate electrode of the fourth MOS tube is connected with the intermediate node of the RC network and the gate electrode of the second MOS tube, the drain electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube and then connected with the gate electrode of the third MOS tube, the drain electrode of the third MOS tube is connected with a power supply, the source electrode of the third MOS tube is grounded, and the source electrode of the second MOS tube is grounded.

[0012] The power supply clamping module comprises a second MOS tube, a third MOS tube, and a fourth MOS tube, the other end of the first resistor is also directly connected with the source electrode of the fourth MOS tube, the gate electrode of the fourth MOS tube is connected with the intermediate node of the RC network and the gate electrode of the second MOS tube, the drain electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube and then connected with the gate electrode of the third MOS tube, the drain electrode of the third MOS tube is connected with a power supply, the source electrode of the third MOS tube is grounded, and the source electrode of the second MOS tube is grounded.

[0013] The off control delay timer comprises a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor and a thirteenth MOS transistor. The gate of the fifth MOS transistor is connected with the gate of the tenth MOS transistor, the source of the tenth MOS transistor is connected with a power supply, the drain of the tenth MOS transistor is connected with the drain and the gate of the sixth MOS transistor, the source of the sixth MOS transistor is grounded, the gates of the seventh MOS transistor, the eighth MOS transistor, the eleventh MOS transistor and the twelfth MOS transistor are connected with the drain of the tenth MOS transistor, the source of the seventh MOS transistor is grounded, the drain of the seventh MOS transistor is connected with the source of the eighth MOS transistor, the drain of the eighth MOS transistor is connected with the drain of the eleventh MOS transistor, the source of the eleventh MOS transistor is connected with the drain of the twelfth MOS transistor, the source of the twelfth MOS transistor is connected with an ESD sampling line, the source of the twelfth MOS transistor is also connected with the source of the ninth MOS transistor, the gate of the ninth MOS transistor is connected with the gate of the thirteenth MOS transistor, the drain of the thirteenth MOS transistor is connected with the ESD sampling line, the drain of the twelfth MOS transistor is also connected with the gate of the second MOS transistor, the source of the thirteenth MOS transistor is connected with the source of the eleventh MOS transistor, and the drain of the thirteenth MOS transistor is grounded.

[0014] The clamp circuit for chip electrostatic protection has the core of realizing the efficient, reliable and false trigger prevention bidirectional protection of the IO port in the face of the electrostatic discharge event from the IO port side or the power supply side through the RC trigger driving and the multi-stage off control. And the first MOS transistor (PMOS transistor) sampling sensing reduces the pressure difference between the IO port and the ESD sampling line, and further reduces the clamping voltage of the IO port in the positive ESD event. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the principles of the application, and do not limit the application. In the drawings: Figure 1 It is a circuit schematic diagram of the existing clamp circuit for chip electrostatic protection.

[0016] Figure 2 It is a circuit diagram of the first preferred embodiment of the clamp circuit for chip electrostatic protection.

[0017] Figure 3 It is a circuit diagram of the second preferred embodiment of the clamp circuit for chip electrostatic protection.

[0018] Figure 4 It is a circuit diagram of the third preferred embodiment of the clamp circuit for chip electrostatic protection. DETAILED DESCRIPTION

[0019] Embodiments of the present application will be described below with reference to specific examples. The drawings provided in the following examples are only schematic and are intended to provide a basic understanding of the application. In no way are the following examples and embodiments to be interpreted as being limiting. The following examples are intended to be combined with one another, where possible, without conflict.

[0020] Reference is made to Figure 2 As shown in the figure, the first preferred embodiment of the clamping circuit for chip electrostatic protection includes an RC trigger power clamping unit, a resistor R2, diodes D1 and D2, and a MOS transistor Mps. The RC trigger power clamping unit includes an RC network and a power clamping module, and the power clamping module includes MOS transistors Mn1, Mn2, and Mp1. The anode of diode D1 and the cathode of diode D2 are connected to the IO port, the cathode of diode D1 is connected to the power supply, and the anode of diode D2 is connected to the ground. The drain of MOS transistor Mps is connected to the IO port, and the source is connected to the ESD sampling line. The ESD sampling line is connected to the power supply through resistor R2. The gate of MOS transistor Mps is connected to the first end of the RC trigger power clamping unit, the second end of the RC trigger power clamping unit is connected to the ESD sampling line, the third end of the RC trigger power clamping unit is connected to the power supply, and the fourth, fifth, and sixth ends are all connected to the ground.

[0021] Specifically, the RC network includes a resistor R1 and a capacitor C1. One end of resistor R1 is connected to the ground through capacitor C1 (as the sixth end of the RC trigger power clamping unit), and the node between resistor R1 and capacitor C1 is the intermediate node of the RC network, which is connected to the gate of MOS transistor Mps as the first end of the RC trigger power clamping unit. The other end of resistor R1 is connected to the ESD sampling line as the second end of the RC trigger power clamping unit. The other end of resistor R1 is also directly connected to the source of MOS transistor Mp1, the gate of MOS transistor Mp1 is connected to the node between resistor R1 and capacitor C1, and is also connected to the gate of MOS transistor Mn1. The drain of MOS transistor Mp1 is connected to the drain of MOS transistor Mn1, and is then connected to the gate of MOS transistor Mn2. The drain of MOS transistor Mn2 is connected to the power supply as the third end of the RC trigger power clamping unit, and the source of MOS transistor Mn2 is connected to the ground as the fourth end of the RC trigger power clamping unit. The source of MOS transistor Mn1 is connected to the ground as the fifth end of the RC trigger power clamping unit. In this embodiment, MOS transistor Mp1 is a PMOS transistor, MOS transistor Mn1 is an NMOS transistor, MOS transistor Mn2 is an NMOS transistor, and MOS transistor Mp1 is a PMOS transistor.

[0022] The RC network is connected between the ESD sampling line and the ground, and the power clamp module is connected between the ESD sampling line, the power supply and the ground, the RC network is used to maintain a low level at the intermediate node when the external high-voltage static electricity is injected through the IO port or the power supply side, and the power clamp module is used to turn on the power-ground discharge path when the IO port side or the power supply side static electricity is detected.

[0023] Specifically, when the external high-voltage static electricity is injected through the IO port, the voltage of the IO port rises rapidly, which is much higher than the normal working level. At this time, the drain of the MOS tube Mps (connected to the IO port) bears a high voltage, and its gate is connected to the node vc between the capacitor C1 and the resistor R1. Since the voltage across the capacitor C1 cannot change abruptly, the initial value of vc is maintained at a low level (close to the ground potential), so the gate-source voltage Vgs of the MOS tube Mps (i.e. vc-IO port voltage) is negative, but since the MOS tube Mps is a PMOS, its conduction condition is VgsVth (threshold voltage), and here Vth is negative. When a high voltage appears at the IO port (the drain of the MOS tube Mps), the drain-body diode of the MOS tube Mps is turned on, and because the source-body electrode is short-circuited, the source potential of the MOS tube Mps is significantly higher than the gate potential, i.e. Vgs is negative. When VgsVth, the MOS tube Mps will be in the on state.

[0024] Specifically, at the moment of ESD impact, the voltage of the ESD sampling line rises rapidly with the voltage of the IO port, while vc cannot respond immediately due to the energy storage characteristics of the capacitor C1, resulting in a source potential of the MOS tube Mps (i.e. the voltage of the ESD sampling line) much higher than the gate potential (vc), forming a large reverse gate-source voltage difference, causing the MOS tube Mps to turn on rapidly. After the MOS tube Mps is turned on, the transient voltage of the IO port is "sampled" and coupled to the ESD sampling line, realizing rapid perception of the ESD event. Since the impedance between the source and the drain of the MOS tube Mps is extremely low after it is turned on, the voltage difference between the IO port and the ESD sampling line is almost zero, thereby ensuring that the ESD sampling line can accurately reflect the true voltage level of the IO port.

[0025] At the same time, the voltage on the ESD sampling line is transmitted to the subsequent MOS tube Mn2 for activation. Since the MOS tube Mps reduces the voltage drop between the IO port and the ESD sampling line after it is turned on, the gate drive voltage of the MOS tube Mn2 is increased, enhancing its conduction capability. This not only speeds up the response of the MOS tube Mn2, but also forms a stronger discharge path between the power supply and the ground, effectively reducing the voltage difference between the power supply and the ground. Finally, the IO clamp voltage of the entire system is significantly reduced, improving the ESD protection performance.

[0026] In addition, the resistance R1 and the capacitor C1 in the RC network constitute a time constant, ensuring a long enough discharge time, and avoiding the situation that the clamping circuit is closed before the static electricity is completely discharged. This design based on the voltage hysteresis characteristics of the capacitor realizes accurate identification and efficient response to ESD events, and balances sensitivity and reliability.

[0027] Please continue to refer to Figure 3 As shown in FIG. 2, it is a second preferred embodiment of the clamping circuit for chip electrostatic protection of the application, which is different from the first embodiment in that the RC trigger type power clamping unit is added with a MOS transistor Mp2. Specifically, the gate of the MOS transistor Mp2 is connected with the gate of the MOS transistor Mp1, the source of the MOS transistor Mp2 is connected with the power supply, and the drain is connected with the drain of the MOS transistor Mp1.

[0028] The gate of the MOS transistor Mps is connected to a node (vc) between the capacitor C1 and the resistance R1, the source is connected to the ESD sampling line, and the drain is connected to the IO port. In normal operation, the voltage of the IO port is in a safe range, the MOS transistor Mps is kept off because the gate voltage is equal to the source voltage, and does not affect signal transmission. When a positive ESD event (such as high voltage transient) occurs at the IO port, the voltage rises rapidly and is coupled to the vc node through the drain-source path of the MOS transistor Mps. Since the capacitor C1 has an integral characteristic, the voltage of the vc node does not change instantaneously, but rises slowly over time, forming a delay response, ensuring that the MOS transistors Mp1 and Mn2 have enough opening time. For a slow event such as power supply power-on, when the rising time of power-on is greater than the R1C1 time constant, the vc follows the voltage changes of the ESD sampling line and the power supply line, and the MOS transistors Mp1 and Mn2 will not be turned on, thereby effectively distinguishing ESD events from normal power-on. This RC delay mechanism avoids false triggering and improves system stability.

[0029] At the same time, the MOS transistor Mp1, as a driving transistor, has its gate also connected to the vc node, the source connected to the ESD sampling line, and the drain connected to the gate of the MOS transistor Mn2. When a positive ESD event occurs at the IO port, a positive voltage difference occurs between the ESD sampling line (source of Mp1) and vc (gate of Mp1), causing the MOS transistor Mp1 to turn on, and further causing the MOS transistor Mn2 to turn on, thereby providing a low-impedance discharge path to ground for the IO port. When a power supply ESD event occurs, the vc voltage cannot change abruptly, and a positive voltage difference occurs between the power supply line (source of the MOS transistor Mp2) and vc (gate of the MOS transistor Mp2), causing the MOS transistor Mp2 to turn on, and further causing the MOS transistor Mn2 to turn on, thereby providing a low-impedance discharge path to ground for the power supply.

[0030] In conclusion, the circuit samples the voltage change of the IO terminal through the MOS transistor Mps, and realizes time filtering by using the RC network, and in combination with the MOS transistors Mp1 and Mp2 responding to ESD events in different directions, the opening timing of the MOS transistor Mn2 is controlled to ensure quick response when the real ESD occurs and keep closed in normal operation, thereby realizing efficient, accurate and reliable bidirectional ESD protection function.

[0031] Please continue to refer to Figure 4 As shown in the figure, the third preferred embodiment of the clamping circuit for chip electrostatic protection of the application is different from the first embodiment in that a Schmidt trigger-based shutdown control delay timer is added, which can reduce the risk of false triggering under the premise of providing sufficient discharge time. The shutdown control delay timer includes MOS transistors Mp2-Mp6 and MOS transistors Mn3-Mn6.

[0032] Specifically, the anode of the diode D1 and the cathode of the diode D2 are connected to the IO port, the cathode of the diode D1 is connected to the power supply, and the anode of the diode D2 is connected to the ground. The drain of the MOS transistor Mps is connected to the IO port, and the source is connected to the ESD sampling line. The ESD sampling line is connected to the power supply through the resistor R2.

[0033] One end of the resistor R1 is connected to the ground through the capacitor C1, and the node between the resistor R1 and the capacitor C1 is connected to the gate of the MOS transistor Mps. The other end of the resistor R1 is connected to the ESD sampling line. The other end of the resistor R1 is also directly connected to the source of the MOS transistor Mp1. The gate of the MOS transistor Mp1 is connected to the node between the resistor R1 and the capacitor C1. The drain of the MOS transistor MP1 is connected to the drain of the MOS transistor Mn1, the gate of the MOS transistor Mn2, and the drain of the MOS transistor Mp2. The sources of the MOS transistor Mn1 and the MOS transistor Mn2 are connected to the ground. The gate of the MOS transistor Mp1 is also connected to the gate of the MOS transistor Mn2. The drain of the MOS transistor Mn2 is connected to the power supply. The source of the MOS transistor Mp2 is connected to the power supply.

[0034] The gate of the MOS transistor Mp2 is connected with the gate of the MOS transistor Mp3, the source of the MOS transistor Mp3 is connected with a power supply, and the drain is connected with the drain and the gate of the MOS transistor Mn3. The source of the MOS transistor Mn3 is grounded. The gates of the MOS transistors Mn4, Mn5, Mp4 and Mp5 are all connected with the drain of the MOS transistor Mp3. The source of the MOS transistor Mn4 is grounded, the drain is connected with the source of the MOS transistor Mn5, the drain of the MOS transistor Mn5 is connected with the drain of the MOS transistor Mp4, the source of the MOS transistor Mp4 is connected with the drain of the MOS transistor Mp5, and the source of the MOS transistor Mp5 is connected with an ESD sampling line. The source of the MOS transistor Mn5 is also connected with the source of the MOS transistor Mn6, and the gate of the MOS transistor Mn6 is connected with the gate of the MOS transistor Mp6. The drain of the MOS transistor Mn6 is connected with the ESD sampling line, and the drain of the MOS transistor Mn5 is also connected with the gate of the MOS transistor Mn1. The source of the MOS transistor Mp6 is connected with the source of the MOS transistor Mp4, and the drain of the MOS transistor Mp6 is grounded.

[0035] In the embodiment, the MOS transistor Mps is connected between the IO port and the ESD sampling line as a sampling device, the gate is connected with the capacitor C1 in the RC network, the source is connected with the ESD sampling line, and the drain is connected with the IO port. In the normal working condition, the MOS transistor Mps is in the off state to avoid affecting the signal transmission; when an abnormal high voltage (such as an ESD event) occurs in the IO port, the voltage change between the gate and the source of the MOS transistor Mps makes the MOS transistor Mps conduct, and the transient voltage information on the IO port side is "sampled" and transmitted to the subsequent control circuit. The design uses the RC delay characteristic to effectively distinguish the transient ESD event from the normal power-on event, and improves the anti-interference ability.

[0036] The MOS transistor Mp1 is used to control the electrostatic discharge path from the IO port. When the MOS transistor Mps detects a high voltage, the sampling signal drives the gate of the MOS transistor Mn2 through the MOS transistor Mp1, so that the MOS transistor Mn2 is turned on, thereby providing a low-impedance discharge path to the ground for the electrostatic on the IO port side. Meanwhile, the gate of the MOS transistor Mn2 is also controlled by the MOS transistor Mn1, so that the corresponding discharge channel can be activated when there is an overvoltage in the power supply domain, thereby realizing bidirectional ESD protection. The turn-off signal control module composed of the MOS transistors Mp3-Mp6 and the MOS transistors Mn3-Mn6 can actively turn off the discharge path of the MOS transistor Mn2 and the like during normal operation of the system, so as to prevent false triggering caused by noise or transient fluctuations and improve the stability of the circuit. The circuit shown in the embodiment realizes intelligent and controllable ESD protection for the IO port through the three mechanisms of sampling, driving and turning off, and takes into account the response speed, safety and reliability.

[0037] The above examples only express the preferred embodiments of the present application, which are described in a more specific and detailed manner, but should not be understood as a limitation to the scope of the patent. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, which are all within the scope of protection of the present application. Therefore, the scope of protection of the present application patent should be subject to the appended claims.

Claims

1. A clamp circuit for chip electrostatic protection, characterized by, The application comprises: a first MOS tube, whose drain is connected to an IO port, and whose source is connected to an ESD sampling line, which is connected to a power supply; and an RC triggered power clamp unit, which comprises an RC network and a power clamp module, the middle node of the RC network is connected to the gate of the first MOS tube, the RC network is connected between the ESD sampling line and the ground, the power clamp module is connected between the ESD sampling line, the power supply and the ground, the RC network is used to keep the middle node at a low level when an external high-voltage electrostatic is injected through the IO port or the power supply side, and the power clamp module is used to turn on the power-ground discharge path when an electrostatic discharge is detected on the IO port side or the power supply side.

2. The clamping circuit for chip electrostatic protection according to claim 1, wherein, The first MOS tube is a PMOS tube.

3. The clamping circuit for chip electrostatic protection according to claim 1, wherein, The RC network comprises a first resistor and a capacitor, the node between the first resistor and the capacitor is the middle node of the RC network, the other end of the first resistor is connected to the ESD sampling line, and the other end of the capacitor is connected to the ground.

4. The clamping circuit for chip electrostatic protection according to claim 3, wherein, The power clamp module comprises a second MOS tube, a third MOS tube and a fourth MOS tube, the other end of the first resistor is also directly connected to the source of the fourth MOS tube, the gate of the fourth MOS tube is connected to the middle node of the RC network and the gate of the second MOS tube, the drain of the fourth MOS tube is connected to the drain of the second MOS tube and then connected to the gate of the third MOS tube, the drain of the third MOS tube is connected to the power supply, the source of the third MOS tube is connected to the ground, and the source of the second MOS tube is connected to the ground.

5. The clamping circuit for chip electrostatic protection according to claim 4, wherein, The second MOS tube is an NMOS tube, the third MOS tube is an NMOS tube, and the fourth MOS tube is a PMOS tube.

6. The clamping circuit for chip electrostatic protection according to claim 1, wherein, It also comprises a first diode and a second diode, the cathode of the first diode is connected to the power supply, the anode of the first diode is connected to the cathode of the second diode, and the node is connected to the IO port, and the anode of the second diode is connected to the ground.

7. The clamping circuit for chip electrostatic protection according to claim 1, wherein, It also comprises a second resistor, which is connected between the ESD sampling line and the power supply.

8. The clamping circuit for chip electrostatic protection according to claim 3, wherein, The power clamp module comprises a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube, the other end of the first resistor is also directly connected to the source of the fourth MOS tube, the gate of the fourth MOS tube is connected to the middle node of the RC network and the gate of the second MOS tube, the drain of the fourth MOS tube is connected to the drain of the second MOS tube and then connected to the gate of the third MOS tube, the drain of the third MOS tube is connected to the power supply, the source of the third MOS tube is connected to the ground, the source of the second MOS tube is connected to the ground, the gate of the fifth MOS tube is connected to the gate of the fourth MOS tube, the source of the fifth MOS tube is connected to the power supply, and the drain of the fifth MOS tube is connected to the drain of the fourth MOS tube.

9. The clamping circuit for chip electrostatic discharge protection of claim 8, wherein, It also comprises a Schmidt trigger-based turn-off control delay timer, which is used to reduce the risk of false triggering under the premise of providing sufficient discharge time.

10. The clamping circuit for chip electrostatic discharge protection of claim 9, wherein, The off control delay timer comprises a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor and a thirteenth MOS transistor; a gate of the fifth MOS transistor is connected with a gate of the tenth MOS transistor; a source of the tenth MOS transistor is connected with a power supply; a drain and a gate of the sixth MOS transistor are connected with the source of the tenth MOS transistor; a source of the sixth MOS transistor is grounded; gates of the seventh MOS transistor, the eighth MOS transistor, the eleventh MOS transistor and the twelfth MOS transistor are connected with the drain of the tenth MOS transistor; a source of the seventh MOS transistor is grounded; a drain of the seventh MOS transistor is connected with a source of the eighth MOS transistor; a drain of the eighth MOS transistor is connected with a drain of the eleventh MOS transistor; a source of the eleventh MOS transistor is connected with a drain of the twelfth MOS transistor; a source of the twelfth MOS transistor is connected with an ESD sampling line; the source of the twelfth MOS transistor is also connected with a source of the ninth MOS transistor; a gate of the ninth MOS transistor is connected with a gate of the thirteenth MOS transistor; a drain of the thirteenth MOS transistor is connected with the ESD sampling line; the drain of the twelfth MOS transistor is also connected with a gate of the second MOS transistor; a source of the thirteenth MOS transistor is connected with a source of the eleventh MOS transistor; and a drain of the thirteenth MOS transistor is grounded.

Images