Driving method and driving system of power switch tube

Abstract

The invention relates to the technical field of power switches, and discloses a driving method and a driving system of a power switch tube, the driving method of the power switch tube is used for a driving circuit, and the method comprises the following steps: S1, controlling a driving transformer to output a pre-charging driving voltage, the amplitude of the pre-charging driving voltage is configured to be capable of driving a reverse bias voltage generation circuit to work so as to establish a reverse bias voltage, and an effective driving voltage applied to the control end of the power switch tube is kept below a conduction threshold voltage of the power switch tube; s2, the output of the pre-charging driving voltage is maintained until a preset reverse bias voltage establishment condition is met; and S3, the driving transformer is controlled to switch and output a working driving voltage, and the working driving voltage is configured to be higher than the sum of the conduction threshold voltage and the reverse bias voltage of the power switch tube so as to drive the power switch tube to be conducted. According to the invention, the misconduction risk of the power switch tube in the starting stage can be reduced.

Description

Technical Field

[0001] This application relates to the field of power switch technology, and in particular to a driving method and driving system for a power switching transistor. Background Technology

[0002] In power switching technology, full-bridge and half-bridge dual-terminal topologies are widely used, typically employing isolation transformers to drive the upper and lower bridge arms. The MCU outputs two complementary PWM drive waveforms, which, after isolation by the transformer, drive the upper and lower bridge arm power switches. These power switches are usually MOSFETs. When one bridge arm MOSFET is turned on, the drain voltage of the other bridge arm MOSFET rises rapidly. Due to the presence of the MOSFET's parasitic capacitor Cgd, its gate will couple a voltage spike, potentially causing the MOSFET to mis-turn on, leading to shoot-through damage to both bridge arms. It is usually necessary to pull the MOSFET's gate drive voltage to a specific negative voltage during the MOSFET's turn-off period to ensure that even if the gate is coupled with interference voltage, the gate voltage remains below the turn-on threshold.

[0003] In existing technologies, reverse bias voltage generation circuits are commonly used, such as charge pump circuits composed of diodes, Zener diodes, and capacitors. These circuits clamp the gate of the power switch at a reverse bias voltage during the turn-off period. However, existing negative voltage clamping schemes based on the charge pump principle rely primarily on the matching of the RC time constant and the circuit switching frequency for negative voltage establishment and maintenance. This is a passive working mechanism that relies on the inherent parameters of the circuit. This design works well in scenarios with fixed circuit parameters and stable operating conditions. However, in the system startup phase, in scenarios requiring frequency adjustment, or in scenarios with dynamic load changes, the timing and amplitude of negative voltage establishment are difficult to adjust in real time according to the actual operating conditions due to the limitations of the inherent response characteristics of the circuit. This may result in situations where the negative voltage has not been stably established before entering the normal driving phase, still posing a shoot-through risk. Summary of the Invention

[0004] To improve the problem of power transistor mis-conduction caused by traditional drive circuits, this application provides a driving method and driving system for power switching transistors.

[0005] Firstly, this application provides a method for driving a power switching transistor, which adopts the following technical solution: A method for driving a power switch transistor, applied to a drive circuit, the drive circuit including a drive transformer for driving the power switch transistor and a reverse bias voltage generation circuit connected between the secondary side of the drive transformer and the power switch transistor, the method including the steps of: S1, controlling the drive transformer to output a pre-charge drive voltage, the amplitude of the pre-charge drive voltage being configured to drive the reverse bias voltage generation circuit to operate, so as to establish a reverse bias voltage, and such that the effective drive voltage applied to the control terminal of the power switch transistor is kept below the turn-on threshold voltage of the power switch transistor; S2, maintaining the output pre-charge drive voltage until a preset reverse bias voltage establishment condition is met; S3, controlling the drive transformer to switch the output working drive voltage, the working drive voltage being configured to be higher than the sum of the turn-on threshold voltage and the reverse bias voltage of the power switch transistor, so as to drive the power switch transistor to turn on.

[0006] By adopting the above technical solution, a pre-charge drive voltage lower than the power switch's turn-on threshold is first output. This voltage is then used to drive the reverse bias voltage generation circuit to establish a reverse bias voltage while the power switch is not turned on. Once the establishment conditions are met, the circuit switches to the normal operating drive voltage, achieving an active control logic of "establishing reverse bias voltage first, then turning on the switch." Compared to traditional passive negative voltage generation schemes, this improves the problem of delayed reverse bias voltage establishment during startup, frequency conversion, or dynamic load scenarios. It ensures that the power switch gate is in a safe reverse bias state from the first normal drive cycle, reducing the risk of shoot-through in the upper and lower bridge arms.

[0007] Optionally, the determination steps until the preset reverse bias voltage establishment condition is met include: starting a timer or counter, and counting the duration of the output precharge drive voltage or the number of switching cycles; if the duration reaches a preset first duration threshold, or the number of cycles reaches a preset first cycle number threshold, then the reverse bias voltage establishment condition is determined to be met.

[0008] By adopting the above technical solution, the timing determination logic is simple and direct, requiring no additional voltage acquisition circuit; it can be implemented using a timer or counter, reducing system complexity and cost. The preset duration or period threshold has been experimentally verified to ensure that the reverse bias voltage generation circuit fully completes charging, meeting the reliability requirements of most common application scenarios and adapting to cost-sensitive, stable operating environments.

[0009] Optionally, the determination steps until the preset reverse bias voltage establishment condition is met include: S21, acquiring the reverse bias voltage amplitude at the control terminal of the power switch tube; S22, comparing the reverse bias voltage amplitude with the preset target reverse bias voltage threshold. If the reverse bias voltage amplitude is greater than or equal to the target reverse bias voltage threshold, it is determined that the reverse bias voltage establishment condition is met.

[0010] By adopting the above technical solution, adaptive judgment is achieved based on voltage feedback, without relying on fixed timing. It can accurately match scenarios with different component parameter tolerances, temperature changes, and input voltage fluctuations. The working signal is only switched when the reverse bias voltage reaches the target reverse bias voltage threshold, ensuring reliable and effective reverse bias voltage clamping, preventing judgment errors caused by parameter drift, and further improving the system's adaptability and stability.

[0011] Optionally, the driving circuit further includes a driving level switching circuit connected to the primary side of the driving transformer, and the controlled terminal of the driving level switching circuit is connected to a control circuit; in step S1, controlling the driving transformer to output the pre-charge driving voltage specifically includes: the control circuit sending a pre-charge control command to the driving level switching circuit, controlling the driving level switching circuit to input a first voltage to the driving transformer, so that the driving transformer outputs the pre-charge driving voltage; in step S3, controlling the driving transformer to switch the output working driving voltage specifically includes: when the preset reverse bias voltage establishment condition is met, the control circuit sending a working control command to the driving level switching circuit, controlling the driving level switching circuit to input a second voltage to the driving transformer, so that the driving transformer switches to output the working driving voltage.

[0012] By adopting the above technical solution, and relying on the cooperation of the control circuit and the drive level switching circuit, the input voltage of the drive transformer is accurately adjusted, thereby realizing the switching of the output voltage amplitude. The logic link is clear and highly controllable, ensuring a smooth transition between pre-charging and operating states, and reducing the impact of voltage surges on the circuit.

[0013] Optionally, the reverse bias voltage generation circuit includes an auxiliary switch, a rectifier diode, an energy storage capacitor, and a Zener diode. The rectifier diode is positioned between the control terminal and the output terminal of the auxiliary switch, forming a switching charging circuit. The input terminal of the switching charging circuit is connected to the secondary side of the drive transformer, and the output terminal is connected to the first terminal of the energy storage capacitor. The second terminal of the energy storage capacitor is connected to the gate of the power switch. The Zener diode is connected in parallel with the energy storage capacitor to clamp the voltage across the energy storage capacitor, thereby forming a reverse bias voltage. In step S1, the pre-charge drive voltage charges the energy storage capacitor through the switching charging circuit, thereby establishing a potential difference across the energy storage capacitor and forming a reverse bias voltage acting on the gate of the power switch. The amplitude of the reverse bias voltage is configured to be lower than the turn-on threshold voltage of the power switch.

[0014] By adopting the above technical solution, the switching charging circuit can efficiently charge the energy storage capacitor, and the Zener diode clamps the reverse bias voltage to ensure that the voltage is stable within a safe range. The pre-charge drive voltage is reliably established through this circuit to achieve the reverse bias voltage. The circuit has a mature structure and low cost. When combined with active control logic, it controls hardware costs while ensuring performance.

[0015] Optionally, the preset first duration threshold is 0.3ms to 0.5ms, and the preset first cycle number threshold is 40 to 60 switching cycles.

[0016] By adopting the above technical solution, the first duration threshold of 0.3ms to 0.5ms or the threshold of 40 to 60 switching cycles can be compatible with energy storage capacitors of different capacitance values, ensuring that they are fully charged and establish a stable reverse bias voltage, thereby improving the system's adaptability to different device parameters.

[0017] Optionally, the method further includes a monitoring and protection step: while outputting the pre-charge drive voltage, start a timer or counter to count the duration or number of switching cycles of the pre-charge drive voltage; if the duration reaches a preset second duration threshold, or the number of cycles reaches a preset second cycle number threshold, and the amplitude of the reverse bias voltage at the control terminal of the power switch is still less than the target reverse bias voltage threshold, then it is determined that there is a fault in the drive circuit, the second duration threshold is greater than the first duration threshold, and the second cycle number threshold is greater than the first cycle number threshold; stop outputting the pre-charge drive voltage, lock the system, or output a fault alarm signal.

[0018] By adopting the above technical solution and adding a fault diagnosis and protection mechanism, the problem of traditional hardware circuits continuing to operate abnormally until they are damaged when the reverse bias voltage fails to establish can be prevented. When it is detected that the reverse bias voltage cannot reach the target within the maximum allowable time, the drive is stopped in time and the protection is triggered. This not only prevents the power switching transistor from being shot-through due to the lack of reverse bias voltage clamping, but also prompts maintenance through fault alarms, thereby improving system safety and maintainability.

[0019] Secondly, the power switching transistor driving system provided in this application adopts the following technical solution: A driving system for a power switch includes a control circuit and a driving circuit. The control circuit is configured to generate control commands and drive control signals. The input terminal of the driving circuit is connected to the control circuit, and the output terminal is connected to the power switch. The driving circuit includes a drive level switching circuit, a drive transformer, and a reverse bias voltage generation circuit. The input terminal of the drive level switching circuit is connected to the control circuit and is configured to adjust the amplitude of the output voltage according to the control commands. The primary side of the drive transformer is connected to the output terminal of the drive level switching circuit, used to isolate and transmit the voltage signal output by the drive level switching circuit to the secondary side. The reverse bias voltage generation circuit is connected between the secondary side of the drive transformer and the control terminal of the power switch. The control circuit controls the drive level switching circuit to output voltages of different amplitudes, which, after transmission through the drive transformer, cooperate with the reverse bias voltage generation circuit to establish a reverse bias voltage or drive conduction voltage at the control terminal of the power switch.

[0020] By adopting the above technical solution, an intelligent drive link of "detection-decision-execution" is constructed. The drive level switching circuit realizes flexible adjustment of voltage amplitude, the drive transformer ensures electrical isolation and signal transmission, and the reverse bias voltage generation circuit completes the establishment of reverse bias voltage. The modules work together to realize active reverse bias voltage drive control, improve the reliability defects of traditional passive solutions, and at the same time utilize mature circuit topology to balance performance, cost and feasibility.

[0021] Optionally, the drive level switching circuit includes at least one of a digital potentiometer, a programmable power supply, or a multiplexer switch, for switching between a first voltage and a second voltage after receiving a command from the control circuit.

[0022] By adopting the above technical solutions, a variety of drive level switching circuit selection options are provided. Digital potentiometers, programmable power supplies, and multi-channel power supply switching switches are all mature power electronic devices or modules with strong compatibility and high control precision. Different selections can adapt to application requirements with different costs and control precision, enhancing the system's flexibility and scalability.

[0023] Optionally, a drive level detection circuit is also included, connected between the gate of the power switch and the control circuit, for acquiring the gate drive voltage and feeding it back to the control circuit.

[0024] By adopting the above technical solution, the drive level detection circuit provides a voltage feedback signal to the control circuit, enabling the control circuit to monitor the establishment of the reverse bias voltage in real time and achieve adaptive judgment and fault diagnosis functions. The introduction of the feedback mechanism gives the system intelligent adjustment capabilities, enabling it to cope with complex operating conditions such as component parameter drift and temperature changes, further improving the reliability of the reverse bias voltage clamping and the overall safety of the system.

[0025] In summary, this application includes at least one of the following beneficial technical effects: 1. A pre-charge drive voltage lower than the power switch's turn-on threshold is first output. This voltage is used to drive the reverse bias voltage generation circuit to establish a reverse bias voltage while the power switch is not conducting. Once the establishment condition is met, the voltage is switched to the normal operating voltage, achieving an active control logic of "establishing negative voltage first, then conducting the switch." Compared to traditional passive negative voltage generation schemes, this improves the problem of delayed negative voltage establishment in startup, frequency conversion, or dynamic load scenarios. It ensures that the power switch gate is in a safe negative voltage state from the first normal drive cycle, preventing shoot-through between the upper and lower bridge arms. 2. Supports two modes: timing determination and voltage feedback adaptive determination, to adapt to different operating conditions. It also adds a fault diagnosis and protection mechanism, which can detect reverse bias voltage establishment failure faults in a timely manner and trigger protection to prevent circuit damage and improve system safety and maintainability. 3. The system relies on existing MCU and other control resources, and achieves hardware security through software algorithm upgrades. It does not require complex and expensive new components, and balances cost-effectiveness and performance advantages. Moreover, the circuit topology is mature and flexible in selection, and it is compatible with various isolation transformer drive scenarios such as full bridge and half bridge double-ended conversion topologies. Attached Figure Description

[0026] Figure 1 This is a structural diagram of the drive system provided by related technologies; Figure 2 This is another drive system structure diagram provided by related technologies; Figure 3 These are simulation waveforms of the driving signal timing provided by related technologies; Figure 4 This is a structural diagram of the driving system provided in the embodiments of this application; Figure 5 This is another drive system structure diagram provided in the embodiments of this application; Figure 6 This is a flowchart of the driving method provided in the embodiments of this application; Figure 7 This is a simulation waveform diagram of the driving signal timing provided in the embodiments of this application; Figure 8 This is a logic flowchart of the driving method provided in the embodiments of this application; Figure 9 This is another logic flowchart of the driving method provided in the embodiments of this application.

[0027] Explanation of reference numerals in the attached figures: 1. Control circuit; 2. Drive circuit; 3. Power switching transistor; 4. Drive level detection circuit. Detailed Implementation

[0028] The following is in conjunction with the appendix Figure 1-9 This application will be described in further detail.

[0029] Reference Figure 1 The transformer-isolated drive structure provided for related technologies uses a MUC to output complementary A and B PWM drive waveforms, which, after isolation by the isolation transformer T1, drive the upper bridge arm MOSFET switch Q1 and the lower bridge arm MOSFET switch Q2. When the drive level is positive, Q1 is turned on via D1. When the drive level changes to 0 or negative, the P-channel MOSFET auxiliary switch Q1A pulls the drive level of Q1 down to 0, turning off Q1. The turn-on and turn-off of Q2 are similar and will not be described further.

[0030] When Q1 is on, Q2 should be off. However, in practical applications, when Q1 is on, the drain voltage of Q2 rises rapidly. Due to the presence of the MOSFET parasitic capacitor Cgd (not shown in the figure), a voltage spike will couple at the gate Vg2 of Q2, which may cause Q2 to be falsely turned on, resulting in shoot-through damage to the upper and lower bridge arms. The false turn-on situation of Q1 is similar.

[0031] To reduce the risk of shoot-through short circuits in the upper and lower bridge arm MOSFETs, it is typically necessary to pull their gate drive voltage to a specific negative voltage (for N-type MOSFETs) during MOSFET turn-off. For example, when the lower bridge arm Q2 is turned off, its gate voltage Vg2 is clamped to a specific negative value. When the upper bridge arm Q1 is turned on, even if interference voltage is coupled to the gate of Q2, it ensures that Vg2 remains below the turn-on threshold, thereby reducing the shoot-through risk of both the upper and lower bridge arms. Figure 2 As shown, a negative voltage generation circuit is set at the input terminals of the upper and lower bridge arm MOSFETs. Its principle lies in utilizing the charge pump characteristic. Taking Q2 as an example, when the isolation transformer T1 is driven positively, Q2 is driven through D2, simultaneously charging capacitor C2. The capacitor is positive on the left and negative on the right, with the maximum voltage across the capacitor being the regulated voltage Vz2 of the Zener diode Z2. When the drive turns negative, the PMOS turns on, and Vg2 discharges. The left end of the capacitor voltage is pulled low to 0 by the PMOS. Since the capacitor voltage cannot change abruptly, the right end of the capacitor voltage is clamped at -Vz2, meaning the gate of Q2 is pulled low at -Vz2. As long as the capacitor energy remains constant, the gate of Q2 will always be clamped at -Vz2.

[0032] like Figure 3 The figure shows the simulated drive waveforms for a transformer isolation drive scheme with negative voltage compensation. The upper waveform Vab in the figure represents the waveform of the primary winding of the drive transformer, and the lower waveform represents the drive waveform generated at Vg2 after passing through the isolation transformer. Due to the presence of C2, the negative capacitor of Vg2 gradually builds up (approximately 10 cycles), and the final negative voltage reaches -Vz2.

[0033] In related technologies, the mainstream negative voltage generation scheme adopts a passive topology structure of "diode D, Zener diode Z, and capacitor C". The reliability of negative voltage establishment in this topology depends entirely on the matching relationship between the RC time constant and the switching frequency. It is a passive response, slow adjustment, and uncontrollable working process. Under conditions such as system startup, parameter drift, frequency conversion operation, or dynamic load switching, the negative voltage clamping failure is easily caused by the untimely or unreliable establishment of the clamping capacitor voltage, which in turn leads to the risk of shoot-through between the upper and lower arms of the bridge circuit.

[0034] To address the aforementioned shortcomings, existing technologies have proposed some improvement solutions, but these either introduce complex auxiliary control circuits, leading to a significant increase in system hardware costs, or employ customized special-purpose devices, reducing the versatility and compatibility of the solutions.

[0035] Therefore, referring to Figure 4 This application discloses a driving system for a power switch transistor, comprising: a control circuit 1 and a driving circuit 2. The control circuit 1 is configured to generate control commands and drive control signals. The input terminal of the driving circuit 2 is connected to the control circuit 1, and the output terminal is used to connect to the power switch transistor 3. The driving circuit 2 includes a drive level switching circuit, a drive transformer T1, and a reverse bias voltage generation circuit. The input terminal of the drive level switching circuit is connected to the control circuit 1 and is configured to adjust the amplitude of the output voltage according to the control command. The primary side of the drive transformer is connected to the output terminal of the drive level switching circuit and is used to isolate and transmit the voltage signal output by the drive level switching circuit to the secondary side. The reverse bias voltage generation circuit is connected between the secondary side of the drive transformer and the control terminal of the power switch transistor 3. The control circuit 1 controls the drive level switching circuit to output voltages of different amplitudes, which are transmitted through the drive transformer and, in conjunction with the reverse bias voltage generation circuit, establish a reverse bias voltage or a drive conduction voltage at the control terminal of the power switch transistor 3.

[0036] Specifically, the driving system of this application is applicable to the driving of power switching devices in power electronic topologies such as full-bridge and half-bridge, for example... Figure 4 As shown, the upper and lower bridge arm power switches 3 (upper bridge power switch Q1 and lower bridge power switch Q2) of the half-bridge topology are illustrated. In the drive system, the control circuit 1 can be a microcontroller unit (MCU), a digital signal processor (DSP), or a field-programmable gate array (FPGA), which can generate control commands such as pre-charge and drive, and output PWM signals (DrvA and DrvB in the figure). The drive circuit 2 includes a drive level switching circuit, a drive transformer T1, and a reverse bias voltage generation circuit. The drive level switching circuit can be a level conversion chip, a programmable power supply, or a multi-channel power supply. The switching network and the amplification ratio switching circuit controlled by the digital potentiometer can switch the output voltage signal of different amplitudes according to the command output by the control circuit 1 to meet the different voltage requirements of pre-charge drive and working drive. The drive transformer T1 is an isolated pulse transformer to achieve electrical isolation between the control side and the power side. The reverse bias voltage generation circuit consists of auxiliary switching transistors (Q1A, Q1B), rectifier diodes (D1, D2), energy storage capacitors (C1, C2), and Zener diodes (Z1, Z2) to generate the reverse bias voltage. The drive system of the power switching transistor 3 in this application, through active control, can ensure that the MOSFET gate is in a safe state from the first normal drive switching cycle, reducing the risk of mis-start.

[0037] The following explanation uses the driving process of the lower bridge power switch Q2 as an example: Reference Figure 4After the system is powered on, control circuit 1 outputs a pre-charge drive signal (PWM pulse, Vg_pre), and drive level switching circuit outputs a low-amplitude first voltage. This low-amplitude voltage is transmitted to the secondary side of drive transformer T1 through primary isolation to form the pre-charge drive voltage.

[0038] On the secondary side of T1, the induced current charges the energy storage capacitor C2 through the rectifier diode D2; simultaneously, the Zener diode Z2 connected in parallel across C2 clamps the voltage across C2. Through this charging process, a stable DC voltage difference (e.g., 2V) is established across the energy storage capacitor C2, which constitutes the reverse bias voltage source for the power switch 3 (Q2). During this pre-charging phase, because the pre-charging drive voltage amplitude is low (e.g., 5V output through DrvA_1), after deducting the voltage drop across C2, the effective voltage applied to the control terminal (Vg2) of Q2 (5-2=3V) is lower than the turn-on threshold of Q2 (e.g., 4V), therefore Q2 remains off.

[0039] Subsequently, control circuit 1 outputs a working drive signal (Vg_nom), and the drive level switching circuit outputs a second voltage with a high amplitude (e.g., 18V via DrvA_1). This high-amplitude voltage is transmitted to the secondary side via T1 to form the working drive voltage, which is superimposed on the voltage already established by the energy storage capacitor C2. At this time, after the voltage amplitude output by T1 overcomes the reverse voltage drop of C2, the remaining voltage (e.g., 18V-2V=16V) is greater than the turn-on threshold of Q2 (e.g., 4V), thus driving Q2 to conduct reliably. During the low level of the PWM signal, since the output of T1 is zero or low, the voltage across C2 will cause the control terminal of Q2 to present a negative voltage (e.g., -2V), achieving reliable turn-off. The driving process of the upper bridge Q1 is symmetrical to that of Q2, and pre-charging and working drive are independently completed through another set of secondary sides of T1, realizing isolated control of the upper and lower bridge arms.

[0040] Understandably, in this embodiment, the drive system achieves flexible adjustment of voltage amplitude through a drive level switching circuit, the drive transformer ensures electrical isolation and signal transmission, and the reverse bias voltage generation circuit establishes the reverse bias voltage. All modules work together to achieve active reverse bias voltage drive control, improving the reliability deficiencies of traditional passive solutions. Simultaneously, by utilizing a mature circuit topology, performance, cost, and feasibility are balanced.

[0041] It should be noted that, given certain hardware circuit parameters (such as the drive transformer turns ratio, energy storage capacitor capacitance, and loop impedance), the time constant required for energy storage capacitors C1 / C2 to charge to the target reverse bias voltage is relatively fixed. Therefore, control circuit 1 (such as an MCU) can internally preset a fixed "pre-charge duration" (this duration can be obtained through theoretical calculation or experimental calibration, with a certain safety margin, for example, set to tens of microseconds to a few milliseconds). After the system is powered on, control circuit 1 first outputs a pre-charge control command to maintain this preset duration. After the timing ends, control circuit 1 assumes that the reverse bias voltage has been established and then automatically switches to the normal operating drive mode.

[0042] In this open-loop control implementation, the hardware drive level detection circuit 4 and its feedback loop can be omitted, which can further reduce the hardware cost and wiring complexity of the circuit, reduce the system size, and is suitable for cost-sensitive or space-constrained application scenarios.

[0043] like Figure 5 As shown, in one embodiment, the driving system of the power switch 3 is equipped with a drive level detection circuit 4. The drive level detection circuit 4 collects the control terminal voltage of the power switch 3 through a sampling circuit (not shown in the figure) composed of a voltage divider resistor and an operational amplifier, and feeds it back to the control circuit 1. The drive level detection circuit 4 provides a voltage feedback signal to the control circuit 1, enabling the control circuit 1 to monitor the establishment of the reverse bias voltage in real time and realize adaptive judgment and fault diagnosis functions. Specifically, the drive level detection circuit 4 collects the voltage signal of Vg2 and feeds it back to the control circuit 1. When the amplitude of the reverse bias voltage (i.e., the voltage across C2) reaches the standard, the control circuit 1 determines that the pre-charging is complete and then outputs the working drive signal (Vg_nom).

[0044] It is understood that the driving system of this application constructs an intelligent driving link of "detection-decision-execution". The introduction of the feedback mechanism enables the system to have intelligent adjustment capabilities, which can cope with complex operating conditions such as component parameter drift and temperature changes, and further improve the reliability of reverse bias voltage clamping and the overall safety of the system.

[0045] It should be noted that in this embodiment, the power switch transistors 3 (Q1, Q2) are N-type MOSFETs, and the corresponding reverse bias voltage is negative to ensure that the voltage between their gate and source is lower than the turn-on threshold, so that the power switch transistors 3 can be reliably turned off. In other embodiments, when the power switch transistors 3 are P-type MOSFETs, the corresponding reverse bias voltage is positive. The polarity of the reverse bias voltage is the opposite of the polarity required for the power switch transistors 3 to turn on. Its function is to make the effective voltage at the control terminal of the power switch transistors 3 lower than the turn-on threshold, so as to achieve reliable turn-off of the device and suppress unexpected turn-on.

[0046] It should be noted that in conventional drive circuit design, the design convention generally followed by technicians is to pursue "fast response of drive signals" and "the strongest possible drive capability," that is, it is generally believed that once the drive signal is issued, the device should respond immediately and enter the conduction state. However, the embodiments of this application optimize the relationship between system safety and performance by introducing a pre-charge timing strategy (signal present but not conducting). By using staged variable amplitude drive, the problem of false turn-on that is prone to occur at the moment of startup of high-voltage high-power devices is suppressed. Specifically, this application uses a low-amplitude pre-charge stage to ensure that the gate of the power device has a negative voltage clamping environment established in advance before it is subjected to the high-voltage bus voltage impact. This active defense mechanism enables the system to reduce the risk of false turn-on caused by Miller effect or line noise at the physical level, even at the moment of power-on in a harsh electromagnetic environment, thereby improving the robustness and reliability of the system.

[0047] In one embodiment, the drive level switching circuit includes at least one of a digital potentiometer, a programmable power supply, or a multiplexer switch, for switching between a first voltage amplitude and a second voltage amplitude after receiving a command from the control circuit 1. Among them, digital potentiometers are suitable for low-power, high-precision driving scenarios, such as laboratory-level power switch tube 3 test platforms or small power electronic devices. They have the advantages of small size and fine adjustment steps, and can achieve millivolt-level voltage amplitude fine adjustment through serial commands of control circuit 1 to meet the matching requirements of pre-charge drive voltage and working drive voltage. Programmable power supplies are suitable for medium and high power, multi-condition switching industrial scenarios, such as drive systems of electric arc furnaces, frequency converters and other equipment. This type of device supports a wide voltage output range and fast amplitude switching response. Multiple sets of voltage parameters can be flexibly configured according to the conduction threshold and reverse bias voltage requirements of different power switch tubes 3. At the same time, it has overvoltage and overcurrent protection functions to improve the stability of the drive system. Multi-power supply switching switches are more suitable for cost-sensitive, fixed-topology standardized drive scenarios, such as mass-produced general-purpose power modules. They achieve fast switching by preset two fixed amplitude power supplies in conjunction with the level signal of control circuit 1. They have the characteristics of simple structure, high reliability and low maintenance cost, and can meet the cost-effectiveness requirements of large-scale applications.

[0048] Specifically, when using a multi-power supply switching scheme, the drive circuit 2 can preset two independent DC power supplies, VCC_pre (e.g., 5V) and VCC_work (e.g., 18V). The control circuit 1 controls an analog switch (such as a high-speed MOSFET switch group) through a simple GPIO high / low level signal, selecting to connect VCC_pre or VCC_work to the primary power supply circuit of the drive transformer T1, achieving rapid switching between the two voltage levels. This scheme is low-cost and has a fast response. When using a programmable power supply or an operational amplifier controlled by a digital potentiometer, the control circuit 1 can send digital commands to the circuit via serial buses such as SPI or I2C to precisely set the amplitude of the output voltage. This scheme is highly flexible, not only achieving two-level switching but also smooth voltage transitions or multi-level adjustment, making it suitable for high-performance applications requiring fine-grained management of the drive waveform.

[0049] Understandably, offering multiple drive level switching circuit options, including digital potentiometers, programmable power supplies, and multi-channel power supply switches, provides a range of mature power electronic devices or modules with strong compatibility and high control precision. Different selections can adapt to application requirements with varying costs and control precision, enhancing system flexibility and scalability.

[0050] like Figure 6 As shown, this application also discloses a driving method for a power switching transistor, applied to a driving circuit 2, the method comprising the following steps: S1. Control the output of the drive transformer to precharge drive voltage. The amplitude of the precharge drive voltage is configured to drive the reverse bias voltage generation circuit to work to establish a reverse bias voltage, and to keep the effective drive voltage applied to the control terminal of the power switch 3 below the turn-on threshold voltage of the power switch 3. Specifically, in combination Figure 4 or Figure 5Taking the driving process of the lower-bridge power switch Q2 as an example, the specific execution process of this step in the half-bridge topology driving system shown is as follows: Control circuit 1 outputs a pre-charge control command (pre-charge drive signal), and the drive level switching circuit outputs a first voltage in response to the command. The first voltage is input to the primary side of drive transformer T1. After the control side and power side are electrically isolated by drive transformer T1, the signal is transmitted to its secondary side, where a pre-charge drive voltage is induced. The pre-charge drive voltage has a first voltage amplitude, for example, 5V. In the secondary circuit of drive transformer T1, the induced current flows to the energy storage capacitor C2 through the rectifier diode D2 in the reverse bias voltage generation circuit, completing the charging of energy storage capacitor C2. At the same time, the Zener diode Z2 connected in parallel across energy storage capacitor C2 works synchronously to clamp the voltage across energy storage capacitor C2, ensuring the stability of the charging process. Through the above charging process, a stable DC voltage difference (for example, 2V) is gradually established across energy storage capacitor C2. This DC voltage difference constitutes the reverse bias voltage source of power switch Q2.

[0051] It should be noted that the first voltage amplitude set in this step (e.g., 5V) can drive the reverse bias voltage generation circuit to work (e.g., greater than the forward voltage drop of rectifier diode D2, 0.2~0.2V for Schottky diode, and 0.7V for silicon rectifier diode). After deducting the 2V voltage drop across energy storage capacitor C2, the effective voltage finally applied to the control terminal (Vg2) of Q2 is still lower than the turn-on threshold of Q2 (e.g., 4V). Therefore, throughout the pre-charging stage, the power switch Q2 remains in the off state, avoiding the risk of mis-turn-on during the pre-charging stage.

[0052] S2. Maintain the output pre-charge drive voltage until the preset reverse bias voltage establishment condition is met. In one embodiment, the reverse bias voltage establishment condition can be set by a fixed timing determination method, specifically as follows: Figure 4 As shown, while outputting the drive signal, the control circuit 1 simultaneously starts the built-in timer or counter to count the duration of the pre-charge drive voltage or the number of output switching cycles. If the counted duration reaches a preset first duration threshold or the counted number of cycles reaches a preset first cycle number threshold, then the reverse bias voltage establishment condition is satisfied.

[0053] Understandably, the timing determination logic is simple and direct, requiring no additional voltage acquisition circuit. It can be implemented using the built-in timer or counter of control circuit 1, reducing system hardware complexity and production costs. The preset duration or period threshold has been experimentally verified to ensure that the reverse bias voltage generation circuit can fully complete charging under normal component parameters and standard operating conditions, meeting the reliability requirements of most general-purpose power electronic devices, and is especially suitable for cost-sensitive, stable, large-scale application environments.

[0054] In one embodiment, the reverse bias voltage establishment condition can also be set through an adaptive determination method based on voltage feedback, such as... Figure 5 As shown, the determination steps include: S21, Drive level detection circuit 4 collects the reverse bias voltage amplitude (i.e., the absolute value of the voltage value of energy storage capacitor C2) on the control terminal (Vg2) of power switch Q2 in real time. S22. Control circuit 1 compares the acquired reverse bias voltage amplitude with a preset target reverse bias voltage threshold (e.g., 2V). If the acquired reverse bias voltage amplitude is greater than or equal to the target reverse bias voltage threshold, the reverse bias voltage establishment condition is determined to be met.

[0055] Specifically, the voltage input to the control terminal of Q2 is acquired in real time through the drive level detection circuit 4. Since this voltage value is negative (e.g., -2V) during the off-state interval of the PWM pulse cycle during pre-charging, the circuit converts it into a positive voltage amplitude signal or digital signal and feeds it back to the MCU (control circuit 1). The preset target reverse bias voltage threshold is set to 2V (corresponding to a physical -2V reverse bias depth). If the feedback reverse bias voltage amplitude gradually rises and reaches 2V or higher (e.g., acquiring 2.2V means the negative voltage depth reaches -2.2V), the control circuit 1 determines that the reverse bias voltage has been reliably established (i.e., the energy storage capacitor C2 is sufficiently charged). At this point, the pre-charging drive voltage can be stopped, and preparations can be made to switch to the working drive stage.

[0056] By adopting the above technical solution, adaptive judgment is achieved based on voltage feedback, eliminating the need for fixed timing and accurately matching scenarios with different component parameter tolerances, temperature changes, and input voltage fluctuations. For example, when the ambient temperature rises, causing a slight decrease in the capacity of the energy storage capacitor, the voltage feedback mechanism can sense the charging progress in real time and extend the pre-charge maintenance time until the voltage reaches the target. Furthermore, if the input voltage fluctuates, voltage acquisition ensures that the reverse bias voltage always reaches the target reverse bias voltage threshold. The operating signal is only switched when the reverse bias voltage reaches the target reverse bias voltage threshold, ensuring reliable and effective reverse bias voltage clamping, preventing judgment errors caused by parameter drift, and further improving the system's adaptability and stability.

[0057] It should be noted that the preset "target reverse bias voltage threshold" is determined based on the safety cut-off requirements of power switch 3. Since the pre-charge drive voltage (e.g., 5V) output by the drive transformer is higher than the turn-on threshold voltage (e.g., 4V) of the N-type power switch Q2 during the pre-charge phase, if a sufficient voltage difference has not yet been established across the energy storage capacitor C2, directly applying this drive voltage signal may cause Q2 to turn on unexpectedly.

[0058] Therefore, the target reverse bias voltage threshold (Vta) must satisfy the following condition: the difference between the pre-charge drive voltage (VD) and the target reverse bias voltage threshold (Vta) is less than the turn-on threshold voltage Vth of power switch 3 (i.e., VD-Vta). <Vth)。

[0059] In this embodiment, if the pre-charge drive voltage is 5V and the Q2 turn-on threshold is 4V, considering the circuit noise margin and safety margin, the target reverse bias voltage threshold is set to 2V. In this case, the Zener diode Z2 connected in parallel across capacitor C2 is preferably a 2V specification adapted to this threshold, used for clamping after the voltage is established.

[0060] S3 controls the drive transformer to switch the output working drive voltage. The working drive voltage is configured to be higher than the sum of the turn-on threshold voltage and the reverse bias voltage of the power switch 3, so as to drive the power switch 3 to turn on.

[0061] Specifically, controlling the drive transformer to switch the output working drive voltage includes: when the preset reverse bias voltage establishment condition is met, the control circuit 1 sends a working control command (working drive signal) to the drive level switching circuit, and controls the drive level switching circuit to input a second voltage higher than the first voltage to the drive transformer, so that the drive transformer switches to output the working drive voltage (e.g., 18V).

[0062] It should be noted that the amplitude of the working drive voltage is higher than the sum of the turn-on threshold voltage and the reverse bias voltage of the power switch 3. For example, the preset turn-on threshold voltage of Q2 is 4V, and the reverse bias voltage established during the pre-charging stage is 2V, with a sum of 6V. However, the amplitude of the working drive voltage set in this embodiment is 18V, which is much higher than 7V. After the second voltage is transmitted to the secondary side through the drive transformer T1, it forms the working drive voltage. This voltage is superimposed on the 2V reverse bias voltage already established by the energy storage capacitor C2. After offsetting the reverse voltage drop of the reverse bias voltage, the effective drive voltage finally applied to the control terminal (Vg2) of Q2 is 16V. This effective voltage is still higher than the 4V turn-on threshold of Q2, thus enabling reliable drive of Q2 to turn on.

[0063] In this embodiment, the input voltage of the drive transformer is accurately adjusted through the cooperation of control circuit 1 and drive level switching circuit, thereby realizing the switching of output voltage amplitude. The logic link is clear and highly controllable, ensuring a smooth transition between pre-charging and operating states and preventing voltage surges from impacting the circuit.

[0064] Understandably, the driving method of this application first outputs a pre-charge driving voltage lower than the conduction threshold of power switch 3. Under the premise that power switch 3 is not conducting, it drives the reverse bias voltage generation circuit to establish a reverse bias voltage. Once the establishment condition is met, it switches to the normal operating driving voltage, realizing the active control logic of "establishing reverse bias voltage first, then turning on the switch". Compared with the traditional passive negative voltage generation scheme, this improves the problem of lag in negative voltage establishment during startup, frequency conversion, or dynamic load scenarios. From the first normal driving cycle, it ensures that the gate of power switch 3 is in a safe reverse bias voltage state, preventing shoot-through of the upper and lower bridge arms.

[0065] like Figure 7 As shown, to describe the switching logic of the drive signal and the establishment process of the reverse bias voltage, a timing simulation waveform of the drive signal in this application is displayed. In one embodiment, the preset first duration threshold is 0.3ms to 0.5ms, and the preset first cycle number threshold is 40 to 60 switching cycles. Preferably, the preset first duration threshold is 0.4ms, and the first cycle number threshold is 40 PWM cycles (the pre-charge drive signal is in PWM form). The control circuit 1 outputs the pre-charge drive signal (Vab) and starts the timer simultaneously. When the timer displays a duration of 0.4ms, or the counter counts the number of output PWM cycles to reach 40, it is determined that the pre-charge is complete and the reverse bias voltage establishment condition is met. In the figure, the 0~0.0004s (0.4ms) stage corresponds to the low-amplitude pre-charge drive stage. After 0.0004s, the waveform switches to a high-amplitude pulse, that is, after the pre-charge is completed, the normal drive stage begins.

[0066] The waveform Vab is the PWM signal output by control circuit 1 (MCU). After being coupled through the drive level switching circuit and the isolation transformer, this waveform is applied to the control terminal (Vg2) of power switch 3. During the 0s~0.0004s (pre-charge phase): the MCU controls the primary side of the isolation transformer to generate a low-voltage excitation, causing the output Vab to be a relatively low-amplitude AC pulse waveform (e.g., ±5V), and controls the drive level switching circuit to input the first voltage to the drive transformer. During this phase, the signal is mainly used to provide energy to the energy storage capacitor C2. After 0.0004s (normal drive phase): the MCU switches its control strategy, causing the output Vab amplitude to expand to a larger amplitude AC pulse waveform (e.g., ±18V).

[0067] The Vg waveform represents the gate-source control voltage of power switch 3, indicating the voltage difference across energy storage capacitor C2. From 0s to 0.0004s, although the input signal Vab maintains a constant amplitude, the Vg waveform shows an overall downward shift. This is because energy storage capacitor C2 is accumulating charge, and its voltage (i.e., reverse bias voltage) gradually increases. According to the series voltage relationship, the DC level of Vg2 is pulled low, and the positive peak value of Vg2 shifts downward and remains below the MOSFET's turn-on threshold (Vth, e.g., 4V), ensuring reliable MOSFET turn-off (non-conducting) during pre-charging. Simultaneously, the negative peak value of Vg2 gradually decreases to the preset clamping voltage (e.g., -2V), marking the completion of negative voltage establishment.

[0068] After 0.0004s, as Vab switches to a high amplitude, the positive peak of Vg jumps to a level sufficient to saturate and turn on the MOSFET (e.g., 12.5V), while the negative voltage during the turn-off period is still clamped at a safe value, thus achieving normal drive with negative voltage turn-off protection.

[0069] Reference Figure 8 The following is a logical flowchart of the driving method provided in one embodiment of the present application. The complete process is as follows: The system first completes the power-on initialization, and then enters the pre-charge drive stage, outputting a low-amplitude pre-charge PWM signal (Vg_pre); at the same time, it continuously monitors the drive level Vg2 at the control terminal of the power switch Q2 to determine whether its reverse bias voltage Vg2_neg reaches the voltage regulation value of the Zener diode Vz2 (i.e., the target threshold for the establishment of the reverse bias voltage).

[0070] If Vg2_neg does not reach Vz2, the output of the pre-charge drive signal will continue to be maintained, and the level detection and threshold judgment will be performed cyclically. If Vg2_neg≥Vz2, it means that the reverse bias voltage has been established stably and the switching condition is met. Then, the drive circuit 2 is controlled to switch to the high-amplitude normal drive signal (Vg_nom), and the system finally enters the normal working state.

[0071] It is understood that this embodiment presents the logic from establishing the reverse bias voltage during pre-charging to reaching the detection threshold and then switching to normal drive, reflecting the reliability of the pre-charging stage and the smoothness of the switching process.

[0072] Reference Figure 9In one embodiment, the method further includes a monitoring and protection step: while outputting the pre-charge drive voltage, a timer or counter is started to count the duration or number of switching cycles of the pre-charge drive voltage; if the duration reaches a preset second duration threshold, or the number of cycles reaches a preset second cycle number threshold, and the reverse bias voltage amplitude at the control terminal of the power switch 3 is still less than the target reverse bias voltage threshold, then the drive circuit 2 is determined to have a fault; the output of the pre-charge drive voltage is stopped, and a protection action of locking the system or outputting a fault alarm signal is performed.

[0073] In one embodiment, the preset second duration threshold is 1ms (greater than the first duration threshold of 0.4ms), and the second cycle number threshold is 100 switching cycles (greater than the second cycle number threshold). While outputting the pre-charge drive signal, the control circuit 1 simultaneously starts the timer and counter. If the duration counted by the timer reaches 1ms, or the number of switching cycles counted by the counter reaches 100, and the reverse bias voltage amplitude of the Q2 control terminal fed back by the drive level detection circuit 4 is still lower than the target threshold of 2V, then it is determined that there is a fault in the drive circuit 2 (e.g., the energy storage capacitor C2 is damaged, the rectifier diode D2 is open, etc.). At this time, the drive level detection circuit 4 outputs a fault alarm signal to the system's control circuit 1, the control circuit 1 stops outputting the pre-charge drive signal, the drive transformer simultaneously stops outputting the pre-charge drive voltage, and locks the signal output of the drive channel to prevent the fault from spreading.

[0074] Specifically, the execution process of this monitoring and protection step is as follows: After the system is powered on and initialized, it first outputs a pre-charge PWM drive (Vg_pre); at the same time, the safety timer starts synchronously and begins to count the duration of the pre-charge drive.

[0075] During the pre-charging phase, the drive level Vg2 at the control terminal of power switch 3 Q2 is continuously monitored, and it is determined whether its reverse bias voltage Vg2_neg reaches the regulated voltage Vz2 of Zener diode Z2 (i.e., the target reverse bias voltage threshold). If Vg2_neg ≥ Vz2, it indicates that the reverse bias voltage has been stably established, and then the system switches to the normal operation drive signal (Vg_nom), and the system enters the normal operation state. If Vg2_neg does not reach the threshold, the pre-charge drive voltage continues to be output, and the safety timer is checked simultaneously to see if it has timed out. If the timer does not time out, the system returns to continuously checking the Vg2 level. If the timer reaches the preset second duration threshold (i.e., timeout), the drive circuit 2 is determined to be faulty, the PWM output is stopped and the fault is reported, and finally the shutdown operation is performed to lock the system.

[0076] Understandably, the addition of fault diagnosis and protection mechanisms prevents traditional hardware circuits from continuing to operate abnormally until they are damaged when the reverse bias voltage fails to establish. When it is detected that the reverse bias voltage cannot reach the target within the maximum allowable time, the drive is stopped in time and the protection is triggered. This not only prevents the power switch transistor 3 from being shot-through due to the lack of reverse bias voltage clamping, but also prompts maintenance through fault alarms, significantly improving system safety and maintainability.

[0077] In one embodiment, the first voltage amplitude ranges from 3V to 6V, and the second voltage amplitude ranges from 10V to 20V; the preset first cycle number threshold is 40 to 60 switching cycles.

[0078] Understandably, the first voltage amplitude of 3V to 6V can be adapted to the turn-on threshold of different models of power switching transistors 3 (usually 2V to 4V), which can not only improve the mis-turn-on during the pre-charge stage, but also drive the reverse bias voltage generation circuit to work stably; the second voltage amplitude of 10V to 20V covers the driving requirements of mainstream power switching transistors 3, and can be adapted to the turn-on drive of different types of devices such as MOSFETs and IGBTs; the threshold of 40 to 60 switching cycles can be compatible with energy storage capacitors of different capacitance values, ensuring that they are fully charged and establish a stable reverse bias voltage, thereby improving the system's adaptability to different device parameters.

[0079] It should be noted that, in one embodiment, the internal software of the control circuit 1 (such as an MCU) may specifically include: an initialization module, a PWM generation module, a state switching logic module, and a fault handling module. After the system is powered on, the initialization module configures the PWM timer parameters (frequency, duty cycle) and GPIO states. Subsequently, the state switching logic module is first placed in a pre-charge state, instructing the PWM generation module to output a drive signal corresponding to the first voltage, and starting an internal timer. The control circuit 1 determines the reverse bias voltage establishment condition through the ADC channel (if there is a drive level detection circuit 4) or solely by relying on the internal timer. Once the condition is met, the state switching logic module switches to the normal operating state, adjusts the PWM drive parameters to output a working drive signal corresponding to the second voltage. If the condition is still not met within the preset timeout threshold, a fault state is entered, the PWM output is turned off, and the fault flag is set.

[0080] Furthermore, this application provides a data foundation for system health management and predictive maintenance. In an embodiment employing voltage feedback, control circuit 1 can record the time required for the reverse bias voltage to build up from zero to the target threshold each time it starts. By analyzing the long-term trend of this voltage build-up time data, the health status of key components (such as energy storage capacitors C1 / C2) in the reverse bias voltage generation circuit can be effectively assessed. If the voltage build-up time is significantly prolonged, it can provide an early warning of potential component aging or failure, guiding preventative maintenance and thus upgrading traditional post-fault repair to pre-fault warning, enhancing the reliability and availability of the power electronic system throughout its entire lifecycle.

[0081] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A method of driving a power switching transistor, characterized by, The method is applied to a drive circuit (2) comprising a drive transformer for driving a power switch tube (3) and a reverse bias voltage generation circuit connected between a secondary side of the drive transformer and the power switch tube (3), and comprises the steps of: S1, controlling the drive transformer to output a pre-charge drive voltage, the amplitude of the pre-charge drive voltage being configured to be able to drive the reverse bias voltage generation circuit to establish a reverse bias voltage, and to keep the effective drive voltage applied to the control end of the power switch tube (3) below the turn-on threshold voltage of the power switch tube (3); S2, maintaining the output of the pre-charge drive voltage until a preset reverse bias voltage establishment condition is met; S3, controlling the drive transformer to switch to output a working drive voltage, the working drive voltage being configured to be higher than the sum of the turn-on threshold voltage of the power switch tube (3) and the reverse bias voltage, to drive the power switch tube (3) to turn on.

2. The driving method according to claim 1, wherein The determination step until the preset reverse bias voltage establishment condition is met comprises: starting a timer or a counter to count the duration or the number of switching cycles of the output of the pre-charge drive voltage; if the duration reaches a preset first time threshold or the number of cycles reaches a preset first cycle threshold, it is determined that the reverse bias voltage establishment condition is met.

3. The driving method according to claim 1, wherein The determination step until the preset reverse bias voltage establishment condition is met comprises: S21, acquiring the amplitude of the reverse bias voltage at the control end of the power switch tube (3); S22, comparing the amplitude of the reverse bias voltage with a preset target reverse bias voltage threshold, and if the amplitude of the reverse bias voltage is greater than or equal to the target reverse bias voltage threshold, it is determined that the reverse bias voltage establishment condition is met.

4. The driving method according to claim 1, wherein The drive circuit (2) further comprises a drive level switching circuit connected to the primary side of the drive transformer, and a control circuit (1) connected to the controlled end of the drive level switching circuit; In step S1, the control of the drive transformer to output the pre-charge drive voltage specifically comprises: the control circuit (1) sends a pre-charge control instruction to the drive level switching circuit, controls the drive level switching circuit to input a first voltage to the drive transformer, and makes the drive transformer output the pre-charge drive voltage; In step S3, the control of the drive transformer to switch to output the working drive voltage specifically comprises: after the preset reverse bias voltage establishment condition is met, the control circuit (1) sends a working control instruction to the drive level switching circuit, controls the drive level switching circuit to input a second voltage to the drive transformer, and makes the drive transformer switch to output the working drive voltage.

5. The driving method according to claim 1, wherein The reverse bias voltage generation circuit comprises an auxiliary switch tube, a rectifier diode, an energy storage capacitor and a voltage stabilizing diode. The rectifier diode is arranged between the control end and the output end of the auxiliary switch tube, and constitutes a switching charging circuit. An input end of the switching charging circuit is connected with a secondary side of the drive transformer, and an output end of the switching charging circuit is connected with a first end of the energy storage capacitor. A second end of the energy storage capacitor is connected with a gate of the power switch tube (3). The voltage stabilizing diode is connected in parallel with the energy storage capacitor, and is used for clamping the voltage across the energy storage capacitor, so as to form a reverse bias voltage. In step S1, the pre-charge driving voltage charges the energy storage capacitor through the switching charging circuit, so that a potential difference is established across the energy storage capacitor, and a reverse bias voltage acting on the gate of the power switch tube (3) is formed. The amplitude of the reverse bias voltage is configured to be lower than the turn-on threshold voltage of the power switch tube (3).

6. The driving method according to claim 2, wherein The preset first time length threshold value is 0.3 ms to 0.5 ms, and the preset first cycle number threshold value is 40 to 60 switching cycles.

7. The driving method according to claim 2, wherein The method further comprises a monitoring protection step: While outputting the pre-charge driving voltage, a timer or a counter is started to count the duration of the pre-charge driving voltage or the number of switching cycles. If the duration reaches a preset second time length threshold value, or the number of cycles reaches a preset second cycle number threshold value, and the amplitude of the reverse bias voltage at the control end of the power switch tube (3) is still less than the target reverse bias voltage threshold value, it is determined that the drive circuit (2) has a fault. The second time length threshold value is greater than the first time length threshold value, and the second cycle number threshold value is greater than the first cycle number threshold value. The output of the pre-charge driving voltage is stopped, and the system is locked or an output fault alarm signal is output.

8. A driving system for a power switching transistor, characterized in that, Comprise: a control circuit (1) configured to generate a control instruction; a drive circuit (2) having an input end connected with the control circuit (1) and an output end connected with the power switch tube (3); The drive circuit (2) comprises: a drive level switching circuit having an input end connected with the control circuit (1) and configured to adjust the amplitude of the output voltage according to the control instruction; a drive transformer having a primary side connected with the output end of the drive level switching circuit and a secondary side for transmitting the voltage signal output by the drive level switching circuit; a reverse bias voltage generation circuit connected between the secondary side of the drive transformer and the control end of the power switch tube (3). The control circuit (1) is configured to control the drive level switching circuit to output voltages with different amplitudes, which are transmitted by the drive transformer to establish a reverse bias voltage or a drive turn-on voltage at the control end of the power switch tube (3) in cooperation with the reverse bias voltage generation circuit.

9. The drive system of claim 8, wherein, The drive level switching circuit comprises at least one of a digital potentiometer, a programmable power supply or a multi-path power supply switching switch, and is used for switching between a first voltage and a second voltage after receiving the control instruction of the control circuit (1).

10. The drive system of claim 8, wherein, Further comprising a drive level detection circuit (4) connected between the gate of the power switch tube (3) and the control circuit (1), and used for collecting the gate drive voltage and feeding back to the control circuit (1).

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