Static random access memory and manufacturing method thereof
By fabricating stepped contact plugs on the gate structure of SRAM devices, the problems of reduced linewidth and poor connection of contact plugs are solved, thereby improving the fabrication yield of SRAM devices.
Patent Information
- Application Number
- CN202411151607.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-07
- Filing Date
- 2024-08-21
- Publication Date
- 2026-02-13
AI Technical Summary
In the manufacturing process of existing SRAM components, there are problems such as reduced linewidth or poor connection of the contact plugs, which affects the quality and yield of the products.
After forming a metal gate on the gate structure, a mask layer is prepared and an opening is defined on it. Contact holes are formed by etching, an intermetallic dielectric layer is filled, and precise photolithography and etching are performed to form a contact plug with a stepped portion, thereby improving the connection quality of the contact plug.
It effectively improved the connection quality of the contact plugs, increased the manufacturing yield of SRAM components, and solved the problems of reduced line width and poor connection.
Smart Images
Figure CN121531704A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a method for fabricating a static random access memory (SRAM), and more particularly to a method for forming a contact plug in a SRAM edge cell region. BACKGROUND
[0002] In an embedded static random access memory (embedded SRAM), there is a logic circuit and a static random access memory connected to the logic circuit. The static random access memory itself is a volatile memory cell, that is, when the power supplied to the static random access memory disappears, the stored data will be erased at the same time. The static random access memory stores data by using the conduction state of the transistor in the memory cell. The design of the static random access memory is based on the intercoupling transistor, and there is no problem of capacitor discharge. It does not need to be charged constantly to keep the data from being lost, that is, it does not need to perform memory update action. This is different from the dynamic random access memory (DRAM) which stores data by using the charged state of the capacitor. The access speed of the static random access memory is quite fast, so it is used as cache memory and the like in computer systems.
[0003] However, with the reduction of the process line width and the exposure pitch, the contact plug prepared in the fabrication of the current SRAM element usually has problems such as shrinkage or poor connection. Therefore, how to improve the fabrication process of the existing SRAM element to improve the above quality is an important issue at present. SUMMARY
[0004] One embodiment of the present application discloses a method for fabricating a semiconductor element, which mainly forms a gate structure on a substrate and an interlayer dielectric layer around the gate structure, then converts the gate structure into a metal gate, forms a hard mask on the metal gate, forms a mask layer on the hard mask, wherein the mask layer includes a first opening arranged directly above the metal gate, forms an intermetal dielectric layer on the mask layer, removes the intermetal dielectric layer and the mask layer to form a second opening, and then forms a metal layer in the second opening to form a contact plug, wherein the contact plug includes a stepped portion.
[0005] Another embodiment of the present application discloses a semiconductor device, which mainly comprises a gate structure disposed on a substrate, an interlayer dielectric layer surrounding the gate structure, and a contact plug contacting above the gate structure, wherein the contact plug comprises a step portion. BRIEF DESCRIPTION OF DRAWINGS
[0006] Figure 1 A circuit diagram of a group of six-transistor static random access memory (6T-SRAM) memory cells in a static random access memory according to the present application;
[0007] Figure 2 A partial layout diagram of a 6T-SRAM according to an embodiment of the present application;
[0008] Figures 3 to 9 A method for manufacturing some transistors in a 6T-SRAM device according to an embodiment of the present application along a tangential AA' direction; Figure 2
[0009] Figure 10 A structure diagram of a semiconductor device according to an embodiment of the present application;
[0010] Figure 11 A structure diagram of a semiconductor device according to an embodiment of the present application.
[0011] LIST OF SYMBOLS
[0012] 10: six-transistor static random access memory
[0013] 12: substrate
[0014] 14: fin structure
[0015] 16: shallow trench isolation
[0016] 18: gate structure
[0017] 20: gate structure
[0018] 22: gate dielectric layer
[0019] 24: gate material layer
[0020] 26: spacer
[0021] 28: source / drain region
[0022] 30: epitaxial layer
[0023] 32: contact hole etch stop layer
[0024] 34: interlayer dielectric layer
[0025] 42: high dielectric constant dielectric layer
[0026] 44: work function metal layer
[0027] 46: low impedance metal layer
[0028] 48: hard mask
[0029] 50: mask layer
[0030] 52: opening
[0031] 54: contact hole
[0032] 56: intermetal dielectric layer
[0033] 58: patterned mask
[0034] 60: opening
[0035] 62: opening
[0036] 64: opening
[0037] 66: opening
[0038] 68: contact hole
[0039] 70: metal layer
[0040] 72: contact plug
[0041] 74: contact plug
[0042] 124: storage node
[0043] 126: storage node
[0044] 128: series circuit
[0045] 130: series circuit DETAILED DESCRIPTION
[0046] While specific configurations and arrangements are discussed herein, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the relevant art that the present disclosure can also be employed in a variety of other applications.
[0047] It is to be noted that the recitations in the specification of "one embodiment," "an embodiment,” “exemplary embodiment,” “some embodiments,” and the like mean that a described embodiment can include, but does not necessarily include, a specific feature, structure, or characteristic. Moreover, such terminology is not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that
[0048] In general, terminology can be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in the singular or can be used to describe combinations of features, structures or characteristics. Similarly, terms such as “a,” “an,” or “the” again, can be understood to express a singular usage or to convey a
[0049] It should be readily understood that the terms “on,” “over,” and “above,” in the present disclosure, should be interpreted in the broadest relative terms consistent with the context of their use such that “on” means not only directly on something but also includes the meaning of being on something with intervening features or layers therebetween, and “over” or “above” means not only above or over something but also can include the meaning of being directly on something.
[0050] In addition, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element’s or feature’s relationship to another element(s) or feature(s) as drawn in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0051] As used herein, the term "substrate" refers to a material upon which layers of material are subsequently added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can comprise a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.
[0052] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entire underlying or overlying structure, or can have an area less than the area of the underlying or overlying structure. In addition, a layer can be a region of uniform or non-uniform thickness that is less than the thickness of a continuous structure. For example, a layer can be between the top surface and the bottom surface of a continuous structure or between any pair of horizontal planes between the top surface and the bottom surface. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon and / or thereunder. A layer can contain multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.
[0053] Please refer to Figure 1 with Figure 2 , Figure 1 is a circuit diagram of a set of six-transistor static random access memory (6T-SRAM) memory cells in the static random access memory of the present application, and Figure 2 is a partial layout diagram of a 6T-SRAM in one embodiment of the present application. As shown in Figure 1 with Figure 2 The static random access memory of the present application preferably comprises at least one set of static random access memory cells, wherein each static random access memory cell comprises a six-transistor static random access memory (6T-SRAM) 10.
[0054] In the present embodiment, each 6T-SRAM memory cell 10 preferably comprises a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first pass gate transistor PG1, and a second pass gate transistor PG2, which together form a flip-flop, wherein the first pull-up transistor PU1 and the second pull-up transistor PU2, the first pull-down transistor PD1 and the second pull-down transistor PD2 form a latch, such that data can be latched at either storage node 24 or 26. In addition, the first pull-up transistor PU1 and the second pull-up transistor PU2 are active loads, which can also be replaced by a general resistor as pull-up element, in which case it is a four-transistor SRAM (4T-SRAM). In the present embodiment, the source region of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 is electrically connected to a voltage source Vcc, and the source region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss.
[0055] Generally, the first pull-up transistor PU1 and the second pull-up transistor PU2 of the 6T-SRAM memory cell 10 are composed of P-type metal oxide semiconductor (PMOS) transistors, and the first pull-down transistor PD1, the second pull-down transistor PD2, the first pass gate transistor PG1, and the second pass gate transistor PG2 are composed of N-type metal oxide semiconductor (NMOS) transistors. The first pull-up transistor PU1 and the first pull-down transistor PD1 together form an inverter, and the series circuit 128 formed by the first pull-up transistor PU1 and the first pull-down transistor PD1 has two ends coupled to a voltage source Vcc and a voltage source Vss, respectively. Similarly, the second pull-up transistor PU2 and the second pull-down transistor PD2 form another inverter, and the series circuit 130 formed by the second pull-up transistor PU2 and the second pull-down transistor PD2 also has two ends coupled to the voltage source Vcc and the voltage source Vss, respectively.
[0056] In addition, at the storage node 124, the gate (G) of the second pull-down transistor PD2 and the second pull-up transistor PU2, and the drain (D) of the first pull-down transistor PD1, the first pull-up transistor PU1 and the first pass-gate transistor PG1 are electrically connected, respectively. Similarly, at the storage node 126, the gate (G) of the first pull-down transistor PD1 and the first pull-up transistor PU1, and the drain (D) of the second pull-down transistor PD2, the second pull-up transistor PU2 and the second pass-gate transistor PG2 are electrically connected, respectively. The gates (G) of the first pass-gate transistor PG1 and the second pass-gate transistor PG2 are coupled to a word line (WL), respectively, and the sources (S) of the first pass-gate transistor PG1 and the second pass-gate transistor PG2 are coupled to a bit line (BL), respectively.
[0057] Please refer to Figure 2 , Figures 2 to 9 Figure 1 is a partial layout diagram of a 6T-SRAM device according to an embodiment of the present application. Figure 2 Figure 2 is a schematic diagram of a method for fabricating some transistors in a 6T-SRAM device according to an embodiment of the present application along a direction of a tangent AA'. Figures 3 to 9 Figure 2 is a schematic diagram of a method for fabricating some transistors in a 6T-SRAM device according to an embodiment of the present application along a direction of a tangent AA'. Figure 2 Figure 2 is a schematic diagram of a method for fabricating some transistors in a 6T-SRAM device according to an embodiment of the present application along a direction of a tangent AA'. Figure 2 Figure 1 is a partial layout diagram of a 6T-SRAM device according to an embodiment of the present application.
[0058] According to an embodiment of the present application, the fin structure 14 can be fabricated by a sidewall image transfer (SIT) technique. The procedure thereof generally includes: providing a layout pattern to a computer system, and defining corresponding patterns in a photomask through appropriate calculation. Subsequently, photolithography and etching fabrication processes can be performed to form a plurality of equidistant and equal-width patterned sacrificial layers on the substrate, so that the individual appearances thereof present a strip shape. Then, deposition and etching fabrication processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. After that, the patterned sacrificial layers are removed, and etching fabrication processes are performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred into the substrate. Finally, a fin cut fabrication process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.
[0059] In addition, the fin structure 14 can be formed by first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the fin structure 14. Alternatively, the fin structure 14 can be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then performing an epitaxial growth process to grow a semiconductor layer, such as a silicon germanium layer, on the substrate 12 exposed by the patterned hard mask layer, which can serve as the corresponding fin structure 14. These embodiments of forming the fin structure 14 are all within the scope of the present application.
[0060] Next, a plurality of gate structures or dummy gates, such as the gate structures 18 and 20, are formed on the substrate 12. The transistors formed subsequently with the gate structures 18 and 20 as the main axis can be any one of the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, the second pull-down transistor PD2, the first transfer gate transistor PG1, and the second transfer gate transistor PG2. Figure 3
[0061] In the present embodiment, the gate structures 18 and 20 can be formed by a gate-first process, a gate-last process, a high-k first process, or a high-k last process, depending on the process requirements. In the present embodiment, the gate structures 18 and 20 are formed by a high-k last process. First, a gate dielectric layer 22 or a dielectric layer composed of silicon oxide, a gate material layer 24 composed of polysilicon, and a selective hard mask (not shown) are sequentially formed on the substrate 12. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer process, in which a portion of the gate material layer 24 and a portion of the gate dielectric layer 22 are removed by a single etching or a step-by-step etching process. Then, the patterned photoresist is removed to form the gate structures 18 and 20 composed of the patterned gate dielectric layer 22 and the patterned gate material layer 24 on the substrate 12.
[0062] Then, at least one spacer 26 is formed on the sidewalls of each gate structure 18, 20, and a source / drain region 28 and an epitaxial layer 30 are formed in the fin structure 14 and / or the substrate 12 on both sides of the spacer 26. In this embodiment, the spacer 26 can be a single spacer or a composite spacer, for example, it can include a bias spacer (not shown) and a main spacer (not shown), and the spacer 26 can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, but is not limited thereto. The source / drain region 28 and the epitaxial layer 30 can contain different dopants or different materials depending on the conductivity type of the transistor being disposed. For example, the source / drain region 28 can contain P-type dopants or N-type dopants, while the epitaxial layer 30 can contain silicon germanide, silicon carbide, or silicon phosphide.
[0063] Then, a contact etch stop layer (CESL) 32 made of silicon nitride can be selectively formed on the substrate 12 and cover the gate structures 18 and 20. Next, an interlayer dielectric layer 34 is formed on the contact etch stop layer 32. Following this, a planarization process is performed, for example, by chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 34 and part of the contact etch stop layer 32, exposing the gate material layer 24, so that the upper surface of the gate material layer 24 is flush with the upper surface of the interlayer dielectric layer 34.
[0064] Subsequently, as Figure 1 As shown, a metal gate replacement (RMG) fabrication process is performed to convert the gate structures 18 and 20 into metal gates. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonia hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 24 and even the gate dielectric layer 22 in the gate structures 18 and 20 to form a groove (not shown) in the interlayer dielectric layer 34. Then, a high dielectric constant dielectric layer 42 and a conductive layer including at least a work function metal layer 44 and a low impedance metal layer 46 are sequentially formed in the groove. A planarization process is then performed to make the surfaces of the U-shaped high dielectric constant dielectric layer 42, the U-shaped work function metal layer 44 and the low impedance metal layer 46 flush with the surface of the interlayer dielectric layer 34. Preferably, the high dielectric constant dielectric layer 42, the work function metal layer 44 and the low impedance metal layer 46 are the gate electrodes of each transistor or each device.
[0065] In this embodiment, the high-k dielectric layer 42 comprises a dielectric material having a dielectric constant greater than 4, for example selected from the group consisting of hafnium oxide (Hf02), hafnium silicon oxide (HfSi04), hafnium silicon oxynitride (HfSiON), aluminum oxide (AI2O3), lanthanum oxide (La203), tantalum oxide (Ta205), yttrium oxide (Y203), zirconium oxide (Zr02), strontium titanate oxide (SrTi03), zirconium silicon oxide (ZrSi04), hafnium zirconium oxide (HfZr04), strontium bismuth tantalate (SrBi2Ta20g, SBT), lead zirconate titanate (PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x Ti03, BST), or combinations thereof.
[0066] The work function metal layer 44 is preferably used to adjust the work function of the metal gate to be suitable for either an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 44 can be selected from a metal material having a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminum (TiAl), zirconium aluminum (ZrAl), tungsten aluminum (WAl), tantalum aluminum (TaAl), hafnium aluminum (HfAl), or TiAlC (titanium aluminum carbide), but not limited thereto. If the transistor is a P-type transistor, the work function metal layer 44 can be selected from a metal material having a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but not limited thereto. Another barrier layer (not shown) can be included between the work function metal layer 44 and the low impedance metal layer 46, wherein the barrier layer can be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or the like. The low impedance metal layer 46 can be selected from a low resistance material such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof. Since the conversion of the dummy gate to the metal gate according to the metal gate replacement process is well known in the art, further description is not provided herein. Then, a portion of the high dielectric constant dielectric layer 42, a portion of the work function metal layer 44, and a portion of the low impedance metal layer 46 are removed to form a recess (not shown), and then a hard mask 48 is filled in the recess and is planarized with the surface of the interlayer dielectric layer 34, wherein the hard mask 48 can be selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride.
[0067] A mask layer 50 is then formed on the gate structures 18, 20, wherein the mask layer 50 includes an opening 52 exposing the hard mask 48 directly above the gate structure 18 of the middle edge transistor, but preferably not exposing the hard mask 48 directly above the gate structure 20 of the middle transistor. Figure 4 More specifically, at this stage, a mask layer 50 can be first formed to cover the gate structures 18, 20, and then a first photolithography and etching process is performed to remove a portion of the mask layer 50 directly above the edge region, such as the gate structure 18, to form the opening 52 exposing the hard mask 48 directly above the gate structure 18, but preferably not removing the mask layer directly above the adjacent gate structure 20. Then, a second photolithography and etching process is performed to remove a portion of the mask layer 50, a portion of the interlayer dielectric layer 34, and a portion of the contact hole etch stop layer 32 on both sides of the gate structures 18, 20 to form a contact hole 54 exposing the source / drain region 28.
[0068] In this embodiment, the width of the opening 52 is preferably smaller than the cross-sectional width of the low-impedance metal layer 46 in the gate structure 18, but it is not limited thereto. According to other embodiments of the present invention, the width of the opening 52 can be adjusted to be larger than the width of the low-impedance metal layer 46, such as the left and right sidewalls of the cleaved work function metal layer 44 or the left and right sidewalls of the gate structure 18, such as the left and right sidewalls of the high dielectric constant dielectric layer 42. These are all within the scope of the present invention. In addition, the mask layer 50 preferably contains tetraethoxysilane (TEOS) and the thickness of the mask layer 50 is preferably between 600 and 800 angstroms or preferably about 700 angstroms.
[0069] Then as Figure 2 As shown, an intermetallic dielectric layer 56 is formed on the mask layer 50, filling the opening 52 and contact hole 54. Then, a patterned mask 58, such as a patterned photoresist, is formed on the intermetallic dielectric layer 56. Preferably, the patterned mask 58 includes an opening 60 exposing the surface of the intermetallic dielectric layer 56, and the width of the opening 60 is preferably greater than [missing information]. Figure 5 The width of the opening 52 formed in the mask layer 50 directly above the gate structure 18. In this embodiment, the intermetallic dielectric layer 56 preferably contains an oxide such as silicon oxide, but may also contain an ultra-low dielectric constant dielectric layer depending on the fabrication process requirements, for example, it may contain a porous dielectric material such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).
[0070] Then as Figure 4 As shown, an etching process is first performed using a patterned mask 58 as a mask to remove part of the intermetallic dielectric layer 56, part of the mask layer 50, and part of the hard mask 48 to form an opening 62. Then, the patterned mask 58 is selectively removed. It should be noted that since the mask layer 50 directly above the gate structure 18 has already been... Figure 6 When a smaller opening 52 is formed, it is preferable to remove more of the mask layer 50 and less of the hard mask 48 during this stage of etching to remove part of the intermetallic dielectric layer 56, part of the mask layer 50, and part of the hard mask 48, so that the opening 62 between the mask layer 50 and the hard mask 48 has a width difference. In other words, the opening 62 formed directly above the gate structure 18 in this stage preferably includes at least two parts, such as the opening 64 located in the hard mask 48 and the opening 66 located in the mask layer 50 or the intermetallic dielectric layer 56. The width of the opening 64 in the hard mask 48 is preferably smaller than the width of the opening 66 in the mask layer 50 and the intermetallic dielectric layer 56, and the contours of the opening 64 and the opening 66 are preferably stepped due to the width difference. Since no mask layer 50 with an opening 52 is formed directly above the gate structure 20, the opening 62 formed by etching away part of the intermetallic dielectric layer 56, part of the mask layer 50, and part of the hard mask 48 in this stage has no steps and only a single width.
[0071] likeFigure 3 As shown, the previously formed openings 62 can then be further expanded by etching away portions of the intermetal dielectric layer 56, portions of the mask layer 50 and portions of the hard mask 48 with or without a patterned mask. Since the openings 62 above the gate structures 18 already contain the smaller width openings 64 and the larger width openings 66, it is preferred that the etching process to expand the openings 62 at this stage expands the width of the openings 64 and the openings 66 at a substantially equal ratio.
[0072] Then as shown in Figure 7 , a photolithography and etching fabrication process is performed to remove portions of the intermetal dielectric layer 56 on both sides of the gate structures 18, 20 to form contact holes 68 to expose the source / drain regions 28 again with a patterned mask (not shown).
[0073] After that as shown in Figure 8 , at least one metal layer 70 is formed within the openings 62 and the contact holes 68 to form contact plugs 72, 74. In this embodiment, the desired conductive or metallic material, such as a barrier layer (not shown) containing titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and the like and a low resistance metal layer 70 selected from tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP) and the like or a combination thereof, can be filled within each of the openings 62 and the contact holes 68. A planarization fabrication process, such as chemical mechanical polishing, is then performed to remove portions of the metal layer 70 and the barrier layer to form the contact plugs 72, 74 within each of the openings 62 and the contact holes 68 to electrically connect the source / drain regions 28 and the gate structures 18, 20, respectively. Thus, the fabrication of the semiconductor device of this embodiment is completed.
[0074] Please refer to Figure 9 again, Figure 9 A structure schematic view of a semiconductor device of this embodiment is also disclosed. As shown in Figure 9 , the semiconductor device mainly comprises at least one gate structure 18 disposed on a substrate 12, an interlayer dielectric layer 56 surrounding the gate structure 18, a hard mask 48 disposed on the gate structure 18, a mask layer 50 disposed on the hard mask 48, an intermetal dielectric layer 56 disposed on the mask layer 50, a contact plug 74 disposed directly above the gate structure 18 and another contact plug 72 disposed on both sides of the gate structure 18 to connect the source / drain regions 28.
[0075] In this embodiment, the contact plug 74 located directly above the gate structure 18 includes a stepped portion, while the contact plugs 72 connecting the source / drain regions 28 on both sides of the gate structure 18 and the contact plugs 74 connecting the gate structure 20 have no stepped portions or only have flat vertical or inclined sidewalls. More specifically, the contact plug 74 located directly above the gate structure 18 includes at least two different widths, wherein the width of the contact plug 74 within the hard mask 48 is preferably smaller than the width of the contact plug 74 within the mask layer 50, and the bottom surface of the contact plug 74 is preferably flush with the top surface of the gate structure 18 or, more specifically, the top surfaces of the high dielectric constant dielectric layer 42, the work function metal layer 44, and the low impedance metal layer 46 in the gate structure 18.
[0076] Please continue to refer to Figure 9 , Figure 10 A schematic diagram of the structure of a semiconductor device according to the present invention is also disclosed. For example... Figure 10 As shown, compared to Figure 10 In this embodiment, the bottom surface of the contact plug 74 is flush with the top surface of the gate structure 18, and preferably the bottom surface of the contact plug 74 is slightly lower than the top surface of the gate structure 18. More specifically, this embodiment can be... Figure 9 When etching to widen the mask layer 50 and hard mask 48, a portion of the low-resistivity metal layer 46 and even a portion of the work function metal layer 44 in the gate structures 18 and 20 are simultaneously removed. Thus, after filling with conductive material to form the contact plug 74, the bottom of the contact plug 74 preferably extends into a portion of the low-resistivity metal layer 46 and / or work function metal layer 44 of the gate structure 18. In other words, the contact plug 74 above the gate structure 18 in this embodiment has two widths, wherein the width of the contact plug 74 disposed in the hard mask 48 and the low-resistivity metal layer 46 is preferably smaller than the width of the contact plug 74 disposed in the mask layer 50. This variation is also within the scope of this invention.
[0077] Please continue to refer to Figures 6 to 7 , Figure 11 A schematic diagram of the structure of a semiconductor device according to the present invention is also disclosed. For example... Figure 11 As shown, this embodiment can be used in the same way. Figure 11 When etching to widen the mask layer 50 and hard mask 48, a portion of the low-resistivity metal layer 46 and even a portion of the work function metal layer 44 in the gate structures 18 and 20 are simultaneously removed. This allows the bottom of the contact plug 74 to better penetrate into a portion of the low-resistivity metal layer 46 and / or work function metal layer 44 of the gate structure 18 after subsequent filling with conductive material to form the contact plug 74. Compared to... Figures 6 to 7The contact plugs 74 extending into the hard mask 48 and the low-resistivity metal layer 46 have the same width. In this embodiment, the contact plugs 74 extending into the hard mask 48 and the low-resistivity metal layer 46 preferably have different widths. In other words, the contact plugs 74 above the gate structure 18 in this embodiment include three widths. The width of the contact plugs 74 disposed in the low-resistivity metal layer 46 is preferably smaller than the width of the contact plugs 74 in the hard mask 48, and the width of the contact plugs 74 in the hard mask 48 is preferably smaller than the width of the contact plugs 74 in the mask layer 50. This variation is also within the scope of this invention.
[0078] In summary, this invention discloses a method for fabricating contact plugs for connecting transistors in the edge cell region of SRAM elements, which mainly relies on... Figure 10 At least one gate structure 18 is formed on the substrate, and an interlayer dielectric layer surrounds the gate structure, converting the gate structure into a metal gate. A mask layer 50 is formed, including an opening 52 located directly above the metal gate. Contact holes are formed between the mask layer and the interlayer dielectric layer on both sides of the metal gate. Figures 3 to 4 A dielectric layer is formed between the metals to fill the openings and contact holes, and then based on... Figure 5 At least one photolithography and etching process is performed to remove the intermetallic dielectric layer and mask layer directly above the metal gate, forming an opening 62, and the intermetallic dielectric layers on both sides of the metal gate are used to re-form contact holes 68. Figures 6 to 7 Figure 4 Before defining the pattern of subsequent contact plugs directly above the metal gate, an opening or groove is formed in the mask layer. This invention allows for the formation of contact plugs 74 with stepped portions to connect to the metal gate in subsequent fabrication processes. Given that contact plugs connecting edge cell transistors in current SRAM devices typically suffer from problems such as linewidth shrinkage or poor connection, the contact plugs 74 fabricated using the above-described process can effectively improve these issues and thus increase fabrication yield.
[0079] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, Include: A gate structure is formed on the substrate and an interlayer dielectric layer surrounds the gate structure; and A contact plug is formed above the gate structure, wherein the contact plug includes a stepped portion.
2. The method of claim 1, comprising: Convert the gate structure to a metal gate; A hard mask is formed on the metal gate; A mask layer is formed on the hard mask, wherein the mask layer includes a first opening located directly above the metal gate; An intermetallic dielectric layer is formed on the mask layer; Remove the intermetallic dielectric layer and the mask layer to form a second opening; as well as A metal layer is formed within the second opening to form the contact plug.
3. The method of claim 2, wherein the first opening is smaller than the second opening.
4. The method of claim 2, further comprising removing the intermetallic dielectric layer, the mask layer, and the hard mask to form a third opening in the hard mask and the second opening in the mask layer and the intermetallic dielectric layer.
5. The method of claim 4, wherein the width of the third opening is smaller than the width of the second opening.
6. The method of claim 2, wherein the contact plug includes a first width within the hard mask and a second width within the mask layer.
7. The method of claim 6, wherein the first width is smaller than the second width.
8. A semiconductor element, characterized in that, Include: A gate structure is disposed on a substrate, and an interlayer dielectric layer surrounds the gate structure; and A contact plug is placed above the gate structure, wherein the contact plug includes a stepped portion.
9. The semiconductor element of claim 8, further comprising: A hard mask is disposed on the gate structure; A mask layer is disposed on the hard mask; and An intermetallic dielectric layer is disposed on the mask layer.
10. The semiconductor device of claim 9, wherein the contact plug has a first width within the hard mask and a second width within the mask layer.
11. The semiconductor element of claim 10, wherein the first width is smaller than the second width.
12. The semiconductor device of claim 8, wherein the bottom surface of the contact plug is flush with the top surface of the gate structure.
13. The semiconductor device of claim 8, wherein the bottom surface of the contact plug is lower than the top surface of the gate structure.
14. The semiconductor device of claim 8, wherein the gate structure comprises a metal gate.