Low-voltage low-clamping low-leakage transient suppression diode and preparation method thereof

Abstract

The invention discloses a low-voltage low-clamping low-leakage transient suppression diode and a preparation method thereof. Relates to the technical field of diodes. Comprising the following steps: step 1, selecting a P-type silicon substrate; step 2, initial oxidation; growing a layer of oxidation film on the surface of the wafer through a thermal oxidation method in a dry oxygen atmosphere; step 3, protecting the front area with a photoresist, and defining a photoresist pattern of the front area through exposure and development; removing the oxide film in the front exposed region by using a BOE corrosive liquid to expose the front N + isolation region to be diffused; step 4, taking POCl as a phosphorus source, and carrying out pre-deposition treatment in a diffusion furnace; step 5, N + isolation region phosphorus propulsion; step 6, etching a mesa structure; the performance attenuation rate is less than 10% after a high-temperature and high-humidity reliability test, and the protection requirements of low-voltage precision circuits of the Internet of Things, consumer electronics and the like are perfectly met.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of diodes, in particular to a low-voltage low-clamp low-leakage transient suppression diode and a preparation method thereof. BACKGROUND

[0002] A mesa type low-voltage transient voltage suppression diode (mesa type low-voltage TVS diode) is a transient voltage suppression device prepared by using a mesa process and suitable for a low-voltage circuit (usually, a reverse breakdown voltage VB is less than or equal to 20 V), and is mainly used for surge / electrostatic protection of a low-voltage precision circuit and has the characteristics of low-voltage adaptability and a mesa structure.

[0003] In the device preparation process, a mesa-shaped profile (different from the flat junction structure of a planar TVS diode) of a P-N junction is formed through etching, and then a passivation layer (such as a SiO2, SiN x and the like) is formed on the mesa sidewall, so as to eliminate the electric field concentration at the edge of the P-N junction and improve the reverse voltage stability and surge resistance of the device. After preparation, the structure mainly includes an N-type substrate, a P-type diffusion layer, a mesa passivation layer and an ohmic contact electrode (anode / cathode). The low-voltage device usually optimizes the doping concentration and junction depth of the P-N junction to realize a low breakdown voltage (VB is less than or equal to 20 V). For a low-voltage circuit design of 3.3 V, 5 V, 12 V and the like, the breakdown voltage is accurately matched with the working voltage of the low-voltage system, the clamping voltage (VC) is controlled within the voltage threshold of a low-voltage sensitive device (such as an MCU, a sensor and an interface chip), and overvoltage damage is avoided.

[0004] In the prior art, there are mainly two preparation process routes for the mesa type low-voltage transient voltage suppression diode (TVS diode), and both of them are difficult to meet the technical requirements of low clamping voltage and low leakage: The first process low-clamping voltage type: taking a 5V unidirectional 160mil size TVS diode as an example, the clamping voltage can be realized at a relatively low level of 8.3-8.7 V, but the surface leakage of the device is large, and the leakage current can reach 300-500 mu A under a 5V reverse voltage, which easily leads to high static power consumption of the circuit and cannot meet the requirements of low-power application scenarios; The second process high-clamping voltage type: also taking a 5V unidirectional 160mil size TVS diode as an example, the surface leakage is better, and the leakage current is only 100-200 mu A under a 5V reverse voltage, but the clamping voltage is increased to 8.8-9.1 V, which easily exceeds the voltage threshold of a low-voltage sensitive device and is difficult to form effective overvoltage protection for a precision circuit.

[0005] In summary, the two existing process solutions for mezzanine-type low-voltage TVS diodes have the technical defect that "low clamping voltage and low leakage current characteristics cannot be achieved simultaneously," making them unsuitable for low-voltage circuit applications with stringent requirements for power consumption and overvoltage protection accuracy. Summary of the Invention

[0006] To address the above problems, this invention provides a mesa-type low-voltage transient suppression diode and its fabrication method that achieve synergistic improvement in low clamping voltage and low leakage current characteristics.

[0007] The technical solution of this invention is: A method for fabricating a low-voltage, low-clamping, low-leakage transient suppression diode includes the following steps: Step 1: Select a P-type silicon substrate; Step 2, initial oxidation; An oxide film is grown on the wafer surface by thermal oxidation in a dry oxygen atmosphere. Step 3: Protect the front area with photoresist, and define the photoresist pattern of the front area through exposure and development; use BOE etching solution to remove the oxide film in the exposed area of ​​the front, exposing the N to be diffused on the front. + Quarantine area; Step 4: Using POCl3 as the phosphorus source, pre-deposition treatment is carried out in a diffusion furnace; Step 5, N + Phosphorus propulsion in the isolation zone; Step six: etching the mesa structure; The initial mesa with a depth of 80-90um and a width of 230-320um is etched out by dry etching process. Then, wet shaping is performed by mixed etching solution to etch the sidewalls of the mesa into arc-shaped grooves. Step 7: Deposition of SIPOS passivation layer; A crescent-shaped semi-insulating polycrystalline silicon layer was deposited in the arc-shaped trench on the sidewall of the device using a low-pressure chemical vapor deposition process with SiH4 and N2 as reaction sources. Step 8: Deposit a glass passivation film inside the arc-shaped trench; Step nine: Place the wafer in a glass melting furnace for the first glass melting process; Step 10: Second glass melting treatment to optimize leakage current; Step 11: Secondary photolithography, defining the electrode window; Step 12: Electrode metallization.

[0008] Specifically, in step four, the furnace temperature is controlled at 850℃, and N2 is introduced as the carrier gas at a flow rate of 500 sccm; O2 is used as the oxidizing gas, and the pre-deposition time is 40-50 minutes. + The phosphorus doping concentration on the surface of the isolation region is 0.55~0.85Ω / m.

[0009] Specifically, in step nine, the glass melting furnace is heated at a rate of 5°C / min, reaching 830~900°C and then held for 30~40 minutes. Subsequently, it is cooled to room temperature at a rate of 3°C / min, allowing the glass powder to completely melt and form Si-O chemical bonds with the silicon substrate, thus forming a dense, non-porous, continuous glass passivation layer.

[0010] Specifically, the glass layer density after fusion is ≥99.5%, allowing the PN junction to immediately obtain ultimate protection with high withstand voltage, low leakage current, and resistance to moisture, ions, and mechanical damage.

[0011] Specifically, step ten adopts a continuous glass melting method of "constant inlet and constant outlet". The glass melting furnace is divided into three zones: a 600°C preheating zone, an 800°C~950°C high temperature zone, and a 400°C cooling zone. The wafer passes through each zone continuously at a speed of 10 mm / min, with a total processing time of 60~80 min. The gradient temperature treatment eliminates the internal stress generated by the first glass melting, further optimizes the interface bonding state between the glass layer and the SIPOS layer, and reduces its surface leakage current.

[0012] Specifically, step twelve involves using an electron beam evaporation process to perform nickel-gold plating: First, a 50-80 nm thick nickel layer is evaporated as an ohmic contact transition layer; then, a 150-200 nm thick gold layer is evaporated to enhance the electrode's conductivity and corrosion resistance; finally, an alloying treatment is performed at 450 °C for 30 min to form a low contact resistance ≤1×10⁻⁶. -4 Ω·cm 2 Ohmic contact.

[0013] Specifically, in step one, a P-type silicon substrate with a resistivity of 0.002-0.004 Ω·cm is selected.

[0014] A low-voltage, low-clamping, low-leakage transient suppression diode includes an N+ isolation layer and a P-type silicon substrate layer connected vertically. The N+ isolation layer and the P-type silicon substrate layer have arc-shaped trenches extending to the top surface on their sides. The arc-shaped groove is provided with an SIPOS passivation layer and a glass passivation film connected sequentially from the inside out; The SIPOS passivation layer and the glass passivation film are both crescent-shaped.

[0015] This invention, through a synergistic design of "deep junction isolation + optimized mesa + composite passivation", produces a low-voltage TVS diode that, compared to traditional processes, reduces the clamping voltage VC from 8.8~9.1V to 8.3~8.7V when VB=5V, and reduces the 5V reverse leakage current to more than half of the original value. At the same time, the performance degradation rate after high temperature and high humidity reliability testing is less than 10%, perfectly meeting the protection requirements of low-voltage precision circuits in IoT, consumer electronics, and other fields. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the initial oxide layer structure fabricated on a P-type silicon substrate. Figure 2 This is a schematic diagram of the structure after a single application of yellow light and BOE etching; Figure 3 This is a schematic diagram of the diffusion structure in the front N+ region; Figure 4 This is a schematic diagram of the N+ zone propulsion structure on the back. Figure 5 This is a schematic diagram of the structure after secondary yellow light and BOE etching; Figure 6 This is a schematic diagram of the SIPOS structure after passivation; Figure 7 This is a schematic diagram of the structure after glass passivation. Detailed Implementation

[0017] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0018] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0019] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0020] The following is for reference. Figures 1-7 Describe the present invention; A method for fabricating a low-voltage, low-clamping, low-leakage transient suppression diode includes the following steps: Step 1: Select a substrate with a resistivity of 0.002-0.004 Ω·cm and an oxygen content of less than 5 x 10⁻⁶. 16 / cm 3 The thickness of the P-type silicon substrate is selected according to the different wafer sizes; Step 2, initial oxidation; In a dry oxygen atmosphere, a dense oxide film with a thickness of 15,000-30,000 angstroms is grown on the wafer surface via thermal oxidation, forming a uniform silicon dioxide layer. This layer serves as a masking layer for subsequent photolithography, preventing impurity diffusion and protecting the silicon surface from contamination. Figure 1 As shown; Step 3: Protect the front area with photoresist, and define the photoresist pattern of the front area through exposure and development; use BOE etching solution to remove the oxide film in the exposed area of ​​the front, exposing the N to be diffused on the front. + Isolation area; such as Figure 2 As shown; Step 4: Using POCl3 as the phosphorus source, pre-deposition treatment is carried out in a diffusion furnace; Specifically, the furnace temperature is controlled at 850℃, with N2 as the carrier gas (flow rate 500 sccm) and O2 as the oxidizing gas (flow rate 300 sccm). The pre-deposition time is 40-50 minutes. + The phosphorus doping concentration on the surface of the isolation region is 0.55~0.85Ω / m; Step 5, N + Phosphorus propulsion in the isolation zone; Specifically, the wafer is fed into a high-temperature diffusion furnace for phosphorus propagation: the furnace temperature is raised to 1200~1250℃, pure N2 is introduced for protection (flow rate 800 sccm), and the propagation time is 120~150 min. By controlling the temperature and time, the phosphorus junction depth is pushed to 35±5 μm, forming a continuous N2 layer. + isolation layer, such as Figures 3-4 As shown, this effectively separates device units and avoids crosstalk between units.

[0021] Step six: etching the mesa structure; The initial mesa with a depth of 80-90um and a width of 230-320um is etched out by dry etching process. Then, wet shaping is performed by mixed etching solution to etch the sidewalls of the mesa into arc-shaped grooves. Step 7: Deposition of SIPOS passivation layer; Using low-pressure chemical vapor deposition (LPCVD) with SiH4 and N2 as reaction sources, a crescent-shaped semi-insulating polycrystalline silicon layer is deposited in the arc-shaped trench on the sidewall of the device, which has significant advantages in high-pressure, high-temperature and high-humidity environments. SIPOS passivation features a complete semi-insulating polycrystalline silicon layer with high resistivity, which can block the intrusion of water vapor and sodium ions. In high temperature and high humidity environments (85℃ / 85%RH), surface leakage current is reduced by 60%, solving the problem of poor humidity resistance of traditional passivation layers.

[0022] Step 8: Deposit a glass passivation film in the arc-shaped trench using a scraping process; Step nine: Place the wafer in a glass melting furnace for the first glass melting process; The glass melting furnace is heated at a rate of 5℃ / min, reaching 830~900℃ and then held for 30~40min. Subsequently, it is cooled to room temperature at a rate of 3℃ / min, allowing the glass powder to completely melt and form Si-O chemical bonds with the silicon substrate, forming a dense, non-porous, continuous glass passivation layer. After melting, the glass layer has a density of ≥99.5%, allowing the PN junction to immediately obtain ultimate protection with high voltage resistance, low leakage current, and resistance to moisture, ions, and mechanical damage.

[0023] Glass passivation film deposition + one-time glass melting suppresses surface leakage and electric field concentration, making HTRB more directionally biased at high temperatures and able to withstand long-term testing at 175℃.

[0024] Step 10: Second glass melting treatment to optimize leakage current; further reducing surface leakage current to less than half of the original (under 5V reverse voltage), which is 85% lower than the traditional process, meeting the low power consumption requirements; The continuous glass melting method of "constant inlet and constant outlet" is adopted. The glass melting furnace is divided into three zones: preheating zone (600℃), high temperature zone (800℃~950℃), and cooling zone (400℃). The wafer passes through each zone continuously at a speed of 10mm / min. The total processing time is 60~80min. The internal stress generated by the first glass melting is eliminated by gradient temperature treatment, which further optimizes the interface bonding state between the glass layer and the SIPOS layer and reduces its surface leakage current.

[0025] Step 11: Secondary photolithography, defining the electrode window; Spin-coating negative photoresist, followed by pre-baking (100℃), exposure (exposure dose 120mJ / cm²), and development, forms opening windows in the anode and cathode regions. The window size accuracy is controlled within ±0.5μm to ensure precise alignment between the electrode and the active region.

[0026] Step 12, electrode metallization; Electron beam evaporation is used for nickel-gold plating: first, a 50-80 nm thick nickel layer is evaporated as an ohmic contact transition layer; then, a 150-200 nm thick gold layer is evaporated to enhance electrode conductivity and corrosion resistance; finally, an alloying treatment is performed at 450℃ for 30 minutes to form a low contact resistance (≤1×10⁻⁻⁶). 4 Ω·cm 2 Ohmic contact.

[0027] The secondary photolithography and electrode metallization process reduces current conduction losses due to low contact resistance, ensuring rapid discharge of surge current and maintaining a stable clamping voltage of 8.3~8.7V.

[0028] A low-voltage, low-clamping, low-leakage transient suppression diode is fabricated by the fabrication method of the low-voltage, low-clamping, low-leakage transient suppression diode as described in claim 1, characterized in that it includes an N+ isolation layer and a P-type silicon substrate layer connected vertically. The N+ isolation layer and the P-type silicon substrate layer have arc-shaped trenches extending to the top surface on their sides. The arc-shaped groove is provided with an SIPOS passivation layer and a glass passivation film connected sequentially from the inside out; The SIPOS passivation layer and the glass passivation film are both crescent-shaped.

[0029] The two existing process solutions for mezzanine-type low-voltage TVS diodes have the technical defect that "low clamping voltage and low leakage current characteristics cannot be achieved simultaneously", making them unsuitable for low-voltage circuit applications with stringent requirements for power consumption and overvoltage protection accuracy.

[0030] Taking a 5.0A voltage rating and a 160mil size TVS tube as an example: Reverse voltage VB is 6.5-6.95V@10mA, leakage current IR≤500ua@5V, clamping voltage VC<9.2V; Leakage IR Clamping voltage VC Conventional process 1 300-500 ua 8.3-8.7V Conventional process 2 100-200 ua 8.8-9.1V This process 100-200 ua 8.3-8.7V The data on leakage current and clamping voltage above show that this process has both low leakage current and low clamping voltage.

[0031] To address the technical limitation of existing mezzanine-type low-voltage TVS diodes where "low clamping voltage and low leakage current characteristics cannot be simultaneously achieved," multi-dimensional technical breakthroughs have been achieved through synergistic optimization of multiple process steps. Specific technical effects are as follows: 1. Significantly reduces device leakage current, making it suitable for low-power applications: This method involves precisely selecting low-oxygen-content P-type silicon substrates (oxygen content less than 5 × 10¹). 6 / cm³), reducing the impact of substrate defects on leakage current from the source; at the same time, it innovatively adopts a composite passivation process of "SIPOS passivation layer deposition + two glass melting treatments". The first glass melting forms a continuous glass passivation layer with a density of ≥99.5%, which effectively blocks the intrusion of water vapor and sodium ions. The second gradient temperature continuous glass melting further eliminates internal stress and optimizes the interface bonding state. Ultimately, the surface leakage current of the device under 5V reverse voltage is reduced by 85% compared with the traditional process, and reduced to less than half of the lowest value of the existing process. It completely solves the problem of excessive leakage current (300~500μA) in the existing low clamping voltage type process, which leads to high static power consumption of the circuit. It can be perfectly adapted to low-voltage precision circuit scenarios with strict power consumption requirements.

[0032] 2. Precisely control the clamping voltage to improve overvoltage protection accuracy: This method, through precise control of the N⁺ isolation region diffusion process (pre-deposition temperature 850℃, advance temperature 1200~1250℃, and junction depth controlled at 35±5μm), combined with a "dry etching + wet shaping" composite process for the mesa structure (forming arc-shaped trench mesa sidewalls), effectively optimizes the electric field distribution of the PN junction, avoiding the problem of excessively high clamping voltage (8.8~9.1V) in existing high-clamping-voltage processes. The fabricated devices can be precisely matched to the operating voltages of low-voltage circuits such as 3.3V, 5V, and 12V, and their clamping voltage can be stably controlled within the withstand voltage threshold of low-voltage sensitive devices (such as MCUs, sensors, and interface chips). Compared with existing processes, it retains the overvoltage protection adaptability of low-clamping-voltage processes while solving their leakage defects, achieving synergistic optimization of "low clamping + low leakage".

[0033] 3. Optimize device structure stability and improve resistance to harsh environments: On the one hand, the precise secondary photolithography process (window size accuracy ±0.5μm) used to prepare a high-density initial oxide film (15000-30000 angstroms) ensures the precise alignment of the N⁺ isolation region, electrodes, and active region, forming a continuous N⁺ isolation layer. This effectively separates device units, avoids crosstalk between units, and improves the stability of device operation. On the other hand, the composite structure of the SIPOS passivation layer and the high-density glass passivation layer reduces surface leakage current by 60% in high-temperature and high-humidity environments (85℃ / 85%RH), and has excellent HTRB high-temperature reverse bias capability, which can withstand long-term testing at 175℃. This solves the problem of humidity resistance of traditional passivation layers, significantly improves the reliability of devices in harsh environments, and broadens its application range in low-voltage circuits under complex operating conditions.

[0034] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case; other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A method for fabricating a low-voltage, low-clamping, low-leakage transient suppression diode, characterized in that, Includes the following steps: Step 1: Select a P-type silicon substrate; Step 2, initial oxidation; An oxide film is grown on the wafer surface by thermal oxidation in a dry oxygen atmosphere. Step 3: Protect the front area with photoresist, and define the photoresist pattern of the front area through exposure and development. The oxide film on the exposed front area was removed using BOE etching solution, exposing the nitrogen atoms to be diffused on the front. + Quarantine area; Step 4: Using POCl3 as the phosphorus source, pre-deposition treatment is carried out in a diffusion furnace; Step 5, N + Phosphorus propulsion in the isolation zone; Step six: etching the mesa structure; The initial mesa with a depth of 80-90um and a width of 230-320um is etched out by dry etching process. Then, wet shaping is performed by mixed etching solution to etch the sidewalls of the mesa into arc-shaped grooves. Step 7: Deposition of SIPOS passivation layer; A crescent-shaped semi-insulating polycrystalline silicon layer was deposited in the arc-shaped trench on the sidewall of the device using a low-pressure chemical vapor deposition process with SiH4 and N2 as reaction sources. Step 8: Deposit a glass passivation film inside the arc-shaped trench; Step nine: Place the wafer in a glass melting furnace for the first glass melting process; Step 10: Second glass melting treatment to optimize leakage current; Step 11: Secondary photolithography, defining the electrode window; Step 12: Electrode metallization.

2. The method for fabricating a low-voltage, low-clamping, low-leakage transient suppression diode according to claim 1, characterized in that, Step 4: The furnace temperature is controlled at 850℃, and N2 is introduced as the carrier gas at a flow rate of 500 sccm; O2 is used as the oxidizing gas, and the pre-deposition time is 40-50 minutes. + The phosphorus doping concentration on the surface of the isolation region is 0.55~0.85Ω / m.

3. The method for fabricating a low-voltage, low-clamping, low-leakage transient suppression diode according to claim 1, characterized in that, Step 9: The glass melting furnace is heated at a rate of 5℃ / min, and after reaching 830~900℃, it is held for 30~40min. Then, it is cooled to room temperature at a rate of 3℃ / min, so that the glass powder is completely melted and forms Si-O chemical bonds with the silicon substrate, forming a dense, non-porous continuous glass passivation layer.

4. The method for fabricating a low-voltage, low-clamping, low-leakage transient suppression diode according to claim 3, characterized in that, After fusion, the glass layer has a density of ≥99.5%, allowing the PN junction to immediately obtain ultimate protection with high voltage resistance, low leakage current, and resistance to moisture, ions, and mechanical damage.

5. The method for fabricating a low-voltage, low-clamping, low-leakage transient suppression diode according to claim 1, characterized in that, Step 10 employs a continuous glass melting method with "constant inlet and constant outlet". The glass melting furnace is divided into three zones: a 600°C preheating zone, an 800°C~950°C high-temperature zone, and a 400°C cooling zone. The wafer passes through each zone continuously at a speed of 10 mm / min, with a total processing time of 60~80 min. The gradient temperature treatment eliminates the internal stress generated by the first glass melting, further optimizes the interface bonding state between the glass layer and the SIPOS layer, and reduces surface leakage.

6. The method for fabricating a low-voltage, low-clamping, low-leakage transient suppression diode according to claim 1, characterized in that, Step 12 involves nickel-gold plating using an electron beam evaporation process. First, a 50-80 nm thick nickel layer is evaporated as an ohmic contact transition layer; then, a 150-200 nm thick gold layer is evaporated to enhance the electrode's conductivity and corrosion resistance; finally, an alloying treatment is performed at 450 °C for 30 min to form a low contact resistance ≤1×10⁻⁶. -4 Ω·cm 2 Ohmic contact.

7. The method for fabricating a low-voltage, low-clamping, low-leakage transient suppression diode according to claim 1, characterized in that, Step 1: Select a P-type silicon substrate with a resistivity of 0.002-0.004 Ω·cm.

8. A low-voltage, low-clamping, low-leakage transient suppression diode, fabricated by the method described in claim 1, characterized in that, This includes an N+ isolation layer and a P-type silicon substrate layer that are connected vertically; The N+ isolation layer and the P-type silicon substrate layer have arc-shaped trenches extending to the top surface on their sides. The arc-shaped groove is provided with an SIPOS passivation layer and a glass passivation film connected sequentially from the inside out; The SIPOS passivation layer and the glass passivation film are both crescent-shaped.

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