Semiconductor device and manufacturing method thereof
By forming a side trench and filling it with a barrier layer at the edge of the active region of the high-voltage transistor, the bird's beak structure problem caused by lateral oxygen diffusion is solved, improving the reliability and miniaturization capability of the device and improving the uniformity of the gate oxide layer.
Patent Information
- Application Number
- CN202411085985.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-08
- Publication Date
- 2026-02-13
AI Technical Summary
During the manufacturing process of high-voltage transistors, the lateral diffusion of oxygen leads to the formation of a bird's beak structure, which affects the uneven thickness of the gate oxide layer, thereby affecting the reliability and miniaturization of the device.
A side trench is formed at the edge of the active region and filled with a barrier layer to prevent the lateral diffusion of oxygen. The barrier layer is extended at the apex of the active region to ensure uniform growth of the gate oxide layer and avoid the formation of a bird's beak structure.
It improves the reliability and miniaturization capability of the device, enhances the thickness uniformity of the gate oxide layer, avoids the formation of bird beak structures, and improves the performance and yield of the device.
Smart Images
Figure CN121531736A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor device manufacturing, in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND
[0002] With the continuous miniaturization of semiconductor components and the requirements of specific application scenarios, the current product design often needs to manufacture high-voltage transistors, which are transistors capable of bearing higher voltage while ensuring that the gate is not broken down under high-voltage operation.
[0003] Please refer to Figure 1 When growing a gate oxide layer HVGOX in situ on the silicon surface of the active area AA of the high-voltage transistor, due to the influence of lateral diffusion oxidation of oxygen (O2), silicon oxide will be formed under the hard mask HM (such as SiN) at a relatively slow growth rate, and the farther the distance from the hard mask HM opening area 10a, the slower the growth rate, resulting in the formation of a beak structure 10b at the edge of the active area AA after the growth of the gate oxide layer. The existence of the beak structure 10b will occupy the area of the oxide that should be shielded by the hard mask HM, resulting in uneven HVGOX thickness, thickening of the oxide, and affecting the formation of subsequent metal silicide or contact holes, etc. affecting the reliability and miniaturization degree of the device.
[0004] Therefore, the improvement of the beak structure is a technical problem that needs to be solved in the field. SUMMARY
[0005] The purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, which can improve the beak problem generated in the process of forming a gate oxide layer.
[0006] To achieve the above-mentioned purpose, the present application provides a manufacturing method of a semiconductor device, which comprises the following steps:
[0007] A substrate is provided, and a device isolation structure is formed in the substrate to define an active area for forming a gate oxide layer in the substrate;
[0008] A patterned mask layer and a side trench are formed, the side trench is formed in the boundary top of the device isolation structure and exposes the top corner of the active area, the bottom surface of the side trench is lower than the bottom surface of the region to be oxidized of the active area, and the patterned mask layer exposes the top surface of the active area and the side trench;
[0009] A barrier layer is formed, the barrier layer fills and closes the side trench, and one side of the barrier layer extends to part of the top surface of the top corner of the active area, and the other side covers the sidewall of the device isolation structure and the patterned mask layer above the side trench to form a barrier sidewall;
[0010] growing a gate oxide layer of a desired thickness in situ on a surface of the active region, a bottom of the gate oxide layer being higher than a bottom of the edge trench.
[0011] Optionally, a recess is formed in a top of the device isolation structure and spaced apart from the edge trench, the barrier layer also filling and closing the recess, a top surface of the barrier layer in the recess being higher than a top surface of the active region, a bottom surface of the recess being flush with or lower than a bottom surface of the edge trench.
[0012] Optionally, the steps of forming the patterned mask layer and the recess and the edge trench comprise:
[0013] depositing a mask layer and etching the mask layer to form the patterned mask layer having a second opening corresponding to the recess and a first opening exposing a top surface of the active region and a top corner of the device isolation structure;
[0014] etching the device isolation structure along the second opening and the first opening to form the recess at a bottom of the second opening and the edge trench under a sidewall of the first opening;
[0015] Alternatively, the steps of forming the patterned mask layer and the recess and the edge trench comprise:
[0016] depositing a mask layer and etching the mask layer to form the patterned mask layer having a second opening for defining an area where the recess is to be formed,
[0017] etching the device isolation structure along the second opening to form the recess at a bottom of the second opening;
[0018] forming a patterned photoresist layer to mask the recess and define an area where the first opening is to be formed;
[0019] etching to remove the patterned mask layer on the top surface of the active region and the top corner of the device isolation structure and the top corner of the device isolation structure with the patterned photoresist layer as a mask to expose the top surface and the top corner of the active region and form the edge trench;
[0020] removing the patterned photoresist layer to re-expose the recess.
[0021] Optionally, the device isolation structure is etched along the second opening and the first opening using a dry etching process first, and then etched along the second opening and the first opening using a wet etching process to form the recess and the edge trench.
[0022] Optionally, the step of forming the barrier layer comprises:
[0023] depositing a barrier layer, the barrier layer enclosing the recess and the edge trench, and the top surface of the barrier layer at each position above the recess and the edge trench being higher than the bottom surface of the mask layer;
[0024] etching the barrier layer to remove the barrier layer on the top surface of the mask layer and the top surface of the active region.
[0025] Optionally, the step of etching the barrier layer comprises: first anisotropically etching the barrier layer to expose the top surface of the mask layer and / or the top surface of the active region, and then wet-etching the barrier layer to ensure the top surface of the active region is clean.
[0026] Optionally, after forming the patterned mask layer and exposing the top surface of the active region, the surface of the active region is further etched to reduce the height of the top of the active region and / or to round the corners of the active region.
[0027] Alternatively, after forming the device isolation structure and before forming the patterned mask layer, the active region is etched to reduce the height of the top of the active region.
[0028] Optionally, the method for manufacturing a semiconductor device further comprises at least one of the following:
[0029] (1) the mask layer comprises a silicon oxide layer and / or a high-k dielectric with a dielectric constant k greater than that of silicon oxide;
[0030] (2) the barrier layer comprises a silicon nitride layer and / or a silicon oxynitride layer;
[0031] (3) the barrier layer has a stepped structure on the side close to the active region;
[0032] (4) the barrier layer forms a filling cavity in the edge trench;
[0033] (5) the device isolation structure is a shallow trench device isolation structure;
[0034] (6) the extension width of the barrier layer on the top surface of the top corner of the active region accounts for 3% to 8% of the total width of the top surface of the active region;
[0035] (7) the extension width of the barrier layer on the top surface of the top corner of the active region is
[0036]
[0037] (8) the upper surface of the barrier layer in the edge trench is higher than the top surface of the active region.
[0038] Based on the same inventive concept, the present application also provides a semiconductor device comprising:
[0039] a substrate;
[0040] a device isolation structure formed in the substrate and defining an active region in the substrate, a side trench formed in a top side of the device isolation structure, the side trench exposing a top corner of the active region, a bottom surface of the side trench being lower than a top surface of the active region;
[0041] a barrier layer filling and closing the side trench, a portion of the barrier layer extending onto a part of the top surface of the top corner of the active region, another portion of the barrier layer covering a sidewall of the device isolation structure above the side trench to form a barrier sidewall;
[0042] a gate oxide layer formed on the top surface of the active region, a bottom of the gate oxide layer being higher than a bottom of the side trench.
[0043] Optionally, the semiconductor device further comprises at least one of the following parameters:
[0044] (1) a recess is further formed in the top side of the device isolation structure and spaced apart from the side trench, the barrier layer further filling and closing the recess, a top surface of the barrier layer in the recess being higher than the top surface of the active region, a bottom surface of the recess being flush with or lower than the bottom surface of the side trench;
[0045] (2) the barrier layer comprises a silicon nitride layer and / or a silicon oxynitride layer;
[0046] (3) the barrier layer has a stepped structure at a side close to the active region;
[0047] (4) the barrier layer forms a filling cavity in the side trench;
[0048] (5) the device isolation structure is a shallow trench device isolation structure;
[0049] (6) an extension width of the barrier layer on the top surface of the top corner of the active region accounts for 3% to 8% of a total width of the top surface of the active region;
[0050] (7) the extension width of the barrier layer on the top surface of the top corner of the active region is
[0051]
[0052] (8) an upper surface of the barrier layer in the side trench is higher than the top surface of the active region;
[0053] (9) a mask layer is further formed on a surface of the substrate and the device isolation structure other than the barrier layer and the gate oxide layer, the barrier sidewall further covering a sidewall of the mask layer at the side trench.
[0054] Compared with the prior art, the technical scheme of the present application has at least one of the following beneficial effects:
[0055] 1. After forming a device isolation structure, a patterned mask layer exposing the top surface of the active region and a side trench exposing the top corner of the active region are further formed, so that the oxidation speed on the surface of the top corner of the active region and the top surface of the central region is similar when forming a gate oxide layer, and the bird-beak structure is avoided at the edge of the active region, thus improving the device reliability and facilitating the further miniaturization of the device.
[0056] 2. The side trench is filled with a barrier layer, which covers part of the device isolation structure and the patterned mask layer to form a barrier side wall, and the barrier side wall and the barrier layer filled in the side trench can block the lateral diffusion of oxygen during the growth of the gate oxide layer, avoiding the problem that oxygen laterally overcomes the device isolation structure to form a bird-beak structure on the surface of the active region on the other side, and the barrier layer also extends to part of the top surface of the top corner of the active region, so that the barrier layer can be used to make the gate oxide layer corner uniform when forming the gate oxide layer, which is beneficial to obtaining a rounded top corner of the active region after the formation of the gate oxide layer, and further avoiding the problem of the sharp tip of the active region.
[0057] 3. A recess is further formed in the top of the device isolation structure, which is spaced apart from the side trench and has a bottom surface lower than or flush with the side trench, and the barrier layer also fills and seals the recess, so that the barrier layer in the recess further enhances the blocking ability of the device isolation structure to oxygen, and maximally avoids the problem that a bird-beak structure is formed on the active region on the other side due to the lateral diffusion of oxygen over the device isolation structure during the growth of the gate oxide layer. BRIEF DESCRIPTION OF DRAWINGS
[0058] Those skilled in the art will understand that the provided drawings are for better understanding of the present application, and do not constitute any limitation on the scope of the present application. Among them:
[0059] Figure 1 is a schematic diagram of a bird-beak structure produced by the prior art when forming a gate oxide layer.
[0060] Figure 2 is a flowchart of the manufacturing method of the semiconductor device of the first embodiment of the present application.
[0061] Figure 3 is a schematic diagram of the device cross-sectional structure in the manufacturing method of the semiconductor device of the first embodiment of the present application.
[0062] Figure 4 is a schematic diagram of another bird-beak structure produced by the prior art when forming a gate oxide layer.
[0063] Figure 5is a flow chart of a manufacturing method of a semiconductor device according to a second embodiment of the present application.
[0064] Figure 6 is a schematic diagram of a cross-sectional structure of an example device in the manufacturing method of a semiconductor device according to the second embodiment of the present application.
[0065] Figures 7 to 9 is a schematic diagram of a cross-sectional structure of another example device in the manufacturing method of a semiconductor device according to the second embodiment of the present application. DETAILED DESCRIPTION
[0066] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon
[0067] The technical solutions of the present application are further described in detail below in combination with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of facilitating and clarifying the description of the embodiments of the present application.
[0068] First Embodiment
[0069] Referring to Figure 2 An embodiment of the present application provides a manufacturing method of a semiconductor device, which comprises the following steps:
[0070] S11, providing a substrate, and forming a device isolation structure in the substrate to define an active region for forming a gate oxide layer in the substrate;
[0071] S12, a patterned mask layer and a side trench are formed. The side trench is formed at the top of the boundary of the device isolation structure and exposes the apex of the active region. The bottom surface of the side trench is lower than the bottom surface of the active region to be oxidized. The patterned mask layer exposes the top surface of the active region and the side trench.
[0072] S13, forming a barrier layer that fills and seals the side trench, with one side of the barrier layer extending to a portion of the top surface of the top corner of the active region, and the other side covering the device isolation structure and the sidewall of the patterned mask layer above the side trench to form a barrier sidewall;
[0073] S14, a gate oxide layer of the required thickness is grown in situ on the surface of the active region, wherein the bottom of the gate oxide layer is higher than the bottom of the side trench.
[0074] In step S11, please refer to Figure 3 In (A), the substrate 100 provided can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC), or silicon-on-insulator (SOI). Furthermore, a device isolation structure 101 can be formed in the substrate 100 using a local field oxide isolation process or a shallow trench isolation process. The device isolation structure 101 can define an active region AA and other active regions in the substrate 100 for forming a gate oxide layer.
[0075] As an example, the process of forming a device isolation structure 101 in a substrate 100 using a shallow trench isolation process may include:
[0076] (1) A pad oxide layer (PAD OX, not shown) is formed on the substrate by any suitable process such as thermal oxidation, atomic layer deposition or plasma-enhanced chemical vapor deposition.
[0077] (2) Shallow trenches (not shown) are formed on the substrate 100 by a series of processes such as hard mask layer deposition, photolithography and etching.
[0078] (3) Please refer to the method of forming a linear oxide layer on the inner surface of the shallow trench by thermal oxidation, atomic layer deposition or plasma-enhanced chemical vapor deposition (not shown).
[0079] (4) The insulating medium material is deposited by a chemical vapor deposition process to fill the shallow trenches, and further removed by a chemical mechanical polishing or wet etching process to form a shallow trench isolation structure (STI) filled in the shallow trenches and as the device isolation structure 101, which defines active areas AA and other active areas for forming gate oxide layers in the substrate 100. The top surface of the formed device isolation structure 101 can be flush with the top surface of the substrate 100, or can be higher than the top surface of the substrate 100.
[0080] It should be understood that after the device isolation structure 101 is formed, the pad oxide layer and the hard mask layer can be removed or retained as needed. In addition, before or after the device isolation structure is formed, boron or other P-type ions can be implanted in the corresponding regions of the substrate to form a P-well region (not shown), and arsenic or phosphorus or other N-type ions can be implanted to form an N-well region (not shown).
[0081] In addition, in an example of the present embodiment, please refer to (A) and (B) in Figure 3 After the device isolation structure 101 is formed and before the mask layer 102 is deposited, any suitable etching process such as dry etching or wet etching can be used to etch the top of the active area AA to reduce the height of the top of the active area AA, so that a relatively flat device surface can be obtained when the gate oxide layer is subsequently formed.
[0082] In step S12, first, please continue to refer to (A) in Figure 3 The mask layer 102 can include any suitable oxide layer such as silicon oxide or high-k dielectric with a dielectric constant k greater than that of silicon oxide, and has a thickness greater than that of the pad oxide layer or the natural oxide layer on the substrate 100. Then, please continue to refer to (B) in Figure 3 The mask layer 102 is subjected to lithography and etching to form a first opening 102a that exposes the top corner of the device isolation structure 101 outside the active area AA and the top surface of the active area AA where the gate oxide layer is to be formed. Next, please continue to refer to (C) in Figure 3 The top corner of the device isolation structure 101 is etched to a corresponding depth d2 (e.g., below the bottom surface of the portion of the active area AA where the gate oxide layer is to be formed) in the first opening 102a by a wet etching or dry etching process or a combination of dry etching and wet etching to form a side trench 101a that exposes the top corner of the active area AA, and the bottom surface of the side trench 101a is lower than the top surface of the active area AA.
[0083] Optionally, when the device isolation structure 101 is etched by wet etching to form the edge trench 101a, the wet etching solution used can be any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, H2O) or SC1 (a mixture of NH4OH, H2O2, H2O).
[0084] It should be understood that the line width of the edge trench 101a can be set as required, for example, to be a size that can be sealed by a barrier layer and form a filling void inside.
[0085] Optionally, in an example of the embodiment, please refer to Figure 8 After the first opening 102a is formed to expose the top surface of the active area AA and before the edge trench 101a is formed, any suitable etching process such as dry etching can be used to etch the top of the active area AA to reduce the height of the top of the active area AA (for example, by a height d4) and to round the corners of the top of the active area AA to improve the thickness uniformity of the barrier layer 103b that will be subsequently formed on the top corners of the top of the active area AA, so as to obtain a relatively flat device surface when the gate oxide layer is subsequently formed and to improve the thickness uniformity of the corners of the gate oxide layer.
[0086] Optionally, in another example of the embodiment, please refer to Figure 9 After the edge trench 101a is formed and before the barrier layer 103 is deposited, any suitable etching process such as dry etching or wet etching can be used to etch the corners of the top of the active area AA to further round the corners of the top of the active area AA.
[0087] In step S13, first, please refer to Figure 3 (D), any suitable process such as furnace tube deposition or chemical vapor deposition is used to deposit any suitable barrier material such as silicon nitride or silicon oxynitride on the surfaces of the patterned mask layer 102, the edge trench 101a and the active area AA to form the barrier layer 103. The deposited barrier layer 103 not only fills and seals the edge trench 101a (i.e., seals the top end of the edge trench 101a), but also overflows by a height h from the top of the edge trench 101a to ensure that the barrier layer 103 completely fills the edge trench 101a (allowing the edge trench 101a to have a filling void sealed inside by the barrier layer). Then, please refer to Figure 3(E) in FIG. 1, the barrier layer 103 is etched by using an anisotropic etching process or any suitable etching process such as wet etching, to remove the barrier layer 103 on the top surface of the patterned mask layer 102 and most of the barrier layer 103 on the top surface of the active area AA of the first opening 102a, leaving the remaining barrier layer 103b filled in the side trench 101a and covering the sidewall of the device isolation structure 101 and the patterned mask layer 102 in the first opening 102a on one side to form a barrier sidewall, and extending to the top surface of the top corner of the active area AA (within the W width) on the other side, so that the part of the remaining barrier layer 103b used as the barrier sidewall, the part filled in the side trench 101a, and the part extending to the top surface of the top corner of the active area AA have top surfaces with decreasing heights in sequence, and the surface of the remaining barrier layer 103b in the side trench 101a near the active area AA on one side is in a stepped shape. The protection of the stepped barrier layer can better prevent the problem of bird's beak caused by oxygen passing through the device isolation structure 101 in the subsequent process of forming a gate oxide layer.
[0088] When the barrier layer 103 is etched by using a wet etching process, the amount of etching liquid (such as acid) needs to be controlled to ensure that the barrier layer outside the W width of the top corner of the active area AA is completely removed, and the remaining barrier layer in the top corner of the active area AA and the side trench 101a is ensured, so as to reduce the bird's beak phenomenon caused by oxygen penetration in the subsequent process of growing a gate oxide layer in situ on the surface of the active area AA. The wet etching process can further remove the residues generated in the process of etching the barrier layer 103, and clean the surface of the active area AA to ensure the uniformity of the gate oxide layer grown on the active area AA subsequently. In addition, the wet etching process for etching the barrier layer 103 can also make the side surface of the barrier layer 103 in the stepped state smooth, which is beneficial to the coverage of the subsequent film layer.
[0089] In this embodiment, the bottom depth d2 of the side trench 101a is greater than the bottom depth d3 of the part of the active area AA to be oxidized into a gate oxide layer subsequently, so as to ensure the barrier ability of the side trench 101a to the lateral diffusion of oxygen when the surface layer of the active area AA is oxidized to form a gate oxide layer subsequently.
[0090] In addition, the width of the edge trench 101a is relatively small, and the depth-to-width ratio of the edge trench 101a causes the deposited barrier layer 103 to form a filling void 104 inside the edge trench 101a while closing the top opening of the edge trench 101a, thereby ensuring the thickness of the barrier layer 103 covering the top corner surface of the active area AA, and further ensuring that, after etching the barrier layer 103 to remove the excess barrier layer, the remaining barrier layer can simultaneously achieve the following effects: (1) fill the edge trench 101a in a manner that the edge trench 101a has the filling void 104 and the top opening of the edge trench 101a is closed; (2) form a barrier side wall 103b on the sidewall of the device isolation structure 101 and the sidewall of the patterned mask layer 102 on the side of the barrier layer 103b, which, together with the barrier layer filled in the edge trench 101a, maximally blocks the lateral diffusion of oxygen during the subsequent gate oxide formation process, thereby avoiding the formation of a bird's beak; and (3) on the other side, generate a stack covering the width W of the top corner top surface of the active area AA, to form coverage at the top corner of the active area AA, in preparation for the next step of forming a uniform gate oxide corner. Exemplarily, the width W is This scheme of forming a filling void 104 during deposition of the barrier layer and further using the stack brought by the filling void during etching of the barrier layer to ensure the blocking effect of the remaining barrier layer can save the process of specially making a corresponding protective film layer or structure, thereby greatly saving costs.
[0091] Of course, in other embodiments of the present application, the depth-to-width ratio of the edge trench 101a can be relatively small, the deposited barrier layer 103 is filled in the edge trench 101a without a filling void, and then the excess barrier layer is removed and the required barrier layer is retained by a method of photolithography combined with etching, which can also achieve the effect of the above-mentioned stepped barrier layer close to the above-mentioned embodiment, and details are not repeated here.
[0092] In step S14, please refer to (F) in Figure 3 According to the thickness requirement of the gate oxide layer, a corresponding hot oxidation process recipe (gate oxide recipe) can be set, and the top of the active area AA exposed by the first opening 102a is hot oxidized according to the process recipe, thereby in-situ growing (also can be said to be "self-aligned growing") a gate oxide layer (HVGOX) 105 with a required thickness. During this process, on the one hand, since the remaining barrier layer 103b only covers the top corner area of the active area AA, it will not produce a bird's beak with the gate oxide layer 105, and on the other hand, the remaining barrier layer 103b can form a barrier side wall 103b on the sidewall of the device isolation structure 101 and the sidewall of the patterned mask layer 102 on the side of the barrier layer 103b, which, together with the barrier layer filled in the edge trench 101a, maximally blocks the lateral diffusion of oxygen during the subsequent gate oxide formation process, thereby avoiding the formation of a bird's beak. Figure 1As shown in the bird's beak problem, on the other hand, the remaining barrier layer 103b at the edge trench 101a not only forms a barrier sidewall but also the bottom depth d2 of the edge trench 101a is greater than the bottom depth d3 of the region of the active area AA being oxidized by the gate oxide layer, thus avoiding the formation of a bird's beak problem at the surface of the active area on the other side of the device isolation structure. In addition, the barrier layer 103b covers the top corner of the active area AA, which can improve the uniformity of the growth rate of the gate oxide layer at the top corner of the active area AA and the thickness uniformity during the formation of the gate oxide layer 105, further maintaining the rounding of the top corner of the active area AA, thereby improving the device reliability and the yield of the product
[0093] As an example, the formed thickness of the gate oxide layer 105 is also sufficient to restore the surface flatness between the top surface of the patterned mask layer 102 and the surrounding region of the active area AA.
[0094] Based on the same inventive concept, please refer to (F) in Figure 3 The present embodiment also provides a semiconductor device which can be formed by using the manufacturing method of the semiconductor device of the present embodiment, and the semiconductor device comprises a substrate 100, a device isolation structure 101, a gate oxide layer 105 and a barrier layer 103b.
[0095] The substrate 100, the device isolation structure 101, the gate oxide layer 105 and the barrier layer 103b can be made of any suitable material, which can be referred to the corresponding content of the manufacturing method above, and will not be described here. As an example, the barrier layer 103b comprises a silicon nitride layer or a silicon oxynitride layer or a composite layer formed by stacking a silicon nitride layer and a silicon oxynitride layer. The device isolation structure 101 is a shallow trench device isolation structure.
[0096] The device isolation structure 101 is formed in the substrate 100 and defines an active area AA for forming a gate oxide layer in the substrate 100, and an edge trench 101a is formed in the top of the boundary of the device isolation structure 101, the edge trench 101a exposes the top corner of the active area AA, and the bottom surface of the edge trench 101a is lower than the top surface of the active area AA.
[0097] The barrier layer 103b fills and seals the edge trench 101a, and one side of the barrier layer 103b extends to the top surface of the top corner of the active area AA with an extension width W, and the other side covers the sidewall of the device isolation structure 101 above the edge trench 101a to form a barrier sidewall.
[0098] The gate oxide layer 105 is formed on the top surface of the active area AA, and the bottom of the gate oxide layer AA is higher than the bottom of the edge trench 101a.
[0099] Optionally, the extending width W of the barrier layer 103b on the top surface of the top corner of the active area AA accounts for 3% to 8% of the total width of the top surface of the active area AA. As an example, the extending width W of the barrier layer 103b on the top surface of the top corner of the active area AA is 0.3 to 0.8 μm.
[0100] In this embodiment, the barrier layer 103b is formed with the filling void 104 in the edge trench 101a. In other embodiments, the barrier layer 103b can fill the edge trench 101a without forming the filling void 104.
[0101] In this embodiment, the top surface of the barrier layer 103b used as the part of the barrier side wall, the part filled in the edge trench 101 and the part extending to the top surface of the top corner of the active area AA are all higher than the top surface of the active area AA, and the heights are lowered in sequence, so that the barrier layer 103b presents a stepped structure near the side of the active area AA.
[0102] In this embodiment, the surface of the substrate 100 and the device isolation structure 101 except the gate oxide layer 105 is further formed with the mask layer 102, and the part of the barrier layer 103b used as the part of the barrier side wall further covers the sidewall of the mask layer 102 at the edge trench 101a.
[0103] In summary, the semiconductor device and the manufacturing method thereof of this embodiment, after forming the device isolation structure, further form a patterned mask layer exposing the top surface of the active area and an edge trench exposing the top corner of the active area, so that the oxidation speed on the surface of the top corner of the active area and the top surface of the central region can be made similar when forming the gate oxide layer, and the bird-beak structure is avoided to be formed at the edge of the active area, thus being beneficial to improve the device reliability and to further scale down the device. Meanwhile, the barrier layer is filled in the edge trench, on one hand, the barrier layer covers part of the device isolation structure and the patterned mask layer to form the barrier side wall, and the barrier side wall and the barrier layer filled in the edge trench can block the lateral diffusion of oxygen during the growth of the gate oxide layer, and avoid the problem that oxygen laterally diffuses over the device isolation structure to form the bird-beak structure on the surface of the active area on the other side, on the other hand, the barrier layer further extends to part of the top surface of the top corner of the active area, so that the barrier layer can be used to make the gate oxide layer even when forming the gate oxide layer, and it is beneficial to obtain the rounded top corner of the active area after forming the gate oxide layer, and further to avoid the problem of the sharp tip of the active area.
[0104] The semiconductor device and the manufacturing method thereof of this embodiment improve the bird-beak problem caused by the lateral diffusion of oxygen during the formation of the gate oxide layer at a lower cost.
[0105] Second embodiment
[0106] Please refer to Figure 4In the process of growing the gate oxide layer HVGOX in situ on the surface of the active area AA1 exposed by the trench 10a, the lateral diffusion of oxygen can also pass through the surrounding device isolation structure STI1 to react with the surface layer of the active area AA2 (used as a source area or a drain area) on the other side of the STI1 to form a beak 10b. The presence of the beak 10b can easily lead to the following problems: (1) the abnormal thickening of the silicon oxide on the surface of the active area AA2, which affects the implementation of subsequent processes; (2) the beak 10b formed on the active area AA2 can be connected with the device isolation structure STI2 outside the beak 10b, thereby causing the subsequent metal silicide (not shown) to be unable to be formed on the active area AA2; (3) even if the beak 10b formed on the top surface of the active area AA2 between the STI1 and the STI2 is not connected, but only the beak is too large, it can also occupy the area of the active area AA2 where the metal silicide should be formed, causing the metal silicide to be unable to be formed on the active area AA2 with normal topography; (4) the amount of etching liquid such as HF acid needs to be increased for wet removal of the beak 10b; (5) due to the presence of the beak 10b on the active area AA2, the contact hole CT (not shown) formed on the active area AA2 in the subsequent process cannot be connected to the metal silicide (for example, when the window for wet removal of the beak is insufficient); (6) due to the presence of the beak 10b on the active area AA2, the metal silicide is insufficiently formed, thereby causing the contact hole CT to have a high resistance state and a high RC delay, the device has a large power consumption, and even cannot work normally.
[0107] Based on this, please refer to Figure 5 The embodiment provides a manufacturing method of a semiconductor device, which comprises the following steps:
[0108] S21, providing a substrate, and forming a device isolation structure in the substrate to define an active area for forming a gate oxide layer in the substrate;
[0109] S22, forming a patterned mask layer and a groove and a side trench, the side trench is formed in the boundary top of the device isolation structure and exposes the top corner of the active area, the groove is formed in the top of the device isolation structure and is spaced apart from the side trench, the bottom surface of the groove is flush with or lower than the bottom surface of the side trench, the bottom surface of the side trench is lower than the bottom surface of the region to be oxidized of the active area, and the patterned mask layer exposes the top surface of the active area and the side trench and the groove;
[0110] S23, forming a barrier layer, the barrier layer fills and seals the side trench and the groove, one side of the barrier layer extends to part of the top surface of the top corner of the active area, and the other side covers the sidewall of the device isolation structure and the patterned mask layer above the side trench to form a barrier side wall;
[0111] S24, growing a gate oxide layer with a desired thickness on the surface of the active area in situ, the bottom of the gate oxide layer being higher than the bottom of the edge trench.
[0112] In step S21, referring to (A) in Figure 6 The substrate 100 provided in step S21 can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC), or silicon on insulator (SOI), etc. A device isolation structure 101 can be formed in the substrate 100 using a local field oxide isolation process or a shallow trench isolation process, which can define an active area AA and other active areas for forming a gate oxide layer in the substrate 100.
[0113] Any suitable process can be used in step S22 to form a patterned mask layer 102 on the substrate 100 and the device isolation structure 101a, and to form an edge trench 101a and a recess 101b in the top of the device isolation structure 101a.
[0114] In an example, the process of forming the patterned mask layer 102, the edge trench 101a, and the recess 101b in step S22 includes:
[0115] First, referring to (A) in Figure 6 The mask layer 102 can be formed on the top surface of the substrate 100 and the device isolation structure 101 using any suitable process, such as atomic layer deposition or plasma-enhanced chemical vapor deposition.
[0116] Next, referring to (B) in Figure 6 The mask layer 102 is subjected to photolithography and etching to form a patterned mask layer 102 with a first opening 102a and a second opening 102b. The first opening 102a exposes the top surface of the active area AA to be formed with a gate oxide layer and the top corner of the device isolation structure 101 outside the active area AA. The second opening 102b is spaced apart from the first opening 102a and exposes part of the top surface of the device isolation structure 101. The patterned mask layer 102 also covers the top surface of other active areas and the device isolation structure 101 outside the first and second openings 102a and 102b.
[0117] Then, any suitable etching process, such as dry etching, wet etching, or a combination of dry and wet etching, can be used to etch the device isolation structure 101 along the second opening 102b and the first opening 102a to form a groove 101b at the bottom of the second opening 102b and a side trench 101a below the sidewall of the first opening 102a. Thus, the side trench 101a and the groove 101b are formed together in the same etching process. The bottom surface of the groove 101b can be approximately flush with the bottom surface of the side trench 101a, that is, the bottom depth d2 of the side trench 101a is equal to the bottom depth d1 of the groove 101b.
[0118] For example, a dry etching process is first used to etch the device isolation structure 101 along the second opening 102b and the first opening 102a, and then a wet etching process is used to continue etching the device isolation structure 101 along the second opening 102b and the first opening 102a to form a groove 101b and a side trench 101a.
[0119] In another example, the process of forming the patterned mask layer 102, the side trench 101a, and the groove 101b in step S22 includes:
[0120] First, please refer to Figure 7 In (A), a mask layer 102 can be covered on the top surface of the substrate 100 and the device isolation structure 101 by any suitable process such as atomic layer deposition or plasma-enhanced chemical vapor deposition.
[0121] Next, please continue to refer to Figure 7 In step (A), the mask layer 102 is photolithographically and etched to form a second opening 102b. The second opening 102b is located within the boundary where the device isolation structure 101 is connected to the active region AA, and exposes part of the top surface of the device isolation structure 101, which is used to define the area where the groove 101b to be formed is formed.
[0122] Then, please continue to refer to Figure 7 In step (A), any suitable etching process, such as dry etching, wet etching, or a combination of dry etching and wet etching, can be used to etch the device isolation structure 101 along the second opening 102b to form a groove 101b in the top of the device isolation structure 101 at the bottom of the second opening 102b. The bottom depth of the groove 101b is d1, which is greater than the bottom depth of the gate oxide layer to be formed.
[0123] Next, please continue to refer to Figure 7 In step (A), photoresist is applied and photolithography is performed to form a patterned photoresist layer (not shown), which masks the groove 101b and defines the area where the first opening 102a is to be formed.
[0124] Then, please continue to refer to Figure 7(B) of FIG. 1 1, the patterned photoresist layer is used as a mask to etch and remove the patterned mask layer on the top surface of the active region AA and the top corner of the device isolation structure 101, and to expose the top surface and the top corner of the active region AA, and to form the edge trench 101a. The bottom surface depth d2 of the edge trench 101a can be less than or equal to the bottom surface depth dl of the recess 101b, but greater than the bottom surface depth d3 of the gate oxide layer to be formed later.
[0125] Then, please continue to refer to Figure 7 (B) of FIG. 1 1, the patterned photoresist layer is used as a mask to etch and remove the patterned mask layer on the top surface of the active region AA and the top corner of the device isolation structure 101, and to expose the top surface and the top corner of the active region AA, and to form the edge trench 101a. The bottom surface depth d2 of the edge trench 101a can be less than or equal to the bottom surface depth dl of the recess 101b, but greater than the bottom surface depth d3 of the gate oxide layer to be formed later.
[0126] Optionally, in an example of the present embodiment, please refer to Figure 8 After the first opening 102a is formed to expose the top surface of the active region AA and before the edge trench 101a is formed, any suitable etching process such as dry etching can be used to etch the top of the active region AA to reduce the height of the top of the active region AA (e.g., by d4 height), and to round the corners of the top of the active region AA to improve the thickness uniformity of the remaining barrier layer 103b covering the top surface of the corners of the active region AA, so as to obtain a relatively flat device surface when the gate oxide layer is formed later, and to improve the thickness uniformity of the corners of the gate oxide layer.
[0127] Optionally, in an example of the present embodiment, please refer to Figure 9 After the edge trench 101a is formed and before the barrier layer 103 is deposited, any suitable etching process such as dry etching or wet etching can be used to etch the corners of the active region AA to further round the corners of the active region AA.
[0128] In step S23, first, please refer to Figure 6 (D) of FIG. 1 1, the barrier layer 103 is deposited on the surfaces of the patterned mask layer 102, the edge trench 101a and the active region AA by any suitable process such as furnace tube deposition or chemical vapor deposition. The deposited barrier layer 103 not only fills and seals the edge trench 101a and the recess 101b (i.e., seals the top end of the edge trench 101a and the recess 101b), but also overflows by a height h from the top of the edge trench 101a to ensure that the barrier layer 103 completely fills the edge trench 101a and the recess 101b (allowing the edge trench 101a and the recess 101b to have a filling cavity sealed inside by the barrier layer). Then, please refer to Figure 6In step (E), the barrier layer 103 is etched using any suitable etching process, such as anisotropic etching or wet etching, to remove most of the barrier layer 103 on the top surface of the patterned mask layer 102 and the top surface of the active region AA of the first opening 102a. The remaining barrier layer 103a fills the groove 101b, and the remaining barrier layer 103b fills the side trench 101a and also covers one side of the device isolation structure 101 in the first opening 102a and the sidewall of the patterned mask layer 102 to form a barrier sidewall. One side extends to the top surface (within the width W) of the active region AA apex in the first opening 102a. Thus, the top heights of the remaining barrier layer 103b, which serves as a barrier sidewall, the portion filling the side trench 101a, and the portion extending to the top surface of the active region AA apex, decrease sequentially. This makes the surface of the remaining barrier layer 103b at the side trench 101a near the active region AA step-shaped. The protective effect of this step-shaped barrier layer can better prevent oxygen from passing through the device isolation structure 101 and forming a bird's beak during the subsequent gate oxide layer formation process.
[0129] In step S24, please refer to Figure 6 In step (F), a corresponding thermal oxidation process recipe can be set according to the required thickness of the gate oxide layer. Based on this recipe, the top of the active region AA exposed by the first opening 102a is thermally oxidized, thereby growing (or "self-aligned growth") the required thickness of the gate oxide layer (HVGOX) 105 in situ. During this process, since the remaining barrier layer 103b only covers the apex region of the active region AA, it will not generate [something related to the gate oxide layer]. Figure 1 Regarding the bird's beak problem shown, on the other hand, the remaining barrier layer 103b at the side trench 101a and the barrier layer 103a filling the groove 101b can block oxygen from passing through the device isolation structure 101, thus avoiding the formation of the bird's beak problem on the surface of the active region on the other side of the device isolation structure. In addition, the barrier layer 103b covers the apex corner of the active region AA, which can improve the uniformity of the growth rate and the uniformity of the thickness of the gate oxide layer at the apex corner of the active region AA during the formation of the gate oxide layer 105, and further maintain the rounded corner of the active region AA, thereby improving device reliability and product yield.
[0130] Based on the same inventive concept, please refer to Figure 6 In (F), this embodiment also provides a semiconductor device that can be formed using the semiconductor device manufacturing method of this embodiment. The semiconductor device includes a substrate 100, a device isolation structure 101, a gate oxide layer 105, and a barrier layer 103b.
[0131] The substrate 100, the device isolation structure 101, the gate oxide layer 105 and the barrier layer 103b can be made of any suitable material, which can be referred to in the above manufacturing method, and will not be repeated here. As an example, the barrier layer 103b includes a silicon nitride layer or a silicon oxynitride layer or a composite layer formed by stacking a silicon nitride layer and a silicon oxynitride layer. The device isolation structure 101 is a shallow trench device isolation structure.
[0132] The device isolation structure 101 is formed in the substrate 100 and defines an active area AA for forming the gate oxide layer 105 in the substrate 100. A side trench 101a is formed in the top of the boundary of the device isolation structure 101. A recess 101b is also formed in the top of the device isolation structure 101 and is spaced apart from the side trench 101a. The side trench 101a exposes a top corner of the active area AA. The bottom surface of the side trench 101a is lower than the top surface of the active area AA. The bottom surface of the recess 101b is flush with or lower than the bottom surface of the side trench 101a.
[0133] The barrier layer fills and seals the side trench 101a and the recess 101b. The top surface of the barrier layer 103a in the recess 101b is higher than the top surface of the active area AA. One side of the barrier layer 103b at the side trench 101a extends to a part of the top surface of the top corner of the active area AA with an extension width W. The other side of the barrier layer 103b covers the sidewall of the device isolation structure 101 above the side trench 101a to form a barrier sidewall.
[0134] The gate oxide layer 105 is formed on the top surface of the active area AA, and the bottom of the gate oxide layer AA is higher than the bottom of the side trench 101a.
[0135] Optionally, the extension width W of the barrier layer 103b on the top surface of the top corner of the active area AA accounts for 3% to 8% of the total width of the top surface of the active area AA. As an example, the extension width W of the barrier layer 103b on the top surface of the top corner of the active area AA is 0.3 μm to 0.8 μm.
[0136] In this embodiment, the barrier layer 103b forms a filling cavity 104 in the side trench 101a, and the barrier layer 103a forms a filling cavity 104 in the recess 101b. In other embodiments, the barrier layer 103b can fill the side trench 101a without forming a filling cavity 104. The barrier layer 103a can fill the recess 101b without forming a filling cavity 104.
[0137] In this embodiment, the top surfaces of the barrier layer 103b used as the part of the barrier sidewall, the part filled in the side trench 101a and the part extending to the top surface of the top corner of the active area AA are all higher than the top surface of the active area AA, and the heights decrease in turn, so that the barrier layer 103b presents a stepped structure near the side of the active area AA.
[0138] In the embodiment, a mask layer 102 is further formed on the surface of the substrate 100 and the device isolation structure 101 except the blocking layers 103a, 103b and the gate oxide layer 105, and the blocking layer 103b used for blocking the sidewall further covers the sidewall of the mask layer 102 at the edge trench 101a.
[0139] In summary, the semiconductor device and the manufacturing method thereof in the embodiment further form a groove in the top of the device isolation structure before forming the blocking layer, the bottom surface depth of the groove is not less than the bottom surface depth of the edge trench, and the blocking layer further fills and seals the groove, thereby further improving the blocking ability of the device isolation structure to the lateral diffusion of oxygen by means of the blocking layer in the groove, avoiding the problem of the beak structure formed on the surface layer of the active region on the other side due to the oxygen passing through the device isolation structure during the formation of the gate oxide layer, thereby further improving the device reliability and facilitating the further miniaturization of the device.
[0140] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application, and any modification or change made by the person skilled in the art according to the above disclosure is within the protection scope of the technical scheme of the present application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, and a device isolation structure is formed in the substrate to define an active region for forming a gate oxide layer in the substrate; A patterned mask layer and a trench are formed, the trench being formed at the top of the boundary of the device isolation structure and exposing the apex corner of the active region, the bottom surface of the trench being lower than the bottom surface of the active region to be oxidized, and the patterned mask layer exposing the top surface of the active region and the trench. A barrier layer is formed, which fills and seals the side trench, and one side of the barrier layer extends to a portion of the top surface of the top corner of the active region, while the other side covers the device isolation structure and the sidewall of the patterned mask layer above the side trench to form a barrier sidewall. A gate oxide layer of the required thickness is grown in situ on the surface of the active region, wherein the bottom of the gate oxide layer is higher than the bottom of the side trench.
2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, A groove spaced apart from the side trench is formed in the top of the device isolation structure. The barrier layer also fills and seals the groove. The top surface of the barrier layer in the groove is higher than the top surface of the active region. The bottom surface of the groove is flush with or lower than the bottom surface of the side trench.
3. The method for manufacturing a semiconductor device as described in claim 2, characterized in that, The steps for forming the patterned mask layer, as well as the grooves and sidewalls, include: A mask layer is deposited and etched to form the patterned mask layer, the patterned mask layer having a second opening corresponding to the groove and a first opening exposing the top surface of the active region and the apex corner of the device isolation structure; The device isolation structure is etched along the second opening and the first opening to form the groove at the bottom of the second opening and the side trench below the sidewall of the first opening; Alternatively, the steps of forming the patterned mask layer, as well as the grooves and sidewalls, include: A mask layer is deposited and etched to form a patterned mask layer with a second opening, the second opening defining the area for forming the groove. The device isolation structure is etched along the second opening to form the groove at the bottom of the second opening; A patterned photoresist layer is formed to mask the groove and define the area where the first opening is to be formed; Using the patterned photoresist layer as a mask, the patterned mask layer and the top corner of the device isolation structure located on the top surface of the active region and the top corner of the device isolation structure are etched away to expose the top surface and top corner of the active region and form the trench. Remove the patterned photoresist layer to re-expose the groove.
4. The method for manufacturing a semiconductor device as described in claim 3, characterized in that, First, a dry etching process is used to etch the device isolation structure along the second opening and the first opening. Then, a wet etching process is used to continue etching the device isolation structure along the second opening and the first opening to form the groove and the side trench.
5. The method for manufacturing a semiconductor device as described in claim 3, characterized in that, The steps for forming the barrier layer include: A deposited barrier layer is provided, which closes the groove and the side trench, and the top surface of the barrier layer at various locations above the groove and the side trench is higher than the bottom surface of the mask layer. The barrier layer is etched to remove the barrier layer on the top surface of the mask layer and the top surface of the active region.
6. The method for manufacturing a semiconductor device as described in claim 5, characterized in that, The step of etching the barrier layer includes: firstly, anisotropically etching the barrier layer to expose the top surface of the mask layer and / or the top surface of the active region, and then wet etching the barrier layer to ensure that the top surface of the active region is clean.
7. The method for manufacturing a semiconductor device according to any one of claims 1-6, characterized in that, After forming the patterned mask layer and exposing the top surface of the active region, the surface of the active region is further etched to reduce the top height of the active region and / or round the corners of the active region. Alternatively, after forming the device isolation structure and before forming the patterned mask layer, the active region can be etched to reduce the top height of the active region.
8. The method for manufacturing a semiconductor device according to any one of claims 1-6, characterized in that, It also includes at least one of the following: (1) The mask layer includes a silicon oxide layer and / or a high-k dielectric with a dielectric constant k greater than that of silicon oxide; (2) The barrier layer includes a silicon nitride layer and / or a silicon oxynitride layer; (3) The barrier layer has a stepped structure on the side near the active region; (4) The barrier layer forms a filling cavity in the side ditch; (5) The device isolation structure is a shallow trench device isolation structure; (6) The extension width of the barrier layer on the top surface of the top corner of the active region accounts for 3% to 8% of the total width of the top surface of the active region; (7) The extension width of the barrier layer on the top surface of the apex corner of the active region is... (8) The upper surface of the barrier layer in the side ditch is higher than the top surface of the active area.
9. A semiconductor device, characterized in that, include: Substrate; A device isolation structure is formed in the substrate and defines an active region in the substrate for forming a gate oxide layer. A side trench is formed at the top of the boundary of the device isolation structure, the side trench exposes the apex corner of the active region, and the bottom surface of the side trench is lower than the top surface of the active region. A barrier layer fills and seals the trench, with one side of the barrier layer extending to a portion of the top surface of the apex corner of the active region, and the other side covering the sidewall of the device isolation structure above the trench to form a barrier sidewall; A gate oxide layer is formed on the top surface of the active region, and the bottom of the gate oxide layer is higher than the bottom of the side trench.
10. The semiconductor device as claimed in claim 9, characterized in that, It also includes at least one of the following parameters: (1) A groove spaced apart from the side trench is also formed in the top of the device isolation structure, and the barrier layer fills and closes the groove. The top surface of the barrier layer in the groove is higher than the top surface of the active region, and the bottom surface of the groove is flush with or lower than the bottom surface of the side trench. (2) The barrier layer includes a silicon nitride layer and / or a silicon oxynitride layer; (3) The barrier layer has a stepped structure on the side near the active region; (4) The barrier layer forms filling voids in the side ditch; (5) The device isolation structure is a shallow trench device isolation structure; (6) The extension width of the barrier layer on the top surface of the top corner of the active region accounts for 3% to 8% of the total width of the top surface of the active region; (7) The extension width of the barrier layer on the top surface of the apex corner of the active region is... (8) The upper surface of the blocking layer in the side ditch is higher than the top surface of the active area; (9) A mask layer is also formed on the surface of the substrate and the device isolation structure other than the barrier layer and the gate oxide layer, and the barrier sidewall also covers the sidewall of the mask layer at the trench.