HEMT device and preparation method thereof

Abstract

The invention discloses an HEMT device and a preparation method thereof, the HEMT device comprises a barrier layer, a first cap layer, a first insertion layer, a second cap layer and a grid electrode, the first cap layer, the first insertion layer, the second cap layer and the grid electrode are sequentially arranged on the barrier layer, and both the first cap layer and the second cap layer are p-GaN. According to the invention, the insertion layer is introduced between the first p-GaN layer and the second p-GaN layer, etching can be stopped on the surface of the insertion layer and the morphology and thickness of the second p-GaN layer can be maintained when the grid electrode is formed in combination with an etching process, so that the second p-GaN layer can be conveniently shaped during second etching to form a step-shaped grid electrode structure, and current collapse is effectively avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a HEMT device, and a method for fabricating the device. Background Technology

[0002] HEMT (High Electron Mobility Transistor) is a field-effect transistor that utilizes a heterojunction or modulation-doped structure. It exhibits excellent high-frequency performance and is widely used in communications, radar, and other fields. The HEMT structure mainly consists of a substrate, followed by a buffer layer, a GaN channel layer, and an AlGaN barrier layer, all positioned sequentially above the substrate. The heterojunction interface between the channel layer and the barrier layer forms a two-dimensional electron gas (2DEG). Above the barrier layer is a gate, flanked by the source and drain electrodes. The gate depletes the corresponding 2DEG below it. With zero gate bias, the source and drain of the device are turned off.

[0003] Current collapse occurs under certain conditions when leakage current I... D The phenomenon of lower-than-expected values ​​is often addressed by forming a p-GaN cap layer between the barrier layer and the gate. However, the fabrication process of the p-GaN cap layer is relatively complex (CN115472686 A A low dynamic resistance enhancement GaN device).

[0004] The gate is often formed using a mask-etching method. The principle is as follows: first, a complete gate structure layer is formed on the surface of the barrier layer, and then the gate structure without the gate is etched away. Dry etching is usually difficult to control the etching amount accurately, and it is easy to over-etch and damage the barrier layer, which in turn affects the concentration of 2DEG (an enhancement-mode HEMT device CN 118630048 A). Summary of the Invention

[0005] Purpose of the invention: The purpose of this invention is to provide a HEMT device that avoids current collapse and is easy to process. Another purpose of this invention is to provide a method for fabricating a HEMT device to avoid barrier layer etching damage.

[0006] Technical solution: The HEMT device of the present invention includes a barrier layer, a first cap layer, a first insertion layer, a second cap layer, and a gate sequentially disposed on the barrier layer, wherein the first cap layer and the second cap layer are both p-GaN.

[0007] Preferably, the first insertion layer is made of InGaN.

[0008] Preferably, the thickness of the first insertion layer is 10~15nm.

[0009] Preferably, the lateral length of the first cap layer is greater than the lateral length of the second cap layer.

[0010] Preferably, the gate has a source and a drain connected to the barrier layer on both sides, and the distance between the second cap layer and the source is smaller than the distance between the second cap layer and the drain.

[0011] Preferably, a second insertion layer for terminating etching is provided between the barrier layer and the first cap layer.

[0012] Preferably, the second insertion layer is made of AlInN and has a thickness of 1~3nm.

[0013] Preferably, the HEMT device surface is provided with a passivation layer, which is at least one of Si3N4, SiO2, Sc2O3, and Al2O3.

[0014] The method for fabricating a HEMT device according to the present invention includes the following steps:

[0015] (1) A first p-GaN layer, a first insertion layer, and a second p-GaN layer are sequentially formed on the surface of the barrier layer, and a metal layer is deposited on the surface of the second p-GaN layer;

[0016] (2) Perform the first etching to remove the non-gate regions of the metal layer and the second p-GaN layer, forming the gate and the second cap layer. The first etching process conditions are: the flow ratio of BCl3:Cl2:Ar is in the range of 1:1:1.1~1.6, the etching gas pressure is 3~4 mTorr, and the etching power is 22W~25W. Under these process conditions, the etching will stop at the first insertion layer.

[0017] (3) Perform a second etching to remove the first insertion layer in the non-corresponding region of the second cap layer. The second etching process conditions are: BCl3:Cl2:SF6 flow ratio range of 1:1:1~2, etching gas pressure of 2.5~3.5mTorr, and etching power of 18~22W. Using this process, the etching stops on the surface of the first p-GaN layer.

[0018] (4) Perform the third etching to remove the first p-GaN layer and form the first cap layer. The third etching process conditions are: BCl3:Cl2:Ar flow ratio range of 1:1:1~2.1, etching gas pressure of 3~4 mTorr, and etching power of 13~15W.

[0019] By setting a first insertion layer and accurately controlling the etching amount, a cap layer with the desired stepped morphology is formed, simplifying the processing technology and effectively avoiding the current collapse effect.

[0020] Preferably, in step (1), a first p-GaN layer, a first insertion layer, and a second p-GaN layer are formed by vapor deposition, and a metal layer is formed by electron beam evaporation.

[0021] Preferably, step (1) further includes forming a second insertion layer between the barrier layer and the first p-GaN layer.

[0022] Preferably, a fourth etching is performed to remove the second insertion layer corresponding to the source and drain, and metal is deposited on the surface of the barrier layer to form the source and drain.

[0023] Preferably, a passivation layer is deposited on the device surface within a low-pressure chemical vapor deposition (LPCVD) chamber. The passivation layer can effectively suppress electron trapping caused by surface defects.

[0024] Compared with the prior art, the present invention has the following beneficial effects: 1. Avoids current collapse and is easy to process: By introducing an insertion layer between the first p-GaN and the second p-GaN layers, combined with the etching process, when forming the gate, the etching can be stopped at the surface of the insertion layer, maintaining the morphology and thickness of the second p-GaN, which facilitates the shaping of the second p-GaN layer during the second etching to form a stepped gate structure, effectively avoiding current collapse; 2. Avoids barrier layer etching damage: A compound semiconductor insertion layer is deposited on the surface of the barrier layer. This structure avoids etching damage to the barrier layer, effectively reduces the interface density, and the process is controllable and stable, which is conducive to large-scale engineering applications; 3. Improves the gate reliability of the device and enhances the gate control capability of the device under high temperature and high pressure. Attached Figure Description

[0025] Figure 1 and Figure 2 A schematic diagram illustrating the principle of forming the gate and the first cap layer;

[0026] Figure 3 and Figure 4 A schematic diagram illustrating the principle of removing the first insertion layer;

[0027] Figure 5 and Figure 6 A schematic diagram illustrating the principle of forming the second cap layer;

[0028] Figure 7 This is a cross-sectional view of the HEMT device structure of the present invention. Detailed Implementation

[0029] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0030] Example 1: As Figure 7 As shown, this invention discloses a HEMT device, which is consistent with the prior art. The HEMT device includes a substrate, a GaN channel layer, and an AlGaN barrier layer 12. The substrate and GaN channel layer are not shown. On the upper surface of the barrier layer 12, an insertion layer 20, a cap layer 13, an insertion layer 14, a cap layer 15, and a gate 16 are sequentially provided. A source 21 and a drain 22 are respectively provided on both sides of the gate 16.

[0031] The insertion layer 20 is used to achieve lattice matching of the cap layer 13. The material can be AlInN or similar, and the thickness is about 2nm, or 1~3nm.

[0032] Both cap layers 13 and 15 are made of p-GaN. The thickness of cap layer 13 is around 30nm (20-30nm), and the thickness of cap layer 15 is around 50nm (40-50nm). The lateral length of cap layer 13 is greater than that of cap layer 15. The distance between cap layer 15 and source 21 is less than the distance between cap layer 15 and drain 22. Cap layer 15 extends towards the drain, providing a discharge path for electrons trapped in the active region. Therefore, this trapezoidal cap layer can mitigate the current collapse effect of the device.

[0033] The insertion layer 14 is used to control the etching degree. It is a compound such as InGaN that does not change the barrier structure of the cap layer 13 and the cap layer 15. The thickness is about 10nm, which can be 10~15nm. InGaN does not affect the Schottky contact efficiency of the p-GaN gate, and InGaN can be grown by periodically switching the gas in the cavity after GaN growth.

[0034] The gate 16 is made of W and has a thickness of about 50nm, which can be 40~50nm. W metal has a high work function, good thermal stability, and can form a high-quality Schottky contact with the cap layer 15.

[0035] A passivation layer 23 is provided on the device surface, namely the insertion layer 20, gate 16, source 21, and drain 21. The passivation layer 23 is consistent with the prior art and can be made of Si3N4, SiO2, Sc2O3, or Al2O3.

[0036] Example 2: The fabrication method of the HEMT device described in this example is as follows:

[0037] like Figure 1 A high-quality compound semiconductor insertion layer 20 is deposited on the AlGaN barrier layer 12 by chemical vapor deposition (MOCVD). The compound semiconductor can be AlInN or the like. The insertion layer 20 can achieve lattice matching with the subsequent p-GaN layer, which can improve the electron mobility between p-GaN and the barrier layer 12. In addition, it can form a smooth interface with GaN, reduce the interface state density, and suppress the current collapse effect.

[0038] On the insertion layer 20, a high-quality p-GaN layer is deposited using MOCVD. This layer serves as an active passivation layer, directly covering the AlGaN surface in the active region, effectively passivating the AlGaN surface states. As a conductive p-type layer, it can provide a low-impedance release path for the charge, quickly conducting the charge away and avoiding the formation of a "virtual gate".

[0039] A high-quality compound semiconductor insertion layer 14 and a high-quality p-GaN layer are deposited on top of the p-GaN layer by MOCVD. Finally, a metal layer is grown on the p-GaN layer by electron beam evaporation. A dielectric layer 17 is grown on the surface of the metal layer by LPCVD. The dielectric layer 17 serves as a mask for dry etching. The dielectric layer 17 is usually made of SiO2 dielectric with a thickness of 200 nm. This dielectric has low cost and good performance as a mask for dry etching.

[0040] like Figure 1 , Figure 2 A photoresist layer is coated on the surface of dielectric layer 17, and a pattern is defined on the photoresist layer by photolithography, such as... Figure 2 Dry etching is used to remove the dielectric layer 17, metal layer, and p-GaN layer in the non-gate region, forming the gate 16 and cap layer 15. The dry etching uses a gas type and flow rate ratio of BCl3:Cl2:Ar = 1:1:1.1, an etching pressure of 3.5 mTorr, and an etching power of 24 W. This etching process, by precisely controlling the plasma power, gas pressure, and gas ratio, adjusts the etching selectivity to stop etching at the surface of the insertion layer 14, obtaining the p-GaN gate structure. This facilitates subsequent precise control of the thickness and cross-sectional length of the active passivation cap layer 13, avoiding over-etching of the cap layer 13 during dry etching, which leads to unsatisfactory passivation effects. This is crucial for improving the dynamic characteristics of the device. After dry etching, the dielectric layer 17 is removed. The cap layer 15 and the gate 16 together constitute the gate of the device, depleting the two-dimensional electron gas beneath it to achieve normally-off characteristics.

[0041] like Figure 3 , Figure 4 A high-quality dielectric layer 18 is grown on the surfaces of the insertion layer 14 and the gate 16 using LPCVD. This dielectric layer 18 serves as a mask for the next step of etching the compound semiconductor insertion layer. A photoresist layer is coated on the surface of the dielectric layer 18, and a pattern is defined on the photoresist layer through photolithography and development steps. The insertion layer 14 in the non-gate region is removed by dry etching. The gas type and flow rate ratio range used is BCl3:Cl2:SF6=1:1:1.2, the etching gas pressure is 3mTorr, and the etching power is 20W. By controlling the dry etching selectivity, the etching stops at the surface of the p-GaN layer. After etching, the photoresist and the dielectric layer 18 are removed.

[0042] like Figure 5 , Figure 6A dielectric layer 19 is deposited on the surface of the GaN layer and the surface of the gate cap metal layer. This dielectric layer serves as a mask for the next step of etching the active passivation structure. A photoresist layer is coated on the surface of the dielectric layer 19, and a pattern is defined on the photoresist layer through photolithography and development steps. A portion of the GaN layer is removed using dry etching to form the cap layer 13. The gas type and flow rate ratio range is BCl3:Cl2:Ar=1:1:1.8, the etching pressure is 3.5 mTorr, and the etching power is 15 W. By controlling the dry etching selectivity, the etching stops on the surface of the insertion layer 20, avoiding the influence of dry etching on the gate-drain barrier layer 12, reducing the device surface states, avoiding etching damage to the AlGaN barrier layer surface, and improving the dynamic performance of the device.

[0043] like Figure 7 A high-quality dielectric layer 23 is deposited on the surfaces of the insertion layer 20, the cap layer 13, and the gate 16. This dielectric layer serves as a mask for fabricating the source and drain of the device and as a passivation medium for the device. Through dielectric passivation, the current collapse effect of the device can be effectively suppressed, and the dynamic performance of the device can be improved.

[0044] Photoresist is coated on the surface of dielectric layer 23, and patterns are defined on the photoresist layer through photolithography and development steps. The dielectric layer and insertion layer 20 of the corresponding regions of the source and drain are removed by dry etching. The source 21 and drain 23 of the device are fabricated by source-drain ohmic alloy process. The source and drain 21 metal adopts a multi-layer metal system. When the source and drain electrodes are thickened with metal, field plate structure and external pin connection are generated at the same time.

[0045] The wafer with thickened source and drain electrode metals is planarized using a dielectric or insulating material. Then, the lead connection board is opened and connected to an external package to obtain the device, thus obtaining a complete HEMT device.

Claims

1. A HEMT device comprising a barrier layer (12), characterized in that, The barrier layer (12) is sequentially provided with a first cap layer (13), a first insertion layer (14), a second cap layer (15) and a gate (16), wherein the first cap layer (13) and the second cap layer (15) are both p-GaN.

2. The HEMT device of claim 1, wherein, The first insertion layer (14) is made of InGaN.

3. The HEMT device of claim 1, wherein, The first insertion layer (14) has a thickness of 10-15 nm.

4. The HEMT device of claim 1, wherein, The first cap layer (13) has a transverse length greater than that of the second cap layer (15).

5. The HEMT device of claim 1, wherein, The gate (16) is provided with a source (21) and a drain (22) connected to the barrier layer, and the distance between the second cap layer (15) and the source (21) is less than the distance between the second cap layer (14) and the drain (22).

6. The HEMT device of claim 1, wherein, The barrier layer (12) and the first cap layer (13) are provided with a second insertion layer (20) for stopping etching.

7. The HEMT device of claim 1, wherein, The second insertion layer (20) is made of AlInN and has a thickness of 1-3 nm.

8. The HEMT device of claim 1, wherein, The HEMT device is provided with a passivation layer (23) made of at least one of Si3N4, SiO2, Sc2O3 and Al2O3.

9. The method of producing a HEMT device according to claim 1, characterized by, The method comprises the following steps: (1) sequentially forming a first p-GaN layer, a first insertion layer and a second p-GaN layer on the surface of the barrier layer, and depositing a metal layer on the surface of the second p-GaN layer; (2) performing first etching to remove the non-gate area of the metal layer and the second p-GaN layer, thereby forming a gate and a second cap layer, wherein the first etching process conditions are as follows: the flow ratio range of BCl3:Cl2:Ar is 1:1:1.1-1.6, the etching gas pressure is 3-4 mTorr, and the etching power is 22-25 W; (3) performing second etching to remove the first insertion layer in the non-corresponding area of the second cap layer, wherein the second etching process conditions are as follows: the flow ratio range of BCl3:Cl2:F is 1:1:1-2, the etching gas pressure is 2.5-3.5 mTorr, and the etching power is 18-22 W; (4) performing third etching / repeating the first etching to remove the first p-GaN layer and form a first cap layer, wherein the third etching process conditions are as follows: the flow ratio range of BCl3:Cl2:Ar is 1:1:1-2.1, the etching gas pressure is 3-4 mTorr, and the etching power is 13-15 W.

10. The production method according to claim 9, characterized by In step (1), a second insertion layer is further formed between the barrier layer and the first p-GaN layer.

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