Semiconductor device structure and preparation method thereof

Abstract

The invention provides a semiconductor device structure and a preparation method thereof, and relates to the technical field of semiconductors, the semiconductor device structure comprises a substrate, a bottom doped region, a drift region, a first doped region and a plurality of mutually independent second doped regions, and the bottom doped region is located in the substrate; the drift region is adjacent to the upper part of the bottom doped region; the first doped region is in contact with the drift region and the bottom doped region, and a first gate connection region is formed at the top of the first doped region; a plurality of mutually independent second doped regions are distributed in the drift region at intervals, and a second gate connection region is formed at the top of each second doped region. Compared with the prior art, the multi-dimensional grid-control electric field is formed by adopting the synergistic effect of the second grid connection region and the bottom doping region which are mutually independent and spaced, the electrostatic control capability on a channel is greatly enhanced, the DIBL effect is effectively inhibited, and the stability and reliability of the device under high working voltage are ensured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor device structure and its fabrication method. Background Technology

[0002] Silicon-based high-voltage normally-on devices (such as depletion-mode MOSFETs / JFETs) are crucial in power management systems, but traditional structures generally suffer from problems such as unadjustable threshold voltage, difficulty in high-voltage turn-off, high noise, and a contradiction between withstand voltage and conduction performance. Under high drain voltage, drain-induced barrier reduction (DIBL) causes pinch-off voltage drift, leading to turn-off failure and degradation of output characteristics. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device structure and a method for fabricating the semiconductor device structure, which can form a multidimensional gate-controlled electric field, greatly enhance the electrostatic control capability of the channel, effectively suppress the DIBL effect, and ensure the stability and reliability of the device under high operating voltage.

[0004] In a first aspect, the present invention provides a semiconductor device structure, comprising: Substrate; The bottom doped region is located within the substrate; A drift region is located within the substrate and adjacent to the top of the bottom doped region; The first doped region is located on one side of the bottom doped region and the drift region along the first direction and is in contact with the drift region and the bottom doped region. A first gate connection region is formed on the top of the first doped region. Multiple independent second doped regions are spaced apart in the drift region along a second direction. A second gate connection region is formed on the top of each second doped region. The second gate connection region and the bottom doped region are respectively located on both sides of the drift region along a direction perpendicular to the substrate. The first direction and the second direction are perpendicular to each other. The first doped region, the second doped region, the first gate connection region, the second gate connection region, and the bottom doped region have the same conductivity type, which is opposite to the conductivity type of the drift region.

[0005] In an alternative embodiment, each of the second doped regions extends toward the bottom doped region in a direction perpendicular to the substrate.

[0006] In an optional embodiment, each of the second doped regions extends through the drift region in a direction perpendicular to the substrate and is connected to the bottom doped region; and / or, each of the second doped regions is spaced apart from the bottom doped region in a direction perpendicular to the substrate.

[0007] In an optional embodiment, an adjustment doped region is formed between adjacent second gate connection regions, the adjustment doped region has the same conductivity type as the drift region, and the adjustment doped region has a higher doping concentration than the drift region.

[0008] In an optional embodiment, the second gate connection region and the adjustment doped region have the same doping depth along a direction perpendicular to the substrate.

[0009] In an optional embodiment, a distance between adjacent second gate connection regions is between 0.5 μm and 1.5 μm, and a width of each second gate connection region along a direction perpendicular to the arrangement direction is between 0.5 μm and 2 μm.

[0010] In an optional embodiment, the semiconductor device structure further comprises: a third doped region located on a side of the drift region and the bottom doped region away from the first doped region, and in contact with the drift region and the bottom doped region; a source region and a drain region located on two sides of the second gate connection region along the first direction and spaced apart from the second gate connection region, the source region being located on a top of the drift region and exposing a top surface, and the drain region being located on a top of the third doped region and exposing a top surface.

[0011] In an optional embodiment, the semiconductor device structure further comprises: a first isolation structure located between the source region and the second gate connection region; a second isolation structure located between the source region and the first gate connection region; a third isolation structure located in the substrate and surrounding the first doped region, the third doped region, and the drift region.

[0012] In an optional embodiment, the substrate comprises: a bottom silicon layer; a buried oxygen layer located on the bottom silicon layer and below the bottom doped region, the first doped region, and the third doped region, the third isolation structure being connected to the buried oxygen layer; a top silicon layer located on the buried oxygen layer, the bottom doped region being located in the top silicon layer.

[0013] In a second aspect, the present application provides a method for manufacturing a semiconductor device structure, comprising: providing a substrate; forming a bottom doped region in the substrate; forming a drift region above the bottom doped region in the substrate; a first doped region is formed on one side of the bottom doped region and the drift region along a first direction, the first doped region being in contact with the drift region and the bottom doped region; a plurality of second doped regions are formed in the drift region, the plurality of second doped regions being spaced apart in the drift region along a second direction, the first direction being perpendicular to the second direction; a first gate connection region is formed on top of the first doped region, and a second gate connection region is formed on top of each of the second doped regions, the second gate connection region being located on two sides of the drift region along a direction perpendicular to the substrate, respectively, with respect to the bottom doped region; wherein the first doped region, the second doped regions, the first gate connection region, the second gate connection region and the bottom doped region have the same conductivity type, and the conductivity type of the drift region is opposite to that of the first doped region, the second doped regions, the first gate connection region, the second gate connection region and the bottom doped region.

[0014] The beneficial effects of the embodiments of the present application include: The semiconductor device structure and the preparation method thereof provided by the embodiments of the present application form a bottom doped region in a substrate, form a drift region above the bottom doped region, form a first doped region on one side of the bottom doped region and the drift region along a first direction, wherein the first doped region is in contact with the drift region and the bottom doped region, and a first gate connection region is formed on top of the first doped region. A plurality of second doped regions are spaced apart in the drift region along a second direction, and a second gate connection region is formed on top of each of the second doped regions, the second gate connection region being located on two sides of the drift region along a direction perpendicular to the substrate, respectively, with respect to the bottom doped region, wherein the first doped region, the second doped regions, the first gate connection region, the second gate connection region and the bottom doped region have the same conductivity type, and the conductivity type of the drift region is opposite to that of the first doped region, the second doped regions, the first gate connection region, the second gate connection region and the bottom doped region.

[0015] Compared with the prior art, the semiconductor device structure provided by the embodiments of the present application uses the synergistic effect of the second gate connection regions and the bottom doped region which are independent and spaced apart from each other, forms a multi-dimensional gate-controlled electric field, greatly enhances the electrostatic control ability of the channel, effectively suppresses the DIBL effect, ensures the stability and reliability of the device under high working voltage, and realizes the same of high performance and process compatibility. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0017] Figure 1A first semiconductor device structure schematic diagram provided by an embodiment of the present application is shown in FIG. 1. Figure 2 A second semiconductor device structure schematic diagram provided by an embodiment of the present application is shown in FIG. 2. Figure 1 A cross-sectional schematic diagram at A-A in the semiconductor device structure provided by an embodiment of the present application is shown in FIG. 3. Figure 3 A third semiconductor device structure schematic diagram provided by an embodiment of the present application is shown in FIG. 4. Figure 4 A parameter comparison schematic diagram of short channel length and long channel length in the channel length direction of the semiconductor device structure provided by an embodiment of the present application is shown in FIG. 5. Figure 5 A parameter comparison schematic diagram of wide channel width and narrow channel width in the semiconductor device structure provided by an embodiment of the present application is shown in FIG. 6. Figure 6 A parameter comparison schematic diagram of having an adjustment doping region and not having an adjustment doping region in the semiconductor device structure provided by an embodiment of the present application is shown in FIG. 7. Figure 7 A fourth semiconductor device structure schematic diagram provided by an embodiment of the present application is shown in FIG. 8. Figure 8 A parameter comparison schematic diagram of deep channel depth and shallow channel depth in the third semiconductor device structure provided by an embodiment of the present application is shown in FIG. 9.

[0018] Legend: 100-semiconductor device structure; 110-substrate; 111-bottom silicon layer; 112-buried oxygen layer; 113-top silicon layer; 120-bottom doping region; 130-drift region; 131-first isolation structure; 132-second isolation structure; 133-third isolation structure; 140-first doping region; 141-first gate connection region; 150-second doping region; 151-second gate connection region; 152-adjustment doping region; 160-third doping region; 170-source region; 180-drain region. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts are within the scope of protection of the present application.

[0021] It should be noted that like reference numerals and characters refer to like elements throughout the following figures and description, and thus, once certain terminologies are defined in one figure, they do not need to be further defined and explained in the subsequent figures.

[0022] In the description of the present application, it should be noted that if the terms "upper", "lower", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the present application is usually placed, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0023] In addition, if the terms "first", "second" and the like appear, they are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0024] It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0025] The semiconductor device structure provided by the embodiments of the present application can form a multi-dimensional gate-controlled electric field, greatly enhancing the electrostatic control ability of the channel, effectively suppressing the DIBL effect, and ensuring the stability and reliability of the device under high operating voltage.

[0026] Referring to Figure 1 and Figure 2 The semiconductor device structure 100 provided by the embodiments of the present application can include a substrate 110, a bottom doped region 120, a drift region 130, a first doped region 140 and a plurality of mutually independent second doped regions 150. The bottom doped region 120 is located in the substrate 110. The drift region 130 is located in the substrate 110 and adjoins above the bottom doped region 120. The first doped region 140 is located on one side of the bottom doped region 120 and the drift region 130 along a first direction and contacts the drift region 130 and the bottom doped region 120, and a top of the first doped region 140 is formed with a first gate connection region 141. The plurality of mutually independent second doped regions 150 are spaced apart in the drift region 130 along a second direction, and a top of each second doped region 150 is formed with a second gate connection region 151. The second gate connection region 151 and the bottom doped region 120 are located on two sides of the drift region 130 along a direction perpendicular to the substrate 110, respectively. The first direction and the second direction are perpendicular to each other and are parallel to the substrate 110.

[0027] Among them, the first doped region 140, the second doped region 150, the first gate connection region 141, the second gate connection region 151 and the bottom doped region 120 have the same conductivity type and are opposite to the conductivity type of the drift region 130.

[0028] It should be noted that the semiconductor device structure 100 can be a threshold-adjustable lateral JFET structure based on the SOI substrate 110, where the first doped region 140, the second doped region 150, the first gate connection region 141, the second gate connection region 151, and the bottom doped region 120 are all P-type doped regions. The first doped region 140 and the second doped region 150 are both P-well regions, and the first gate connection region 141 and the second gate connection region 151 are heavily doped regions. The drift region 130 is an N-type doped region and can form an electrically conductive channel between the second gate connection regions 151. The first gate connection region 141 can control the overall pinch-off of the channel through reverse bias. The multiple second gate connection regions 151 spaced apart and independently designed in the drift region 130 can form a multi-dimensional gate-controlled electric field in cooperation with the bottom doped region 120, greatly enhancing the electrostatic control ability of the channel, effectively suppressing the DIBL effect, and ensuring the stability and reliability of the device under high operating voltage.

[0029] Further, the semiconductor device structure 100 further includes a third doped region 160, a source region 170, and a drain region 180. The third doped region 160 is located on a side of the bottom doped region 120 and the drift region 130 away from the first doped region 140 and in contact with the drift region 130 and the bottom doped region 120. The source region 170 and the drain region 180 are located on both sides of the second gate connection region 151 along the first direction and are spaced apart from the second gate connection region 151. The source region 170 is located on the top of the drift region 130 and exposes the top surface, and the drain region 180 is located on the top of the third doped region 160 and exposes the top surface. The third doped region 160, the source region 170, and the drain region 180 are all N-type doped regions, and the third doped region 160 is an N-well region. The source region 170 and the drain region 180 are both heavily doped N-type doped regions. The source region 170 and the drain region 180 are connected to a source electrode and a drain electrode respectively, and the source electrode is connected to the drain electrode through the channel. The first gate electrode is connected to the first gate connection region 141, and the second gate electrode is connected to the second gate connection region 151. The first gate electrode can control the overall pinch-off of the channel through reverse bias.

[0030] It should be noted that the substrate 110 in the embodiment of the present application can be a P-type SOI substrate 110. Further, the substrate 110 can include a bottom silicon layer 111, a buried oxygen layer 112, and a top silicon layer 113. The buried oxygen layer 112 is located on the bottom silicon layer 111 and below the bottom doped region 120, the first doped region 140, and the third doped region 160. The top silicon layer 113 is located on the buried oxygen layer 112, and the bottom doped region 120 is located in the top silicon layer 113.

[0031] Further, the semiconductor device structure 100 can further include a first isolation structure 131, a second isolation structure 132 and a third isolation structure 133. The first isolation structure 131 is located between the source region 170 and the second gate connection region 151. The second isolation structure 132 is located between the source region 170 and the first gate connection region 141.

[0032] The first isolation structure 131 and the second isolation structure 132 can be shallow trench isolation (STI) structures, which can be formed by photolithography, etching, oxide filling and chemical mechanical polishing (CMP) processes, and define the boundary of the source region 170. The second isolation structure 132 can prevent the source region 170 from shorting with the first doped region 140, and define the boundary of the source region 170, i.e., the source region 170 is limited between the first isolation structure 131 and the second isolation structure 132. The third isolation structure 133 is located in the substrate 110 and can be connected to the buried oxide layer 112, and the third isolation structure 133 surrounds the first doped region 140, the third doped region 160 and the drift region 130. The third isolation structure 133 can be a deep trench isolation (DTI) structure, which is formed by photolithography, deep reactive ion etching (DRIE), dielectric filling and planarization processes to form an isolation ring around the device, and the isolation ring extends to the buried oxide layer 112 or the bottom silicon layer 111 to achieve electrical isolation of the device.

[0033] In some embodiments, each second doped region 150 extends towards the bottom doped region 120 along a direction perpendicular to the substrate 110.

[0034] Specifically, the plurality of second doped regions 150 are arranged at intervals along the second direction, and the implantation depth of the second doped regions 150 is controllable, thereby controlling the extension distance of the second doped regions 150 towards the bottom doped region 120.

[0035] It should be noted that the bottom doped region 120, the drift region 130, the first doped region 140, the second doped region 150, the third doped region 160, the first gate connection region 141, the second gate connection region 151, the source region 170 and the drain region 180 in the embodiment can be formed by an ion implantation process.

[0036] In some embodiments, each second doped region 150 extends through the drift region 130 along a direction perpendicular to the substrate 110 and is connected to the bottom doped region 120.

[0037] Specifically, the second doped region 150 is connected with the bottom doped region 120, and when turned on, the channel between the adjacent second gate connection regions 151 in the drift region 130 serves as a low-resistance path, and the second gate connection regions 151 provide distributed gate control at this time; when turned off, the second gate connection regions 151 and the bottom doped region 120 can form a depletion region and jointly deplete the channel. In the manufacturing stage, by controlling the energy and dose of ion implantation, the physical junction depth of the second doped region 150 can be accurately set, so that the second doped region 150 is electrically connected with the bottom doped region 120.

[0038] Referring to Figure 3 In some embodiments, an adjusting doped region 152 is formed between the adjacent second gate connection regions 151, the adjusting doped region 152 has the same conductivity type as the drift region 130, and the doping concentration of the adjusting doped region 152 is greater than the doping concentration of the drift region 130.

[0039] Specifically, the adjusting doped region 152 is an N-type doped region, and N-type impurities can be implanted in the channel between the second gate connection regions 151 by an ion implantation process, so as to accurately adjust the original threshold voltage of the device.

[0040] Further, along the direction perpendicular to the substrate 110, the doping depth of the second gate connection region 151 is the same as that of the adjusting doped region 152, so as to effectively avoid the influence of the adjusting doped region 152 on the normal on-off of the channel.

[0041] Please continue to refer to Figure 1 Or Figure 3 In some embodiments, the spacing W between the adjacent second gate connection regions 151 along the second direction is between 0.5 μm and 1.5 μm, which can represent the channel width, for example, the spacing W between each adjacent second gate connection region 151 can be any value or a point value between any two of 0.5 μm, 1 μm or 1.5 μm. The width L of the second gate connection region 151 along the first direction is between 0.5 μm and 2 μm, which can represent the channel length, for example, the width L of the second gate connection region 151 along the direction perpendicular to the arrangement direction can be any value or a point value between any two of 0.5 μm, 1 μm or 2 μm.

[0042] Referring to Figures 4 to 6 Wherein, Figure 4 The difference between the short channel length and the long channel length in the channel length direction is shown, Figure 5 The difference between the wide channel width and the narrow channel width is shown, Figure 6The difference between the JFET with the adjustment doping region 152 and the JFET without the adjustment doping region 152 is shown, where Id represents the drain current, Vg represents the gate voltage, and Vd represents the drain voltage. The embodiments of the present application adjust the performance of the device by designing the length and width of the channel. The width of the channel in the embodiments of the present application can affect the threshold voltage and the saturation current of the device. The reduction of the width of the channel can cause the threshold voltage to move in the positive direction (for the N-JFET) and reduce the saturation current (Idsat). The specific values and ranges can be set according to specific requirements. In addition, the additional adjustment doping region 152 (Figure 6) can be optionally introduced between the second gate connection regions 151, which can be designed in cooperation with the second gate connection regions 151 to adjust the threshold voltage and the saturation current of the JFET in a very wide range on the basis of improving the short channel effect. Figure 4 ), the threshold voltage and the saturation current of the JFET can be adjusted in a very wide range.

[0043] Referring to Figure 7 and Figure 8 , Figure 8 The difference between the deep channel depth and the shallow channel depth is shown. In other preferred embodiments of the present application, each second doping region 150 is spaced apart from the bottom doping region 120 in the direction perpendicular to the substrate 110. Specifically, the distance D between the second doping region 150 and the bottom doping region 120 can represent the channel depth. The distance between the second doping region 150 and the bottom doping region 120 can further improve the device performance and the design freedom, and increase the adjustable parameter of the channel depth (channel depth) in the vertical dimension to achieve a wider range of performance adjustment.

[0044] The embodiments of the present application also provide a preparation method of the semiconductor device structure 100, which is used for preparing the semiconductor device structure 100 as described in the foregoing embodiments. The method can include the following steps. S1: providing a substrate 110.

[0045] Specifically, the substrate 110 can be a P-type SOI substrate 110.

[0046] Further, the substrate 110 can include a bottom silicon layer 111, a buried oxygen layer 112, and a top silicon layer 113. The buried oxygen layer 112 is located on the bottom silicon layer 111, and the top silicon layer 113 is located on the buried oxygen layer 112.

[0047] It should be noted that after providing the substrate 110, the preparation of the isolation structure can be completed first, and the third isolation structure 133 is formed first, i.e., a deep trench isolation structure (DTI) is formed. Through photolithography, deep reactive ion etching (DRIE), dielectric filling and planarization processes, an isolation ring is formed in the periphery of the device, which extends into the buried oxygen layer 112 or the bottom silicon layer 111 to realize electrical isolation of the device. Then the first isolation structure 131 and the second isolation structure 132 are formed, i.e., a shallow trench isolation structure (STI) is formed. Through photolithography, etching, oxide filling and chemical mechanical polishing (CMP) processes, the boundary of the active region 170 is defined.

[0048] S2: Forming a bottom doped region 120 in the substrate 110.

[0049] Specifically, a high-energy ion implantation process can be used to implant P-type impurities into the bottom region of the top silicon or the interface between the top silicon and the buried oxygen layer 112 to form the bottom doped region 120, i.e., a P-type buried layer.

[0050] S3: Forming a drift region 130 in the substrate 110, adjacent to the top of the bottom doped region 120.

[0051] Specifically, an ion implantation process is used to form an N-type doped drift region 130 above the bottom doped region 120.

[0052] S4: Forming a first doped region 140 on one side of the bottom doped region 120 and the drift region 130, the first doped region 140 being in contact with the drift region 130 and the bottom doped region 120.

[0053] Specifically, a first doped region 140 is formed in the active region 170 by an ion implantation process, and the first doped region 140 is a P-type well region.

[0054] S5: Forming a plurality of second doped regions 150 in the drift region 130, the plurality of second doped regions 150 being spaced apart in the drift region 130 in a direction parallel to the substrate 110.

[0055] Specifically, a plurality of second doped regions 150 are formed in the drift region 130 by an ion implantation process, and the second doped regions 150 are also P-type well regions.

[0056] It should be noted that steps S4 and S5 can be performed together, and the distance between the second doped region 150 and the bottom doped region 120 can be controlled by precisely controlling the ion implantation depth of the second doped region 150.

[0057] S6: Forming a first gate connection region 141 on top of the first doped region 140 and a second gate connection region 151 on top of the second doped region 150, the second gate connection region 151 and the bottom doped region 120 are respectively located on both sides of the drift region 130 along the direction perpendicular to the substrate 110.

[0058] Specifically, the heavily doped P-type first gate connection region 141 and the second gate connection region 151 are formed by ion implantation process. After the step of forming the first gate connection region 141 and the second gate connection region 151, a gate dielectric layer and a gate electrode material layer are deposited, and the first gate and the arrayed second gate structure are formed by one-time photolithography and etching process.

[0059] Optionally, after the preparation of the second gate connection region 151 is completed, N-type impurities can be introduced into the channel region between the second gate connection regions 151 by ion implantation process for accurate adjustment of the original threshold voltage of the device.

[0060] S7: Forming a source region 170 and a drain region 180.

[0061] Specifically, the third doped region 160 is first formed by ion implantation process, and then the heavily doped N-type source region 170 is formed between the first isolation structure 131 and the second isolation structure 132 by ion implantation, and the heavily doped N-type drain region 180 is formed on top of the third doped region 160.

[0062] After the preparation of the source region 170 and the drain region 180 is completed, subsequent processes can be performed, such as side wall formation, contact hole etching, metallization, and multi-layer interconnection, etc. standard back-end-of-line processes to complete the manufacturing of devices and circuits. Among them, the first doped region 140, the second doped region 150, the first gate connection region 141, the second gate connection region 151 and the bottom doped region 120 have the same conductivity type, and the conductivity type is opposite to that of the drift region 130.

[0063] In summary, the semiconductor device structure and the preparation method thereof provided by the embodiment of the present application form a bottom doped region 120 in a substrate 110, form a drift region 130 above the bottom doped region 120, and form a first doped region 140 on one side of the bottom doped region 120 and the drift region 130, wherein the first doped region 140 is in contact with the drift region 130 and the bottom doped region 120, and a top of the first doped region 140 is formed with a first gate connection region 141. A plurality of second doped regions 150 which are independent of each other are distributed in the drift region 130 along a direction parallel to the substrate 110, a top of each second doped region 150 is formed with a second gate connection region 151, and the second gate connection region 151 and the bottom doped region 120 are respectively located on two sides of the drift region 130 along a direction perpendicular to the substrate 110, wherein the first doped region 140, the second doped region 150, the first gate connection region 141, the second gate connection region 151 and the bottom doped region 120 have the same conductivity type, and the drift region 130 has an opposite conductivity type. Compared with the prior art, the semiconductor device structure 100 provided by the embodiment of the present application uses the synergistic effect of the second gate connection region 151 which is independent of each other and spaced apart and the bottom doped region 120 to form a multi-dimensional gate-controlled electric field, greatly enhances the electrostatic control ability of the channel, effectively suppresses the DIBL effect, ensures the stability and reliability of the device under high working voltage, and realizes the same of high performance and process compatibility.

[0064] The above merely describes the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device structure, characterized in that, include: Substrate; The bottom doped region is located within the substrate; A drift region is located within the substrate and adjacent to the top of the bottom doped region; The first doped region is located on one side of the bottom doped region and the drift region along the first direction and is in contact with the drift region and the bottom doped region. A first gate connection region is formed on the top of the first doped region. Multiple independent second doped regions are spaced apart in the drift region along a second direction. A second gate connection region is formed on the top of each second doped region. The second gate connection region and the bottom doped region are respectively located on both sides of the drift region along a direction perpendicular to the substrate. The first direction and the second direction are perpendicular to each other. The first doped region, the second doped region, the first gate connection region, the second gate connection region, and the bottom doped region have the same conductivity type, which is opposite to the conductivity type of the drift region.

2. The semiconductor device structure according to claim 1, characterized in that, Each of the second doped regions extends toward the bottom doped region in a direction perpendicular to the substrate.

3. The semiconductor device structure according to claim 2, characterized in that, Each of the second doped regions extends through the drift region in a direction perpendicular to the substrate and is connected to the bottom doped region; and / or, each of the second doped regions is spaced apart from the bottom doped region in a direction perpendicular to the substrate.

4. The semiconductor device structure according to claim 1, characterized in that, An adjustment doping region is formed between adjacent second gate connection regions. The conductivity type of the adjustment doping region is the same as that of the drift region, and the doping concentration of the adjustment doping region is greater than that of the drift region.

5. The semiconductor device structure according to claim 4, characterized in that, Along the direction perpendicular to the substrate, the second gate connection region has the same doping depth as the adjusted doping region.

6. The semiconductor device structure according to claim 1, characterized in that, The spacing between adjacent second gate connection regions along the second direction is between 0.5μm and 1.5μm, and the width of each second gate connection region along the first direction is between 0.5μm and 2μm.

7. The semiconductor device structure according to claim 1, characterized in that, The semiconductor device structure also includes: The third doped region is located on the side of the bottom doped region and the drift region away from the first doped region, and is in contact with the drift region and the bottom doped region; The source region and the drain region are located on both sides of the second gate connection region along the first direction and are spaced apart from the second gate connection region. The source region is located on top of the drift region and exposes the top surface. The drain region is located on top of the third doped region and exposes the top surface. The conductivity type of the third doped region, the source region, and the drain region is the same as that of the drift region.

8. The semiconductor device structure according to claim 7, characterized in that, The semiconductor device structure also includes: A first isolation structure is located between the source region and the second gate connection region; A second isolation structure is located between the source region and the first gate connection region; A third isolation structure is located within the substrate and surrounds the first doped region, the third doped region, and the drift region.

9. The semiconductor device structure according to claim 8, characterized in that, The substrate includes: Underlying silicon layer; A buried oxide layer is located on the bottom silicon layer and below the bottom doped region, the first doped region, and the third doped region, and the third isolation structure is connected to the buried oxide layer; The top silicon layer is located on the buried oxide layer, and the bottom doped region and the third isolation structure are both located within the top silicon layer.

10. A method for fabricating a semiconductor device structure, characterized in that, include: Provide a substrate; A bottom doped region is formed within the substrate; A drift region is formed in the substrate adjacent to the bottom doped region; A first doped region is formed on one side of the bottom doped region and the drift region along the first direction, and the first doped region is in contact with the drift region and the bottom doped region; Multiple independent second doped regions are formed within the drift region, and the multiple second doped regions are distributed at intervals along a second direction within the drift region, wherein the first direction and the second direction are perpendicular; A first gate connection region is formed on top of the first doped region, and a second gate connection region is formed on top of the second doped region. The second gate connection region and the bottom doped region are respectively located on both sides of the drift region along the direction perpendicular to the substrate. The first doped region, the second doped region, the first gate connection region, the second gate connection region, and the bottom doped region have the same conductivity type, which is opposite to the conductivity type of the drift region.

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