Integrated circuit (IC)

Abstract

An integrated circuit (IC) includes: a plurality of first layers extending in a first direction and disposed in a second direction perpendicular to the first direction; and a second layer including a first unit layer extending in a third direction intersecting the first direction and the second direction, and a second unit layer connected to the first unit layer and extending in a fourth direction symmetrical to the third direction with respect to the first direction, and the second cell layer is electrically connected to one of the plurality of first layers through a first via in the one first layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0108571, filed on August 13, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to integrated circuits and methods for manufacturing integrated circuits. Background Technology

[0004] Integrated circuits (ICs) that process digital signals can be designed based on standard cells. Functional circuits can be formed by arranging and routing standard cells, enabling the IC to achieve the desired function.

[0005] Meanwhile, with the increasing demand for high performance, high speed, and / or multifunctionality of ICs, the integration density of ICs is also increasing. This trend towards higher IC integration leads to a reduction in the spacing between wiring layers and vias, which decreases process margin. Summary of the Invention

[0006] This disclosure provides an integrated circuit (IC) that can increase process margin.

[0007] This disclosure provides an IC that can reduce process costs.

[0008] An integrated circuit (IC) according to some embodiments includes: a plurality of first layers extending in a first direction and disposed in a second direction perpendicular to the first direction; and a second layer including a first unit layer extending upward in a third direction intersecting the first and second directions, and a second unit layer connected to the first unit layer and extending in a fourth direction symmetrical to the third direction relative to the first direction, the second unit layer being electrically connected to the first layer via a first via located in one of the plurality of first layers.

[0009] According to some embodiments, the IC includes a standard cell comprising: a plurality of cell boundaries extending in a first direction; a first layer extending in the first direction between a first cell boundary and a second cell boundary among the plurality of cell boundaries; and a second layer extending from a first point of the first cell boundary to a second point spaced apart from the first point in the first direction by a first length and located in a second direction perpendicular to the first direction at a second point between the first cell boundary and the second cell boundary, wherein the second layer is symmetrical about the standard cell in the first direction and is located on the first layer.

[0010] The IC according to some embodiments includes: a first standard cell; a second standard cell adjacent to the first standard cell in a first direction; a first layer extending over the first standard cell and the second standard cell in a second direction perpendicular to the first direction; and a second layer including a plurality of first cell layers over the first layer on the first standard cell and the second standard cell and extending in a third direction between the first direction and the second direction, and a plurality of second cell layers symmetrical to the plurality of first cell layers in the second direction and disposed alternately with the plurality of first cell layers in the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a cross-sectional view of an integrated circuit (IC) according to some embodiments.

[0012] Figure 2 is a layout view of a partial region of an IC according to some embodiments.

[0013] Figure 3 is a cross-sectional view of the IC taken along a line A-A' of Figure 2 .

[0014] Figure 4 is a cross-sectional view of the IC taken along a line B-B' of Figure 2 .

[0015] Figure 5 is a layout view of an IC according to some embodiments.

[0016] Figure 6 is a layout view of a standard cell and a layer on the standard cell according to some embodiments.

[0017] Figure 7 is a layout view of a standard cell and a layer on the standard cell according to some embodiments.

[0018] Figure 8 is a layout view of a partial region of an IC according to some embodiments.

[0019] Figure 9 is a layout view of a partial region of an IC according to a comparative example.

[0020] Figure 10 is a layout view of a partial region of an IC according to some embodiments.

[0021] Figure 11 is a layout view of a standard cell and a layer in the standard cell according to some embodiments.

[0022] Figure 12 is a flowchart for explaining a method of designing and manufacturing an IC according to an embodiment.

[0023] Figure 13 is a diagram schematically illustrating a design system of an IC according to some embodiments. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described in greater detail with reference to the accompanying drawings. In the drawings, like reference numerals are used for the same components and redundant descriptions of the same components are omitted.

[0025] It should be understood that the embodiments described herein are intended to implement various features of the present disclosure. These are merely examples and are not limiting. For example, the dimensions of components are not limited to the disclosed ranges or values and can vary depending on the process conditions and / or the properties of the desired device. For example, forming a first structure over or on a second structure in the following description can include embodiments in which the first structure and the second structure are formed in direct contact, and can also include embodiments in which an additional structure can be formed between the first structure and the second structure such that the first structure and the second structure can not be in direct contact. For simplicity and clarity, various structures can be arbitrarily drawn in different scales.

[0026] In addition, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and the like can be used herein to describe one element or describe the relationship between a structure and another element or structure as shown in the drawings.

[0027] In addition, ordinal numbers such as "first," "second," "third," and the like can be used as a label to distinguish a particular element, step, direction, and the like from another element, step, direction, and the like. A term described in the specification without "first," "second," and the like can still be referred to as "first" or "second" in the claims. In addition, a term referred to by a particular ordinal number (for example, "first" in a particular claim) can be described elsewhere with a different ordinal number (for example, "second" in the specification or another claim).

[0028] The terms "comprise," "include," "contain," and / or "comprising," "including," "containing," and / or "comprises" when used herein, indicate the presence of the stated element but do not preclude the presence of additional elements.

[0029] The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] The term "connected" can be used herein to refer to physical and / or electrical connections.

[0031] In addition, in order to clearly illustrate the present disclosure in the drawings, components irrelevant to the description are omitted, and similar parts are given similar reference numerals throughout the specification. In the flowchart described with reference to the drawings, the order of operations can be changed, several operations can be combined, a specific operation can be divided, and a specific operation can not be performed.

[0032] Furthermore, expressions described in the singular can encompass the singular or plural, unless otherwise expressly stated, such as "a" or "an". Terms such as first, second, etc. can be used to describe various components, but these components should not be limited by these terms. These terms can be used for the purpose of distinguishing one component from another.

[0033] Figure 1 is a cross-sectional view of an integrated circuit (IC) 100 according to some embodiments.

[0034] In some embodiments, the IC 100 can include a front-end-of-line (FEOL) region 110 and a back-end-of-line (BEOL) region 120. Specifically, the FEOL region 110 can correspond to a region including various layers and patterns required for functions of active semiconductor devices (i.e., transistors for transmitting / handling signals) in the IC 100, and the BEOL region 120 can correspond to a region including wiring layers electrically connecting the semiconductor devices.

[0035] Referring to Figure 1 , the FEOL region 110 can include a substrate 10. The substrate 10 can be a P-type substrate. Alternatively, the substrate 10 can be an N-type substrate.

[0036] The FEOL region 110 can include an active region 20 formed on the substrate 10 and a source / drain region 21 formed on the active region 20. The FEOL region 110 can further include a gate structure 31 located between the source / drain regions 21. The source / drain regions 21 and the gate structure 31 can form a transistor.

[0037] The FEOL region 110 can include an insulating layer 30 disposed on the active region 20 and a contact layer 33 disposed on the insulating layer 30. The contact layer 33 can electrically contact the source / drain regions 21. The contact layer 33 can connect the source / drain regions 21 to a via member V0. The source / drain regions 21 can be connected to the via members V0, V1, V2, V3, and V4 and the wiring layers M1, M2, M3, M4, and M5 in the BEOL region 120 through the contact layer 33. The integrated circuit 100 can further include the via member V0 connected to the gate structure 31.

[0038] A BEOL region 120 may be formed above the FEOL region 110. The BEOL region 120 electrically connects to the semiconductor devices within the IC 100 to allow the IC 100 to operate. Specifically, the IC 100 includes multiple insulating layers 40, 50, 60, 70, and 80, with vias V0, V1, V2, V3, and V4 formed in the insulating layers 40, 50, 60, 70, and 80, respectively, and wiring layers M1, M2, M3, M4, and M5. Each of the vias V0, V1, V2, V3, and V4 connects the wiring layers M1, M2, M3, M4, and M5 located on different layers to each other, and connects the contact layer 33 to the wiring layers M1, M2, M3, M4, and M5. The wiring layers M1, M2, M3, M4, and M5 may intersect and extend to each other. For example, the first wiring layer M1 in insulating layer 40 may extend in a first direction, and the second wiring layer M2 in insulating layer 50 may extend in a second direction intersecting the first direction. The third wiring layer M3 in insulating layer 60 may extend in the first direction, and the fourth wiring layer M4 in insulating layer 70 may extend in the second direction. The first wiring layer M1 and the third wiring layer M3 extending in the first direction may each be referred to as horizontal layers, and the second wiring layer M2 and the fourth wiring layer M4 extending in the second direction may each be referred to as vertical layers. Each of the wiring layers M1, M2, M3, M4, and M5, which are conductive layers, may be referred to as a metal layer. In the following text, for ease of description, wiring layers will be referred to as layers.

[0039] Furthermore, the construction of IC 100 according to some embodiments is not limited thereto. For example, IC 100 may also include additional layers between layers, may not include some of the aforementioned layers, may include additional structures formed in each layer, or may not include some of the structures formed in each of the aforementioned layers. In addition, IC 100 may include more upper layers (not shown, such as M6, M7, etc., located on M5). Detailed descriptions of the materials of each structure and the methods of forming each structure are omitted herein.

[0040] Figure 2 This is a layout diagram of a portion of IC 200 according to some embodiments. Figure 3 It is along Figure 2 The cross-sectional view of IC 300 taken by line A-A'. Figure 4 It is along Figure 2 The cross-sectional view of IC 400 taken from line B-B'.

[0041] Specifically, Figure 2 It is shown that in the setting of IC ( Figure 1 A layout diagram of two layers stacked adjacent to each other among multiple routing layers on a 100). For example, the first layer LAYER 1 may correspond to Figure 1The first wiring layer M1, and the second layer LAYER 2 can correspond to Figure 1 The second wiring layer M2 stacked adjacent to the first wiring layer M1, but the disclosure is not limited thereto.

[0042] Referring to Figure 2 , the IC 200 can extend in a first direction (e.g., an X direction), and include a plurality of first layers LAYER 1 disposed in a second direction (e.g., a Y direction) perpendicular to the first direction. The plurality of first layers LAYER 1 can be parallel to each other. The plurality of first layers LAYER 1 can extend in the first direction (X), and can be arranged in the second direction (Y). For example, the first layers LAYER 1 can be relatively continuously distributed or disposed in or along the second direction Y (e.g., as shown in FIG. 2A). Figure 2 In some embodiments, the first layers LAYER 1 can have a first width W1. Here, the width of the first layers LAYER 1 can refer to the width of the first layers LAYER 1 in the second direction Y. Further, the plurality of first layers LAYER 1 can repeat in the second direction Y by every first length S1.

[0043] In some embodiments, the IC 200 can include a plurality of second layers LAYER 2 stacked on the first layers LAYER 1 in a vertical direction (e.g., a Z direction). In some embodiments, the second layers LAYER 2 can have a second width W2. Here, the width of the second layers LAYER 2 can refer to the width of the second layers LAYER 2 in the first direction X. Further, the plurality of second layers LAYER 2 adjacent in the first direction X can repeat in the first direction X by every second length S2. Here, the first width W1 and the second width W2 can be different from each other, and the first length S1 and the second length S2 can be different from each other. For example, the second width W2 can be greater than the first width W1, and the second length S2 can be greater than the first length S1, but the disclosure is not limited thereto. Further, the first width W1 can be less than the first length S1, and the second width W2 can be less than the second length S2.

[0044] In some embodiments, the second layers LAYER 2 can include a plurality of unit layers. For example, the second layers LAYER 2 can include first unit layers 210 and second unit layers 220. The second layers LAYER 2 can be layers extending in the second direction Y by alternately arranging the first unit layers 210 and the second unit layers 220 in the second direction Y (e.g., alternately continuously distributing the first unit layers 210 and the second unit layers 220 in the second direction Y). The first unit layers 210 and the second unit layers 220 can contact each other and be electrically connected to each other in the second direction Y.

[0045] In some embodiments, each of the first unit layer 210 and the second unit layer 220 can extend along the second direction Y in a range of a second length S2 in the first direction X. For ease of description, Figure 2 The first vertical line 231 and the second vertical line 233 are shown to extend along the second direction Y at a minimum value Xmin and a maximum value Xmax in the coordinate value in the first direction X of each of the first unit layer 210 and the second unit layer 220. Specifically, the first vertical line 231 and the second vertical line 233 can be spaced apart by the second length S2 in the first direction X, in which the first vertical line 231 extends along the second direction Y at the minimum value Xmin in the coordinate value in the first direction X of each of the first unit layer 210 and the second unit layer 220, and the second vertical line 233 extends along the second direction Y at the maximum value Xmax in the coordinate value in the first direction X of each of the first unit layer 210 and the second unit layer 220.

[0046] In some embodiments, each of the first vertical line 231 and the second vertical line 233 can correspond to a gate line of a transistor. That is, the second length S2 between the first vertical line 231 and the second vertical line 233 can be equal to 1 contacted poly pitch (cpp). However, the disclosure is not limited thereto. In other embodiments, the length of each unit layer in the first direction X can be greater than or less than 1 cpp.

[0047] In some embodiments, each of the first unit layer 210 and the second unit layer 220 can extend in different directions with respect to the reference line R. Specifically, the first unit layer 210 positioned along the second direction Y from the reference line R can extend along a fourth direction D1 intersecting each of the first direction X and the second direction Y. Here, the fourth direction D1 can refer to a direction tilted by a certain angle θ from the first direction X toward the second direction Y, and the certain angle θ can be, for example, 0° to 90°, but is not limited thereto. The second unit layer 220 positioned along a direction -Y opposite to the second direction Y from the reference line R can extend along a fifth direction D2 intersecting each of the first direction X and the direction -Y. Here, the fifth direction D2 can refer to a direction tilted by a certain angle θ from the first direction X toward the direction -Y opposite to the second direction Y, and the certain angle θ can be, for example, 0° to 90°, but is not limited thereto. The fourth direction D1 and the fifth direction D2 can be symmetrical to each other along the first direction X. The first unit layer 210 and the second unit layer 220 can be symmetrical to each other with respect to the reference line R extending along the first direction X.

[0048] In some embodiments, the lower surface 211 of the first cell layer 210 can be in contact with the reference line R, and the upper surface 221 of the second cell layer 220 can be in contact with the reference line R. The lower surface 211 of the first cell layer 210 and the upper surface 221 of the second cell layer 220 can be in contact with each other, so the first cell layer 210 and the second cell layer 220 can be electrically connected to each other. Meanwhile, the reference line R can be repeated every certain length along the second direction Y. The lengths of the first cell layer 210 and the second cell layer 220 in the second direction Y can be equal to half of the interval between the reference lines R adjacent to each other in the second direction Y. In some embodiments, the reference line R can correspond to a row described below. It will be referred to Figure 5 The row is described in detail.

[0049] In some embodiments, the first layer LAYER 1 and the second layer LAYER 2 can be connected to each other by a via member VIA. Each of the first layer LAYER 1, the second layer LAYER 2, and the via member VIA can be formed of a metal, a conductive metal nitride, a metal silicide, or a combination thereof, but is not limited thereto. It will be referred to Figure 2 The first layer LAYER 1 and the second layer LAYER 2 can be electrically connected to each other by a first via member VA, a second via member VB, and a third via member VC. The first via member VA, the second via member VB, and the third via member VC can be spaced apart from each other in the first direction X and / or the second direction Y. For example, the first via member VA and the third via member VC can be spaced apart by a first interval 201, the first via member VA and the second via member VB can be spaced apart by a second interval 202, and the second via member VB and the third via member VC can be spaced apart by a third interval 203. The first interval 201, the second interval 202, and the third interval 203 can be the same as or different from each other. According to some embodiments, the second layer LAYER 2 is disposed on the first layer LAYER 1 extending in the first direction X by extending in a fourth direction D1 inclined by an angle θ from the first direction X or extending in a fifth direction D2 inclined by an angle -θ from the first direction X, and thus the first interval 201, the second interval 202, and the third interval 203 of the first via member VA, the second via member VB, and the third via member VC can be increased. Accordingly, there is an advantage in that a process margin is increased and a process cost is reduced.

[0050] In some embodiments, the first via part VA and the third via part VC can be adjacent to each other in the second direction Y. That is, the first via part VA and the third via part VC can be electrically connected to one second layer LAYER 2 extending in the second direction Y, and any via part connected to one second layer LAYER 2 can not be positioned between the first via part VA and the third via part VC in the second direction Y. According to embodiments, the positions of the first via part VA and the third via part VC in the first direction X can be different according to the structure of the second layer LAYER 2. The difference in the positions of the first via part VA and the third via part VC adjacent to each other in the second direction Y in the first direction X can be the same as the third length GA. In this regard, the following will be described with reference to Figure 3 and Figure 4 .

[0051] Referring to Figure 3 (a cross-sectional view along a line A-A' of Figure 2 ), the IC 300 can include a FEOL region 310 and a plurality of insulating layers 320 and 330 disposed on the FEOL region 310. The FEOL region 310 can correspond to the FEOL region 110 of Figure 1 , and the plurality of insulating layers 320 and 330 can include a first layer LAYER 1, a second layer LAYER 2, and the like. Detailed descriptions of each of the insulating layers 320 and 330 are omitted herein.

[0052] In some embodiments, the first layer 321 can extend in the first direction X. The first layer 321 can be electrically connected to a second layer 333 through a via part 331 in the insulating layer 330. The plurality of second layers LAYER 2 can be repeated in the first direction X with each second length S2. Meanwhile, the position of the via part 331 in the first direction X can correspond to a coordinate value X1.

[0053] Referring to Figure 4 (a cross-sectional view along a line B-B' of Figure 2 ), the IC 400 can include a FEOL region 410 and a plurality of insulating layers 420 and 430 disposed on the FEOL region 410. In some embodiments, a first layer 421 can extend in the first direction X. The first layer 421 can be electrically connected to a second layer 433 through a via part 431 in the insulating layer 430. The plurality of second layers LAYER 2 can be repeated in the first direction X with each second length S2. Meanwhile, the position of the via part 431 in the first direction X can correspond to a coordinate value X2.

[0054] Referring to Figure 2 and Figure 3 , Figure 3 the via part 331 of Figure 2 corresponds to the first via part VA, and Figure 4 the via part 431 of corresponds toFigure 2 The third via VC. Figure 3 The via 331 and Figure 4 The vias 431 can be adjacent to each other in the second direction Y. Figure 3 The position of the through hole 331 in the first direction X can correspond to the coordinate value X1, and Figure 4 The position of the via 431 in the first direction X can correspond to the coordinate value X2. That is, according to the structure of the second layer 2 in some embodiments, the positions of the vias 331 and 431 that are adjacent to each other in the second direction Y in the first direction X can differ by a third length GA.

[0055] Figure 5 This is a layout diagram of IC 500 according to some embodiments.

[0056] Reference Figure 5 IC 500 may include multiple standard cells SC, each SC comprising a circuit pattern for constructing various circuits. The multiple standard cells SC may have the function of performing various logic functions. In some embodiments, the multiple standard cells SC may include logic devices such as AND, OR, inverters, etc., and memory devices such as latches, flip-flops, etc., or may be one of logic devices and memory devices. Meanwhile, although not shown here, IC 500 may also include physical units, such as padding units.

[0057] A standard element SC may include multiple element boundaries. Specifically, the standard element SC may be defined by multiple element boundaries, and the size of the standard element SC may be determined by these multiple element boundaries. For example, the multiple element boundaries of the first standard element 501 may include multiple element boundaries CB_X1 and CB_X2 in the first direction X and multiple element boundaries CB_Y1 and CB_Y2 in the second direction Y perpendicular to the first direction X. Furthermore, the multiple element boundaries of the second standard element 502 may include multiple element boundaries CB_X3 and CB_X4 in the first direction X and multiple element boundaries CB_Y3 and CB_Y4 in the second direction Y.

[0058] Multiple standard cells SC on IC 500 can be arranged along multiple predetermined rows R1, R2, ..., R7 extending in the first direction X. For example, the multiple cell boundaries CB_X1 and CB_X2 of the first standard cell 501 in the first direction X can be arranged to overlap with the first row R1 and the second row R2 of the multiple rows R1, R2, ..., R7. Alternatively, the multiple cell boundaries CB_X3 and CB_X4 of the second standard cell 502 in the first direction X can be arranged to overlap with the second row R2 and the fourth row R4 of the multiple rows R1, R2, ..., R7.

[0059] The heights of the plurality of standard cells SC in the second direction Y can be the same as or different from each other. Specifically, the heights of the plurality of standard cells SC in the second direction Y can be determined according to intervals between rows in which corresponding standard cells overlap in the plurality of cell boundaries in the first direction X. For example, the height of the first standard cell 501 in the second direction Y can be equal to an interval h between the first row R1 in which the first standard cell 501 overlaps in the cell boundary CB X1 in the first direction X and the second row R2 in which the first standard cell overlaps in the cell boundary CB X2 in the first direction X. Hereinafter, a standard cell can be referred to as a single-row cell. Alternatively, the height of the second standard cell 502 in the second direction Y can be equal to an interval 2h between the second row R2 in which the second standard cell 502 overlaps in the cell boundary CB X3 in the first direction X and the fourth row R4 in which the first standard cell overlaps in the cell boundary CB X4 in the first direction X. Hereinafter, a standard cell can be referred to as a multi-row cell. However, the disclosure is not limited thereto, and a multi-row cell can include a standard cell each having a cell height of 3h or more.

[0060] Figure 5 The IC 500 is shown to include seven rows R1, R2,..., and R7, but this is merely an example, and the IC 500 can include various numbers of rows, and a row can include various numbers of standard cells.

[0061] Figure 6 is a layout diagram of a standard cell 600 and layers on the standard cell 600 according to some embodiments. Specifically, the standard cell 600 can correspond to the standard cell 501 of Figure 5 is a layout diagram of a standard cell 600 and layers on the standard cell 600 according to some embodiments. Specifically, the standard cell 600 can correspond to the standard cell 501 of Figure 6 is a diagram for explaining a structure of a second layer LAYER 2 on the standard cell 600.

[0062] Referring to Figure 6 , the standard cell 600 can include a first cell boundary CB X1 and a second cell boundary CB X2 extending in the first direction X and a cell boundary CB Y1 and CB Y2 extending in the second direction Y. The standard cell 600 can be disposed along the first row R1 and the second row R2. Specifically, among the plurality of cell boundaries CB X1, CB X2, CB Y1, and CB Y2 of the standard cell 600, the first cell boundary CB X1 extending in the first direction X can be disposed to overlap the first row R1, and the second cell boundary CB X2 can be disposed to overlap the second row R2. The standard cell 600 can be a single-row cell.

[0063] The standard cell 600 can include a plurality of first layers LAYER 1 extending in the first direction X. The plurality of first layers LAYER 1 can be located between the first cell boundary CB_X1 and the second cell boundary CB_X2 in the second direction Y. The plurality of first layers LAYER 1 can correspond to pins of the standard cell 600. For example, in the plurality of first layers LAYER 1, a layer 621 can correspond to an input pin of the standard cell 600, and a layer 623 can correspond to an output pin of the standard cell 600, but the present disclosure is not limited thereto.

[0064] The second layer LAYER 2 can be stacked (in the third direction Z) on the first layer LAYER 1. The first layer LAYER 1 and the second layer LAYER 2 can be electrically connected to each other by a via member VIA located between the first layer LAYER 1 and the second layer LAYER 2 in the third direction Z. The second layer LAYER 2 can extend along the second direction Y within a second length S2 in the first direction X. For example, the second layer LAYER 2 can extend between a first vertical line 631 corresponding to a first position in the first direction X and a second vertical line 633 corresponding to a second position in the first direction X. The detailed arrangement method and structure of the second layer LAYER 2 are the same as or similar to those of the second layer LAYER 2 of the standard cell 600, and thus a detailed description thereof is omitted here. Figure 2

[0065] In some embodiments, the second layer LAYER 2 on the standard cell 600 can extend from the first row R1 to the second row R2. The second layer LAYER 2 on the standard cell 600 can extend from the first cell boundary CB_X1 to the second cell boundary CB_X2 of the standard cell 600. The second layer LAYER 2 on the standard cell 600 can be symmetrical in the first direction X. Specifically, the second layer LAYER 2 can be symmetrical with respect to a line 610 between the first row R1 and the second row R2 on which the standard cell 600 is disposed.

[0066] ​In some embodiments, the second layer LAYER 2 on the standard cell 600 can be in contact with a first region 637 of the first cell boundary CB X1 at a first point 635 where the first cell boundary CB X1 intersects the first vertical line 631. Further, the second layer LAYER 2 can be in contact with a second vertical line 633, where the second vertical line 633 is spaced apart from the first vertical line 631 by a second length S2 in the first direction X between the first cell boundary CB X1 and the second cell boundary CB X2. The second layer LAYER 2 can extend from the first point 635 to a second point 639, where the first cell boundary CB X1 intersects the first vertical line 631 at the first point 635, the second point 639 is spaced apart from the first vertical line 631 by the second length S2 in the first direction X and is between the first cell boundary CB X1 and the second cell boundary CB X2. The second layer LAYER 2 can be symmetrical along the first direction X on the standard cell 600.

[0067] The second layer LAYER 2 according to some embodiments can extend in different directions relative to the line 610. For example, the second layer LAYER 2 of the line 610 in the second direction Y can extend in a fifth direction D2 between the first direction X and a direction -Y opposite to the second direction Y. The second layer LAYER 2 of the line 610 in the direction -Y opposite to the second direction Y can extend in a fourth direction D1 between the first direction X and the second direction Y. The line 610 can be in the middle of the first row R1 and the second row R2 in the second direction Y. The first row R1 and the second row R2 can be adjacent to each other in the second direction Y. That is, a length from the first row R1 to the line 610 in the second direction Y can be the same as a length from the second row R2 to the line 610.

[0068] Meanwhile, the second length S2 in the first direction X at which the second layer LAYER 2 extends can be equal to 1 cpp. However, the disclosure is not limited thereto. In some embodiments, the length of each cell layer in the first direction X can be greater or less than 1 cpp.

[0069] Figure 7 is a layout diagram of a standard cell 700 and layers on the standard cell 700 according to some embodiments. Specifically, the standard cell 700 can correspond to the standard cell 502 of Figure 5 and the layers on the standard cell 700. Figure 7 is a diagram for explaining a structure of a second layer LAYER 2 on the standard cell 700.

[0070] Referring to Figure 7The standard cell 700 can include a third cell boundary CB X3 and a fourth cell boundary CB X4 extending in the first direction X and a cell boundary CB Y3 and CB Y4 extending in the second direction Y. The standard cell 700 can be disposed along the first row Rl and the third row R3. Specifically, among the plurality of cell boundaries CB X3, CB X4, CB Y3, and CB Y4 of the standard cell 700, the third cell boundary CB X3 extending in the first direction X can be disposed to overlap the first row Rl, and the fourth cell boundary CB X4 can be disposed to overlap the third row R3. The second row R2 can be disposed between the first row Rl and the third row R3 in the second direction Y. A length from the first row Rl to the second row R2 in the second direction Y can be the same as a length from the third row R3 to the second row R2. The standard cell 700 can be a multi-row cell.

[0071] The standard cell 700 can include a plurality of first layers LAYER 1 extending in the first direction X. The plurality of first layers LAYER 1 can correspond to pins of the standard cell 700. The first layers LAYER 1 located on the standard cell 700 can be similar or identical to the first layers LAYER 1 located on the standard cell 600 of FIG. 6, and thus, a detailed description thereof is omitted herein. Figure 6

[0072] The second layers LAYER 2 can be stacked (in the third direction Z) on the first layers LAYER 1. The first layers LAYER 1 and the second layers LAYER 2 can be electrically connected to each other by a via member VIA. In some embodiments, the second layers LAYER 2 on the standard cell 700 can extend from the first row Rl to the third row R3. The second layers LAYER 2 on the standard cell 700 can extend from the third cell boundary CB X3 to the fourth cell boundary CB X4. The second layers LAYER 2 on the standard cell 700 can be symmetrical in the first direction X. Specifically, the second layers LAYER 2 can be symmetrical about the second row R2 located in the middle of the third cell boundary CB X3 and the fourth cell boundary CB X4.

[0073] In some embodiments, the second row R2 can correspond to a reference line R of the standard cell 600 of FIG. 6. Figure 2 That is, the second layers LAYER 2 can include a first cell layer 721 positioned in the second direction Y with respect to the second row R2 and a second cell layer 723 positioned in a direction -Y opposite the second direction Y. The first cell layer 721 can extend from the second row R2 in a fourth direction Dl between the first direction X and the second direction Y, and the second cell layer 723 can extend in a fifth direction D2 between the first direction X and the direction -Y opposite the second direction Y.

[0074] ​In some embodiments, each of the first unit layer 721 and the second unit layer 723 can have a length in the second direction Y equal to half of a spacing between adjacent rows in the second direction Y. Specifically, the first line 711 can be located in the middle of the first row R1 and the second row R2 in the second direction Y, and the first unit layer 721 can extend from the second row R2 to the first line 711 in the second direction Y. The second line 713 can be located in the middle of the second row R2 and the third row R3 in the second direction Y, and the second unit layer 723 can extend from the second row R2 to the second line 713 in the second direction Y. The first unit layer 721 and the second unit layer 723 can be symmetric to each other with respect to the second row R2, and the first unit layer 721 and the second unit layer 723 can be alternately arranged on the standard cell 700 in the second direction Y. In some embodiments, each of the first unit layer 721 and the second unit layer 723 can have a length in the second direction Y equal to 1 / 4 of a distance between the third cell boundary CB_X3 and the fourth cell boundary CB_X4 extending in the first direction X. On the standard cell 700, each of the first unit layer 721 and the second unit layer 723 can have a length in the second direction Y equal to 1 / 2n (n is a natural number) of the distance between the third cell boundary CB_X3 and the fourth cell boundary CB_X4 extending in the first direction X.

[0075] According to some embodiments, the second layer LAYER 2 extending between the cell boundaries of the standard cell 700 in the first direction X can be symmetric in the first direction X on the standard cell 700. The second layer LAYER 2 according to some embodiments can include unit layers extending in different directions with respect to rows on an IC, and the unit layers can be symmetric with respect to the rows. The second layer LAYER 2 according to some embodiments can extend in the second direction Y by alternately arranging a plurality of unit layers in the second direction Y (e.g., alternately distributing the unit layers consecutively in the second direction Y). The number of the first unit layers 721 and the number of the second unit layers 723 on the standard cell 700 can be the same.

[0076] Figure 8 is a layout diagram of a partial region of the IC 800 according to some embodiments. Specifically, Figure 8 is a layout diagram showing standard cells located on the IC 800 and layers located on the standard cells.

[0077] Referring to Figure 8IC 800 can include a first standard cell 801, a second standard cell 802, and a third standard cell 803. Each of the first to third standard cells 801, 802, and 803 can be disposed along a row. Specifically, the first standard cell 801 can be disposed along a first row R1 and a second row R2, the second standard cell 802 can be disposed along the second row R2 and a third row R3, and the third standard cell 803 can be disposed along the third row R3 and a fifth row R5. The first standard cell 801 and the second standard cell 802 can be single-row cells, and the third standard cell 803 can be a multi-row cell.

[0078] In some embodiments, a portion of the second layer LAYER 2 can extend across a cell boundary of a standard cell in a first direction X on the standard cell. Specifically, the second layer LAYER 2 on the first standard cell 801 can extend from the first row R1 to the second row R2. The first row R1 and the second row R2 can respectively overlap with the cell boundary of the first standard cell 801 in the first direction X. The second layer LAYER 2 on the first standard cell 801 can be symmetrical along the first direction X.

[0079] In some embodiments, the second layer LAYER 2 can include a plurality of cell layers extending in different directions with respect to a row. For example, a first cell layer 821 positioned with respect to the fourth row R4 along a second direction Y can extend along a fourth direction D1 between the first direction X and the second direction Y, and a second cell layer 823 positioned with respect to the fourth row R4 along a direction -Y opposite the second direction Y can extend along a fifth direction D2 between the first direction X and the direction -Y opposite the second direction Y. Each of the first cell layer 821 and the second cell layer 823 can have a length in the second direction Y equal to half of a length between adjacent rows (e.g., R3 and R4) in the second direction Y (e.g., a length from the line 815 to R4), and the first cell layer 821 and the second cell layer 823 can be symmetrical to each other with respect to the fourth row R4. The second layer LAYER 2 can be a layer extending in the second direction Y by alternately arranging a certain number of the first cell layer 821 and the second cell layer 823 in the second direction Y (e.g., the first cell layer 821 and the second cell layer 823 are alternately distributed continuously in the second direction Y).

[0080] The structure of the second layer LAYER 2 can be applied regardless of the size of a standard cell (e.g., a single-row cell or a multi-row cell) disposed on an IC.

[0081] Meanwhile, the first layer LAYER 1 can be electrically connected with the second layer LAYER 2 through a via member VIA1 located on the first layer LAYER 1, and the second layer LAYER 2 can be electrically connected with the third layer LAYER 3 through a via member VIA2 located on the second layer LAYER 2.

[0082] Figure 9 is a layout diagram of a partial region of the IC 900 according to a comparative example. Specifically, Figure 9 is a layout diagram illustrating two layers that are stacked adjacent to each other among a plurality of layers provided on the IC 900 according to a comparative example. For example, the first layer LAYER 1 can correspond to a first wiring layer (M1) in Figure 1 , and the second layer LAYER 2 can correspond to a second wiring layer (M2) that is stacked adjacent to the first wiring layer M1 in the third direction Z, but the present disclosure is not limited thereto. Figure 1

[0083] The IC 900 according to the comparative example can include a plurality of first layers LAYER 1 extending in the first direction X. The plurality of first layers LAYER 1 can be parallel to each other. The plurality of first layers LAYER 1 can be repeated in the second direction Y by every first length S1. The first layer LAYER 1 can have a first width W1.

[0084] The IC 900 according to the comparative example can include a second layer LAYER 2 stacked on the first layer LAYER 1 in the vertical direction Z. The plurality of second layers LAYER 2 can extend in the second direction Y. The plurality of second layers LAYER 2 can be parallel to each other. The plurality of second layers LAYER 2 can be repeated in the first direction X by every second length S2. The second layer LAYER 2 can have a second width W2.

[0085] The first layer LAYER 1 and the second layer LAYER 2 can be electrically connected to each other by a via member VIA. The first layers 921 and 923 adjacent to each other in the second direction Y can be electrically connected to the second layer LAYER 2 by the via members 901 and 902. Here, the via members 901 and 902 can be provided on the same layer, and can be adjacent to each other in the second direction Y.

[0086] On the other hand, via members located on the same layer need to be spaced apart at a certain distance. For example, according to a design rule that can be defined by a semiconductor process, a minimum distance at which via members located on the same layer need to be spaced apart is predetermined as a minimum spacing rule, and the via members located on the same layer are spaced apart from each other by a distance greater than according to the minimum spacing rule.

[0087] ​According to the comparative example, because the second layer LAYER 2 extends linearly in the second direction Y, the positions of the via members 901 and 902 in the first direction X can be the same as each other. On the first layers 921 and 923 adjacent to each other in the second direction Y, the interval distance 910 of the via members 901 and 902 disposed on the same layer in the second direction Y can be smaller than the previously determined minimum interval distance of the via members. Therefore, on the first layers 921 and 923 adjacent to each other in the second direction Y, the via members 901 and 902 of the same layer can not be disposed at the same positions in the first direction X. Because the first width W1 and the second width W2 of the lower layer (e.g., the first layer LAYER 1) and the upper layer (e.g., the second layer LAYER 2) are different from each other, and the first length S1 and the second length S2 between the lower layer and the upper layer are different from each other, the IC 900 including the second layer LAYER 2 according to the comparative example has a problem that the arrangement of the via members 901 and 902 is limited.

[0088] Figure 10 is a layout diagram of a partial region of an IC 1000 according to some embodiments. For ease of description, descriptions redundant to the descriptions of Figure 9 are omitted here.

[0089] In some embodiments, the IC 1000 can include a second layer LAYER 2 stacked on the first layer LAYER 1 in the vertical direction Z. The second layer LAYER 2 according to some embodiments can be electrically connected to the first layer LAYER 1 by via members VIA.

[0090] According to some embodiments, the first layers 1021 and 1023 adjacent to each other in the second direction Y can be electrically connected to the second layer LAYER 2 by the via members 1001 and 1003. According to the structure of the second layer LAYER 2 according to some embodiments, the positions of the via members 1001 and 1003 located on the same layer and adjacent to each other in the second direction Y can be different from each other in the first direction X. Therefore, on the first layers 1021 and 1023 adjacent to each other in the second direction Y, the interval distance 1010 of the via members 1001 and 1003 disposed on the same layer and adjacent to each other in the second direction Y can be greater than the distance 910 according to the comparative example. Figure 9 According to some embodiments, the interval distance 1010 of the via members 1001 and 1003 disposed on the same layer and adjacent to each other in the second direction Y can be greater than the previously determined minimum interval distance of the via members.

[0091] Figure 11 is a layout diagram of a standard cell 1100 and layers on the standard cell 1100 according to some embodiments. For ease of description, descriptions the same as or similar to the above-described descriptions are omitted here.

[0092] Referring to Figure 11 The standard cells 1100 can be arranged along the first row R1 and the second row R2. The standard cells 1100 can be single-row cells.

[0093] In some embodiments, the standard cells 1100 can include a plurality of first layers LAYER 1 extending along the first direction X, and a second layer LAYER 2 can be stacked on the first layers LAYER 1.

[0094] The second layer LAYER 2 according to some embodiments can include a first cell layer 1101. The cell layer 1101 can extend from a first vertical line 1131 to a second vertical line 1133 in the second direction Y. A length of the cell layer 1101 in the second direction Y can be equal to half H / 2 of a pitch H of the first row R1 and the second row R2 adjacent in the second direction Y.

[0095] The second layer LAYER 2 according to some embodiments can include a plurality of first cell layers 1101 and second cell layers 1103 arranged repeatedly in the second direction Y. The second layer LAYER 2 on the standard cells 1100 can extend from the first row R1 to the second row R2. The second layer LAYER 2 on the standard cells 1100 can be symmetrical along the first direction X, while a second length S2 between the first vertical line 1131 and the second vertical line 1133 can be equal to 1 cpp, but is not limited thereto.

[0096] Figure 12 is a flowchart for explaining a method 1200 of designing and manufacturing an IC according to some embodiments.

[0097] Referring to Figure 12 The method 1200 of designing and manufacturing an IC can include a design step S110 of an IC and a manufacturing step S120 of an IC. The design step S110 of an IC is a step of generating a gate-level netlist 1250, designing layout data 1260 of an IC, and verifying the layout data 1260, and the design step S110 can be performed in an IC design tool to design and verify an IC.

[0098] The design step S110 of an IC can include a logic synthesis step S10 and a physical design step S20. The logic synthesis step S10 can refer to a step of generating a gate-level netlist 1250 from RTL data 1230. For example, an IC design tool (for example, a logic synthesis tool) can perform a logic synthesis operation that generates a gate-level netlist 1250 (hereinafter, referred to as a "netlist") from the RTL data 1230 written as a VHSIC hardware description language (VHDL) and a hardware description language (HDL) such as Verilog. The netlist 1250 represents a connection relationship between cells in an IC, and can refer to a logic circuit diagram.

[0099] The physical design step S20 can include a placement step S21, a routing step S23, and a verification step S25. The IC design tool can receive the cell library 1241 and the technology file 1243, and perform each step based on the cell library 1241 and the technology file 1243.

[0100] In the placement step S21, a standard cell can be placed. For example, the IC design tool (e.g., a P&R tool) can place a standard cell used in the netlist 1250. The IC design tool can place the standard cell along a predetermined line based on information about the standard cell stored in the cell library 1241. The cell library 1241 can include layout information such as height, size, or geometry information of a pattern forming the standard cell, and characteristic information such as delay and leakage current of the standard cell. Here, the standard cell can include a logic device such as AND, OR, an inverter, and a memory device such as a flip-flop. The standard cell can be implemented by at least one transistor, a metal oxide semiconductor field effect transistor (MOSFET), a finFET, etc., but is not limited thereto.

[0101] In the routing step S23, pins of the standard cell can be routed. For example, the IC design tool can electrically connect the pins of the standard cell placed in the placement step S21 based on a connection relationship of the standard cell of the netlist 1250.

[0102] The IC can include layers electrically connecting the standard cells. Specifically, the IC can include layers stacked in a vertical direction. The structure of the layers stacked on the IC can be the same as or similar to that of the routing layer of Figure 1 The layers can be connected by a via formed on the layers, and the layers and the via can electrically connect the pins of the standard cells.

[0103] The IC design tool can generate a plurality of layers based on information stored in the technology file 1243. The technology file 1243 can include information about the plurality of layers and a plurality of vias. For example, the technology file 1243 can define names of the layers and the vias, widths, intervals, or areas of the metal layers and the vias according to design rules.

[0104] In some embodiments, the IC design tool can place the second layer as a cell layer. For example, a first cell layer positioned along a second direction from a row extending in a first direction can extend along a fourth direction intersecting the first direction and the second direction, and a second cell layer positioned along a direction opposite to the second direction from the row extending in the first direction can extend along a fifth direction intersecting the first direction and the direction opposite to the second direction. The first cell layer and the second cell layer can be symmetrical to each other with respect to the row. The second layer can include the first cell layer and the second cell layer alternately arranged in the second direction. Among a plurality of via members electrically connected to a plurality of first layers extending in the first direction and one second layer extending in the second direction, positions of the via members adjacent to each other in the second direction can be different from each other in the first direction. According to some embodiments, the second layer extending between cell boundaries of standard cells in the first direction can be symmetrical along the first direction on the standard cells.

[0105] The IC design tool can generate layout data 1260 defining the placed standard cells and the generated plurality of layers and via members. The layout data 1260 can have a format such as GDSII, and can include geometric information of the standard cells and the plurality of layers and via members.

[0106] The verification step S25 can be a step of verifying and modifying the generated layout. Items to be verified can include static timing analysis (STA) verifying whether the layout satisfies timing conditions of the design, design rule check (DRC) verifying whether the layout properly complies with design rules, electrical rule check (ERC) verifying whether the layout is properly made inside without electrical disconnection, layout versus schematic (LVS) verifying whether the layout matches a netlist, and the like.

[0107] The manufacturing step S120 of the IC can include a plurality of steps for manufacturing masks and forming a semiconductor package.

[0108] The manufacturing step S120 of the IC can include a step of generating mask data for forming various patterns of the plurality of layers by performing optical proximity correction (OPC) on the layout data 1260 generated in the design step S110 of the IC, and a step of manufacturing masks by using the mask data. In the manufacturing step S120 of the IC, various types of exposure and etching processes can be repeatedly performed. Through these processes, shapes of patterns configured at the time of design layout can be sequentially formed on a silicon substrate.

[0109] Further, in the manufacturing step S120 of the IC, a packaging process of mounting a semiconductor device resulting from the IC on a PCB and molding the semiconductor device with a molding material can be performed. Through the packaging process, the semiconductor device can be flip-chip mounted or bonded on a substrate by using a plurality of contact members.

[0110] Figure 13is a diagram schematically illustrating a design system 1300 of an IC according to some embodiments.

[0111] The design system 1300 can include a storage 1310, a design module 1330, a processor 1350, and an analysis module 1370. Figure 13 The design system 1300 of FIG. 1 can perform at least some of the design operations of the IC described in the design method of the IC described with reference to Figures 1 to 8 and Figures 10 to 12 FIGS. 2 and 3. The design system 1300 can be implemented as an integrated device, and thus, can be referred to as a design device. The design system 1300 can be provided as a dedicated device for designing an IC, but can be a computer for driving various simulation tools or design tools.

[0112] According to some embodiments, the storage 1310 can include a standard cell library 1311, a technology file 1312, and a design rule 1313. According to some embodiments, the standard cell library 1311 can include layout information of standard cells, and the technology file 1312 can include information about a plurality of layers within an IC. The standard cell library 1311, the technology file 1312, and the design rule 1313 in the storage 1310 can be provided from the storage 1310 to the design module 1330 and the analysis module 1370. The number of cell libraries included in the storage 1310 can vary differently.

[0113] The design module 1330 according to some embodiments can receive the standard cell library 1311, the technology file 1312, and the design rule 1313 from the storage 1310 to perform Figures 1 to 8 and Figures 10 to 12 design operations of an integrated circuit. In some embodiments, the design module 1330 can perform a placement operation on standard cells by using the standard cell library 1311, and can perform a routing operation on the standard cells after a plurality of layers are generated according to the technology file 1312. The design module 1330 according to some embodiments can set a second layer of the plurality of layers as a cell layer. Specifically, the cell layer symmetrical along a first direction can be alternately placed with respect to a row in which the standard cells are placed. Meanwhile, the cell layer of the second layer according to some embodiments can extend a predetermined length along a second direction between a first vertical line and a second vertical line spaced apart in the first direction. Here, the interval between the first vertical line and the second vertical line can be equal to 1 cpp. In addition, in the present disclosure, the term "module" can refer to software, hardware such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), or a combination of software and hardware.

[0114] Processor 1350 can be used in design module 1330 and analysis module 1370 to perform calculations. For example, processor 1350 may include a microprocessor, application processor (AP), digital signal processor (DSP), graphics processing unit (GPU), etc. Figure 13 Only one processor 1350 is shown, but according to embodiments, the system 1300 may include multiple processors. The processor 1350 may include cache memory to improve computing performance.

[0115] In execution Figures 1 to 8 as well as Figures 10 to 12 During or after the design operation of the IC, the analysis module 1370 can analyze and verify the layout generated by the design module 1330. In some embodiments, the analysis module 1370 can analyze and verify, based on design rules 1313 received from the storage device 1310, whether the distance between adjacent vias in the second direction and located in the same layer meets the minimum spacing distance according to the design rules. Specifically, the analysis module 1370 can analyze and verify whether the distance between adjacent vias in the second direction meets the minimum spacing distance according to the design rules among a plurality of vias electrically connected to a plurality of first layers extending in the first direction and a second layer extending in the second direction. In addition, the analysis module 1370 can analyze and verify, based on design rules 1313 received from the storage device 1310, whether the standard cell and the plurality of layers connecting the standard cell meet the design rules.

[0116] Many changes and modifications can be made by those skilled in the art based on the benefits of this disclosure without departing from the spirit and scope of the inventive concept. Therefore, it must be understood that the illustrated embodiments are set forth for illustrative purposes only and should not be considered as limiting the inventive concept as defined by the appended claims. Thus, the appended claims should be understood to include not only combinations of the literally set elements, but also all equivalent elements for performing substantially the same function in substantially the same manner to obtain substantially the same result. Therefore, the claims should be understood to include the content specifically described and illustrated above, conceptually equivalent content, and content incorporating the basic ideas of the inventive concept.

Claims

1. An integrated circuit, comprising: A plurality of first layers, the plurality of first layers extending in a first direction and arranged in a second direction perpendicular to the first direction; as well as The second layer includes: The first unit layer extends upward at a third point intersecting the first and second directions, and The second unit layer is connected to the first unit layer and extends along a fourth direction symmetrical to the third direction relative to the first direction, and is electrically connected to the first layer through a first via located on one of the plurality of first layers.

2. The integrated circuit as claimed in claim 1, wherein: The first unit layer extends along the third direction between the first position and the second position, and the first position and the second position are spaced apart by a first length in the first direction; and The second unit layer extends along the fourth direction between the first position and the second position in the first direction.

3. The integrated circuit as described in claim 2, wherein: The first length is 1 contact polycrystalline pitch.

4. The integrated circuit as claimed in claim 1, wherein: The third direction is a direction that is inclined from the first direction to the second direction at a predetermined angle, and the predetermined angle is between 0° and 90°.

5. The integrated circuit as claimed in claim 1, wherein: The second layer includes at least one first unit layer and at least one second unit layer alternately arranged along the second direction.

6. The integrated circuit of claim 1, further comprising: A standard cell includes a first cell boundary extending in the first direction and a second cell boundary spaced apart from the first cell boundary and extending in the first direction in the second direction.

7. The integrated circuit of claim 6, wherein: The first unit layer and the second unit layer are arranged in the same number within the standard unit.

8. The integrated circuit as claimed in claim 6, wherein: The standard unit is a single-row unit.

9. The integrated circuit as claimed in claim 6, wherein: A standard cell is a multi-row cell.

10. The integrated circuit of claim 6, wherein: The length of each of the first and second unit layers in the second direction is 1 / 2n of the length between the first unit boundary and the second unit boundary in the second direction, where n is a positive integer.

11. The integrated circuit as claimed in claim 1, wherein: The second layer is electrically connected to the other layer via a second via located on the other of the plurality of first layers.

12. The integrated circuit of claim 11, wherein: The positions of the first through hole and the second through hole are different from each other in the first direction.

13. An integrated circuit, comprising: A standard cell, comprising a plurality of cell boundaries extending in a first direction; The first layer extends along the first direction between the first and second unit boundaries among the plurality of unit boundaries; as well as The second layer extends from a first point on the boundary of the first unit to a second point spaced apart from the first point by a first length in the first direction, and is positioned between the boundary of the first unit and the boundary of the second unit in a second direction perpendicular to the first direction, wherein the second layer is symmetrical about the first direction in the standard unit and is located on the first layer.

14. The integrated circuit of claim 13, wherein: The second point is located in the middle between the first unit boundary and the second unit boundary in the second direction.

15. The integrated circuit of claim 13, wherein: The first length is 1 contact polycrystalline pitch.

16. The integrated circuit of claim 13, wherein: The width of the second layer is less than the length of the first layer.

17. The integrated circuit of claim 13, further comprising: The third layer is located on the same layer as the second layer, is spaced apart from the second layer in the first direction, and has the same structure as the second layer.

18. The integrated circuit of claim 17, wherein: The spacing length between the second layer and the third layer in the first direction is the same as the first length.

19. An integrated circuit, comprising: First standard unit; The second standard unit is adjacent to the first standard unit in the first direction; The first layer extends along a second direction perpendicular to the first direction on the first standard unit and the second standard unit; as well as The second layer includes: A plurality of first unit layers, wherein the plurality of first unit layers are located on the first layer in the first standard unit and the second standard unit, and extend upward on a third side between the first direction and the second direction, and A plurality of second unit layers, which are symmetrical to the plurality of first unit layers in the second direction and are alternately arranged with the plurality of first unit layers in the first direction.

20. The integrated circuit of claim 19, wherein: The height of the first standard unit in the first direction is different from the height of the second standard unit in the first direction.

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