Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention relates to a solar cell, a preparation method thereof and a photovoltaic module. The solar cell comprises a silicon substrate, a first intrinsic silicon layer, a tunneling layer, a first doped silicon layer and a first electrode which are arranged on the front surface of the silicon substrate, and a second intrinsic silicon layer, a second doped silicon layer and a second electrode which are arranged on the back surface of the silicon substrate, wherein the front face is provided with electrode areas and non-electrode areas which are alternately arranged, and the electrode areas are sunken towards the back face to form grooves between the adjacent non-electrode areas; the first intrinsic silicon layer is arranged in the groove, and the tunneling layer is arranged in the non-electrode area; the first doped silicon layer and the first electrode are sequentially stacked on the sides, away from the silicon substrate, of the first intrinsic silicon layer and the tunneling layer, and the first electrode is arranged corresponding to the electrode area. The second intrinsic silicon layer, the second doped silicon layer and the second electrode are sequentially stacked on the back face of the silicon substrate, and the conduction type of the second doped silicon layer is opposite to that of the first doped silicon layer. The solar cell has improved passivation effect and optical performance.

Description

Technical Field

[0001] This application relates to the field of batteries, and in particular to solar cells and their preparation methods, and photovoltaic modules. Background Technology

[0002] Heterojunction solar cells are a type of solar cell formed on a silicon substrate by two semiconductors with opposite conductivity types. Their front structure typically includes an intrinsic silicon layer and an N-type doped silicon layer, while the back structure typically includes an intrinsic silicon layer and a P-type doped silicon layer. Due to their simple fabrication process and high photoelectric conversion efficiency, they have broad application prospects and their development is becoming increasingly mature. However, traditional heterojunction solar cells still suffer from insufficient passivation and require further improvement in optical performance. Summary of the Invention

[0003] Based on this, some embodiments of this application provide a solar cell with improved passivation and optical properties.

[0004] In addition, some other embodiments of this application also provide a method for preparing a solar cell and a photovoltaic module.

[0005] A solar cell, comprising:

[0006] A silicon substrate having a front side and a back side disposed opposite each other along the thickness direction, the front side having alternating electrode regions and non-electrode regions, the electrode regions being recessed toward the back side to form grooves between adjacent non-electrode regions;

[0007] A first intrinsic silicon layer, a tunneling layer, a first doped silicon layer, and a first electrode are disposed on the front side; wherein, the first intrinsic silicon layer is disposed in the groove, and the tunneling layer is disposed in the non-electrode region; the first doped silicon layer and the first electrode are disposed on the side of the first intrinsic silicon layer and the tunneling layer away from the silicon substrate, and the first electrode is disposed corresponding to the electrode region;

[0008] A second intrinsic silicon layer, a second doped silicon layer, and a second electrode are sequentially stacked on the back side of the silicon substrate. The second doped silicon layer has the opposite conductivity type to the first doped silicon layer.

[0009] In some embodiments, the depth of the groove is 3nm to 5nm; and / or, the width of the groove is 30μm to 50μm.

[0010] In some embodiments, the thickness of the first intrinsic silicon layer is 5nm to 6nm, and the thickness of the tunneling layer is 1nm to 2nm.

[0011] In some embodiments, the tunneling layer is made of silicon oxide; and / or,

[0012] The first intrinsic silicon layer comprises hydrogenated intrinsic amorphous silicon.

[0013] In some embodiments, the bottom of the groove has a flat structure; and / or,

[0014] The silicon substrate in the non-electrode region has a textured surface; and / or,

[0015] The back side of the silicon substrate has a flat structure.

[0016] In some embodiments, the solar cell further includes a first transparent conductive layer disposed between the first doped silicon layer and the first electrode, and a second transparent conductive layer disposed between the second doped silicon layer and the second electrode.

[0017] A method for fabricating a solar cell includes the following steps:

[0018] A silicon substrate is obtained, the silicon substrate having a front side and a back side disposed opposite to each other along the thickness direction, the front side having alternating electrode regions and non-electrode regions, the electrode regions being recessed toward the back side to form grooves between adjacent non-electrode regions;

[0019] A first intrinsic silicon layer is formed in the groove, and a tunneling layer is formed in the non-electrode region;

[0020] A first doped silicon layer and a first electrode are sequentially stacked on the side of the first intrinsic silicon layer and the tunneling layer away from the silicon substrate, wherein the first electrode is formed at a position corresponding to the electrode region;

[0021] A second intrinsic silicon layer, a second doped silicon layer, and a second electrode are sequentially stacked on the back side of the silicon substrate. The second doped silicon layer has the opposite conductivity type to the first doped silicon layer.

[0022] In some embodiments, prior to the step of forming the first intrinsic silicon layer within the groove, the method further includes:

[0023] The silicon substrate is texturized to form a textured surface structure on the front side;

[0024] The groove is formed in the electrode area on the front side, so that the bottom of the groove has a flat structure.

[0025] In some embodiments, the step of texturing the silicon substrate includes: texturing the silicon substrate on both sides, forming a texturized structure on both the front and back sides.

[0026] In some embodiments, prior to the step of creating the groove in the electrode area on the front side, the method further includes:

[0027] A mask layer is formed on the front side after texturing;

[0028] The back surface after flocking is polished to give it a flat structure;

[0029] Remove the mask layer.

[0030] In some embodiments, the step of forming a tunneling layer in the non-electrode region includes: preparing the tunneling layer by plasma chemical vapor deposition using silane and nitrous oxide as raw materials.

[0031] A photovoltaic module includes a solar cell and an encapsulation structure. The solar cell is a solar cell as described above, or is prepared by the preparation method described above. The encapsulation structure is used to encapsulate the solar cell.

[0032] In some embodiments of this application, a groove is formed in the electrode region corresponding to the first electrode on the front side of the solar cell. A first intrinsic silicon layer is disposed within the groove, and a tunneling layer is disposed in the non-electrode region. Because the tunneling layer can transmit a wider wavelength of sunlight (from ultraviolet to near-infrared) compared to the first intrinsic silicon layer, the silicon substrate can receive more light, thereby increasing the short-circuit current (Isc). Furthermore, because ultraviolet light is transmitted, it is not absorbed by the film layer, reducing the damage of ultraviolet light to the film layer and improving UV attenuation. By setting the groove, on the one hand, the thickness difference between the tunneling layer and the first intrinsic silicon layer prevents the reduction of the effective illumination area caused by surface inhomogeneity; on the other hand, the placement of the first intrinsic silicon layer within the groove is beneficial to improving carrier transport capacity and passivation effect, reducing series resistance (Rs), and increasing fill factor (FF).

[0033] Therefore, the solar cells of some embodiments of this application have improved passivation effects and optical performance. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the structure of a solar cell according to some embodiments of this application;

[0036] Figure 2 for Figure 1 A schematic diagram of the structure of the silicon substrate, the first intrinsic silicon layer, and the tunneling layer shown in the figure;

[0037] Figure 3 This is a schematic diagram of a process flow for the fabrication method of a solar cell according to some embodiments of this application;

[0038] Figure 4 This is a schematic diagram of a process flow for the fabrication method of a solar cell according to other embodiments of this application.

[0039] Explanation of reference numerals in the attached figures:

[0040] Solar cell 100, silicon substrate 110, front side 102, back side 104, electrode region 1022, non-electrode region 1024, first intrinsic silicon layer 120, tunneling layer 130, first doped silicon layer 140, first transparent conductive layer 150, first electrode 192, second intrinsic silicon layer 160, second doped silicon layer 170, second transparent conductive layer 180, second electrode 194, electrode layer 190. Detailed Implementation

[0041] To facilitate understanding of this application, a more comprehensive description of the application will be provided below in conjunction with specific embodiments. Preferred embodiments of the application are given in the specific embodiments. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0043] Unless otherwise stated or in case of conflict, the terms or phrases used in this application shall have the following meanings:

[0044] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" and "second" may explicitly or implicitly include at least one of those features.

[0045] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0046] In this application, "one or more" refers to any one, two, or more of the listed items. "Multiple" refers to any two or more of the listed items.

[0047] Unless otherwise specified, all percentage concentrations mentioned in this application refer to the final concentration. The final concentration refers to the proportion of the added component in the system after the addition of that component.

[0048] In this application, terms such as "further," "even more," "particularly," "for example," "like," "example," and "exemplary" are used for descriptive purposes to indicate a connection in the coverage of different technical solutions presented earlier and later, but should not be construed as limiting the preceding technical solution or restricting the scope of protection herein. Unless otherwise specified herein, A (e.g., B) indicates that B is a non-limiting example of A, and it can be understood that A is not limited to B.

[0049] In this application, "optionally," "optionally," and "optional" mean that something is optional, that is, it is selected from either "present" or "absent." If multiple "options" appear in a technical solution, unless otherwise specified and there are no contradictions or mutual constraints, each "option" is independent. In this application, descriptions such as "optionally contains" and "optionally includes" indicate "contains or does not contain." "Optional component X" indicates whether component X exists or does not exist, or whether component X is contained or not.

[0050] When a numerical range is disclosed in this application, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be merged. In other words, unless otherwise specified, all ranges disclosed in this application should be understood to include any and all subranges to which they are included.

[0051] In this application, the technical features described in an open-ended manner include both closed technical solutions consisting of the listed features and open technical solutions that include the listed features.

[0052] The terms "comprising" and "having," and any variations thereof, used in the embodiments of this application, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or components inherent to such processes, methods, products, or devices.

[0053] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0054] In the flowchart of this application, although the steps are shown sequentially according to the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps. They can be executed in other orders. Moreover, at least some of the steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. Their execution order is not necessarily sequential, but can be performed alternately or in turn with at least some of other steps or other sub-steps or stages.

[0055] The first aspect of this application provides a solar cell; please refer to [link / reference]. Figure 1 and Figure 2 The solar cell 100 includes: a silicon substrate 110, a first intrinsic silicon layer 120, a tunneling layer 130, a first doped silicon layer 140 and a first electrode 193 disposed on the front side 102 of the silicon substrate 110, and a second intrinsic silicon layer 160, a second doped silicon layer 170 and a second electrode 194 disposed on the back side 104 of the silicon substrate 110.

[0056] The silicon substrate 110 has a front side 102 and a back side 104 disposed opposite to each other along the thickness direction. The front side 102 has alternating electrode regions 1022 and non-electrode regions 1024. The electrode regions are recessed towards the back side 104 and form grooves between adjacent non-electrode regions 1024.

[0057] The first intrinsic silicon layer 120 is disposed in the groove, and the tunneling layer 130 is disposed in the non-electrode region 1024; the first doped silicon layer 140 and the first electrode 193 are sequentially stacked on the side of the first intrinsic silicon layer 120 and the tunneling layer 130 away from the silicon substrate 110, and the first electrode 192 is disposed in the electrode region 1022.

[0058] The second intrinsic silicon layer 160, the second doped silicon layer 170, and the second electrode 194 are sequentially stacked on the back side 104 of the silicon substrate 110. The second doped silicon layer 170 has the opposite conductivity type to the first doped silicon layer 140.

[0059] This application research found that traditional heterojunction solar cell research mostly focuses on silicon wafer surface texturing, transparent conductive layer patterning, and grid line metallization. Based on the principles of increasing light transmittance, reducing light reflection, and minimizing interface recombination losses, these studies aim to improve the cell's short-circuit current, open-circuit voltage, and fill factor, ultimately enhancing the cell's photoelectric conversion efficiency and achieving cost reduction and efficiency improvement. However, research on intrinsic silicon layers is relatively limited. In some embodiments of this application, the applicant improves the first intrinsic silicon layer 120 by creating a groove in the electrode region corresponding to the first electrode 192. The first intrinsic silicon layer 120 is disposed within the groove, and a tunneling layer 130 is disposed in the non-electrode region 1024 outside the groove. Due to the wide transparency range of the tunneling layer 130 (from ultraviolet to near-infrared), the silicon substrate 110 can receive more light, thereby increasing the short-circuit current (Isc). Furthermore, because ultraviolet light is transmitted, it is not absorbed by the film layer, reducing the damaging effects of ultraviolet light on the film layer and improving UV attenuation. By setting the groove, on the one hand, the thickness difference between the tunneling layer 130 and the first intrinsic silicon layer 120 prevents the reduction of the effective area for illumination caused by surface inhomogeneity. On the other hand, setting the first intrinsic silicon layer 120 in the groove is beneficial to improving the carrier transport capacity, improving the passivation effect, reducing Rs, and improving the fill factor (FF).

[0060] Therefore, the solar cell 100 of some embodiments of this application has improved passivation effect and optical performance.

[0061] In this application, the front side 102 can be understood as the side facing the sunlight when the solar cell 100 is installed, and the back side 104 can be understood as the side facing away from the sunlight when the solar cell 100 is installed.

[0062] In some embodiments, the silicon substrate 110 may be a monocrystalline silicon substrate or a polycrystalline silicon substrate, etc., without particular limitation. For example, the silicon substrate 110 may be N-type monocrystalline silicon, P-type monocrystalline silicon, N-type polycrystalline silicon, or P-type polycrystalline silicon. In one example, the silicon substrate 110 is an N-type monocrystalline silicon substrate. The N-type monocrystalline silicon substrate is mainly phosphorus-doped and does not contain boron-oxygen complexes or boron-iron complexes as found in P-type monocrystalline silicon, which can further reduce photo-induced degradation.

[0063] In some embodiments, the depth of the groove is 3nm to 5nm.

[0064] In some embodiments, the width of the groove is 30μm to 50μm.

[0065] In some embodiments, the thickness of the first intrinsic silicon layer 120 is 5 nm to 6 nm, and the thickness of the tunneling layer 130 is 1 nm to 2 nm. This configuration ensures that the surfaces of the first intrinsic silicon layer 120 and the tunneling layer 130 are uniform, preventing a reduction in the effective area for illumination due to surface unevenness.

[0066] Specifically, the tunneling layer 130 comprises silicon oxide. Silicon oxide has extremely high transparency to ultraviolet, visible, and near-infrared light, and its nanometer-scale thickness ensures almost no absorption loss of the solar spectrum (especially light reaching this location inside the cell).

[0067] Specifically, the first intrinsic silicon layer 120 comprises hydrogenated intrinsic amorphous silicon. It will be understood that in some other embodiments, the first intrinsic silicon layer 120 may also comprise hydrogenated intrinsic microcrystalline silicon.

[0068] In some embodiments, the bottom of the groove is a flat structure. This configuration helps reduce recombination centers between the first intrinsic silicon layer 120 and the silicon substrate 110, further improving the passivation effect.

[0069] In some embodiments, the non-electrode region 1024 on the front side 102 of the silicon substrate 110 has a textured structure. The textured structure of the non-electrode region 1024 helps reduce reflectivity, allowing more incident light to enter the cell, improving optical performance, and ultimately increasing the cell's photoelectric conversion efficiency.

[0070] In some embodiments, the back surface 104 of the silicon substrate 110 has a flat structure. The back surface 104 of the silicon substrate 110 does not receive light, and the flat structure of the back surface 104 can further reduce recombination centers between the silicon substrate 110 and the second intrinsic silicon layer 160, which is beneficial to further improve the passivation effect.

[0071] In this application, a velvety structure refers to a microscopic velvety structure obtained through processes such as flocking, such as a pyramidal velvety structure. This velvety structure has a relatively large surface roughness and low light reflectivity. For example, the reflectivity of a velvety structure is less than 10%. Specifically, in the velvety structure, the pyramid base length is 0.5 μm to 1.5 μm, and the pyramid height:pyramid length ratio is 4:5. A flat structure, relative to a velvety structure, refers to a structure without a velvety surface, exhibiting a relatively flat morphology. Its surface roughness is significantly lower than that of a velvety structure, resulting in high light reflectivity. In some embodiments, the flat structure is obtained through polishing and is relatively flat compared to a velvety structure. For example, the reflectivity of a flat structure is 10% to 15%. Specifically, the pyramid base length of the flat structure is 2.5 μm to 4 μm, and the pyramid height:pyramid length ratio is 3:5. This configuration is advantageous for printing. If a completely flat structure is used, it can easily cause printing failures and grid breaks during screen printing.

[0072] In some embodiments, the second intrinsic silicon layer 160 is hydrogenated intrinsic amorphous silicon. It will be understood that in other embodiments, the second intrinsic silicon layer 160 may also comprise hydrogenated intrinsic microcrystalline silicon.

[0073] In some embodiments, the thickness of the second intrinsic silicon layer 160 can be what is commonly used in the art, and is not particularly limited here. In one embodiment, the thickness of the second intrinsic silicon layer 160 is 5 nm to 6 nm.

[0074] In some embodiments, one of the first doped silicon layer 140 and the second doped silicon layer 170 is an N-type doped silicon layer and the other is a P-type doped silicon layer. In one example, the first doped silicon layer 140 is an N-type doped silicon layer and the second doped silicon layer 170 is a P-type doped silicon layer. Specifically, the doping element in the first doped silicon layer 140 includes phosphorus, and the doping element in the second doped silicon layer 170 includes boron.

[0075] In some embodiments, the first doped silicon layer 140 and the second doped silicon layer 170 each independently comprise one or more of doped microcrystalline silicon, doped amorphous silicon, and doped polycrystalline silicon.

[0076] In some embodiments, both the first doped silicon layer 140 and the second doped silicon layer 170 comprise doped microcrystalline silicon. Doped microcrystalline silicon is derived from the structure of doped amorphous silicon. Compared with doped amorphous silicon, doped microcrystalline silicon is beneficial for further improving the carrier transport capability, thereby improving the photoelectric conversion efficiency of the battery.

[0077] In some embodiments, the first doped silicon layer 140 is an N-type doped microcrystalline silicon layer, and the second doped silicon layer 170 is a P-type doped microcrystalline silicon layer.

[0078] In some embodiments, the thicknesses of the first doped silicon layer 140 and the second doped silicon layer 170 can be those commonly used in the art and are not particularly limited herein. In one embodiment, the thicknesses of the first doped silicon layer 140 and the second doped silicon layer 170 are each independently 20 nm to 35 nm.

[0079] In some embodiments, the materials and thicknesses of the first electrode 192 and the second electrode 194 can be those commonly used in the art and are not particularly limited herein. For example, the first electrode 192 and the second electrode 194 can be silver electrodes or copper electrodes, etc.

[0080] In some embodiments, the solar cell 100 further includes a first transparent conductive layer 150 disposed between the first doped silicon layer 140 and the first electrode 192, and a second transparent conductive layer 180 disposed between the second doped silicon layer 170 and the second electrode 194. By providing a transparent conductive layer (TCO), it is beneficial to further improve light transmittance, reduce light reflection, reduce light absorption loss, improve the utilization rate of sunlight by the cell, and at the same time, improve conductivity, which is beneficial to carrier transport.

[0081] In some embodiments, the materials and thicknesses of the first transparent conductive layer 150 and the second transparent conductive layer 180 can be those commonly used in the art and are not particularly limited herein. For example, the materials of the first transparent conductive layer 150 and the second transparent conductive layer 180 are each independently selected from one or more of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), indium-doped zinc oxide (IZO), and fluorine-doped tin oxide (FTO). When the transparent conductive layer includes multiple materials, it can be a single-layer structure composed of multiple materials or a multilayer structure composed of multiple materials.

[0082] Specifically, the solar cell 100 includes a silicon substrate 110, which has a front side 102 and a back side 104 disposed opposite to each other along its thickness direction. The front side 102 has alternating electrode regions 1022 and non-electrode regions 1024. The electrode regions 1022 are provided with grooves. A first intrinsic silicon layer 120, a tunneling layer 130, a first doped silicon layer 140, a first transparent conductive layer 150, and a first electrode 192 are disposed on the front side 102 of the silicon substrate 110. A second intrinsic silicon layer 160, a second doped silicon layer 170, a second transparent conductive layer 180, and a second electrode 194 are sequentially stacked on the back side 104 of the silicon substrate 110. The first electrode 192 and the second electrode 194 constitute the electrode layer 190.

[0083] The second aspect of this application provides a method for fabricating a solar cell; please refer to [link to relevant documentation]. Figure 3 It includes the following steps:

[0084] Step S210: Obtain a silicon substrate. The silicon substrate has a front side and a back side disposed opposite to each other along the thickness direction. The front side has alternating electrode areas and non-electrode areas. The electrode areas are recessed towards the back side to form grooves between adjacent non-electrode areas.

[0085] Step S220: Form a first intrinsic silicon layer in the groove and form a tunneling layer in the non-electrode region.

[0086] Step S230: On the side of the first intrinsic silicon layer and the tunneling layer away from the silicon substrate, the first doped silicon layer and the first electrode are stacked sequentially, with the first electrode formed at the position of the corresponding electrode region.

[0087] Step S240: A second intrinsic silicon layer, a second doped silicon layer, and a second electrode are sequentially stacked on the back side of the silicon substrate. The conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer.

[0088] The aforementioned method for fabricating solar cells involves creating a groove in the electrode region corresponding to the first electrode. A first intrinsic silicon layer is formed within the groove, while a tunneling layer is formed in the non-electrode region outside the electrode region. Because the tunneling layer has a wide transparency range (from ultraviolet to near-infrared), it allows the silicon substrate to receive more light, thereby increasing the short-circuit current (Isc). Furthermore, because ultraviolet light is transmitted, it is not absorbed by the film layer, reducing the damaging effects of ultraviolet light and improving UV attenuation. By creating the groove, on the one hand, the thickness difference between the tunneling layer and the first intrinsic silicon layer prevents the reduction in effective illumination area caused by surface inhomogeneity; on the other hand, the presence of the first intrinsic silicon layer within the groove helps improve carrier transport capacity, enhances passivation, reduces series resistance (Rs), and increases the fill factor (FF).

[0089] In some embodiments, prior to the step of forming the first intrinsic silicon layer within the trench, the method further includes:

[0090] Texturing the silicon substrate creates a textured surface structure on the front side.

[0091] A groove is made in the electrode area on the front side, so that the bottom of the groove has a flat structure.

[0092] In some embodiments, laser grooving is used to create the grooves. During laser grooving, the laser beam is focused into a very small spot, generating extremely high energy density at the focal point. This high energy density acts on the textured surface of the silicon substrate, causing the silicon material to rapidly melt into a liquid or vaporize. This not only removes the peaks of the pyramidal textured surface but also forms the groove structure. When the laser beam is removed, the molten silicon material cools, forming a flat surface.

[0093] Specifically, the depth of the groove is 3nm~5nm and the width is 30μm~50μm.

[0094] In some embodiments, the step of texturing a silicon substrate includes: texturing the silicon substrate on both sides to form a textured structure on both the front and back sides.

[0095] In some embodiments, prior to the step of creating a groove in the electrode area on the front side, the method further includes:

[0096] A mask layer is formed on the front side after texturing;

[0097] Polish the back side after flocking;

[0098] Remove the mask layer.

[0099] Polishing the back of the silicon wafer helps reduce interfacial recombination during the subsequent deposition of the second intrinsic silicon layer, further enhancing the passivation effect, thereby reducing Rs and increasing FF.

[0100] In some embodiments, the mask layer comprises silicon oxide. By setting the mask layer, the front side of the silicon wafer retains a pyramidal textured structure, while the back side is polished, resulting in a single-sided textured and single-sided polished structure.

[0101] Specifically, a mask layer is prepared using silane and nitrous oxide as raw materials via plasma chemical vapor deposition (PECVD).

[0102] In some embodiments, the mask layer is removed using HCl and HF.

[0103] In some embodiments, the texturing step can be achieved using techniques commonly used in the art. For example, texturing methods include wet texturing. In some embodiments, a texturing solution is used to clean and texturize the silicon substrate, forming a textured surface structure on the silicon substrate to obtain a texturized silicon substrate. By texturing the silicon substrate, organic contaminants and metallic impurities on the surface are removed, the mechanically damaged layer of the silicon substrate during cutting is removed, composite centers are reduced, an uneven textured surface is formed, and light absorption is increased.

[0104] In some embodiments, prior to the texturing step of the silicon substrate, the process further includes: rough polishing and pre-cleaning the silicon substrate. Rough polishing removes the mechanical damage layer on the silicon wafer surface. Pre-cleaning removes surface oil and metallic impurities. Specific rough polishing and pre-cleaning steps can be those commonly used in the art and are not particularly limited here.

[0105] In some embodiments, after texturing the silicon substrate and before forming a mask layer on the textured front side, the process further includes: pre-cleaning, rounding, post-cleaning, passivation, slow lifting, and drying. Pre-cleaning removes additive organic particles; rounding polishes and creates a pyramidal textured surface; post-cleaning removes surface metal ions; passivation removes the oxide layer and passivates the surface; slow lifting removes adsorbed impurities and residual pharmaceuticals; and dehydration is performed.

[0106] In some embodiments, the polishing method includes alkaline polishing. For example, alkaline polishing is performed using at least one of KOH and NaOH solutions.

[0107] It is understood that the above only provides a relatively specific method for preparing a single-sided texturing and single-sided polishing structure, but it is not limited to this. Other methods can also be used, such as masking the back side of the silicon wafer, texturing the front side, removing the mask layer on the back side, masking the front side, and polishing the back side.

[0108] In some embodiments, the step of forming a tunneling layer in the non-electrode region includes: preparing the tunneling layer by plasma chemical vapor deposition using silane and nitrous oxide as raw materials.

[0109] In some embodiments, the first intrinsic silicon layer is prepared by plasma chemical vapor deposition using silane and hydrogen as raw materials.

[0110] Specifically, the thickness of the first intrinsic silicon layer is 5nm~6nm.

[0111] In some embodiments, the tunneling layer is prepared by plasma chemical vapor deposition (PECVD) using silane and nitrous oxide as raw materials. It is understood that in other embodiments, other methods may also be used to prepare the tunneling layer, such as thermal oxidation or vapor deposition.

[0112] Specifically, the thickness of the tunneling layer is 1nm~2nm.

[0113] In some embodiments, the preparation step of the first doped silicon layer includes: preparing the first doped silicon layer on the front side of a silicon substrate using silane, hydrogen, a first dopant source, and nitrous oxide as raw materials. In some embodiments, the first doped silicon layer is an N-type doped silicon layer, and the first dopant source is a phosphorus source, such as phosphine.

[0114] In some embodiments, the first doped silicon layer is an N-type hydrogenated microcrystalline silicon layer.

[0115] The first doped silicon layer forms a front surface field, reducing minority carrier recombination and increasing the open-circuit voltage.

[0116] In some embodiments, the preparation step of the second doped silicon layer includes: preparing a second doped silicon layer on the back side of a silicon wafer using silane, hydrogen, a second dopant source, and nitrous oxide as raw materials. In some embodiments, the second doped silicon layer is a p-type doped silicon layer, and the second dopant source is a boron source, such as borane.

[0117] In some embodiments, the second doped silicon layer is a P-type hydrogenated microcrystalline silicon layer. It is understood that in other embodiments, the second doped silicon layer may also be a P-type hydrogenated amorphous silicon layer.

[0118] Specifically, the thickness of the second doped silicon layer is 20nm~35nm.

[0119] The second doped silicon layer forms a PN junction, constructing a built-in battery.

[0120] In some embodiments, the fabrication process of the first electrode and the second electrode can be a method commonly used in the art, such as screen printing, and is not particularly limited herein.

[0121] In some embodiments, the method for fabricating a solar cell further includes: forming a first transparent conductive layer between a first doped silicon layer and a first electrode, and forming a second transparent conductive layer between a second doped silicon layer and a second electrode. Specifically, the fabrication processes of the first and second transparent conductive layers can be those commonly used in the art, such as deposition using a PVD device, and are not particularly limited here.

[0122] In some embodiments, please refer to Figure 4 The fabrication method of solar cells includes the following steps:

[0123] Step S310: Obtain a silicon substrate with a textured surface on the front and a polished surface on the back.

[0124] Step S320: Perform laser grooving on the electrode area on the front side to obtain a groove.

[0125] Step S330: Form a first intrinsic silicon layer in the groove.

[0126] Step S340: A tunneling layer is formed in the non-electrode region on the front side, with the non-electrode region and the electrode region alternating.

[0127] Step S350: Form a second intrinsic silicon layer on the back side.

[0128] Step S360: A first doped silicon layer is formed on the side of the first intrinsic silicon layer and the tunneling layer that is away from the silicon substrate.

[0129] Step S370: A second doped silicon layer is formed on the side of the second intrinsic silicon layer away from the silicon substrate.

[0130] Step S380: A first transparent conductive layer is formed on the side of the first doped silicon layer away from the silicon substrate, and a second transparent conductive layer is formed on the side of the second doped silicon layer away from the silicon substrate.

[0131] Step S390: A first electrode is formed on the side of the first transparent conductive layer away from the silicon substrate, and the first electrode is disposed in the corresponding electrode region. A second electrode is formed on the side of the second transparent conductive layer away from the silicon substrate.

[0132] Specifically, step S310 includes:

[0133] The front and back sides of the silicon substrate are texturized to obtain a double-textured silicon substrate;

[0134] A mask layer is formed on the front side of the silicon substrate;

[0135] Polish the back side;

[0136] After removing the mask layer, a silicon substrate with a textured front and a flat back is obtained.

[0137] The methods for fabricating solar cells according to some of the above embodiments have at least the following advantages:

[0138] (1) After the first intrinsic silicon layer is deposited after the front side of the silicon substrate is slotted, it is beneficial to improve the carrier transport capacity and passivation effect, reduce Rs, improve FF, and improve uniformity.

[0139] (2) Replacing the first intrinsic silicon layer with a tunneling layer in the non-electrode region (i.e., non-gate region) on the front side of the silicon substrate with a tunneling layer is beneficial to improving Isc.

[0140] (3) Polishing the back side of the silicon substrate can further reduce recombination centers between the silicon substrate and the second intrinsic silicon layer, which is beneficial to further improve the passivation effect.

[0141] A third aspect of this application provides a photovoltaic module, including a solar cell and an encapsulation structure. The solar cell is a solar cell as described above or prepared by the preparation method described above, and the encapsulation structure is used to encapsulate the solar cell.

[0142] To make the objectives and advantages of this application clearer, the solar cell and its effects of this application are further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are only for explaining this application and should not be used to limit this application. Unless otherwise specified, the following embodiments do not include components other than unavoidable impurities. Unless otherwise specified, the drugs and instruments used in the embodiments are conventional choices in the art. Experimental methods in the embodiments that do not specify specific conditions are implemented according to conventional conditions, such as those described in literature, books, or methods recommended by the manufacturer.

[0143] Example 1

[0144] This embodiment provides a solar cell, the structure of which is as follows: Figure 1 As shown, the preparation method includes the following steps:

[0145] (1) Wet texturing is performed on the N-type crystalline silicon substrate to obtain a double-textured N-type crystalline silicon substrate.

[0146] (2) Using silane and nitrous oxide as raw materials, a silicon oxide mask layer is deposited on the front side of the double-sided texturized N-type crystalline silicon substrate by PECVD.

[0147] (3) Polish the back side of the silicon substrate with KOH solution, and then remove the silicon oxide mask layer on the front side by using HCl and HF to obtain a silicon substrate with a textured front side and a polished back side.

[0148] (4) Laser grooving is performed on the front electrode area (also known as the gate line area) of the silicon substrate obtained in step (3) to obtain a groove with a depth of 4nm and a width of 40μm.

[0149] (5) Using silane and hydrogen as raw materials, a first intrinsic hydrogenated amorphous silicon layer with a thickness of 5~6 nm is formed in the groove by PECVD.

[0150] (6) Using silane and nitrous oxide, a 1.5 nm silicon oxide tunneling layer is formed in the non-electrode region (also known as the non-gate region) by PECVD.

[0151] (7) A second intrinsic hydrogenated amorphous silicon layer is deposited on the entire back side of the silicon substrate.

[0152] (8) Using silane, hydrogen, phosphine and nitrous oxide as raw materials, an N-type hydrogenated microcrystalline silicon oxide layer is deposited on the first intrinsic silicon layer and the tunneling layer away from the silicon substrate.

[0153] (9) Using silane, hydrogen, borane and nitrous oxide as raw materials, a P-type hydrogenated microcrystalline silicon oxide layer is deposited on the second intrinsic silicon layer away from the silicon substrate.

[0154] (10) Deposit an ITO anti-reflection blue film on the side of the N-type hydrogenated microcrystalline silicon oxide layer away from the silicon substrate and on the side of the P-type hydrogenated microcrystalline silicon oxide layer away from the silicon substrate.

[0155] (11) Silver grid lines are printed on both sides of a silicon substrate to obtain the solar cell of this embodiment.

[0156] Example 2

[0157] This embodiment provides a solar cell, similar to the solar cell in Embodiment 1, except that the back side is not polished, i.e., steps (2) and (3) are not included. The other steps are similar to those in Embodiment 1 and will not be described again.

[0158] Comparative Example 1

[0159] Comparative Example 1 provides a solar cell that is similar to the solar cell in Example 2, except that it does not have laser grooving and does not have a tunneling layer, i.e. it does not contain steps (4) and (6), and the first intrinsic hydrogen amorphous silicon layer in step (5) is formed on the entire front side of the silicon substrate.

[0160] Comparative Example 2

[0161] Comparative Example 2 provides a solar cell similar to that of Example 2, except that it does not have a groove, and instead directly forms a first intrinsic silicon layer and a tunneling layer on the front side. That is, it does not include step (4).

[0162] The solar cells prepared in the above embodiments and comparative examples were tested, and the test results are shown in Table 1 below.

[0163] Table 1

[0164]

[0165] As can be seen from Table 1 above, the efficiency of the conventional process in Comparative Example 1 is 0.31% lower than that in Example 1. Example 2, compared to Comparative Example 2, involves grooving, resulting in a 16mA increase in current, a significant decrease in Rs, and an improved fill factor. Furthermore, as can be seen from Examples 1 and 2, back-side polishing is beneficial for further improving various electrical performance parameters, thereby increasing photoelectric conversion efficiency.

[0166] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0167] The embodiments described above are merely illustrative of several implementation methods of this application, intended to facilitate a detailed understanding of the technical solutions of this application, but should not be construed as limiting the scope of protection of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. It should be understood that technical solutions obtained by those skilled in the art based on the technical solutions provided in this application through logical analysis, reasoning, or limited experimentation are all within the scope of protection of the appended claims. Therefore, the scope of protection of this patent application should be determined by the content of the appended claims, and the specification and drawings can be used to interpret the content of the claims.

Claims

1. A solar cell, characterized in that, include: A silicon substrate having a front side and a back side disposed opposite each other along the thickness direction, the front side having alternating electrode regions and non-electrode regions, the electrode regions being recessed toward the back side to form grooves between adjacent non-electrode regions; A first intrinsic silicon layer, a tunneling layer, a first doped silicon layer, and a first electrode are disposed on the front side; wherein, the first intrinsic silicon layer is disposed in the groove, and the tunneling layer is disposed in the non-electrode region; the first doped silicon layer and the first electrode are sequentially stacked on the side of the first intrinsic silicon layer and the tunneling layer away from the silicon substrate, and the first electrode is disposed corresponding to the electrode region; A second intrinsic silicon layer, a second doped silicon layer, and a second electrode are sequentially stacked on the back side, wherein the second doped silicon layer has the opposite conductivity type to the first doped silicon layer.

2. The solar cell according to claim 1, characterized in that, The depth of the groove is 3nm~5nm; and / or the width of the groove is 30μm~50μm.

3. The solar cell according to claim 1 or 2, characterized in that, The thickness of the first intrinsic silicon layer is 5nm~6nm, and the thickness of the tunneling layer is 1nm~2nm.

4. The solar cell according to claim 1, characterized in that, The tunneling layer comprises silicon oxide; and / or, The first intrinsic silicon layer comprises hydrogenated intrinsic amorphous silicon.

5. The solar cell according to claim 1, 2 or 4, characterized in that, The bottom of the groove has a flat structure; and / or, On the front side of the silicon substrate, the non-electrode region has a textured surface; and / or, The back side of the silicon substrate has a flat structure.

6. The solar cell according to claim 1, 2 or 4, characterized in that, The first doped silicon layer is an N-type doped silicon layer, and the second doped silicon layer is a P-type doped silicon layer; and / or, The solar cell further includes a first transparent conductive layer disposed between the first doped silicon layer and the first electrode, and a second transparent conductive layer disposed between the second doped silicon layer and the second electrode.

7. A method for fabricating a solar cell, characterized in that, Includes the following steps: A silicon substrate is obtained, the silicon substrate having a front side and a back side disposed opposite to each other along the thickness direction, the front side having alternating electrode regions and non-electrode regions, the electrode regions being recessed toward the back side to form grooves between adjacent non-electrode regions; A first intrinsic silicon layer is formed in the groove, and a tunneling layer is formed in the non-electrode region; A first doped silicon layer and a first electrode are sequentially stacked on the side of the first intrinsic silicon layer and the tunneling layer away from the silicon substrate, wherein the first electrode is formed at a position corresponding to the electrode region; A second intrinsic silicon layer, a second doped silicon layer, and a second electrode are sequentially stacked on the back side of the silicon substrate. The second doped silicon layer has the opposite conductivity type to the first doped silicon layer.

8. The method for preparing a solar cell according to claim 7, characterized in that, Prior to the step of forming the first intrinsic silicon layer within the groove, the method further includes: The silicon substrate is texturized to form a textured surface structure on the front side; The groove is formed in the electrode area on the front side, so that the bottom of the groove has a flat structure.

9. The method for preparing a solar cell according to claim 8, characterized in that, The step of texturing the silicon substrate includes: texturing the silicon substrate on both sides, forming a texturized structure on both the front and back sides.

10. The method for preparing a solar cell according to claim 9, characterized in that, Before the step of creating the groove in the electrode area on the front side, the method further includes: A mask layer is formed on the front side after texturing; The back surface after flocking is polished to make it flat. Remove the mask layer.

11. The method for preparing a solar cell according to claim 7, characterized in that, The step of forming a tunneling layer in the non-electrode region includes: preparing the tunneling layer by plasma chemical vapor deposition using silane and nitrous oxide as raw materials.

12. A photovoltaic module, characterized in that, The invention includes a solar cell and a packaging structure, wherein the solar cell is the solar cell as described in any one of claims 1 to 6, or a solar cell prepared by any one of claims 7 to 11, and the packaging structure is used to encapsulate the solar cell.

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