Display panel, preparation method of display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display. In the display panel, the surface of the substrate has the first flatness, the side, away from the substrate, of the leveling layer has the second flatness, and the first flatness is larger than the second flatness, that is, the leveling layer can improve the flatness of the side, away from the substrate, of the pixel defining layer, so that the side, away from the substrate, of the pixel defining layer becomes smoother; the continuous electrode film layer can be formed on one side far away from the substrate, and in the subsequent process of removing the evaporation film layer on the light-emitting device in advance through patterning of the light-emitting device, the dry etching gas can be blocked through the continuous electrode film layer to ensure that the film layer below the electrode film layer is not over-etched by the dry etching gas; therefore, the film layer of the light-emitting device manufactured in advance is prevented from being damaged by etching in the patterning process of the subsequent light-emitting device, and the light-emitting device manufactured in advance can emit light normally.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the display panel, and an electronic device. Background Technology

[0002] Organic light-emitting diode (OLED) display technology is considered the most promising next-generation display technology. Compared with liquid crystal display technology, OLED display technology has advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed.

[0003] In the traditional OLED display panel manufacturing process, a fine metal mask (FMM) is typically used to pattern the light-emitting pixels. FMM technology is mature and has extensive mass production experience. However, FMM technology also suffers from limitations in precision and high cost. Fine metal mask-less technology eliminates the limitations of traditional OLED processes on display size, resolution, and other screen performance characteristics, offering advantages such as high performance, full-size display, and agile delivery. Patents CN118251982A, CN116648095A, CN117062489A, CN118742138A, CN118678783A, CN118660598A, CN118675450A, CN118824188A, and CN118781966A describe relevant content regarding fine metal mask-less technology and are provided for reference.

[0004] However, the current manufacturing process of OLED display products still needs further improvement. Summary of the Invention

[0005] In order to overcome the technical problems mentioned in the above background, this application provides a display panel, a method for manufacturing the display panel, and an electronic device.

[0006] A first aspect of this application provides a display panel, the display panel comprising: substrate; A flattening layer is located on the substrate. In the region where the flattening layer is disposed, the surface of the substrate has a first flatness, and the side of the flattening layer away from the substrate has a second flatness. The first flatness is greater than the second flatness, wherein the smaller the flatness, the flatter the surface. A pixel defining layer is located on the side of the planarization layer away from the substrate. The pixel defining layer defines a plurality of pixel openings on the substrate. The orthographic projection of the pixel defining layer on the substrate covers the orthographic projection of the planarization layer on the substrate. An isolation structure is located on the pixel defining layer and encloses an isolation opening that communicates with the pixel opening; The light-emitting device is located at least partially within the pixel opening.

[0007] In one possible implementation of this application, the material of the planarization layer is an organic material, and the material of the pixel defining layer is an inorganic material; Preferably, the material of the planarization layer includes an organic adhesive, and the material of the pixel defining layer includes at least one of silicon oxide and silicon nitride.

[0008] In one possible implementation of this application, the orthographic projection of the isolation structure on the substrate lies within the orthographic projection of the planarization layer on the substrate.

[0009] In one possible implementation of this application, the distance between the end of the planarization layer facing the pixel opening and the corresponding sidewall of the pixel opening is 0.5 micrometers to 2 micrometers.

[0010] In one possible implementation of this application, the substrate includes a substrate, a conductive layer stacked on the substrate, and an insulating layer located between adjacent conductive layers; The substrate includes a pixel circuit formed by at least the conductive layer, and the pixel circuit includes transistors; The conductive layer includes a first conductive layer, a second conductive layer, and a third conductive layer stacked on the substrate. The insulating layer includes a first insulating layer located between the first conductive layer and the second conductive layer and a second insulating layer located between the second conductive layer and the third conductive layer. The first conductive layer forms at least the gate of the transistor, and the third conductive layer forms at least the source and drain of the transistor. The display panel also includes a planarization layer located on the side of the third conductive layer away from the substrate; The light-emitting device is electrically connected to the source or drain of the transistor through a first electrode via penetrating the planarization layer; Preferably, the first insulating layer and the second insulating layer are inorganic insulating layers, and the planarization layer is made of an organic material.

[0011] In one possible implementation of this application, the orthographic projection of the first electrode via on the substrate lies within the orthographic projection of the planarization layer on the substrate.

[0012] In one possible implementation of this application, the orthographic projection of the first electrode via on the substrate overlaps at most with the orthographic projection portion of the isolation structure on the substrate; Alternatively, the orthographic projection of the first electrode via on the substrate is misaligned with the orthographic projection of the isolation structure on the substrate, and the orthographic projection of the first electrode via on the substrate is located between the orthographic projection of the isolation structure on the substrate and the orthographic projection of the pixel opening on the substrate.

[0013] In one possible implementation of this application, in the direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting material layer and a second electrode stacked together, and the first electrode is connected to a transistor in the pixel circuit through a first electrode via. A portion of the first electrode is located between the pixel defining layer and the substrate, while another portion of the first electrode is exposed by the pixel opening; The second electrode is connected to the isolation structure, wherein the isolation structure is a conductive isolation structure.

[0014] In one possible implementation of this application, the planarization layer fills at least half the depth of the first electrode via, and in a direction perpendicular to the plane of the substrate, the height of the surface of the planarization layer away from the substrate relative to the surface of the first electrode away from the substrate is less than or equal to half the depth of the first electrode via. Preferably, the surface of the planarization layer away from the substrate is flush with the surface of the first electrode away from the substrate.

[0015] In one possible implementation of this application, the planarization layer covers the edge of the first electrode; The orthographic projection of the edge of the planarization layer on the substrate lies within the orthographic projection of the first electrode on the substrate.

[0016] In one possible implementation of this application, the isolation opening includes opposing first and second sides; On the first side, the portion of the pixel defining layer that extends relative to the planarization layer has a gap with the first electrode; On the second side, the portion of the pixel defining layer that extends relative to the planarization layer contacts the first electrode; Preferably, the height of the gap is greater than the height of the luminescent material layer.

[0017] In one possible implementation of this application, the end of the light-emitting material layer located on the first side away from the pixel opening and the end of the isolation structure located on the second side facing the isolation opening form a first straight line, and the first straight line forms a first angle with the plane where the substrate is located; The end of the light-emitting material layer located on the second side away from the corresponding pixel opening and the end of the isolation structure located on the first side facing the corresponding isolation opening form a second straight line, and the second straight line forms a second included angle with the plane where the substrate is located; The first included angle is smaller than the second included angle; Preferably, on the first side, the luminescent material layer overlaps with the isolation structure; on the second side, the luminescent material layer does not overlap with the isolation structure.

[0018] In one possible implementation of this application, the isolation structure includes a first isolation portion and a second isolation portion stacked together, the second isolation portion being disposed on the side of the first isolation portion away from the substrate, and the orthographic projection of the first isolation portion on the substrate being located within the orthographic projection of the second isolation portion on the substrate. Preferably, the second isolation portion is a conductive isolation portion, and the first electrode overlaps with the sidewall of the second isolation portion facing the corresponding isolation opening; Preferably, the isolation structure further includes a third isolation portion, wherein the third isolation portion, the first isolation portion, and the second isolation portion are stacked sequentially in a direction away from the substrate, and the orthographic projection of the first isolation portion on the substrate is located within the orthographic projection of the third isolation portion on the substrate; Preferably, the orthographic projection of the third isolation portion on the substrate is located within the orthographic projection of the second isolation portion on the substrate; Preferably, the third isolation portion is a conductive isolation portion, and the first electrode is also electrically connected to the third isolation portion; Preferably, the material of the first isolation part includes aluminum, silver or copper, the material of the second isolation part includes titanium or molybdenum, and the material of the third isolation part includes molybdenum or titanium.

[0019] In one possible implementation of this application, the display panel further includes a first encapsulation layer, the first encapsulation layer including a plurality of encapsulation units, the encapsulation units being located on the side of the light-emitting device away from the substrate, at least a portion of the encapsulation units being located within the isolation opening, and at least a portion of the encapsulation units extending along the sidewall of the isolation structure toward the isolation opening to the side of the isolation structure away from the substrate. Preferably, the display panel further includes a second encapsulation layer, the side of the second encapsulation layer away from the substrate having a flat surface; Preferably, the display panel further includes a third encapsulation layer, the third encapsulation layer being located on the side of the second encapsulation layer away from the substrate; Preferably, the first encapsulation layer and the third encapsulation layer are inorganic encapsulation layers, and the second encapsulation layer is an organic encapsulation layer.

[0020] A second aspect of this application also provides a display panel, the display panel comprising: substrate; A leveling layer is located on the substrate, and the leveling layer is used to reduce the unevenness of the substrate surface; A pixel defining layer is located on the side of the planarization layer away from the substrate and covers the planarization layer, wherein the pixel defining layer defines a plurality of pixel openings on the substrate; An isolation structure is located on the pixel defining layer and encloses an isolation opening that communicates with the pixel opening. In the region where the flattening layer is set, the surface of the substrate has a third flatness, and the side of the isolation structure away from the substrate has a fourth flatness. The third flatness is greater than the fourth flatness, wherein the smaller the flatness, the flatter the corresponding surface. The light-emitting device is located at least partially within the pixel opening.

[0021] In one possible implementation of this application, the display panel further includes: the light-emitting device is electrically connected to a transistor in the substrate through a first electrode via; The orthographic projection of the first electrode via on the substrate lies within the orthographic projection of the planarization layer on the substrate.

[0022] In one possible implementation of this application, the orthographic projection of the first electrode via on the substrate overlaps at most with the orthographic projection portion of the isolation structure on the substrate; Alternatively, the orthographic projection of the first electrode via on the substrate is misaligned with the orthographic projection of the isolation structure on the substrate, and the orthographic projection of the first electrode via on the substrate is located between the orthographic projection of the isolation structure on the substrate and the orthographic projection of the pixel opening on the substrate.

[0023] A third aspect of this application also provides a method for manufacturing a display panel, the method comprising: Provide a substrate; An organic material layer is fabricated on the substrate to mitigate the unevenness of the substrate surface, and the organic material layer is patterned to obtain a smooth layer. A pixel defining material layer and an isolation material layer are sequentially fabricated on the side of the planarization layer away from the substrate; The isolation material layer is etched to form an isolation structure and an isolation opening; The pixel defining material layer exposed at the isolation opening is etched to form a pixel defining layer and a pixel opening, wherein the orthographic projection of the pixel defining layer on the substrate covers the orthographic projection of the planarization layer on the substrate; A light-emitting device is fabricated within the pixel opening.

[0024] In one possible implementation of this application, after the step of providing a substrate, the method includes: A conductive material layer is fabricated on the substrate, and the conductive material layer is patterned to form a first electrode, wherein the first electrode is connected to a transistor in the substrate through a first electrode via. The step of fabricating an organic material layer on the substrate to mitigate the unevenness of the substrate surface, and then patterning the organic material layer to obtain a smooth layer, includes: An organic material layer is fabricated on the substrate, and the organic material layer is patterned to obtain a flat layer that at least covers the first electrode via.

[0025] In one possible implementation of this application, the step of etching the pixel defining material layer exposed at the isolation opening to form a pixel defining layer and a pixel opening includes: The pixel defining material layer and the planarization layer are etched on the first side of the isolation opening to form a pixel defining layer that extends relative to the planarization layer and has a gap with the first electrode. The pixel defining material layer is etched on the second side of the isolation opening to form a pixel defining layer that extends relative to the planarization layer and has a gap with the first electrode. The pixel opening is formed by the pixel defining layer obtained after etching, wherein the first side and the second side are opposite sides of the isolation opening.

[0026] A fourth aspect of this application also provides an electronic device, the electronic device comprising a display panel as described in any possible implementation of the first or second aspect, or a display panel prepared by any possible implementation of the third aspect. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram illustrating the area distribution of the display panel is provided. Figure 2 Example Figure 1 One of the schematic diagrams of a partial film layer cross-section structure in the BB direction of a local area of ​​a display panel; Figure 3 Example Figure 1Schematic diagram of a partial cross-sectional structure of the film layer in the BB direction of a local area of ​​the display panel; Figure 4 An example is a schematic diagram of a pixel circuit structure; Figure 5 A schematic diagram of the film structure of the light-emitting material layer in a light-emitting device is shown in the example. Figure 6 A schematic diagram of the cross-sectional structure of some film layers in a display panel is shown; Figure 7 A schematic diagram of an isolation structure is shown; Figure 8 Another schematic diagram of the isolation structure is shown; Figure 9 Example Figure 1 Schematic diagram three of the partial film layer cross-section structure in the BB direction of a local area of ​​the display panel; Figure 10 Example Figure 1 Schematic diagram of a partial cross-sectional structure of the film layer in the BB direction of a local area of ​​the display panel; Figure 11 A flowchart illustrating the method for manufacturing the display panel provided in this embodiment is shown. Figure 12-1 and Figure 12-2 Example Figure 11 The corresponding process flow diagram; Figure 13 This example illustrates one possible process flow for etching to form the pixel delimiting layer in this embodiment.

[0029] Icons: 1-Display panel; 11-Substrate; 1101-Substrate; 1103-Buffer layer; 1104-Active layer; 1105-Gate; 1106-Source; 1107-Drain; 1108-First insulating layer; 1109-Second insulating layer; 1110-Gate insulating layer; 1111-First capacitor electrode; 1112-Second capacitor electrode; 1114-Planing layer; 1115-First electrode via; 110-Transistor; 12-Isolation structure; 12a-First isolation structure; 12b-Second isolation structure; 12c-Third isolation structure; 1201-Isolation opening; 12011-First side; 12012-Second side; 1201a-First isolation opening; 1201b-Second isolation opening; 1201c-Third isolation opening; 121-First isolation portion; 122-Second isolation portion; 123 - Third isolation layer; 13- Light-emitting device; 131- First electrode; 132- Light-emitting material layer; 133- Second electrode; 13a- First light-emitting device; 13b- Second light-emitting device; 13c- Third light-emitting device; 14- Planarization layer; 15- Pixel defining layer; 1501- Pixel opening; 1501a- First pixel opening; 1501b- Second pixel opening; 1501c- Third pixel opening; 161- First encapsulation layer; 1611- Encapsulation unit; 1611a- First encapsulation unit; 1611b- Second encapsulation unit; 1611c- Third encapsulation unit; 162- Second encapsulation layer; 163- Third encapsulation layer; 18- Transistor; 19- Planarization layer; 20- Organic material layer; 30- Pixel defining material layer; 40- Isolation material layer; 41- First isolation material layer; 42- Second isolation material layer. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0032] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0033] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0034] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this application is in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. For example, for certain elements, sometimes the terms "upper" or "above" are used when describing the position of an element located in the Z direction, and "lower" or "below" are used when describing the position of an element located in the opposite direction. In addition, when using terms such as "upper," "above," "lower," "below," and "relative" to define the positional relationship between two elements, it includes not only the state in which the two elements are directly connected, but also the state in which the two elements are separated by a gap or other elements. Furthermore, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0035] In the field of display technology, increasing the density of light-emitting devices (i.e., pixel density) in display panels is an important way to improve display performance. However, display panels currently manufactured using Fine Metal Mask (FMM) technology are limited by technology and cannot further increase the density of light-emitting devices. Through long-term research, the inventors discovered that to solve the technical problem of not being able to further increase the density of light-emitting devices, an isolation structure can be incorporated into some display panels. During the full-layer evaporation of the light-emitting material layer and cathode, the light-emitting material layer and cathode can be separated at the isolation structure location. Through multiple evaporation and etching processes, light-emitting devices of different colors can be formed in different isolation openings, thus fabricating display panels through patterned light-emitting devices.

[0036] In display panels, some light-emitting devices exhibit malfunctions. To address these technical problems, the inventors have innovatively designed the following technical solutions, which will be described in detail below with reference to the accompanying drawings. It should be noted that the deficiencies in the existing solutions described above are the result of the inventors' practical experience and careful research. Therefore, the discovery process of the aforementioned technical problems and the solutions proposed in this embodiment below are contributions made by the inventors to this application during the invention process, and should not be construed as technical content known to those skilled in the art.

[0037] Figure 1 This is a schematic diagram of the structure of a display panel 1 according to one embodiment of this application. The display panel 1 can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. The display panel 1 includes a display area AA with display function and a non-display area NA.

[0038] The display area AA of the display panel 1 can be rectangular, square, circular, elliptical, or other shapes. The non-display area NA can at least partially surround the display area AA. Preferably, the non-display area NA surrounds the entire display area AA and is a ring corresponding to the shape of the display area AA. For example, when the display area AA is rectangular, the shape of the non-display area NA is a rectangular ring; when the display area AA is circular, the shape of the non-display area NA is a circular ring.

[0039] The display area AA includes a plurality of pixels PX arranged in the X and Y directions. Each pixel PX includes a plurality of sub-pixels SPX displaying different colors. In some embodiments, a pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. For example, the first sub-pixel SPX1 is a blue sub-pixel, the second sub-pixel SPX2 is a green sub-pixel SPX2, and the third sub-pixel SPX3 is a red sub-pixel SPX3. In some embodiments, in addition to sub-pixels SPX1, SPX2, and SPX3, a pixel PX also includes sub-pixels SPX that emit white or other colors of light.

[0040] A sub-pixel (SPX) includes a pixel circuit and a light-emitting device driven by the pixel circuit to emit light of the corresponding color. The first sub-pixel (SPX1) includes a first light-emitting device, the second sub-pixel (SPX2) includes a second light-emitting device, and the third sub-pixel (SPX3) includes a third light-emitting device. One pixel circuit drives at least one light-emitting device to emit light. For example, the display area AA includes a normal display area and a light-transmitting display area. The light-transmitting display area is a display area set according to a corresponding sensor and has light-transmitting properties, while the normal display area is a display area not set according to a corresponding sensor. In the normal display area, one pixel circuit drives one light-emitting device to emit light, and in the light-transmitting display area, one pixel circuit drives one or more light-emitting devices to emit light.

[0041] In one implementation, Figure 2 It shows Figure 1 A schematic diagram of a partial cross-sectional structure of the film layer in the BB direction of a local area of ​​the display panel 1. (Reference) Figure 2 The display panel 1 includes a substrate 11, a planarization layer 14, a pixel defining layer 15, an isolation structure 12, and a light-emitting device 13.

[0042] A planarization layer 14 is located on the substrate 11. In the region where the planarization layer 14 is located, the surface of the substrate 11 has a first flatness, and the side of the planarization layer 14 away from the substrate 11 has a second flatness. The first flatness is greater than the second flatness. Flatness is a parameter used to characterize the flatness of an object's surface; the smaller the flatness, the flatter the surface. Since the substrate 11 has a multi-layer structure, pixel circuits are formed within the substrate 11, resulting in poor surface flatness of the substrate 11 and poor flatness of the films fabricated on the substrate 11. By providing a planarization layer 14 on the surface of the substrate 11, the surface flatness of the subsequently fabricated films can be improved.

[0043] The pixel defining layer 15 is located on the side of the planarization layer 14 away from the substrate 11. The pixel defining layer 15 defines a plurality of pixel openings 1501 on the substrate 11. The orthographic projection of the pixel defining layer 15 on the substrate 11 covers the orthographic projection of the planarization layer 14 on the substrate 11.

[0044] An isolation structure 12 is located on the pixel defining layer 15 and encloses an isolation opening 1201 that communicates with the pixel opening 1501. The pixel opening 1501 and the isolation opening 1201 correspond one-to-one. The orthographic projection of the pixel opening 1501 onto the substrate 11 lies within the orthographic projection of the corresponding isolation opening 1201 onto the substrate 11. The isolation opening 1201 can be used to accommodate a light-emitting device 13, wherein the light-emitting device 13 is at least partially located within the pixel opening 1501. The isolation structure 12 forms an undercut structure, which allows the light-emitting device layer (such as a light-emitting material layer or an electrode layer) deposited over the entire surface to be disconnected at this location, so that the film layer of the light-emitting device can be independently formed in different pixel openings 1501.

[0045] The inventors discovered that the main problem causing the poor display of the light-emitting device 13 is due to the etching of the light-emitting device 13. Taking the blue light-emitting device, green light-emitting device and red light-emitting device manufactured in sequence as an example, the blue light-emitting device and green light-emitting device manufactured first have display problems. The main reason for the above defects is that when manufacturing the subsequent light-emitting device 13 (e.g., red light-emitting device), due to the distribution of the underlying traces, the surface flatness of the pixel defining layer 15 away from the substrate 11 is poor. The electrode layer of the manufactured light-emitting device 13 cannot be continuously distributed on the side away from the substrate 11. As a result, when etching away the device film layer (e.g., the light-emitting material layer and electrode layer of the red light-emitting device) and the encapsulation layer on the first manufactured light-emitting device 13 (e.g., blue light-emitting device) and the encapsulation layer, the electrode layer cannot block the dry etching gas used to etch away the encapsulation layer. This causes the dry etching gas to over-etch the film layer below the electrode layer. Finally, during the patterning process of the subsequently manufactured light-emitting device, the film layer of the first manufactured light-emitting device 13 will be etched and damaged, thus making the first manufactured light-emitting device 13 unable to display.

[0046] The above-described solution provided in this embodiment provides a planarization layer 14 between the substrate 11 and the pixel defining layer 15. The surface of the substrate 11 has a first flatness, and the side of the planarization layer 14 away from the substrate 11 has a second flatness. The first flatness is greater than the second flatness, that is, the planarization layer 14 can improve the flatness of the side of the pixel defining layer 15 away from the substrate 11. When the device film layer is deposited on the entire surface, a continuous electrode film layer can be formed on the side away from the substrate 11. During the subsequent patterning and removal of the film layer deposited on the previously fabricated light-emitting device 13, the continuous electrode film layer can block the dry etching gas to ensure that the film layer below the electrode film layer is not over-etched by the dry etching gas, thereby ensuring that the film layer of the previously fabricated light-emitting device 13 is not etched and damaged during the subsequent patterning process of the light-emitting device, and the previously fabricated light-emitting device 13 can emit light normally.

[0047] In one embodiment, the pixel defining layer 15 is made of an inorganic material, such as an inorganic insulating material made of at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). That is, the pixel defining layer 15 can be a single-layer structure of silicon oxide (SiOx) or silicon nitride (SiNx), or a stacked structure formed by alternating silicon oxide and silicon nitride.

[0048] The material of the leveling layer 14 is an organic material. The leveling layer 14 can be formed by coating or pouring, etc. For example, the leveling layer 14 can be an organic adhesive. The organic adhesive has a certain fluidity and can fill the unevenness on the surface of the substrate 11 better, so that the flatness of the film layer on the substrate 11 after adding the leveling layer 14 is less than the flatness of the film layer on the substrate 11 before adding the leveling layer 14.

[0049] In one embodiment, in order to ensure that the side of the isolation structure 12 away from the substrate 11 has a surface with less flatness, the isolation structure 12 can be provided with a position area having a pair of flattening layers 14, that is, the orthographic projection of the isolation structure 12 on the substrate 11 is located within the orthographic projection of the flattening layer 14 on the substrate 11.

[0050] In one implementation, please refer again. Figure 2 The distance d between one end of the planarization layer 14 facing the pixel opening 1501 and the sidewall of the corresponding pixel opening 1501 is 0.5 micrometers to 2 micrometers. For example, the distance d between one end of the planarization layer 14 facing the pixel opening 1501 and the sidewall of the corresponding pixel opening 1501 includes 0.5 micrometers, 0.55 micrometers, 0.58 micrometers, 0.65 micrometers, 0.72 micrometers, 0.78 micrometers, 0.85 micrometers, 0.96 micrometers, 1 micrometer, 1.05 micrometers, 1.13 micrometers, 1.25 micrometers, 1.35 micrometers, 1.5 micrometers, 1.64 micrometers, 1.75 micrometers, 1.83 micrometers, 1.9 micrometers, 1.93 micrometers, or 2 micrometers, etc. This design allows the flattening layer 14 and the pixel opening 1501 to be separated by the pixel defining layer 15, preventing the flattening layer 14 from connecting the light-emitting devices 13 within adjacent isolation openings 1201. Since the flattening layer 14 is generally made of organic material, this ensures that the independent encapsulation performance of each light-emitting device 13 is not affected, preventing moisture from entering adjacent light-emitting devices 13 through the flattening layer 14 after the encapsulation of one light-emitting device 13 fails. The aforementioned distance setting ensures that the flattening layer 14 can improve the flatness of the surface of the pixel defining layer 15 away from the substrate 11, while also ensuring that the light-emitting devices 13 within adjacent isolation openings 1201 are not connected by the flattening layer 14.

[0051] Further, please refer to Figure 3 The substrate 11 has a multi-layer structure, which can form a pixel circuit, wherein the pixel circuit includes a transistor 110.

[0052] The substrate 11 includes a substrate 1101, a plurality of conductive layers stacked on the substrate 1101, and an insulating layer located between adjacent conductive layers, wherein the conductive layers include metal layers.

[0053] Optionally, the substrate 11 includes a first conductive layer M1, a second conductive layer M2 and a third conductive layer M3 sequentially stacked in the direction away from the substrate 1101.

[0054] In detail, the following is combined with Figure 3 The specific film structure of substrate 11 is described below.

[0055] The substrate 11 includes a buffer layer 1103, an active layer 1104, a plurality of conductive layers, and an insulating layer located between adjacent conductive layers, which are sequentially stacked on the substrate 1101.

[0056] A buffer layer 1103 is located on one side of the substrate 1101, and an active layer 1104 is located on the side of the buffer layer 1103 away from the substrate 1101. In this embodiment, the buffer layer 1103 may be formed from inorganic materials, such as silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the buffer layer 1103 may be a bilayer structure consisting of a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer sequentially formed on the substrate 1101.

[0057] An active layer 1104 is formed on and partially covers a buffer layer 1103. The active layer 1104 can be formed of an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon), an organic semiconductor, or an oxide semiconductor. The active layer 1104 can have a source region (S), a drain region (D), and a channel region (P-Si).

[0058] Multiple conductive layers and insulating layers located between adjacent conductive layers form a gate insulating layer 1110, a gate 1105, a source 1106, a drain 1107, a first insulating layer 1108, a second insulating layer 1109, and a first capacitor electrode 1111 and a second capacitor electrode 1112 for forming a capacitor.

[0059] A gate insulating layer 1110 is formed on the active layer 1104 and the buffer layer 1103 not covered by the active layer 1104 to insulate and isolate the active layer 1104 and the gate 1105. The gate insulating layer 1110 may be made of materials such as silicon oxide or silicon nitride, but is not limited thereto.

[0060] A gate 1105 is formed on one side of the gate insulating layer 1110 at the corresponding position of the active layer 1104. The gate 1105 can be formed using one or more of the following metals: Al, Mo, Cu, Ti, or other low-resistivity metals. Simultaneously, a first capacitor electrode 1111 is formed on the gate insulating layer 1110. This first capacitor electrode 1111 is formed on and partially covers the gate insulating layer 1110. The first capacitor electrode 1111 and the gate 1105 can be made of the same material. For example, a first conductive layer M1 can be fabricated on the gate insulating layer 1110, and the first capacitor electrode 1111 and the gate 1105 can be formed from the first conductive layer M1, thus achieving the simultaneous fabrication of the gate 1105 and the first capacitor electrode 1111.

[0061] A second insulating layer 1109 is formed on the gate insulating layer 1110 and covers the gate 1105 and the first capacitor electrode 1111. The second capacitor electrode 1112 is located on the side of the second insulating layer 1109 corresponding to the first capacitor electrode 1111 that is away from the substrate 1101. The orthographic projection of the second capacitor electrode 1112 on the substrate 1101 overlaps with the orthographic projection of the first capacitor electrode 1111 on the substrate 1101. The second insulating layer 1109 is used to insulate the gate 1105 from the source 1106 and the drain 1107, and to insulate the first capacitor electrode 1111 from the second capacitor electrode 1112. The second insulating layer 1109 electrically insulates the gate 1105 from the source 1106 and the drain 1107, respectively, and allows the first capacitor electrode 1111 and the second capacitor electrode 1112 to form a capacitor. The second insulating layer 1109 can also be formed of inorganic materials, such as silicon nitride and silicon oxide. The second capacitor electrode 1112 is located in the second conductive layer M2 fabricated above the second insulating layer 1109.

[0062] A first insulating layer 1108 is formed on the second insulating layer 1109 and covers the second capacitor electrode 1112, serving to isolate the source electrode 1106, drain electrode 1107, and second capacitor electrode 1112, thereby insulating them from each other. The first insulating layer 1108 can also be formed of inorganic materials (such as silicon nitride and silicon oxide). The structure of the first insulating layer 1108 can be a two-layer or three-layer structure formed of silicon nitride and silicon oxide.

[0063] Source 1106 and drain 1107 are formed on the first insulating layer 1108. Source 1106 is electrically connected to the source region (S) in the active layer 1104 through a via, and drain 1107 is electrically connected to the drain region (D) in the active layer 1104 through a via. The electrode materials of gate 1105, source 1106, drain 1107, first capacitor electrode 1111, and second capacitor electrode 1112 can all be one or more of metals such as Al, Mo, Cu, Ti, or other low-resistivity metals. Source 1106 and drain 1107 are located in a third conductive layer M3 formed on the first insulating layer 1108. In this embodiment, a thin film transistor (TFT) 110 is formed by gate 1105, source 1106, drain 1107, and active layer 1104.

[0064] The display panel 1 also includes a planarization layer 1114 located on the side of the third conductive layer M3 away from the substrate 1101. The planarization layer 1114 includes a first electrode via 1115 penetrating the planarization layer 1114. The light-emitting device 13 is electrically connected to the source 1106 or drain 1107 of the transistor through the first electrode via 1115 penetrating the planarization layer 1114. For example, Figure 3As shown, the light-emitting device 13 is electrically connected to the drain 1107 of the transistor through a first electrode via 1115 penetrating the planarization layer 1114. In this embodiment, the material of the planarization layer 1114 is an organic material.

[0065] The substrate 11 also includes scan lines that provide scan signals Scan for the pixel circuit and data lines that provide data signals Data.

[0066] like Figure 4 As shown, the pixel circuit includes a driving transistor T1 and a data transistor T2. The source of the data transistor T2 is connected to the data line that provides the data signal Data, the gate of the data transistor T2 is connected to the scan line that provides the scan signal Scan, and the drain of the data transistor T2 is connected to the gate of the driving transistor T1. The two ends of the storage capacitor C1 are respectively connected to the gate and the source of the driving transistor T1, and the drain of the driving transistor T1 is connected to the light-emitting device 13. Figure 4 This is one implementation of a pixel circuit; the pixel circuit described in this application is not limited to... Figure 4 The 2T1C pixel circuit shown can also be other pixel circuits, such as 7T1C, 8T1C pixel circuits, etc.

[0067] The film layer structure in the substrate 11 described above is merely illustrative. In other embodiments, those skilled in the art can also adjust the film layer in the substrate 11 according to actual needs.

[0068] In one possible implementation, since the presence of the first electrode via 1115 causes unevenness in the upper film layer at the corresponding location, to solve the above problem, a flattening layer 14 can be disposed above the first electrode via 1115 to reduce the influence of the first electrode via 1115 on the flatness of the upper film layer. That is, the orthographic projection of the first electrode via 1115 on the substrate 11 can be located within the orthographic projection of the flattening layer 14 on the substrate 11.

[0069] Furthermore, since the flattening layer 14 can alleviate the problem of unevenness of the upper film layer caused by the first electrode via 1115, the first electrode via 1115 does not need to be located far from the pixel opening 1501. The orthographic projection of the first electrode via 1115 on the substrate 11 can overlap with the orthographic projection of the isolation structure 12 on the substrate 11 at most. For example, the first electrode via 1115 can be located in the area corresponding to the isolation structure 12 and the pixel opening 1501, that is, the orthographic projection of the first electrode via 1115 on the substrate 11 does not overlap or misalign with the orthographic projection of the isolation structure 12 on the substrate 11, and the orthographic projection of the first electrode via 1115 on the substrate 11 is located between the orthographic projection of the isolation structure 12 on the substrate 11 and the orthographic projection of the pixel opening 1501 on the substrate 11. This design can reduce the impact of unevenness on the surface of the isolation structure 12 caused by the first electrode via 1115, while also reducing the size of the pixel defining layer 15 between adjacent pixel openings 1501, which is beneficial to improving the aperture ratio of the pixel openings 1501.

[0070] Please refer to this again. Figure 3 The light-emitting device 13 includes a first light-emitting device 13a, a second light-emitting device 13b, and a third light-emitting device 13c with different light-emitting colors. The isolation opening 1201 includes a first isolation opening 1201a, a second isolation opening 1201b, and a third isolation opening 1201c. At least a portion of the first light-emitting device 13a is located in the first isolation opening 1201a, at least a portion of the second light-emitting device 13b is located in the second isolation opening 1201b, and at least a portion of the third light-emitting device 13c is located in the third isolation opening 1201c. For example, the first light-emitting device 13a can be a blue light-emitting device, the second light-emitting device 13b can be a green light-emitting device, and the third light-emitting device 13c can be a red light-emitting device.

[0071] The pixel defining layer 15 is provided with a first pixel opening 1501a communicating with a first isolation opening 1201a, a second pixel opening 1501b communicating with a second isolation opening 1201b, and a third pixel opening 1501c communicating with a third isolation opening 1201c. The areas of the orthographic projections of the first pixel opening 1501a, the second pixel opening 1501b, and the third pixel opening 1501c on the substrate 11 may be the same or different. In this embodiment, the areas of the orthographic projections of the first pixel opening 1501a, the second pixel opening 1501b, and the third pixel opening 1501c on the substrate 11 are different. The shapes of the orthographic projections of the pixel opening 1501 and the corresponding isolation opening 1201 on the substrate 11 may be the same or different. In this embodiment, the shapes of the orthographic projections of the pixel opening 1501 and the corresponding isolation opening 1201 on the substrate 11 are the same. Generally speaking, the area of ​​the orthographic projection of the isolation opening 1201 on the substrate 11 is larger than the area of ​​the orthographic projection of the pixel opening 1501 connected to the isolation opening 1201 on the substrate 11.

[0072] Furthermore, please refer to again Figure 3 In this embodiment, the light-emitting device 13 further includes a first electrode 131, a light-emitting material layer 132, and a second electrode 133. In a direction away from the substrate 11 (Z direction in the figure), the first electrode 131, the light-emitting material layer 132, and the second electrode 133 are sequentially stacked. The first electrode 131 is located on the side of the pixel defining layer 15 facing the substrate 11 and is disposed on the substrate 11. The pixel defining layer 15 covers the end of the first electrode 131, and the pixel opening 1501 exposes at least a portion of the first electrode 131. The light-emitting material layers 132 of the first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c cover the pixel opening sidewall of the pixel defining layer 15 and the side of the pixel defining layer 15 facing away from the substrate 11. Each light-emitting material layer 132 is located within the pixel opening 1501 and is in contact with the first electrode 131.

[0073] The second electrodes 133 of the first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c are respectively covered with corresponding light-emitting material layers 132.

[0074] The first electrode 131 can be the anode of the light-emitting device 13, and the second electrode 133 can be the cathode of the light-emitting device 13. The first electrode 131 of each light-emitting device 13 can be connected to the pixel circuit through a via, so that the pixel circuit drives the light-emitting device 13 to emit light.

[0075] The first electrode 131 may include a multilayer structure, such as a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, using silver, a metallic material with excellent light reflectivity. Each conductive oxide layer can be formed, for example, from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The second electrode 133 is formed, for example, from a metallic material such as an alloy of magnesium and silver (MgAg).

[0076] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a light-emitting material layer 132 according to one embodiment of this application. The light-emitting material layer 132 of at least one of the first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL, stacked along a direction away from the substrate 11 (i.e., the Z direction). The light-emitting material layer 132 may include a single light-emitting material layer EML, or a stacked light-emitting structure including multiple light-emitting material layers EML.

[0077] In order for the light-emitting material layer 132 to emit light, a pixel voltage is provided to the first electrode 131 and a common voltage (e.g., ELVSS voltage) is provided to the second electrode 133. A potential difference is formed between the first electrode 131 and the second electrode 133, causing the light-emitting material layer 132 disposed between the first electrode 131 and the second electrode 133 to emit light. In one possible embodiment, if a potential difference is formed between the first electrode 131 and the second electrode 133 of the first light-emitting device 13a, the light-emitting material layer EML of the light-emitting material layer 132 emits blue light; if a potential difference is formed between the first electrode 131 and the second electrode 133 of the second light-emitting device 13b, the light-emitting material layer EML of the light-emitting material layer 132 emits green light; and if a potential difference is formed between the first electrode 131 and the second electrode 133 of the third light-emitting device 13c, the light-emitting material layer EML of the light-emitting material layer 132 emits red light.

[0078] In this design, the pixel voltage of the first electrode 131 is provided by the pixel circuit 1, and the common voltage of the second electrode 133 is provided by the isolation structure 12. Specifically, the second electrode 133 is electrically connected to the isolation structure 12, and the common voltage is supplied to the second electrode 133 by providing the isolation structure 12. That is, the isolation structure 12 has the function of supplying a common voltage to the second electrode 133. For example, the isolation structure 12 can provide a common voltage signal, such as an ELVSS voltage signal, to the second electrode 133 of the light-emitting device 13.

[0079] In one possible implementation, in order to ensure that the isolation structure 12 fabricated in the location region of the flattening layer 14 has a smaller flatness on the side away from the substrate 11 so that a continuous electrode film layer can be formed in the location region subsequently, the thickness of the flattening layer 14 in this implementation meets the following requirements.

[0080] The planarization layer 14 fills at least half the depth of the first electrode via 1115, and in the direction perpendicular to the plane of the substrate 11 (Z direction in the figure), the height of the surface of the planarization layer 14 away from the substrate 11 relative to the surface of the first electrode 131 away from the substrate 11 is less than or equal to half the depth of the first electrode via 1115.

[0081] In this embodiment, in the direction perpendicular to the plane of the substrate 11, the planarization layer 14 may be slightly lower than the first electrode 131; or, the planarization layer 14 may be flush with the first electrode 131; or, the planarization layer 14 may be slightly higher than the first electrode 131.

[0082] Preferably, the surface of the planarization layer 14 away from the substrate 11 is flush with the surface of the first electrode 131 away from the substrate 11. That is, the planarization layer 14 is flush with the first electrode 131.

[0083] The edge of the first electrode 131 can also affect the flatness of the film layer above it. In order to avoid the effect of the edge of the first electrode 131 on the flatness of the film layer above it, in one possible implementation, the flattening layer 14 wraps around the edge of the first electrode 131, and the orthographic projection of the edge of the flattening layer 14 on the substrate 11 is located within the orthographic projection of the first electrode 131 on the substrate 11.

[0084] In one possible implementation, please refer to Figure 6 The isolation opening 1201 includes a first side 12011 and a second side 12012 that are opposite each other. For example, on a cross section perpendicular to the plane where the substrate 11 is located and passing through the center of the isolation opening 1201, the first side 12011 may correspond to the left side of the isolation opening 1201, and the second side 12012 may correspond to the right side of the isolation opening 1201.

[0085] On the first side 12011, the portion of the pixel defining layer 15 extending relative to the planarization layer 14 has a gap with the first electrode 131, meaning that the portion of the pixel defining layer 15 extending relative to the planarization layer 14 does not contact the first electrode 131. On the first side 12011, the pixel defining layer 15 and the planarization layer 14 form an undercut structure.

[0086] Optionally, the height h of the gap is greater than the height of the light-emitting device layer 132, so that the light-emitting device layer 132 can be isolated at this position.

[0087] On the second side 12012, the portion of the pixel defining layer 15 that extends relative to the planarization layer 14 contacts the first electrode 131.

[0088] The above design allows the light-emitting device layer 13 to be isolated on the first side of the isolation opening 1201. On the other hand, the pixel defining layer 15 on the second side wrapping the flattening layer 14 can prevent the light-emitting devices 13 in adjacent isolation openings 1201 from being connected by the flattening layer 14 (organic material layer), thus preventing damage to the independent packaging performance of each light-emitting device 13.

[0089] Furthermore, please refer to again Figure 6 The end A1 of the light-emitting material layer 132 located on the first side 12011 away from the corresponding pixel opening and the end B1 of the isolation structure 12 located on the second side 12012 facing the corresponding isolation opening 1201 form a first straight line L1, and the first straight line L1 forms a first included angle α1 with the plane where the substrate 11 is located.

[0090] The end A2 of the light-emitting material layer 132 located on the second side 12012 away from the corresponding pixel opening and the end B2 of the isolation structure 12 located on the first side 12011 facing the corresponding isolation opening 1201 form a second straight line L2, and the second straight line L2 forms a second included angle α2 with the plane where the substrate 11 is located.

[0091] In this embodiment, the first included angle α1 is smaller than the second included angle α2. That is, when depositing the light-emitting material layer 132, the light-emitting material layer 132 can be deposited in a direction closer to the first side 12011, so that the distribution amount of the light-emitting material layer 132 on the first side 12011 is greater than the distribution amount of the light-emitting material layer 132 on the second side 12012. That is, the distance between the end A1 of the light-emitting material layer 132 on the first side 12011 that is far from the corresponding pixel opening and the corresponding pixel opening is greater than the distance between the end A2 of the light-emitting material layer 132 on the second side 12012 that is far from the corresponding pixel opening and the corresponding pixel opening.

[0092] Because the first side 12011 has an undercut structure, even if the light-emitting material layer 132 overlaps with the isolation structure 12, there will be no leakage. Furthermore, since the light-emitting material layer 132 is deposited biased towards the first side 12011 during evaporation, the light-emitting material layer 132 on the second side 12012 will not overlap with the isolation structure 12, thus preventing leakage on the second side 12012. This design avoids leakage caused by the overlap of the light-emitting material layer 132 with the isolation structure 12, preventing display defects in the display panel 1 due to such leakage.

[0093] In detail, in this embodiment, on the first side 12011, the light-emitting material layer 132 overlaps with the isolation structure 12. On the second side 12012, the light-emitting material layer 132 does not overlap with the isolation structure 12.

[0094] Furthermore, in one possible implementation, please refer to Figure 7 In the direction away from the substrate 11 (Z direction in the figure), the isolation structure 12 includes a first isolation portion 121 and a second isolation portion 122. The orthographic projection of the first isolation portion 121 on the substrate 11 is located within the orthographic projection of the second isolation portion 122 on the substrate 11, that is, the second isolation portion 122 extends toward the corresponding isolation opening 1201 relative to the first isolation portion 121.

[0095] The first isolation portion 121 and the second isolation portion 122 are made of different materials, and the etching rate of the second isolation portion 122 is lower than that of the first isolation portion 121. The material of the first isolation portion 121 includes conductive materials, specifically including at least one of aluminum (Al) and aluminum alloys, and the aluminum alloys may include at least one of aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). The second isolation portion 122 can be a single-layer structure or a multi-layer structure. When the second isolation portion 122 is a single-layer structure, the material of the second isolation portion 122 may include at least one of titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy. When the second isolation portion 122 is a multi-layer structure, one layer of the second isolation portion 122 is made of at least one of titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy, and the other layer of the second isolation portion 122 may be made of conductive oxides or inorganic insulating materials, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0096] In some embodiments, please refer to Figure 8The isolation structure 12 may further include a third isolation portion 123 located on the side of the first isolation portion 121 near the substrate 11. The third isolation portion 123 protrudes relative to the first isolation portion 121 in the direction toward the isolation opening 1201, and the orthographic projection of the first isolation portion 121 on the substrate 11 lies within the orthographic projection of the third isolation portion 123 on the substrate 11. The material of the third isolation portion 123 may include at least one of molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb).

[0097] Furthermore, in one possible implementation, please refer to Figure 9 The display panel 1 also includes a thin-film encapsulation layer located on the light-emitting side of the light-emitting device 13. The thin-film encapsulation layer includes a first encapsulation layer 161, which includes multiple encapsulation units 1611. Each encapsulation unit 1611 is located on the side of the first electrode 131 facing away from the substrate 11 and extends through the sidewall of the isolation structure 12 to the side of the isolation structure 12 facing away from the substrate 11. The multiple encapsulation units 1611 include multiple first encapsulation units 1611a corresponding to multiple first light-emitting devices 13a, multiple second encapsulation units 1611b corresponding to multiple second light-emitting devices 13b, and multiple third encapsulation units 1611c corresponding to multiple third light-emitting devices 13c. The first encapsulation unit 1611a is located on the side of the corresponding first light-emitting device 13a facing away from the substrate 11, the second encapsulation unit 1611b is located on the side of the corresponding second light-emitting device 13b facing away from the substrate 11, and the third encapsulation unit 1611c is located on the side of the corresponding third light-emitting device 13c facing away from the substrate 11.

[0098] For example, two adjacent packaging units 1611 for encapsulating light-emitting devices 13 of different colors are disconnected on the side of the isolation structure 12 away from the substrate 11; two adjacent packaging units 1611 for encapsulating light-emitting devices 13 of the same color can be connected to each other on the side of the isolation structure 12 away from the substrate 11.

[0099] Further, please refer to Figure 10 In this embodiment, the thin-film encapsulation layer further includes a second encapsulation layer 162, which covers the isolation structure 12 and the encapsulation unit 1611. Exemplarily, the second encapsulation layer 162 has a flat surface on the side away from the substrate 11.

[0100] Furthermore, please refer to again Figure 10 The thin-film encapsulation layer also includes a third encapsulation layer 163, which is located on the side of the second encapsulation layer 162 away from the substrate 11.

[0101] Optionally, the first encapsulation layer 161 and the third encapsulation layer 163 are inorganic encapsulation layers, and the second encapsulation layer 162 is an organic encapsulation layer. For example, the first encapsulation layer 161 and the third encapsulation layer 163 can be formed by chemical vapor deposition (CVD), and the second encapsulation layer 162 can be formed by inkjet printing (IJP). The materials of the first encapsulation layer 161 and the third encapsulation layer 163 include at least one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON). The second encapsulation layer 162 is an organic insulating material, such as epoxy resin, acrylic resin, or other resin materials. The second encapsulation layer 162 and the third encapsulation layer 163 are continuously disposed at least over the entire display area AA, with a portion also disposed in the bezel area NA.

[0102] It is understood that the display panel 1 may also include a touch function layer, an optical adhesive layer, a polarizer and a cover plate, etc., which are stacked sequentially on the side of the third encapsulation layer 163 away from the substrate 11. The above-mentioned film layers are conventional film layers of the display panel 1, and will not be described in detail here.

[0103] Based on the same concept, this embodiment also provides a display panel, please refer again. Figure 2 The display panel 1 includes a substrate 11, a planarization layer 14, a pixel defining layer 15, an isolation structure 12, and a light-emitting device 13.

[0104] The planarization layer 14 is located on the substrate 11. Since the substrate 11 has a multi-layer structure, a pixel circuit 110 is formed inside the substrate 11. This results in poor flatness of the surface of the substrate 11 and poor flatness of the film layer fabricated on the substrate 11. By setting the planarization layer 14 on the surface of the substrate 11, the surface flatness of the film layer fabricated in the subsequent process can be improved.

[0105] The pixel defining layer 15 is located on the side of the planarization layer 14 away from the substrate 11. The pixel defining layer 15 defines a plurality of pixel openings 1501 on the substrate 11. The orthographic projection of the pixel defining layer 15 on the substrate 11 covers the orthographic projection of the planarization layer 14 on the substrate 11.

[0106] An isolation structure 12 is located on the pixel defining layer 15 and encloses an isolation opening 1201 that communicates with the pixel opening 1501. The pixel opening 1501 and the isolation opening 1201 correspond one-to-one. The orthographic projection of the pixel opening 1501 onto the substrate 11 lies within the orthographic projection of the corresponding isolation opening 1201 onto the substrate 11. The isolation opening 1201 can be used to accommodate a light-emitting device 13, wherein at least a portion of the light-emitting device 13 is located within the pixel opening 1501. The isolation structure 12 forms an undercut structure, which allows the entire vapor-deposited light-emitting device layer (such as a light-emitting material layer or an electrode layer) to be disconnected at this location, so that the film layer of the light-emitting device can be independently formed in different pixel openings 1501.

[0107] In this embodiment, in the region where the flattening layer 14 is set, the surface of the substrate 11 has a third flatness, and the side of the isolation structure 12 away from the substrate 11 has a fourth flatness. The third flatness is greater than the fourth flatness. Flatness is a parameter used to characterize the flatness of an object's surface. The smaller the flatness, the flatter the surface.

[0108] Through the above design, by setting the flatness of the pixel defining layer 15 away from the substrate 11, a continuous electrode film can be formed on the side away from the substrate 11 when the device film layer is deposited on the whole surface. In the subsequent process of patterning and removing the film layer deposited on the previously fabricated light-emitting device 13, the continuous electrode film layer can block the dry etching gas to ensure that the film layer below the electrode film layer will not be over-etched by the dry etching gas. This ensures that the film layer of the previously fabricated light-emitting device 13 will not be etched and damaged in the subsequent patterning process of the light-emitting device, and the previously fabricated light-emitting device 13 can emit light normally.

[0109] In one possible implementation, in order to ensure that the side of the isolation structure 12 away from the substrate 11 has a surface with less flatness, the isolation structure 12 can be provided with a position area having a pair of flattening layers 14, that is, the orthographic projection of the isolation structure 12 on the substrate 11 is located within the orthographic projection of the flattening layer 14 on the substrate 11.

[0110] In one possible implementation, please refer to Figure 3 Since the presence of the first electrode via 1115 causes unevenness in the upper film layer at the corresponding location, to solve the above problem, a flattening layer 14 can be disposed above the first electrode via 1115 to reduce the influence of the first electrode via 1115 on the flatness of the upper film layer. That is, the orthographic projection of the first electrode via 1115 on the substrate 11 can be located within the orthographic projection of the flattening layer 14 on the substrate 11.

[0111] Furthermore, since the flattening layer 14 can alleviate the problem of unevenness of the upper film layer caused by the first electrode via 1115, the first electrode via 1115 does not need to be located far from the pixel opening 1501. The orthographic projection of the first electrode via 1115 on the substrate 11 can overlap with the orthographic projection of the isolation structure 12 on the substrate 11 at most. For example, the first electrode via 1115 can be located in the area corresponding to the isolation structure 12 and the pixel opening 1501, that is, the orthographic projection of the first electrode via 1115 on the substrate 11 does not overlap or misalign with the orthographic projection of the isolation structure 12 on the substrate 11, and the orthographic projection of the first electrode via 1115 on the substrate 11 is located between the orthographic projection of the isolation structure 12 on the substrate 11 and the orthographic projection of the pixel opening 1501 on the substrate 11. This design can reduce the impact of unevenness on the surface of the isolation structure 12 caused by the first electrode via 1115, while also reducing the size of the pixel defining layer 15 between adjacent pixel openings 1501, which is beneficial to improving the aperture ratio of the pixel openings 1501.

[0112] Based on the same concept, this embodiment also provides a method for manufacturing a display panel, please refer to... Figure 11 , Figure 12-1 and Figure 12-2 , Figure 11 A flowchart illustrating the display panel fabrication method is provided. Figure 12-1 and Figure 12-2 Example Figure 11 The corresponding process diagram is shown below. Figure 11 Figure 12 describes the specific steps of the preparation method of the display master provided in this embodiment.

[0113] Step S11: Provide a substrate 11.

[0114] In this embodiment, the substrate 11 has a multi-layer structure, which can form a pixel circuit, wherein the pixel circuit includes a transistor. Furthermore, the substrate also includes at least one insulating layer, which may include at least one of an inorganic layer and an organic layer. Additionally, the substrate 11 includes scan lines providing a scan signal Scan and data lines providing a data signal Data for the pixel circuit.

[0115] Please refer to Figure 4 The pixel circuit includes a driving transistor T1 and a data transistor T2. The source of the data transistor T2 is connected to the data line that provides the data signal Data, the gate of the data transistor T2 is connected to the scan line that provides the scan signal Scan, and the drain of the data transistor T2 is connected to the gate of the driving transistor T1. The two ends of the storage capacitor C1 are respectively connected to the gate and the source of the driving transistor T1, and the drain of the driving transistor T1 is connected to the light-emitting device 13. Figure 4This is one implementation of a pixel circuit; the pixel circuit described in this application is not limited to... Figure 4 The 2T1C pixel circuit shown can also be other pixel circuits, such as 7T1C, 8T1C pixel circuits, etc.

[0116] In this embodiment, step S11 can be implemented in the following way.

[0117] A conductive material layer is fabricated on the substrate 11, and the conductive material layer is patterned to form a first electrode 131, wherein the first electrode 131 is connected to a transistor in the substrate through a first electrode via.

[0118] Step S12: An organic material layer 20 is fabricated on the substrate 11 to mitigate the unevenness of the surface of the substrate 11, and the organic material layer 20 is patterned to obtain a flat layer 14.

[0119] For example, an organic adhesive layer can be coated on the substrate 11 by coating, and the organic adhesive can be used as the organic material layer 20 in this step. Then, the organic material layer 20 can be patterned to obtain a flat layer 14 that at least covers the first electrode via.

[0120] In step S13, a pixel defining material layer 30 and an isolation material layer 40 are sequentially fabricated on the side of the planarization layer 14 away from the substrate 11.

[0121] In this step, the pixel defining material layer 30 is first fabricated by chemical vapor deposition, and then the isolation material layer 40 is fabricated.

[0122] The pixel defining material layer 30 is made of an inorganic material, such as an inorganic insulating material made of at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). That is, the pixel defining material layer 30 can be a single-layer structure of silicon oxide (SiOx) or silicon nitride (SiNx), or a stacked structure formed by alternating silicon oxide and silicon nitride.

[0123] The isolation material layer 40 may include a first isolation material layer 41 and a second isolation material layer 42 stacked together. The first isolation material layer 41 may be formed first on the side of the flat layer 14 away from the substrate 11, and then the second isolation material layer 42 may be formed on the side of the first isolation material layer 41 away from the substrate 11.

[0124] For example, the material of the first insulating material layer 41 includes a conductive material, which may specifically include at least one of aluminum (Al), aluminum alloys, and aluminum alloys may include at least one of aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi).

[0125] The second insulating material layer 42 can be a single-layer structure or a multi-layer structure. If the second insulating material layer 42 is a single-layer structure, its material can include at least one of titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. If the second insulating material layer 42 is a multi-layer structure, one layer of the second insulating material layer 42 is made of at least one of titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy, and the other layer of the second insulating material layer 42 can be made of a conductive oxide or an inorganic insulating material. The conductive oxide may be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0126] Step S14: Etch the isolation material layer 40 to form the isolation structure 12 and the isolation opening 1201.

[0127] In one possible implementation, please refer to Figure 3 The isolation opening 1201 includes a plurality of first isolation openings 1201a, a plurality of second isolation openings 1201b and a plurality of third isolation openings 1201c.

[0128] Step S15: Etch the pixel defining material layer 30 exposed at the isolation opening 1201 to form the pixel defining layer 15 and the pixel opening 1501.

[0129] In this embodiment, the orthographic projection of the pixel defining layer 15 on the substrate 11 covers the orthographic projection of the planarization layer 14 on the substrate 11.

[0130] Step S16: Fabricate a light-emitting device 13 within the pixel opening 1501.

[0131] In one possible implementation, the light-emitting device 13 includes a first light-emitting device 13a, a second light-emitting device 13b, and a third light-emitting device 13c that emit different colors.

[0132] At least a portion of the first light-emitting device 13a is located in the first isolation opening 1201a, at least a portion of the second light-emitting device 13b is located in the second isolation opening 1201b, and at least a portion of the third light-emitting device 13c is located in the third isolation opening 1201c. For example, the first light-emitting device 13a can be a blue light-emitting device, the second light-emitting device 13b can be a green light-emitting device, and the third light-emitting device 13c can be a red light-emitting device.

[0133] The above process will be described in detail below, taking the sequential fabrication of the first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c as an example.

[0134] First, a film layer and a first encapsulation layer for the first light-emitting device 13a are fabricated over the entire surface. The film layer of the first light-emitting device 13a includes a light-emitting material layer and a second electrode layer. The film layer and the first encapsulation layer of the first light-emitting device 13a are present at the locations of multiple first isolation openings 1201a, multiple second isolation openings 1201b, and multiple third isolation openings 1201c. The material of the first encapsulation layer includes at least one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON). The first encapsulation layer can be formed using chemical vapor deposition (CVD). The film layer and the first encapsulation layer of the first light-emitting device 13a at the locations of the multiple second isolation openings 1201b and multiple third isolation openings 1201c are etched away. Only at the locations of the multiple first isolation openings 1201a are the light-emitting material layer 133 and the second electrode 133 of the first light-emitting device 13a, as well as a first encapsulation unit 1611a for encapsulating the first light-emitting device 13a, formed.

[0135] Next, the film layer and the first encapsulation layer of the second light-emitting device 13b are fabricated on the entire surface. The film layer of the second light-emitting device 13b includes a light-emitting material layer and a second electrode layer. The film layer and the first encapsulation layer of the second light-emitting device 13b are present at the locations of the plurality of first isolation openings 1201a, the plurality of second isolation openings 1201b, and the plurality of third isolation openings 1201c. The material of the first encapsulation layer includes at least one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON). The first encapsulation layer can be formed by chemical vapor deposition (CVD). The film layer and the first encapsulation layer of the second light-emitting device 13b at the locations of the plurality of first isolation openings 1201a and the plurality of third isolation openings 1201c are etched away. Only at the locations of the plurality of second isolation openings 1201b are the light-emitting material layer 133 and the second electrode 133 of the second light-emitting device 13b, as well as the second encapsulation unit 1611b for encapsulating the second light-emitting device 13b, formed.

[0136] Then, the film layer and the first encapsulation layer of the third light-emitting device 13c are fabricated on the entire surface. The film layer of the third light-emitting device 13c includes a light-emitting material layer and a second electrode layer. The film layer and the first encapsulation layer of the third light-emitting device 13c are present at the locations of the plurality of first isolation openings 1201a, the plurality of second isolation openings 1201b, and the plurality of third isolation openings 1201c. The material of the first encapsulation layer includes at least one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON). The first encapsulation layer can be formed by chemical vapor deposition (CVD). The film layer and the first encapsulation layer of the third light-emitting device 13c at the locations of the plurality of first isolation openings 1201a and the plurality of second isolation openings 1201b are etched away. The light-emitting material layer 133 and the second electrode 133 of the third light-emitting device 13c, as well as the third encapsulation unit 1611c for encapsulating the third light-emitting device 13c, are formed only at the locations of the plurality of third isolation openings 1201c.

[0137] In one possible implementation, please refer to Figure 13 Step S15 can be achieved in the following way.

[0138] The pixel defining material layer 30 and the planarization layer 14 are etched on the first side 12011 of the isolation opening 1201 to form a pixel defining layer 15 that extends relative to the planarization layer 14 and has a gap between the extended portion and the first electrode 131. The pixel defining material layer 30 is etched on the second side 12012 of the isolation opening 1201 to form a pixel defining layer 15 that extends relative to the planarization layer 14 and has a portion in contact with the first electrode 131. The pixel opening 1501 is formed by the etched pixel defining layer 15, wherein the first side 12011 and the second side 12012 are opposite sides of the isolation opening 1201. In this embodiment, the etched area forming the pixel opening is as follows: Figure 13 In the area indicated by the dashed box, the pixel defining material layer 30 and the planarization layer 14 need to be etched on the first side 12011, while only the pixel defining material layer 30 needs to be etched on the second side 12012.

[0139] In the above implementation process, the pixel defining material layer 30 and the planarization layer 14 are etched on the first side 12011. The etching rate of the planarization layer 14 is greater than the etching rate of the pixel defining material layer 30. After etching, the planarization layer 14 is formed on the first side 12011 that is recessed relative to the pixel defining layer 15. The pixel defining layer 15 and the planarization layer 14 form an undercut structure on the first side 12011.

[0140] Based on the same inventive concept, embodiments of this application also provide an electronic device. The electronic device includes the display panel provided in this application. This electronic device may include devices with image processing capabilities, such as mobile phones, desktop computers, laptops, tablets, in-vehicle displays, wearable devices, etc. Because this electronic device includes the display panel described in this application, it has a better overall display effect, a better user experience, and stronger market competitiveness.

[0141] This application provides a display panel, a method for fabricating the display panel, and an electronic device. In the display panel, the surface of the substrate has a first flatness, and the side of the flattening layer away from the substrate has a second flatness. The first flatness is greater than the second flatness, meaning that the flattening layer can improve the flatness of the pixel defining layer on the side away from the substrate, making the side away from the substrate flatter. When depositing the device film layer across the entire surface, a continuous electrode film layer can be formed on the side away from the substrate. During the subsequent patterning and removal of the deposited film layer on the previously fabricated light-emitting device, the continuous electrode film layer can block the dry etching gas to ensure that the film layer below the electrode film layer is not over-etched by the dry etching gas, thereby ensuring that the film layer of the previously fabricated light-emitting device is not etched and damaged during the subsequent patterning process of the light-emitting device, and that the previously fabricated light-emitting device can emit light normally.

[0142] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a planarization layer on the substrate, the substrate has a first planarity in a region where the planarization layer is arranged, and a second planarity on a side of the planarization layer away from the substrate, the first planarity being greater than the second planarity, wherein a smaller planarity corresponds to a more planar surface; a pixel definition layer on the side of the planarization layer away from the substrate, the pixel definition layer defines a plurality of pixel openings on the substrate, and a normal projection of the pixel definition layer on the substrate covers a normal projection of the planarization layer on the substrate; an isolation structure on the pixel definition layer and enclosing an isolation opening in communication with the pixel opening; a light emitting device at least partially in the pixel opening.

2. The display panel of claim 1, wherein, The planarization layer is made of an organic material, and the pixel definition layer is made of an inorganic material; Preferably, the planarization layer is made of an organic glue, and the pixel definition layer is made of at least one of silicon oxide and silicon nitride.

3. The display panel of claim 1, wherein, A normal projection of the isolation structure on the substrate is within a normal projection of the planarization layer on the substrate.

4. The display panel of claim 1, wherein, A distance between an end of the planarization layer towards the pixel opening and a corresponding sidewall of the pixel opening is 0.5-2 microns.

5. The display panel according to any one of claims 1 to 4, wherein The substrate comprises a substrate, a conductive layer stacked on the substrate, and an insulating layer between adjacent conductive layers; The substrate comprises a pixel circuit formed at least by the conductive layer, and the pixel circuit comprises a transistor; The conductive layer comprises a first conductive layer, a second conductive layer, and a third conductive layer stacked on the substrate, the insulating layer comprises a first insulating layer between the first conductive layer and the second conductive layer, and a second insulating layer between the second conductive layer and the third conductive layer, the first conductive layer forms at least a gate of the transistor, and the third conductive layer forms at least a source and a drain of the transistor; The display panel further comprises a planarization layer on a side of the third conductive layer away from the substrate; The light emitting device is electrically connected to the source or the drain of the transistor through a first electrode via hole penetrating through the planarization layer; Preferably, the first insulating layer and the second insulating layer are inorganic insulating layers, and the planarization layer is made of an organic material.

6. The display panel of claim 5, wherein, A normal projection of the first electrode via hole on the substrate is within a normal projection of the planarization layer on the substrate.

7. The display panel of claim 5, wherein: A normal projection of the first electrode via hole on the substrate at most partially overlaps with a normal projection of the isolation structure on the substrate; Or, a normal projection of the first electrode via hole on the substrate is misaligned with a normal projection of the isolation structure on the substrate, and the normal projection of the first electrode via hole on the substrate is between the normal projection of the isolation structure on the substrate and a normal projection of the pixel opening on the substrate.

8. The display panel of claim 5, wherein, In a direction away from the substrate, the light emitting device comprises a first electrode, a light emitting material layer, and a second electrode stacked, and the first electrode is connected to the transistor in the pixel circuit through the first electrode via hole. Part of the first electrode is located between the pixel defining layer and the substrate, and another part of the first electrode is exposed by the pixel opening; The second electrode is connected with the isolation structure, wherein the isolation structure is a conductive isolation structure.

9. The display panel of claim 8, wherein, The planarization layer fills at least half of the depth of the first electrode via, and in a direction perpendicular to the plane in which the substrate lies, the surface of the planarization layer away from the substrate is higher than the surface of the first electrode away from the substrate by a height less than or equal to half of the depth of the first electrode via; Preferably, the surface of the planarization layer away from the substrate is flush with the surface of the first electrode away from the substrate.

10. The display panel of claim 8, wherein, The planarization layer wraps the edge of the first electrode; The edge of the planarization layer on the substrate is located within the projection of the first electrode on the substrate.

11. The display panel of claim 1, wherein, The isolation structure includes a first isolation part and a second isolation part arranged in layers, the second isolation part is arranged on the side of the first isolation part away from the substrate, and the projection of the first isolation part on the substrate is located within the projection of the second isolation part on the substrate; Preferably, the second isolation part is a conductive isolation part, and the first electrode overlaps the side wall of the second isolation part facing the corresponding isolation opening; Preferably, the isolation structure further includes a third isolation part, in a direction away from the substrate, the third isolation part, the first isolation part and the second isolation part are arranged in layers in sequence, and the projection of the first isolation part on the substrate is located within the projection of the third isolation part on the substrate; Preferably, the projection of the third isolation part on the substrate is located within the projection of the second isolation part on the substrate; Preferably, the third isolation part is a conductive isolation part, and the first electrode is electrically connected with the third isolation part; Preferably, the material of the first isolation part includes aluminum, silver or copper, the material of the second isolation part includes titanium or molybdenum, and the material of the third isolation part includes molybdenum or titanium.

12. The display panel of claim 1, wherein, The display panel further includes a first encapsulation layer, the first encapsulation layer includes a plurality of encapsulation units, the encapsulation units are located on the side of the light emitting device away from the substrate, at least part of the encapsulation units are located in the isolation opening, and at least part of the encapsulation units extend to the side of the isolation structure away from the substrate along the side wall of the isolation structure facing the isolation opening; Preferably, the display panel further includes a second encapsulation layer, and the side of the second encapsulation layer away from the substrate has a flat surface; Preferably, the display panel further includes a third encapsulation layer, and the third encapsulation layer is located on the side of the second encapsulation layer away from the substrate; Preferably, the first encapsulation layer and the third encapsulation layer are inorganic encapsulation layers, and the second encapsulation layer is an organic encapsulation layer.

13. A display panel, characterized by The display panel includes: a substrate; a planarization layer on the substrate; a pixel defining layer on the side of the planarization layer away from the substrate and covering the planarization layer, the pixel defining layer defining a plurality of pixel openings on the substrate; An isolation structure is located on the pixel defining layer and encloses an isolation opening in communication with the pixel opening. In the position area where the planarization layer is arranged, the surface of the substrate has a third flatness, and the side of the isolation structure away from the substrate has a fourth flatness. The third flatness is greater than the fourth flatness. The smaller the flatness, the more flat the surface. A light emitting device is at least partially located in the pixel opening.

14. The display panel of claim 13, wherein, The display panel further comprises that the light emitting device is electrically connected with the transistor in the substrate through a first electrode via hole. The orthographic projection of the first electrode via hole on the substrate is located in the orthographic projection of the planarization layer on the substrate.

15. The display panel of claim 14, wherein, The orthographic projection of the first electrode via hole on the substrate at most partially overlaps with the orthographic projection of the isolation structure on the substrate. Alternatively, the orthographic projection of the first electrode via hole on the substrate is misaligned with the orthographic projection of the isolation structure on the substrate. The orthographic projection of the first electrode via hole on the substrate is located between the orthographic projection of the isolation structure on the substrate and the orthographic projection of the pixel opening on the substrate.

16. A method for manufacturing a display panel, characterized by, The method comprises: providing a substrate; forming an organic material layer for reducing the unevenness of the surface of the substrate on the substrate, and patterning the organic material layer to obtain a planarization layer; sequentially forming a pixel defining material layer and an isolation material layer on the side of the planarization layer away from the substrate; etching the isolation material layer to form an isolation structure and an isolation opening; etching the pixel defining material layer exposed at the isolation opening to form a pixel defining layer and a pixel opening, wherein the orthographic projection of the pixel defining layer on the substrate covers the orthographic projection of the planarization layer on the substrate; forming a light emitting device in the pixel opening.

17. The method of producing a display panel according to claim 16, wherein After the step of providing a substrate, the method comprises: forming a conductive material layer on the substrate, and patterning the conductive material layer to form a first electrode, wherein the first electrode is connected with a transistor in the substrate through a first electrode via hole; the step of forming an organic material layer for reducing the unevenness of the surface of the substrate on the substrate, and patterning the organic material layer to obtain a planarization layer comprises: forming an organic material layer on the substrate, and patterning the organic material layer to obtain a planarization layer covering at least the first electrode via hole.

18. The method of producing a display panel according to claim 17, wherein the step of etching the pixel defining material layer exposed at the isolation opening to form a pixel defining layer and a pixel opening comprises: etching the pixel defining material layer and the planarization layer on the first side of the isolation opening to form a pixel defining layer protruding relative to the planarization layer and having a gap between the protruding part and the first electrode, and etching the pixel defining material layer on the second side of the isolation opening to form a pixel defining layer protruding relative to the planarization layer and having a contact between the protruding part and the first electrode. The pixel defining layer obtained after etching encloses the pixel opening. The first side and the second side are opposite sides of the isolation opening.

19. An electronic device, comprising: The electronic device comprises the display panel according to any one of claims 1-15, or the display panel prepared by the preparation method according to any one of claims 16-18.

Images