Magnetoresistive random access memory and manufacturing method thereof

Abstract

The invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof, and the manufacturing method of the magnetoresistive random access memory (MRAM) mainly comprises the following steps: forming a spin-orbit torque (SOT) layer on a substrate, then forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first covering layer on the MTJ, forming a second covering layer on the MTJ, forming a second covering layer on the first covering layer, and forming a second magnetic tunneling junction (MTJ) on the second covering layer. A first oxidation process is then performed to form a first spacer beside the MTJ. Wherein the bottom surface of the first covering layer is lower than the bottom surface of the first gap wall.

Description

TECHNICAL FIELD

[0001] The present application relates to a magnetoresistive random access memory (MRAM) element and a method for fabricating the same. BACKGROUND

[0002] It is known that the magnetoresistance (MR) effect is an effect in which the resistance of a material changes with an applied magnetic field. The physical quantity is defined as the difference in resistance with and without a magnetic field divided by the original resistance, and is used to represent the resistance change rate. At present, the magnetoresistance effect has been successfully applied in the production of hard disks, and has important commercial application value. In addition, using the characteristic that the giant magnetoresistance material has different resistance values in different magnetization states, a magnetic random access memory (MRAM) can also be made, which has the advantage of being able to continue to retain stored data without power.

[0003] The above-mentioned magnetoresistance effect is also applied in the field of magnetic field sensors, for example, an electronic compass component in a mobile phone matched with a global positioning system (GPS), which is used to provide the user with information about the direction of movement. At present, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art usually include: occupying a large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity, and being easily affected by temperature changes, etc., and it is necessary to further improve. SUMMARY

[0004] An embodiment of the present application discloses a method for fabricating a magnetoresistive random access memory (MRAM) element, which mainly forms a spin-orbit torque (SOT) layer on a substrate, then forms a magnetic tunneling junction (MTJ) on the SOT layer, forms a first cover layer on the MTJ, and then performs a first oxidation manufacturing process to form a first spacer on the side of the MTJ. The bottom surface of the first cover layer is lower than the bottom surface of the first spacer.

[0005] Another embodiment of the present application discloses a magnetic random access memory (MRAM) element, which mainly comprises a spin-orbit torque (SOT) layer disposed on a substrate, a magnetic tunnel junction (MTJ) disposed on the SOT layer, a first capping layer disposed beside the MTJ, a second capping layer disposed beside the first capping layer, and a spacer disposed between the first capping layer and the second capping layer.

[0006] Yet another embodiment of the present application discloses a magnetic random access memory (MRAM) element, which mainly comprises a spin-orbit torque (SOT) layer disposed on a substrate, a magnetic tunnel junction (MTJ) disposed on the SOT layer, a first capping layer disposed beside the MTJ, and a spacer disposed beside the first capping layer, wherein a bottom surface of the first capping layer is flush with a bottom surface of the spacer. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1 to 9 A schematic diagram of a method of fabricating an MRAM cell according to an embodiment of the present application;

[0008] Figures 10 to 12 A schematic diagram of a method of fabricating an MRAM cell according to an embodiment of the present application.

[0009] LIST OF SYMBOLS

[0010] 12: substrate

[0011] 14: MRAM region

[0012] 16: interlayer dielectric layer

[0013] 18: metal interconnect structure

[0014] 20: metal interconnect structure

[0015] 22: intermetal dielectric layer

[0016] 24: metal interconnect

[0017] 26: stop layer

[0018] 28: intermetal dielectric layer

[0019] 34: barrier layer

[0020] 36: metal layer

[0021] 40: logic region

[0022] 42: lower electrode

[0023] 44: SOT layer

[0024] 46: free layer

[0025] 48: barrier layer

[0026] 50: fixed layer

[0027] 60: cover layer

[0028] 62: upper electrode

[0029] 64: dielectric layer

[0030] 66: MTJ stack

[0031] 70: MTJ

[0032] 72: first cover layer

[0033] 74: intermetal dielectric layer

[0034] 76: bottom anti-reflective layer

[0035] 78: patterned mask

[0036] 80: second cover layer

[0037] 82: oxidation fabrication process

[0038] 84: intermetal dielectric layer

[0039] 86: metal interconnect

[0040] 88: stop layer

[0041] 90: intermetal dielectric layer

[0042] 92: metal interconnect

[0043] 94: stop layer

[0044] 96: doped layer

[0045] 98: spacer

[0046] 100: spacer

[0047] 102: doped region

[0048] 104: doped region

[0049] 106: patterned mask

[0050] 108: oxidation fabrication process DETAILED DESCRIPTION

[0051] Please refer to Figures 1 to 9 , Figures 1 to 9 is a schematic diagram of a method of fabricating a semiconductor device, or more specifically, an MRAM cell, in one direction, such as the X direction, according to one embodiment of the present application. As shown in Figure 1As shown, a substrate 12, such as a substrate 12 formed of a semiconductor material selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., is first provided, wherein the substrate 12 is preferably defined with an MRAM region 14 and a logic region 40.

[0052] Active (or source) devices, such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and dielectric layers, such as interlayer dielectric (ILD) 16, can be formed on the substrate 12. More specifically, the substrate 12 can include planar or non-planar (e.g., fin-type transistors) MOS transistor devices, which can include gate structures (e.g., metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, etc., and the ILD 16 can be formed on the substrate 12 and cover the MOS transistors, and the ILD 16 can have contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistors. Since the fabrication of planar or non-planar transistors and ILD are well known in the art, further description is not provided herein.

[0053] Then, metal interconnect structures 18, 20 are formed on the ILD 16 of the MRAM region 14 and electrically connected to the contact plugs described above, wherein the metal interconnect structure 18 includes an intermetal dielectric layer 22 and metal interconnects 24 embedded in the intermetal dielectric layer 22, and the metal interconnect structure 20 includes a stop layer 26, an intermetal dielectric layer 28, and metal interconnects (not shown) embedded in the stop layer 26 and the intermetal dielectric layer 28. It is noted that, compared to the MRAM region 14, which has both the metal interconnects 24, the logic region 40 only has the metal interconnects 24 in the intermetal dielectric layer 22 but no metal interconnects in the intermetal dielectric layer 28 at this stage.

[0054] In this embodiment, each metal interconnect 24 in the metal interconnect structure 18 preferably comprises a trench conductor, and the metal interconnects (not shown) in the metal interconnect structure 20 preferably comprise via conductors. In addition, each metal interconnect 24 in each metal interconnect structure 18, 20 can be embedded in the inter-metal dielectric layers 22, 28 and / or the stop layer 26 and electrically connected to each other according to a single damascene process or a dual damascene process. For example, each metal interconnect 24 can further comprise a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), and the like, but not limited thereto. Since the single damascene or dual damascene process is well known in the art, no further elaboration is provided herein. In addition, in this example, the metal layer 36 in the metal interconnect 24 preferably comprises copper, the inter-metal dielectric layers 22, 28 preferably comprise silicon oxide or ultra-low dielectric constant dielectric layers, and the stop layer 26 preferably comprises a nitrogen doped carbide (NDC) layer, silicon nitride, or silicon carbon nitride (SiCN), but not limited thereto.

[0055] Next, a selective lower electrode 42, a spin orbit torque (SOT) layer 44, an MTJ stack 66, a capping layer 60, and a patterned hard mask or upper electrode 62 are formed on the metal interconnect structure 20. In this embodiment, the MTJ stack 66 is formed by sequentially forming a free layer 46, a barrier layer 48, a reference layer (not shown), a spacer (not shown), and a pinned layer 50 on the SOT layer 44. The free layer 46 can be formed of a ferromagnetic material, such as iron, cobalt, nickel, or an alloy thereof, such as cobalt-iron-boron (CoFeB), but not limited thereto, and the magnetization direction of the free layer 46 is "free" to change under an external magnetic field. The barrier layer 48 can be formed of an insulating material including an oxide, such as aluminum oxide (AlO x ) or magnesium oxide (MgO), but not limited thereto.

[0056] The reference layer is preferably disposed between the barrier layer 48 and the spacer layer, which can comprise a ferromagnetic material such as iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), but is not limited thereto. The spacer layer comprises a non-magnetic layer of a non-magnetic material such as selected from the group consisting of ruthenium, iridium, and rhodium.

[0057] The fixed layer 50 can comprise a ferromagnetic material such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), cobalt (Co), etc. Alternatively, the fixed layer 50 can comprise an antiferromagnetic (AFM) material such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc. to fix or pin the direction of the magnetic moment of the adjacent layer. In detail, the fixed layer 50 can comprise a lower synthetic antiferromagnetic (SAF) layer, a coupling layer, and an upper synthetic antiferromagnetic layer, wherein the lower and upper synthetic antiferromagnetic layers can comprise the same or different materials and both can comprise a ferromagnetic material such as cobalt (Co), nickel (Ni), platinum (Pt), palladium (Pd), or combinations thereof, and the coupling layer preferably comprises a material such as ruthenium (Ru), tantalum (Ta), gadolinium (Gd), platinum (Pt), hafnium (Hf), or combinations thereof to provide mechanical and / or lattice support to the lower and upper synthetic antiferromagnetic layers.

[0058] In addition, in the present embodiment, the selective bottom electrode 42 preferably comprises a conductive material such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), the SOT layer 44 preferably serves as a channel for a spin orbit torque (SOT) MRAM and thus can comprise tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (BiSe x Se 1-x ), or combinations thereof, the capping layer 60 preferably comprises a metal such as ruthenium, and the upper electrode 62 can comprise a conductive or dielectric material such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or combinations thereof.

[0059] In addition, in this embodiment, the patterned upper electrode 62 can be formed by forming a dielectric layer 64 made of silicon oxide on the unpatterned upper electrode 62, and then using a patterned mask (not shown), such as a patterned photoresist, to remove part of the dielectric layer 64 and the upper electrode 62 by means of, for example, reactive ion etching (RIE) to form a patterned dielectric layer 64 and a patterned upper electrode 62, and then selectively removing the dielectric layer 64 made of silicon oxide.

[0060] like Figure 2 As shown, a patterned dielectric layer 64 or a patterned top electrode 62 can then be used as a mask to remove part of the masking layer 60, part of the MTJ stack structure 66, and even part of the SOT layer 44 of the MRAM region 14 to form the MTJ 70. Then, a first masking layer 72 and an intermetallic dielectric layer 74 are sequentially formed on the MTJ 70. Preferably, the MTJ stack structure 66 of the logic region 40 is completely removed at this stage, and in this embodiment, the etching process parameters are preferably adjusted in the aforementioned patterning process so that the top surface of the top electrode 62 directly above the MTJ 70 has a curved surface. In this embodiment, the first masking layer 72 preferably contains silicon nitride, while the intermetallic dielectric layer 74 contains silicon oxide, such as tetraethoxysilane (TEOS). It should be noted that when the patterned upper electrode 62 is used to pattern the MTJ stack structure 66 to form the MTJ 70 in this stage, a portion of the SOT layer 44 can be selectively removed, so that the top surfaces of the remaining SOT layers 44 on both sides of the MTJ 70 are slightly lower than the top surface of the SOT layer 44 directly below the MTJ 70. According to another embodiment of the present invention, if no SOT layer 44 is removed when forming the MTJ 70, the top surfaces of the remaining SOT layers 44 on both sides of the MTJ 70 are preferably flush with the top surface of the SOT layer 44 directly below the MTJ 70. Furthermore, the first masking layer 72 and the intermetallic dielectric layer 74 formed in this stage are preferably simultaneously disposed on the MRAM region 14 and the logic region 40.

[0061] like Figures 3 to 4As shown, a bottom anti-reflective coating (BARC) 76 can be formed on the intermetallic dielectric layer 74. Then, using a patterned mask 78, such as a patterned photoresist, an etching process is performed. For example, an ion beam etching process can be used to remove part of the bottom anti-reflective coating 76 and part of the intermetallic dielectric layer 74 in the MRAM region 14, and all of the bottom anti-reflective coating 76 and intermetallic dielectric layer 74 in the logic region 40, exposing the underlying first masking layer 72. This leaves the remaining intermetallic dielectric layer 74 only in the MRAM region 14, but the underlying first masking layer 72 remains simultaneously in both the MRAM region 14 and the logic region 40. The bottom anti-reflective coating 76 can then be removed to expose the intermetallic dielectric layer 74 in the MRAM region 14. According to one embodiment of the present invention, the first masking layer 72 deposited in this stage preferably includes a width W1.

[0062] Then, a processing technique, such as an oxidation process 82, can be performed using the patterned intermetallic dielectric layer 74 as a mask to oxidize the first masking layer 72 on both sides of the intermetallic dielectric layer 74 to form a doped layer 96. Since the first masking layer 72 preferably contains silicon nitride, the doped layer 96 formed after the oxidation process 82 preferably contains silicon oxynitride (SiON). According to one embodiment of the present invention, after forming the doped layer 96, the original thickness W1 of the first masking layer 72 is preferably reduced to the width W2, and the formed doped layer 96 preferably has a width W3, wherein the width W2 = 0.5 to 0.8 (W1) and the width W3 = 0.3 to 0.5 (W2). It should also be noted that although the processing performed in this stage is preferably performed by oxidation to form the doped layer 96, it is not limited to this. According to other embodiments of the present invention, other methods of oxygen introduction, such as ion implantation, can be selected to drive oxygen atoms into the first masking layer 72 to form the doped layer 96.

[0063] Subsequently, as Figure 5As shown, an etching process is performed without forming an additional patterned mask. For example, an ion beam etching (IBE) process, different from the one described above, is used to remove all the intermetallic dielectric layers 74, part of the doped layer 96, part of the first masking layer 72, part of the SOT layer 44, part of the lower electrode 42, and even part of the intermetallic dielectric layer 28 of the MRAM region 14, as well as all the first masking layer 72, all SOT layers 44, all lower electrodes 42, and part of the intermetallic dielectric layer 28 of the logic region 40. This causes the left and right sidewalls of the first masking layer 72, doped layer 96, SOT layer 44, and lower electrode 42 of the MRAM region 14 to be slightly recessed and aligned. The top surface of the remaining intermetallic dielectric layer 28 of the logic region 40 can be selectively slightly lower than the top surface of the intermetallic dielectric layer 28 of the MRAM region 14. The doped layer 96, which originally extended from the sidewall of the first cover layer 72 to the dielectric layer between the metals on both sides of the MTJ 70, is partially removed, preferably forming a spacer wall 98 on the remaining sidewall of the first cover layer 72. As described above, the formed spacer wall 98, like the doped layer 96, contains silicon oxynitride (SiON). It should be noted that the height of the spacer wall 98 formed in this embodiment can be adjusted by the thickness of the first cover layer 72. For example, the bottom surface of the spacer wall 98 can be selected to be higher than the bottom surface of the upper electrode 62, lower than the bottom surface of the upper electrode 62 but higher than the top surface of the MTJ 70, lower than the top surface of the cover layer 60 but higher than the top surface of the MTJ 70, flush with the bottom surface of the cover layer 60, flush with the top surface of the MTJ 70, or lower than the top surface of the MTJ 70, such as lower than the top surface of the fixing layer 50 but higher than the bottom surface of the MTJ 70. These are all within the scope of this invention.

[0064] It should also be noted that although the IBE fabrication process performed in this stage removes part of the underlying intermetallic dielectric layer 28 when patterning the first cover layer 72, SOT layer 44, and lower electrode 42, it is not limited to this. According to other embodiments of the present invention, no intermetallic dielectric layer 28 may be removed when patterning the first cover layer 72, SOT layer 44, and lower electrode 42 using the IBE fabrication process. In other words, after patterning the first cover layer 72, SOT layer 44, and lower electrode 42, the top surface of the intermetallic dielectric layer 28 on both sides of the first cover layer 72 or SOT layer 44 can still be aligned with the top surface of the intermetallic dielectric layer 28 directly below the MTJ 70. This variation is also within the scope of the present invention.

[0065] like Figure 6As shown, a second masking layer 80 is then formed on the spacer wall 98, the first masking layer 72, and the intermetallic dielectric layer 28. The second masking layer 80 preferably covers the top surface of the first masking layer 72, the sidewalls of the spacer wall 98, the sidewalls of the first masking layer 72, the sidewalls of the SOT layer 44, the sidewalls of the lower electrode 42, and the top surface of the intermetallic dielectric layer 28. In this embodiment, the first masking layer 72 and the second masking layer 80 preferably contain the same material, for example, both preferably contain silicon nitride. According to an embodiment of the present invention, after the formation of the second masking layer 80 in this stage, the total thickness of the aforementioned first masking layer 72 or part of the first masking layer 72 plus the spacer wall 98 is again reduced to a width W4. The spacer wall 98 has a width W5, and the second masking layer 80 has a width W6, where W4 = 0.4–0.7 (W1), W5 = 0.1–0.5 (W4), and W6 = 0.5–1.5 (W4).

[0066] Then as Figure 7 As shown, an etching process can be performed without forming a patterned mask to remove a portion of the second masking layer 80 of the MRAM region 14 and all of the second masking layers 80 of the logic region 40, exposing the top surface of the intermetallic dielectric layer 28. Preferably, the curved top surface of the second masking layer 80 located on the sidewall of the first masking layer 72 is flush with or extends continuously and uninterruptedly from the curved top surface of the first masking layer 72 to the curved top surface of the second masking layer 80. Furthermore, in this embodiment, the bottom surface of the second masking layer 80 is preferably lower than the bottom surfaces of the first masking layer 72 and the spacer wall 98, while the bottom surface of the first masking layer 72 is also lower than the bottom surface of the spacer wall 98.

[0067] In this embodiment, the thickness of the first masking layer 72 is preferably greater than the thickness of the second masking layer 80, where "preferably" refers to the maximum distance or width of the first masking layer 72 and the second masking layer 80 extending along the X direction. According to one embodiment of the invention, the thickness of the second masking layer 80 is preferably about 40% to 80% or most preferably about 60% of the thickness of the first masking layer 72. Furthermore, although both the first masking layer 72 and the second masking layer 80 are preferably made of silicon nitride, the silicon concentration of the first masking layer 72 is preferably greater than that of the second masking layer 80, and the refractive index ratio of the first masking layer 72 relative to the second masking layer 80 is preferably between 1.2 and 1.7. According to a preferred embodiment of the invention, this configuration allows for the subsequent filling of a larger intermetallic dielectric layer next to the MTJ, thereby improving the insulation capability between components.

[0068] Subsequently, as Figure 8As shown, another intermetallic dielectric layer 84 is first formed in the MRAM region 14 and the logic region 40. A planarization process, such as chemical mechanical polishing (CMP), is used to remove part of the intermetallic dielectric layer 84. Then, a pattern transfer process is performed. For example, a patterned mask can be used to remove part of the intermetallic dielectric layer 84, part of the second masking layer 80 and part of the first masking layer 72 in the MRAM region 14, and part of the intermetallic dielectric layer 84, part of the intermetallic dielectric layer 28 and part of the stop layer 26 in the logic region 40 to form contact holes (not shown) and expose the underlying upper electrode 62 and the metal interconnect 24. Then, the contact hole is filled with the desired conductive material, such as a barrier layer containing titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization process is performed, for example, by chemical mechanical polishing to remove some of the conductive material to form a metal interconnect 86 electrically connecting the upper electrode 62 and the metal interconnect 24 within the contact hole. A stop layer 88 is then formed on the metal interconnect 86. In this embodiment, the intermetallic dielectric layer 84 and the intermetallic dielectric layer 74 may contain the same or different materials, for example, both containing silicon oxide, while the stop layer 88 may contain silicon dioxide, silicon nitride, or silicon carbide (SiCN), preferably silicon carbide, but is not limited thereto.

[0069] Then as Figure 9As shown, an intermetallic dielectric layer 90 is first formed on the stop layer 88 of the MRAM region 14 and logic region 40. Then, a pattern transfer fabrication process is performed, for example, using a patterned mask (not shown) to remove part of the intermetallic dielectric layer 90 and part of the stop layer 88 to form contact holes (not shown) and expose the underlying metal interconnects 86. The contact holes are then filled with the desired conductive material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. Next, a planarization fabrication process is performed, for example, using a chemical mechanical polishing process to remove part of the metal material to form contact plugs or metal interconnects 92 electrically connecting the metal interconnects 86 within the contact holes. Afterward, a stop layer 94 is selectively formed on the metal interconnects 92. In this embodiment, the intermetallic dielectric layer 90 preferably includes an ultra-low dielectric constant dielectric layer, which may include, for example, a porous dielectric material such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).

[0070] Please continue to refer to Figures 10 to 12 , Figures 10 to 12 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 10 As shown, this embodiment can be based on the foregoing Figures 1 to 5 The manufacturing process involves forming a gap wall 98 on the sidewall of the first covering layer 72. However, compared to the aforementioned embodiment... Figure 6 Regarding the ratio of width W4 to width W5, in this embodiment, after forming a doped layer 96 on the sidewall of the first masking layer 72 using an oxidation fabrication process 82 and removing part of the doped layer 96 by etching to form a spacer wall 98, the widths of the first masking layer 72 and the spacer wall 98 are preferably slightly adjusted. For example, in this embodiment, after forming the spacer wall 98, the total thickness of the aforementioned first masking layer 72 or part of the first masking layer 72 plus the spacer wall 98 is preferably slightly increased to a width W7, while the spacer wall has a width W8, where W7 = 0.6~0.8 (W1) and W8 = 0.1~0.3 (W7).

[0071] Then as Figure 11As shown, another oxidation fabrication process 108 can be performed using another patterned mask 106. By introducing oxygen, the sidewalls of the first masking layer 72 below the spacer 98 are oxidized again, causing the spacer 98 to extend downward to form another spacer 100. The spacer 100 and the original spacer 98 are generally formed by the first masking layer 72, which is composed of silicon nitride oxide, and therefore also contain silicon nitride oxide (SiON). It is worth noting that, in addition to oxidizing the sidewalls of the first masking layer 72 below the spacer 98, the oxidation fabrication process 108 performed in this stage preferably also oxidizes the sidewalls of the SOT layer 44 and the sidewalls of the lower electrode 42 to form doped regions 102 and 104. The composition of each doped region 102 and 104 preferably varies depending on the materials of the SOT layer 44 and the lower electrode layer 42. For example, the doped regions 102 and 104 may contain different materials, but both contain oxygen atoms.

[0072] From an overall structural perspective, the bottom surface of the first masking layer 72 is preferably flush with the bottom surface of the gap wall 100. The gap wall 100, the doped region 102 located on the sidewall of the SOT layer 44, and the doped region 104 located on the sidewall of the lower electrode 42 may have the same or different widths depending on the flow rate of the oxidation fabrication process 108. In this embodiment, the width of the gap wall 100 is preferably smaller than the width of the doped region 104 on the sidewall of the lower electrode 42, and the width of the doped region 104 on the sidewall of the lower electrode 42 is smaller than the width of the doped region 102 on the sidewall of the SOT layer 44, but neither is limited to this.

[0073] Then as Figure 12 As shown, the step of forming the aforementioned second covering layer 80 can be omitted and based on the aforementioned Figure 8 The fabrication process directly forms an intermetallic dielectric layer 84 in the MRAM region 14 and the logic region 40. A planarization process, such as chemical mechanical polishing (CMP), is used to remove part of the intermetallic dielectric layer 84, and metal interconnects 86 are formed in the MRAM region 14 and the logic region 40, electrically connecting the electrode 62 to the metal interconnects 24. A stop layer 88 is formed on the metal interconnects 86. Then, according to... Figure 9 The fabrication process first forms an intermetallic dielectric layer 90 on the stop layer 88 of the MRAM region 14 and the logic region 40, then forms a metal interconnect 92 to electrically connect the metal interconnect 86 in the MRAM region 14 and the logic region 40, and then selectively forms a stop layer 94 on the metal interconnect 92. The materials of the metal interconnects 86, 92, the intermetallic dielectric layers 84 and 90, and the stop layers 88 and 94 can be the same as in the aforementioned embodiments, and will not be described again here.

[0074] In summary, this invention mainly discloses a method for fabricating SOT MRAM devices and its related structures. The method primarily involves first forming an SOT layer 44 and an MTJ 70 on a substrate, forming a first masking layer 72 next to the MTJ, and then performing at least one oxidation process to oxidize part of the sidewalls of the first masking layer to form spacer walls next to the MTJ. The spacer walls 98 can be configured according to... Figure 9 The embodiment may be slightly higher than the bottom surface of the first covering layer 72 or the gap wall 100, depending on Figure 12 The bottom surface of the first masking layer 72 is cut flush with the embodiment. According to a preferred embodiment of the present invention, the formation of a spacer wall next to the MTJ or the first masking layer using the above-described oxidation process can not only improve the SOT efficiency of the device, but also reduce its driving current density.

[0075] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for fabricating a magnetoresistive random access memory (MRAM) element, characterized in that, Include: A spin orbit torque (SOT) layer is formed on the substrate; A magnetic tunneling junction (MTJ) is formed on the spin-orbit torque layer; A first shielding layer is formed on the magnetic tunnel junction; and A first oxidation process is performed to form a first spacer wall next to the magnetic tunnel junction.

2. The method of claim 1, wherein the substrate comprises an MRAM region and a logic region, and the method further comprises: An intermetallic dielectric layer is formed on the substrate; The spin-orbit torque layer is formed on the intermetallic dielectric layer; An upper electrode is formed on the magnetic tunnel junction; The first covering layer is formed on the magnetic tunneling junction and the spin-orbit torque layer; The first oxidation process is performed to form a doped layer within the first masking layer; Remove a portion of the doped layer and a portion of the first masking layer to form the first spacer wall; A second covering layer is formed on the first covering layer; as well as An oxide layer is formed on the second masking layer.

3. The method of claim 2, wherein the top surface of the upper electrode comprises a curved surface.

4. The method of claim 2, wherein the bottom surface of the second covering layer is lower than the bottom surface of the first gap wall.

5. The method of claim 2, wherein the bottom surface of the second cover layer is lower than the bottom surface of the first cover layer.

6. The method of claim 1, wherein the bottom surface of the first covering layer is lower than the bottom surface of the first gap wall.

7. The method of claim 1, wherein the substrate comprises an MRAM region and a logic region, the method further comprising: An intermetallic dielectric layer is formed on the substrate; The spin-orbit torque layer is formed on the intermetallic dielectric layer; An upper electrode is formed on the magnetic tunnel junction; The first covering layer is formed on the magnetic tunneling junction and the spin-orbit torque layer; The first oxidation process is performed to form a doped layer within the first masking layer; Remove a portion of the doped layer and a portion of the first masking layer to form the first spacer wall; A second oxidation process is performed to extend the first spacer wall to form a second spacer wall; as well as An oxide layer is formed on the first masking layer.

8. The method of claim 7, wherein the bottom surface of the magnetic tunnel junction is flush with the bottom surface of the second gap wall.

9. A magnetoresistive random access memory (MRAM) device, characterized in that, Include: A spin orbit torque (SOT) layer is disposed on the substrate; A magnetic tunneling junction (MTJ) is located on the spin-orbit torque layer; The first shielding layer is disposed next to the magnetic tunnel junction; A second covering layer is disposed next to the first covering layer; and A spacer wall is provided between the first covering layer and the second covering layer.

10. The MRAM element of claim 9, further comprising: An intermetallic dielectric layer is disposed on the substrate; The spin-orbit torque layer is disposed on the intermetallic dielectric layer; The upper electrode is disposed on the magnetic tunnel junction; The first shielding layer is disposed next to the upper electrode and the magnetic tunneling junction; and An oxide layer surrounds the second covering layer.

11. The MRAM element of claim 10, wherein the top surface of the upper electrode comprises a curved surface.

12. The MRAM element of claim 9, wherein the bottom surface of the first cover layer is lower than the bottom surface of the gap wall.

13. The MRAM element of claim 9, wherein the bottom surface of the second cover layer is lower than the bottom surface of the gap wall.

14. The MRAM element of claim 9, wherein the bottom surface of the second cover layer is lower than the bottom surface of the first cover layer.

15. A magnetoresistive random access memory (MRAM) element, characterized in that, Include: A spin orbit torque (SOT) layer is disposed on the substrate; A magnetic tunneling junction (MTJ) is located on the spin-orbit torque layer; A first shielding layer is disposed beside the magnetic tunnel junction; and A gap wall is provided next to the first covering layer, wherein the bottom surface of the first covering layer is flush with the bottom surface of the gap wall.

16. The MRAM element of claim 15, further comprising: An intermetallic dielectric layer is disposed on the substrate; The spin-orbit torque layer is disposed on the intermetallic dielectric layer; The upper electrode is disposed on the magnetic tunnel junction; The first shielding layer is disposed next to the upper electrode and the magnetic tunneling junction; and An oxide layer surrounds the spacer wall.

17. The MRAM element of claim 16, wherein the top surface of the upper electrode comprises a curved surface.

18. The MRAM element of claim 15, wherein the bottom surface of the MTJ is flush with the bottom surface of the gap wall.

19. The MRAM element of claim 15, further comprising a doped region disposed within the spin-orbit torque layer below the spacer wall.

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