High-temperature superconductive Josephson bicrystal junction array and preparation method thereof

Abstract

The invention relates to a high-temperature superconductive Josephson bicrystal junction array and a preparation method thereof. The preparation method comprises the following steps: providing a bicrystal substrate; the first surface of the bicrystal substrate comprises a high-temperature superconductor layer, a metal layer and a photoresist layer which are sequentially arranged in the direction away from the bicrystal substrate; after a crystal boundary line of the double-crystal substrate is determined by adopting an ultraviolet lithography machine microscope, an alignment mark with a preset pattern is formed in the metal layer; the crystal boundary line is located in the orthographic projection of the alignment mark on the first surface; based on the alignment mark, forming a high-temperature superconductive Josephson junction array pattern in the residual photoresist layer by adopting an electron beam exposure or laser direct writing process; the high-temperature superconductive Josephson junction array pattern crosses a domain and is perpendicular to the crystal boundary line; and removing part of the high-temperature superconductor layer by adopting an ion etching process, wherein the rest of the high-temperature superconductor layer and the metal layer are used for forming a high-temperature superconductive Josephson junction array with a preset junction width. The overlay alignment difficulty of the transparent bicrystal substrate can be reduced, and the integration level of the high-temperature superconductive Josephson junction array is improved.

Description

TECHNICAL FIELD

[0001] The application relates to the field of quantum voltage standard, in particular to a high-temperature superconducting Josephson bicrystal junction array and a preparation method thereof. BACKGROUND

[0002] The Josephson voltage reference is a metrological reference for reproducing the voltage value based on the Josephson effect. Compared with the traditional physical reference based on the standard Weston saturated cell, the quantum voltage reference has the advantages of high precision, high reproducibility and easy preservation. With superconducting materials, it is mainly divided into low-temperature and high-temperature two materials. The large-scale integrated Josephson junction array prepared by the low-temperature superconducting material can stably output a 10-volt quantumized direct-current voltage. The programmable junction array can also synthesize complex alternating current waveforms. The high-voltage breakthrough further meets the demand of the frontier, but the liquid helium refrigeration system has high cost, difficult operation and maintenance, and heavy equipment, which has become a significant bottleneck.

[0003] The high-temperature superconducting Josephson junction array can work in a liquid nitrogen environment due to the high critical temperature of the material, which greatly reduces the refrigeration cost, simplifies the system, and is expected to promote the popularization of quantum voltage standard to industrial sites and has potential in higher frequency applications. However, it faces the problems of immature materials and technology, difficulty in preparing high-quality Josephson junctions, limited performance of the junction array, millivolt-level output voltage, and unverified stability and anti-interference ability. In the related preparation method, the alignment of the transparent bicrystal substrate is difficult. SUMMARY

[0004] Therefore, it is necessary to provide a high-temperature superconducting Josephson bicrystal junction array and a preparation method thereof to at least reduce the alignment difficulty of the transparent bicrystal substrate and improve the integration of the Josephson junction array in view of the technical problems in the prior art.

[0005] In a first aspect, the application provides a high-temperature superconducting Josephson bicrystal junction array preparation method, comprising: providing a bicrystal substrate; the first surface of the bicrystal substrate comprises a high-temperature superconductor layer, a metal layer and a photoresist layer arranged in sequence in the direction away from the bicrystal substrate;

[0006] After the bicrystal substrate grain boundary line is determined by the ultraviolet photolithography microscope, an alignment mark with a preset pattern is formed in the metal layer; the grain boundary line is located in the orthographic projection of the alignment mark on the first surface;

[0007] Based on the alignment mark, an electron beam exposure or laser direct writing process is used to form a Josephson junction array pattern in the remaining photoresist layer; the Josephson junction array pattern spans and is perpendicular to the grain boundary line;

[0008] An ion beam etching process is used to remove part of the high-temperature superconductor layer, and the remaining high-temperature superconductor and metal layer are used to constitute a high-temperature superconducting Josephson junction array with a preset junction width; the working temperature range of the high-temperature superconductor layer is 40K-300K.

[0009] In the fabrication method described in the above embodiments, the position is precisely determined using an ultraviolet laser lithography microscope, and alignment marks are created. These alignment marks are then used for normal overlay etching, directly forming a Josephson array pattern aligned with the grain boundaries in the photoresist layer. The fabrication method provided in this embodiment avoids repeated adjustments and the use of a lithography microscope to identify grain boundaries, effectively shortening the fabrication cycle and reducing the risk of contamination or errors introduced by multi-step operations, thereby indirectly reducing the fabrication cost.

[0010] In addition, electron beam lithography or laser direct writing processes can refine micron-scale patterns into submicron-scale structures, enabling narrow junction fabrication and improving the integration density of high-temperature superconducting Josephson junction arrays.

[0011] In some embodiments, the preset pattern includes a cross shape, a circle, or a rectangle.

[0012] In some embodiments, when the preset graphic is a cross shape, the alignment mark includes a first part and a second part;

[0013] The first part's orthographic projection on the first surface covers a portion of the grain boundary line; the second part's orthographic projection on the first surface is perpendicular to the grain boundary line.

[0014] In some embodiments, the orthographic projection of the high-temperature superconducting Josephson array on the first surface is a rectangular wave, including a plurality of first segments alternately distributed on both sides of the grain boundary line along a first direction parallel to the first surface, and a second segment extending along a second direction and connecting adjacent first segments.

[0015] In some embodiments,

[0016] The width of the first segment is 10nm-10μm;

[0017] The width of the second segment is used to characterize the preset junction width, which ranges from 10 nm to 10 μm;

[0018] The length of the second segment ranges from 1μm to 1000μm.

[0019] In some embodiments, after the metal layer is formed, an in-situ annealing process is performed on the high-temperature superconductor layer and the metal layer.

[0020] In some embodiments, the thickness of the bicrystalline substrate ranges from 0.1 mm to 1 mm;

[0021] The thickness of the high-temperature superconductor layer ranges from 30 nm to 5000 nm;

[0022] The thickness of the metal layer ranges from 10nm to 500nm.

[0023] In some embodiments, the material of the high-temperature superconductor layer includes yttrium barium copper oxide, thallium barium calcium copper oxide, bismuth strontium calcium copper oxide, iron-based superconductor, nickel-based superconductor, or a combination thereof; the bicrystalline substrate is strontium titanate, magnesium oxide, lanthanum aluminate, strontium titanium-doped lanthanum aluminate, or yttrium-stabilized zirconium oxide.

[0024] Secondly, this application also provides a high-temperature superconducting Josephson bicrystalline array, which is fabricated using the fabrication method described in any of the above embodiments. The high-temperature superconducting Josephson bicrystalline array fabricated by the fabrication method provided in this application effectively overcomes the limitations of traditional photolithography resolution by combining micron-level photolithography and nano-level etching, significantly increasing the number of junctions per unit area, resulting in a highly integrated junction array, which can improve the accuracy of quantum voltage.

[0025] In some embodiments, the high-temperature superconducting Josephson twin array comprises 1 to 100 high-temperature superconducting Josephson twins connected in series.

[0026] The high-temperature superconducting Josephson bicrystalline array and its preparation method provided in this application have the following unexpected technical effects:

[0027] By precisely locating the grain boundary line and creating alignment marks using an ultraviolet lithography microscope, a high-temperature superconducting Josephson array pattern precisely aligned with the grain boundary line is formed using electron beam exposure or laser direct writing. This ensures that the array spans across domains and is perpendicular to the grain boundary line, eliminating the need for repeated adjustments and multiple identifications of the grain boundary line, reducing the risk of contamination and errors. This not only shortens the fabrication cycle and reduces costs, but also enhances the reliability of device performance.

[0028] Meanwhile, the combination of micron-level lithography and nano-level etching breaks through the traditional lithography resolution limitations while ensuring alignment accuracy, successfully fabricating high-temperature superconducting Josephson junction arrays with submicron widths. This significantly increases the number of junctions per unit area, greatly improving integration while also offering the advantages of simple process and low cost. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a flowchart of a method for preparing a high-temperature superconducting Josephson bicrystalline array provided in one embodiment;

[0031] Figure 2 This is a schematic diagram of the specific structure of a high-temperature superconducting Josephson bicrystalline array provided in one embodiment;

[0032] Figure 3 A schematic cross-sectional view of the structure obtained after forming a high-temperature superconductor layer and a metal layer in step S202 of the preparation method provided in an embodiment of this application;

[0033] Figure 4 A schematic cross-sectional view of the structure obtained after forming a photoresist layer in step S204 of the preparation method provided in an embodiment of this application;

[0034] Figure 5 A cross-sectional schematic diagram of the structure obtained after forming the alignment mark pattern in step S402 of the preparation method provided in an embodiment of this application;

[0035] Figure 6 A cross-sectional schematic diagram of the structure obtained after forming alignment marks in step S404 of the preparation method provided in an embodiment of this application;

[0036] Figure 7 A cross-sectional schematic diagram of the structure obtained after forming a high-temperature superconducting Josephson array pattern in step S60 of the preparation method provided in the first embodiment of this application;

[0037] Figure 8a A schematic cross-sectional view of the structure obtained after forming a high-temperature superconducting Josephson array in step S80 of the preparation method provided in an embodiment of this application;

[0038] Figure 8b for Figure 8a A magnified view of a portion of a medium-to-high temperature superconducting Josephson array.

[0039] Explanation of reference numerals in the attached figures:

[0040] 10. Bicrystalline substrate; 11. High-temperature superconductor layer; 12. Metal layer; 13. Photoresist layer; 20. Alignment mark; 21. First section; 22. Second section; 30. High-temperature superconducting Josephson junction array; 31. First segment; 32. Second segment. Detailed Implementation

[0041] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0043] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0044] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0045] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0046] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0047] The fabrication methods for high-temperature superconducting Josephson junctions mainly include bijunctions, stepped junctions, and bridging junctions, among which bijunctions are widely studied due to their relatively simple fabrication process and stable performance. The fabrication of bijunctions typically involves epitaxially growing high-temperature superconducting thin films on a bicrystalline substrate with specific grain boundaries, using the grain boundaries as weak connections to form the Josephson junction. This method can effectively generate individual Josephson junctions and arrange them into arrays through series or parallel connections for the realization of quantum voltage standards. In recent years, researchers have successfully fabricated small-scale arrays based on bijunctions and achieved quantum voltage outputs in the microvolt to millivolt range at liquid nitrogen temperatures, demonstrating their potential in precision measurement. However, the fabrication methods for bijunctions still have significant limitations, restricting their application in large-scale arrays and high-output quantum voltages.

[0048] The most critical step in fabricating bicrystalline junctions is aligning and exposing the Josephson junction pattern with the grain boundaries of the bicrystalline structure. However, most bicrystalline substrates have good light transmittance and are surface-polished, making it impossible to identify the grain boundaries in reflected light imaging. Although similar positioning methods are mentioned in related technologies, the overall formation process is complex and difficult.

[0049] Furthermore, the fabrication methods typically rely on photolithography, which, due to its resolution limitations, makes it difficult to achieve sub-micron widths for Josephson junctions. This results in a limited number of junctions per unit area, restricting the array's integration density. Therefore, how to reduce the difficulty of aligning and overlaying bicrystalline junctions while simultaneously improving the integration density of high-temperature superconducting Josephson junction arrays has become one of the urgent technical challenges for researchers in this field.

[0050] Please see Figure 1 This application provides a method for preparing a high-temperature superconducting Josephson bicrystalline array, including steps S20-S80;

[0051] Step S20: Provide a bicrystalline substrate; the first surface of the bicrystalline substrate includes a high-temperature superconductor layer, a metal layer and a photoresist layer arranged sequentially in a direction away from the bicrystalline substrate.

[0052] For example, the materials of the bicrystalline substrate include strontium titanate (STO), magnesium oxide (MgO), lanthanum aluminate (LaAlO3), strontium titanium doped lanthanum aluminate (LSAT), or yttrium-stabilized zirconium oxide (YSZ).

[0053] For example, the material of the high-temperature superconducting layer includes a high-temperature superconducting thin film, optionally including rare-earth barium copper oxide (ReBa2Cu3O4). 7-x (Re represents rare earth elements), such as yttrium barium copper oxide (YBCO), thallium barium calcium copper oxide (TBCCO), bismuth strontium calcium copper oxide (BSCCO), iron-based superconductors, nickel-based superconductors, or combinations thereof. In this embodiment, the bicrystalline substrate is formed by sintering two substrates with different orientations together at a certain angle, with the interface between the two substrates being a grain boundary line.

[0054] For example, the thickness of the bicrystalline substrate ranges from 0.1 mm to 1 mm, such as 0.1 mm, 0.5 mm, or 1 mm; the area of ​​the bicrystalline substrate ranges from (5 mm to 50 mm) * (5 mm to 50 mm).

[0055] For example, the thickness of the high-temperature superconductor layer ranges from 30nm to 5000nm, such as 30nm, 300nm, 3000nm or 5000nm, and the operating temperature range is 40K to 300K.

[0056] For example, the thickness of the metal layer ranges from 10 nm to 500 nm, such as 10 nm, 100 nm, or 500 nm. The thickness of the high-temperature superconductor layer and the metal layer can be specifically determined according to actual needs.

[0057] For example, the materials of the metal layer include, but are not limited to, titanium (Ti), chromium (Cr), palladium (Pd), or gold (Au). The metal layer serves as a protective layer for the high-temperature superconductor layer, ensuring that the superconducting thin film is protected from damage during subsequent processing.

[0058] Step S40: After determining the grain boundary line of the bicrystalline substrate using an ultraviolet lithography microscope, an alignment mark with a preset pattern is formed in the metal layer; the grain boundary line is located within the orthographic projection of the alignment mark on the first surface.

[0059] For example, the preset pattern includes a cross shape or a rectangle. It should be understood that if it is another shape, it is only necessary to ensure that the orthographic projection of its preset pattern on the first surface of the bicrystalline substrate includes the grain boundary line.

[0060] Furthermore, in this embodiment, the light source of the ultraviolet lithography microscope is set below the stage, and the light is emitted from the bottom up to illuminate the bicrystalline substrate. The grain boundary line can be found by using a reflective microscope through the photoresist layer. Then, a pre-defined pattern is aligned with the grain boundary line, and the photoresist layer is patterned by exposure and development to form alignment marks with the pre-defined pattern in the photoresist layer.

[0061] Step S60: Based on the alignment marks, a high-temperature superconducting Josephson array pattern is formed in the remaining photoresist layer using electron beam exposure or laser direct writing process; the high-temperature superconducting Josephson array pattern spans the domain and is perpendicular to the grain boundary line.

[0062] In the above embodiments, when defining the high-temperature superconducting Josephson array pattern using electron beam lithography, a preset alignment mark is used as the overlay reference. Electron beam lithography employs automatic detection and compensation to accurately locate grain boundaries, eliminating the need for physical mask fabrication. This not only avoids the time costs associated with mask design and fabrication but also allows for rapid adjustment of the array pattern by directly modifying the electron beam lithography data, significantly improving process iteration efficiency. Furthermore, it eliminates the step of identifying grain boundaries using a microscope, as required in related technologies, thus eliminating subjective errors from manual judgment and significantly improving the consistency of batch production.

[0063] Laser direct writing also eliminates the need for physical masks, automatically identifies alignment marks to meet the positioning requirements of grain boundaries, and has a short single writing time and fast scanning speed. Similar to electron beam lithography, it refines micron-scale patterns into submicron-scale structures, enabling narrow junction fabrication and improving the integration of high-temperature superconducting Josephson junction arrays.

[0064] Step S80: Part of the high-temperature superconductor layer is removed by ion beam etching. The remaining high-temperature superconductor and metal layer are used to form a high-temperature superconducting Josephson junction array with a preset junction width.

[0065] The high-temperature superconducting Josephson bicrystalline array obtained after steps S20-S80 can be found in [reference needed]. Figure 2 .in, Figure 2 This application provides an example of a high-temperature superconducting Josephson bicrystalline array prepared using the method described herein. Other suitable examples of high-temperature superconducting Josephson bicrystalline arrays prepared using the method described herein are also possible, and no limitations are imposed herein.

[0066] The following examples illustrate in detail the fabrication method of high-temperature superconducting Josephson bicrystalline arrays.

[0067] In this embodiment, the bicrystalline substrate may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. Intersecting (e.g., perpendicular) first and third directions are defined on the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies). For example, the arrangement direction of a high-temperature superconducting Josephson junction array is the first direction, and the plane in which the bicrystalline substrate lies can be determined based on the first and second directions. The first and second directions are perpendicular to each other. In this embodiment, the first direction is defined as the Y-axis direction, the second direction is defined as the X-axis direction, and the direction away from the bicrystalline substrate is defined as the Z-axis direction.

[0068] First Embodiment

[0069] Figure 3 Figures 8 to 8 are step-by-step cross-sectional views illustrating an exemplary fabrication method of a high-temperature superconducting Josephson bicrystalline array according to this application.

[0070] Please see Figure 3 , Figure 3 Figure a in the middle is a cross-sectional view along line A-A' of a high-temperature superconducting Josephson bicrystalline array. Figure 4 Figure b is a top view of the high-temperature superconducting Josephson bicrystalline array. In this top view, line B-B' represents the grain boundary. It should be understood that Figures a and b also correspond to the cross-sectional and top views of the device in the respective steps, which will not be elaborated upon further. The extension step of step S20 further includes:

[0071] Step S202: After forming a high-temperature superconductor layer 11 on the bicrystalline substrate 10 using a multi-target co-evaporation method, a metal layer 12 is sputtered and deposited on the surface of the high-temperature superconductor layer 11.

[0072] For example, the deposition temperature range of the multi-target co-evaporation method is 700°C-900°C, such as 700°C, 800°C or 900°C.

[0073] In this embodiment, the material of the bicrystalline substrate 10 is strontium titanium-doped lanthanum aluminate (LSAT); the material of the high-temperature superconductor layer 11 is any rare earth barium copper oxide (ReBa2Cu3O4). 7-x The thickness of the metal layer 12 is 200 nm; the metal layer 12 is made of gold (Au) and has a thickness of 50 nm.

[0074] Please see Figure 4 Step S204: Perform in-situ annealing on the high-temperature superconductor layer 11 and the metal layer 12 at a temperature of 500°C for 10 hours. Subsequently, a photoresist layer 13 is coated on the top surface of the metal layer 12.

[0075] The extension step of step S40 further includes:

[0076] Please see Figure 5 Step S402: Using ultraviolet lithography, the alignment mark pattern is aligned with the grain boundary lines within the bicrystalline substrate 10. The photoresist layer 13 is then exposed and developed to prepare a cross-shaped alignment mark pattern. It should be understood that... Figure 5 The alignment mark graphic size shown is for illustrative purposes only and does not represent the actual size.

[0077] Please see Figure 6 Step S404: Using ion beam etching technology, based on the patterned photoresist layer 13, the metal layer 12 is etched to form alignment marks 20 within the metal layer 12.

[0078] Of course, the metal layer 12 and the high-temperature superconductor layer 11 can also be etched simultaneously to form alignment marks 20 within the high-temperature superconductor layer 11. In the embodiments mentioned in the application, only one of these cases will be described. In this embodiment, the alignment mark 20 includes a first part 21 and a second part 22; wherein, the orthographic projection of the first part 21 on the first surface 10a covers a portion of the grain boundary line; and the orthographic projection of the second part 22 on the first surface is perpendicular to the grain boundary line.

[0079] Please see Figure 7 In step S60, using electron beam lithography, the high-temperature superconducting Josephson array pattern is etched into the photoresist layer 13 by aligning with the alignment mark 20; the high-temperature superconducting Josephson array pattern spans the domain and is perpendicular to the grain boundary line.

[0080] Please see Figure 8a In step S80, after etching the metal layer 12 and the high-temperature superconductor layer 11 using an ion beam etching process, the photoresist layer is removed to expose the metal layer 12. At this time, the remaining high-temperature superconductor layer 11 and metal layer 12 are used to form a high-temperature superconducting Josephson junction array 30.

[0081] The high-temperature superconducting Josephson array 30, when projected onto the first surface 10a, is a rectangular wave (i.e., a rectangular frame extending and connected along the OY direction), comprising multiple first segments 31 (horizontal segments along the OY direction) alternately distributed on both sides of the grain boundary line along the OY direction, and second segments 32 (vertical segments along the OX direction) extending along the OX direction and connecting adjacent first segments 31, as detailed below. Figure 8b As shown.

[0082] For example, the second segment 32 is used to characterize the preset junction width (i.e., the dimension along the OY direction) of the high-temperature superconducting Josephson junction array 30, which ranges from 10 nm to 10 μm, for example, 10 nm, 100 nm, 1 μm, or 10 μm; the junction length ranges from 1 μm to 1000 μm, for example, 1 μm, 10 μm, 100 μm, or 1000 μm. In this embodiment, the junction width of the high-temperature superconducting Josephson junction array is 100 nm.

[0083] For example, the width of the first segment 31 is used to characterize the spacing of the Josephson junction along the OY direction, ranging from 10nm to 10μm, such as 10nm, 100nm, 1μm, or 10μm.

[0084] After step S80, electrical tests are performed on the array to verify the Josephson effect and quantum voltage step characteristics.

[0085] Second Embodiment

[0086] The step-by-step cross-sectional view of the exemplary preparation method in the second embodiment is the same as that in the first embodiment, and will not be described in detail here.

[0087] Please see Figure 3 The extension step of step S20 further includes:

[0088] Step S202: After forming a high-temperature superconductor layer 11 on the bicrystalline substrate 10 using pulsed laser deposition, a metal layer 12 is evaporated and deposited on the surface of the high-temperature superconductor layer 11.

[0089] In this embodiment, the material of the bicrystalline substrate 10 is lanthanum aluminate (LaAlO3); the material of the high-temperature superconductor layer 11 is bismuth strontium calcium copper oxide (Bi2Sr2CaCu2O) 8+x The thickness of the metal layer 11 is 150 nm; the metal layer 12 is made of gold (Au) and has a thickness of 30 nm.

[0090] Please see Figure 4 Step S204: Photoresist is coated on the top surface of metal layer 12 to form photoresist layer 13.

[0091] Step S40 is the same as in the first embodiment, and will not be described in detail here. The resulting structure is as follows: Figure 6 As shown.

[0092] Please see Figure 7 In step S60, the laser direct writing technology is used to align with the alignment mark 20 and to etch the photoresist layer 13 to form a high-temperature superconducting Josephson array pattern; the high-temperature superconducting Josephson array pattern spans the domain and is perpendicular to the grain boundary line.

[0093] The high-temperature superconducting Josephson array 30 includes high-temperature superconducting layers 11 spaced apart along the OY direction and extending across the grain boundary line along the OX direction. The distance between the sidewall of the high-temperature superconducting layer 11 near the grain boundary line and the grain boundary line on the first surface 10a is within a preset range.

[0094] In this embodiment, the preset junction width of the high-temperature superconducting Josephson array is 500 nm.

[0095] Step S80 is the same as in the first embodiment, and will not be described in detail here. The resulting structure is shown in Figure 8.

[0096] After step S80, the array undergoes magnetic and electrical tests to evaluate its performance.

[0097] In some embodiments, this application also provides a high-temperature superconducting Josephson bicrystalline junction array, fabricated using the preparation method described in any of the above embodiments. In related technologies, the bicrystalline substrate size is 10mm*10mm*0.5mm, and the Josephson junction fabrication technology with a width of 4μm~6μm can only achieve fewer than 1000 tandem high-temperature superconducting Josephson junction arrays, limiting the output quantum voltage. The high-temperature superconducting Josephson junction array prepared using this application, employing electron beam lithography or laser direct writing technology to etch Josephson junctions with a width at the nanometer level, can achieve the fabrication of 1 to 1 million tandem Josephson junctions, improving the integration density of the junction array.

[0098] In the above embodiments, the unexpected technical effect of this application is:

[0099] By precisely locating grain boundaries and creating alignment marks using a UV lithography microscope, combined with electron beam lithography or laser direct writing, high-temperature superconducting Josephson junction patterns precisely aligned with the grain boundaries can be formed, ensuring that the junctions span across domains and are perpendicular to the grain boundaries. This process eliminates the need for repeated adjustments and multiple identifications of grain boundaries, reducing contamination and error risks. It not only shortens the fabrication cycle and lowers costs but also improves device reliability. Furthermore, the combination of micron-level lithography and nanon-level etching techniques overcomes the resolution limitations of traditional lithography while maintaining alignment accuracy, enabling narrow junction fabrication and successfully obtaining sub-micron-width high-temperature superconducting Josephson junction arrays. This significantly increases the number of junctions per unit area and substantially improves integration density.

[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for preparing a high-temperature superconducting Josephson bicrystalline array, characterized in that, include: A bicrystalline substrate is provided; the first surface of the bicrystalline substrate includes a high-temperature superconductor layer, a metal layer and a photoresist layer arranged sequentially in a direction away from the bicrystalline substrate; After determining the grain boundary line of the bicrystalline substrate using an ultraviolet lithography microscope, alignment marks with a preset pattern are formed in the metal layer; The grain boundary line lies within the orthographic projection of the alignment mark onto the first surface; Based on the alignment marks, a Josephson array pattern is formed in the remaining photoresist layer using electron beam lithography or laser direct writing; the Josephson array pattern spans the domain and is perpendicular to the grain boundary line; A portion of the high-temperature superconductor layer is removed using an ion beam etching process, and the remaining high-temperature superconductor and the metal layer are used to form a Josephson junction array with a preset junction width; the operating temperature range of the high-temperature superconductor layer is 40K-300K.

2. The preparation method according to claim 1, characterized in that, The preset pattern includes a cross shape or a rectangle.

3. The preparation method according to claim 2, characterized in that, When the preset graphic is a cross shape, the alignment mark includes a first part and a second part; Wherein, the orthographic projection of the first part on the first surface covers a portion of the grain boundary line; the orthographic projection of the second part on the first surface is perpendicular to the grain boundary line.

4. The preparation method according to claim 3, characterized in that, The Josephson array's orthographic projection onto the first surface is a rectangular wave, comprising a plurality of first segments alternately distributed on both sides of the grain boundary line along a first direction parallel to the first surface, and a second segment extending along a second direction and connecting adjacent first segments.

5. The preparation method according to claim 4, characterized in that, The width of the first segment is 10nm-10μm; The width of the second segment is used to characterize the preset junction width, which ranges from 10 nm to 10 μm; The length of the second segment ranges from 1μm to 1000μm.

6. The preparation method according to any one of claims 1-5, characterized in that, After the metal layer is formed, an in-situ annealing process is performed on the high-temperature superconductor layer and the metal layer.

7. The preparation method according to any one of claims 1-5, characterized in that, The thickness of the bicrystalline substrate ranges from 0.1 mm to 1 mm; The thickness of the high-temperature superconductor layer ranges from 30 nm to 5000 nm; The thickness of the metal layer ranges from 10 nm to 500 nm.

8. The preparation method according to any one of claims 1-6, characterized in that, The materials for the high-temperature superconductor layer include yttrium barium copper oxide, thallium barium calcium copper oxide, bismuth strontium calcium copper oxide, iron-based superconductors, nickel-based superconductors, or combinations thereof; The bicrystalline substrate is strontium titanate, magnesium oxide, lanthanum aluminate, strontium titanium-doped lanthanum aluminate, or yttrium-stabilized zirconium oxide.

9. A high-temperature superconducting Josephson bicrystalline array, characterized in that, It is prepared by the preparation method according to any one of claims 1-9.

10. The high-temperature superconducting Josephson bicrystalline array according to claim 9, characterized in that, This includes 1 to 1 million tandem high-temperature superconducting Josephson twin junctions.

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