Test key structure and wafer

Abstract

The invention discloses a test key structure and a wafer. The test key structure comprises a substrate, and at least one first test port, a second test port and at least one test circuit which are arranged on the substrate, each test circuit comprises two sub-circuits which are connected in parallel, each sub-circuit comprises a one-way conduction element and a test pattern unit which are connected in series, and the one-way conduction elements in the two sub-circuits which are connected in parallel have opposite conduction directions; wherein each first test port is electrically connected with one test circuit in a one-to-one correspondence manner, and all the test circuits are electrically connected with the second test port. According to the test key structure, the test ports are shared, the number of the test ports can be reduced, and the integration density of the test pattern units is improved, so that the wafer occupied area of the test key structure is reduced, full support is provided for process monitoring and device performance evaluation, and potential risks caused by insufficient number of the test pattern units are reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a test bond structure and a wafer. Background Technology

[0002] In the field of semiconductor integrated circuits, test keys play a crucial role, such as monitoring potential process anomalies in the production process, evaluating device performance and long-term reliability, and providing quantitative data support for subsequent process optimization and design improvements.

[0003] In related technologies, the test key structure includes multiple test ports connected in series, with a test pattern unit connected in series between two adjacent test ports. This makes the number of test ports and the number of test pattern units have a fixed correspondence of "n test ports correspond to n-1 test pattern units" - for example: 2 test ports correspond to 1 test pattern unit, 3 test ports correspond to 2 test pattern units, 4 test ports correspond to 3 test pattern units, and so on.

[0004] In wafer layout, test bond structures are typically located in the dicing area between dies. For a fixed-size wafer, the total dicing area is constant; however, as the demand for test patterning units continues to grow, their occupied area on the wafer increases accordingly, which can easily lead to insufficient usable dicing area. This can result in the forced removal of some test patterning units, posing a potential risk to process monitoring and device performance evaluation. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a test key structure, including: Substrate; At least one first test port is disposed on the substrate; A second test port is disposed on the substrate; At least one test circuit is disposed on the substrate, each test circuit includes two parallel sub-circuits, each sub-circuit includes a unidirectional conducting element and a test pattern unit connected in series, and the unidirectional conducting elements in the two parallel sub-circuits have opposite conducting directions. Each of the first test ports is electrically connected to one of the test circuits, and all the test circuits are electrically connected to the second test ports.

[0007] In some embodiments of this application, in the test circuit, at least two of the test pattern units are arranged in a height direction perpendicular to the substrate surface, at least partially overlapping.

[0008] In some embodiments of this application, in the test circuit, at least two of the test pattern units have the same cross-sectional size in the height direction perpendicular to the substrate surface.

[0009] In some embodiments of this application, the first test port and the second test port can be configured such that one is a high-voltage port and the other is a low-voltage port, so that only one of the two parallel sub-circuits electrically connected to the same first test port is in a conducting state.

[0010] In some embodiments of this application, each of the sub-circuits has a first terminal and a second terminal, and the unidirectional conducting element is connected in series with the test pattern unit along the direction from the first terminal to the second terminal; In each of the test circuits, the first ends of the two parallel sub-circuits are connected to the same node and electrically connected to a first test port, and the second ends of the two parallel sub-circuits are both electrically connected to the second test port.

[0011] In some embodiments of this application, the unidirectional conducting element includes a diode.

[0012] In some embodiments of this application, the substrate is a wafer, on which a plurality of chips are disposed, and a dicing channel is disposed between two adjacent chips, and the test bond structure is disposed in the dicing channel of the wafer.

[0013] In some embodiments of this application, the test bond structure is used for wafer acceptability testing.

[0014] In another aspect, this application provides a wafer in which the test bond structure described above is provided in the dicing path.

[0015] The test bond structure and wafer of this application include two parallel sub-circuits for each test circuit. Each sub-circuit includes a series-connected unidirectional conducting element and a test pattern unit, and the unidirectional conducting elements of the two parallel sub-circuits have opposite conduction directions. At the same time, each first test port is electrically connected to a test circuit in a one-to-one correspondence, and all test circuits are electrically connected to the second test port. This realizes the sharing of test ports, which can reduce the number of test ports and increase the integration density of test pattern units, thereby reducing the wafer area occupied by the test bond structure. This provides sufficient support for process monitoring and device performance evaluation, and reduces the potential risks caused by insufficient number of test pattern units. Attached Figure Description

[0016] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0017] In the attached image: Figure 1 A schematic diagram of a test key structure in the related art is shown.

[0018] Figure 2 A schematic diagram of another test key structure in the related art is shown.

[0019] Figure 3 A schematic diagram of the test key structure according to a specific embodiment of this application is shown.

[0020] Figure 4 A schematic diagram of the test key structure according to a specific embodiment of this application is shown.

[0021] Figure 5 A schematic diagram of the test key structure according to a specific embodiment of this application is shown. Detailed Implementation

[0022] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0023] It should be understood that this application can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0024] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0025] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0027] In related technologies, the test key structure includes multiple test ports connected in series, with a test pattern unit connected in series between two adjacent test ports. This results in a fixed correspondence between the number of test ports and the number of test pattern units: "n test ports correspond to n-1 test pattern units"—for example, 2 test ports correspond to 1 test pattern unit (e.g., ...). Figure 1 As shown), the three test ports correspond to two test graphical units (e.g. Figure 2 As shown), the four test ports correspond to three test graphic units, and so on.

[0028] In wafer layout, test bond structures are typically located in the dicing area between dies. For a fixed-size wafer, the total dicing area is constant; however, as the demand for test patterning units continues to grow, their occupied area on the wafer increases accordingly, which can easily lead to insufficient usable dicing area. This can result in the forced removal of some test patterning units, posing a potential risk to process monitoring and device performance evaluation.

[0029] Therefore, in view of the aforementioned technical problems, this application proposes a test bond structure, including: Substrate; At least one first test port is disposed on the substrate; A second test port is disposed on the substrate; At least one test circuit is disposed on the substrate, each test circuit includes two parallel sub-circuits, each sub-circuit includes a unidirectional conducting element and a test pattern unit connected in series, and the unidirectional conducting elements in the two parallel sub-circuits have opposite conducting directions. Each of the first test ports is electrically connected to one of the test circuits, and all the test circuits are electrically connected to the second test ports.

[0030] In this application, each test circuit includes two parallel sub-circuits, each sub-circuit including a series-connected unidirectional conducting element and a test pattern unit, and the unidirectional conducting elements of the two parallel sub-circuits have opposite conduction directions; at the same time, each first test port is electrically connected to a test circuit in a one-to-one correspondence, and all test circuits are electrically connected to the second test port, realizing the sharing of test ports, which can reduce the number of test ports and increase the integration density of test pattern units, thereby reducing the wafer area occupied by the test bond structure, providing sufficient support for process monitoring and device performance evaluation, and reducing the potential risks caused by insufficient number of test pattern units.

[0031] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0032] The following is for reference. Figures 3-5 This application describes a test key structure according to one embodiment. The test key structure includes: a substrate; at least one first test port 111, one second test port 112, and at least one test circuit disposed on the substrate. Each test circuit includes two parallel sub-circuits, each sub-circuit including a unidirectional conducting element 121 and a test pattern unit 122 connected in series, and the unidirectional conducting elements 121 in the two parallel sub-circuits have opposite conduction directions. Each first test port 111 is electrically connected to one test circuit, and all test circuits are electrically connected to the second test port 112.

[0033] On the one hand, compared with the fixed correspondence of "n test ports corresponding to n-1 test pattern units 122" in related technologies, the test key structure in this embodiment realizes shared test ports: each test circuit includes two parallel sub-circuits, each sub-circuit includes a unidirectional conducting element 121 connected in series with the test pattern unit 122, and the unidirectional conducting elements 121 of the two parallel sub-circuits have opposite conduction directions; at the same time, a single first test port 111 is electrically connected to a test circuit in a one-to-one correspondence, and all test circuits are electrically connected to the second test port 112. With the help of the unidirectional conductivity of the unidirectional conducting element 121, selective conduction of two sub-circuits in the same test circuit can be realized, so that a single first test port 111 can correspond to two test pattern units 122, and a single second test port 112 can correspond to all test pattern units 122, thereby sharing test ports and breaking the fixed number correspondence between test ports and test pattern units 122 in related technologies.

[0034] This means that, compared with related technologies, with the same number of test pattern units 122, the number of test ports can be reduced, saving the area occupied by the test ports; and with the same number of test ports, more test pattern units 122 can be set to increase the integration density of test pattern units 122 within the test bond structure, thereby reducing the wafer area occupied by the test bond structure.

[0035] On the other hand, the reduction in the number of test ports and the increase in the integration density of the test patterning unit 122 reduce the area occupied by the test bond structure in the wafer dicing area. Under the premise that the total dicing area of ​​a fixed-size wafer remains constant, this design can alleviate the problem of insufficient usable dicing area caused by the increased demand for the test patterning unit 122, avoiding the forced reduction of the test patterning unit 122 due to area limitations. This ensures that a sufficient number of test patterning units 122 are retained, providing ample support for process monitoring and device performance evaluation, and reducing related potential risks.

[0036] In some embodiments, such as Figure 4 As shown, in the test circuit, at least two test pattern units 122 are arranged in a height direction perpendicular to the substrate surface, at least partially overlapping.

[0037] Specifically, in the test circuit, at least two test pattern units 122 can be respectively disposed on process layers of different heights above the substrate, and the at least two test pattern units 122 form at least partial overlap in the height direction perpendicular to the substrate surface, corresponding to the same planar position. Compared with the design of different test pattern units 122 arranged in a planar parallel manner in related technologies, which easily occupies a large planar space, this embodiment realizes the reuse of the same planar position by multiple test pattern units 122 through the overlapping arrangement in the height direction, effectively saving the overall planar area occupied by the test pattern units 122; combined with the layout scenario of the test bond structure in the wafer dicing area, this design can further reduce the planar size of the test bond structure, better adapt to the limited space resources of the dicing channel, reduce the situation of test pattern units 122 being reduced due to area limitations, and provide more sufficient support for process monitoring and device performance evaluation.

[0038] In some embodiments, in the test circuit, at least two test pattern units 122 have the same cross-sectional dimensions in the height direction perpendicular to the substrate surface.

[0039] Specifically, by making the test pattern units 122 have the same cross-sectional size in the direction perpendicular to the height, the test pattern units 122 with the same cross-sectional size can be completely overlapped in the height direction perpendicular to the substrate surface, thereby further reducing the overall planar area occupied by the test pattern units 122; this helps to accommodate more test pattern units 122 in the same area, further reducing the reduction of test pattern units 122 due to area limitations, and ensuring the adequacy of process monitoring and device performance evaluation.

[0040] Of course, this application does not exclude the possibility that at least two test pattern units 122 may have inconsistent cross-sectional dimensions in the height direction perpendicular to the substrate surface. In this case, even if the cross-sectional dimensions of the at least two test pattern units 122 differ in the height direction perpendicular to the substrate surface, since the test pattern units 122 are still at least partially overlapped in the height direction perpendicular to the substrate surface, partial area overlap will still be formed, thereby reducing the overall planar area occupied by the test pattern units 122.

[0041] In some embodiments, such as Figures 3-5As shown, each sub-circuit has a first end and a second end, and along the direction from the first end to the second end, the unidirectional conducting element 121 and the test pattern unit 122 are connected in series in sequence; the first ends of the two parallel sub-circuits in each test circuit are connected to the same node and electrically connected to a first test port 111, and the second ends of the two parallel sub-circuits are both electrically connected to the second test port 112.

[0042] In some embodiments, the unidirectional conducting element 121 may include a diode. Specifically, the diode may be a PN junction diode, which forms P-type and N-type regions through an ion doping process on a semiconductor substrate. It utilizes the unidirectional conductivity of the PN junction to achieve the function of "allowing current to flow only in a specific direction". Moreover, its structure is simple, its fabrication process is compatible with the manufacturing process of semiconductor devices, and it can be integrated onto the substrate synchronously with the test pattern unit 122 without the need for additional complex process steps.

[0043] Of course, the unidirectional conducting element 121 is not limited to the aforementioned diode. Any element that has the characteristic of "allowing current to flow in only one direction" and can be integrated into a substrate and adapted to a test circuit falls within the protection scope of the unidirectional conducting element 121 in this application, such as a unidirectional thyristor or a unidirectional conductive metal-oxide-semiconductor field-effect transistor, etc., and is not limited thereto.

[0044] In some embodiments, the first test port 111 and the second test port 112 can be configured such that one is a high-voltage port and the other is a low-voltage port, so that only one of the two parallel sub-circuits electrically connected to the same first test port 111 is in the on state.

[0045] Specifically, taking the first test port 111 as the high-voltage port and the second test port 112 as the low-voltage port as an example, since the unidirectional conducting elements 121 in the two parallel sub-circuits electrically connected to the first test port 111 have opposite conduction directions, under this voltage configuration, only one sub-circuit can satisfy the conduction condition of the unidirectional conducting element 121 and be in the conducting state. Taking the first test port 111 as the low-voltage port and the second test port 112 as the high-voltage port as an example, since the unidirectional conducting elements 121 in the two parallel sub-circuits electrically connected to the first test port 111 have opposite conduction directions, under this voltage configuration, the other sub-circuit that was originally in the off state can be switched to the conducting state, while the sub-circuit that was previously in the conducting state is switched to the off state. Thus, the individual testing of the two parallel sub-circuits electrically connected to the same first test port 111 can be achieved sequentially; combined with the independent configuration of multiple first test ports 111, the comprehensive testing operation of all sub-circuits in each test circuit can ultimately be completed.

[0046] In some embodiments, the substrate is a wafer, on which multiple chips are disposed, and a dicing channel is disposed between two adjacent chips. The test bond structure is disposed in the dicing channel of the wafer. The test bond structure of this embodiment can reduce the area occupied in the wafer dicing channel region, reduce the possibility of reducing the test pattern unit 122 due to area limitations, and provide sufficient support for process monitoring and device performance evaluation.

[0047] In some embodiments, the test bond structure is used for wafer acceptability testing. Of course, this embodiment does not preclude the use of the above-described test bond structure for other types of semiconductor testing, and such use is not limited.

[0048] For example, such as Figures 3-5 As shown, the test key structure includes four first test ports 111, one second test port 112, and four test circuits. Each test circuit contains two parallel sub-circuits, each sub-circuit including a series-connected unidirectional conducting element 121 and a test pattern unit 122, and the unidirectional conducting elements 121 of the two parallel sub-circuits have opposite conducting directions. In terms of connection, each first test port 111 is electrically connected to one test circuit in a one-to-one correspondence, and all four test circuits are electrically connected to the second test port 112.

[0049] The four test circuits contain a total of eight test pattern units 122, which are stacked at the same position in a height direction perpendicular to the substrate surface.

[0050] This results in the following effects: On the one hand, by sharing the test ports, the number of test ports can be reduced, saving port area; and with the same number of test ports, more test pattern units 122 can be configured, thereby increasing the integration density of the test pattern units 122 within the test bond structure, ultimately reducing the wafer area occupied by the test bond structure; on the other hand, by overlapping the eight test pattern units 122 in the height direction, multiple test pattern units 122 can reuse the same plane position, effectively saving the overall planar area occupied by the test pattern units 122, further reducing the planar size of the test bond structure, thereby further reducing the wafer area occupied by the test bond structure.

[0051] Of course, this application does not limit the number of first test ports 111 and test circuits in the test key structure. It does not exclude the possibility that it includes two first test ports 111, one second test port 112 and two test circuits, nor does it exclude the possibility that it includes three first test ports 111, one second test port 112 and three test circuits, nor does it exclude the possibility that it includes a larger number of first test ports 111 and test circuits.

[0052] According to another aspect of this application, a wafer is provided, wherein a test bond structure is provided in the dicing channel of the wafer.

[0053] The test key structure can be implemented as described above, and will not be repeated here.

[0054] In summary, the test bond structure and wafer of this application embodiment include two parallel sub-circuits for each test circuit. Each sub-circuit includes a series-connected unidirectional conducting element and a test pattern unit, and the unidirectional conducting elements of the two parallel sub-circuits have opposite conduction directions. At the same time, each first test port is electrically connected to a test circuit in a one-to-one correspondence, and all test circuits are electrically connected to the second test port, realizing the sharing of test ports. This reduces the number of test ports and increases the integration density of the test pattern unit, thereby reducing the wafer area occupied by the test bond structure, providing sufficient support for process monitoring and device performance evaluation, and reducing the potential risks caused by insufficient number of test pattern units.

[0055] This application has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit this application to the scope of the described embodiments. Furthermore, those skilled in the art will understand that this application is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this application, all of which fall within the scope of protection claimed in this application. The scope of protection of this application is defined by the appended claims and their equivalents.

Claims

1. A test key structure, characterized by, The test key structure comprises: a substrate; at least one first test port arranged on the substrate; a second test port arranged on the substrate; at least one test circuit arranged on the substrate, each of the test circuits comprising two parallel sub-circuits, each of the sub-circuits comprising a unidirectional conduction element and a test pattern unit connected in series, and the unidirectional conduction elements in the two parallel sub-circuits having opposite conduction directions; wherein each of the first test ports is electrically connected to one of the test circuits in one-to-one correspondence, and all the test circuits are electrically connected to the second test port.

2. The test key structure of claim 1, wherein, In the test circuit, at least two of the test pattern units are arranged at least partially overlapped in the height direction perpendicular to the surface of the substrate.

3. The test key structure of claim 2, wherein, In the test circuit, the cross-sectional dimensions of at least two of the test pattern units in the height direction perpendicular to the surface of the substrate are the same.

4. The test key structure of claim 1, wherein, The first test port and the second test port can be configured as one high-voltage port and the other low-voltage port, so that only one of the two parallel sub-circuits electrically connected to the same first test port is in a conduction state.

5. The test key structure of claim 1, wherein, Each of the sub-circuits has opposite first and second ends, and the unidirectional conduction element and the test pattern unit are connected in series in the direction from the first end to the second end. In each of the test circuits, the first ends of the two parallel sub-circuits are connected to the same node and electrically connected to one of the first test ports, and the second ends of the two parallel sub-circuits are electrically connected to the second test port.

6. The test key structure of claim 1, wherein, The unidirectional conduction element comprises a diode.

7. The test key structure of claim 1, wherein, The substrate is a wafer, and a plurality of chips are arranged on the wafer, and a cutting path is arranged between adjacent two chips, and the test key structure is arranged in the cutting path of the wafer.

8. The test key structure of claim 1, wherein, The test key structure is used for wafer acceptable test.

9. A wafer, characterized by The cutting path of the wafer is provided with the test key structure according to any one of claims 1-8.

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