Insulating layer of interposer through hole and preparation method thereof
By forming a self-assembled monolayer on the sidewall of the via in the intermediate layer and combining it with atomic layer deposition, the performance problem caused by Si-O dangling bonds was solved, and the metal filling uniformity and high-frequency signal transmission capability of the via with high aspect ratio were achieved.
Patent Information
- Application Number
- CN202511701776.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-19
- Publication Date
- 2026-02-13
AI Technical Summary
In existing technologies, the Si-O dangling bonds in the glass interlayer increase dramatically with the aspect ratio, affecting the interlayer performance and resulting in poor metal filling uniformity, increased leakage current, and reduced breakdown voltage, making it unsuitable for high-frequency applications.
A compound monolayer containing silicon-oxygen bonds, phosphorus-oxygen bonds, or sulfur-oxygen bonds is formed on the sidewall of the via by self-assembly monolayer deposition to terminate the Si-O dangling bonds. An oxide or nitride insulating layer is formed by atomic layer deposition to shield the residual dangling bonds. Combined with low temperature and low pressure conditions, it can be adapted to high aspect ratio vias.
It effectively avoids the impact of Si-O dangling bonds on the properties of the interlayer, improves metal filling efficiency and adhesion, reduces leakage current, and increases breakdown voltage, making it suitable for high-frequency signal transmission.
Smart Images
Figure CN121532018A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor packaging, in particular to a preparation method of an insulating layer of a via of an interposer. BACKGROUND
[0002] With the rapid development of artificial intelligence, high-performance computing, 5G communication and the Internet of Things, semiconductor packaging technology is shifting from traditional 2D layout to 2.5D and 3D integration. Among them, the interposer serves as a bridge for inter-chip interconnection, providing high-density connection, thermal management and typical optimization. Among various interposer substrates, proportional interposers are widely used in semiconductor packaging due to their low CTE, low dielectric loss and large-area process potential.
[0003] However, the Si-O dangling bonds in the glass interposer increase sharply with the aspect ratio, affecting the performance of the interposer. SUMMARY
[0004] Based on the content of the background art, the present application provides an insulating layer of a via of an interposer and a preparation method thereof.
[0005] In a first aspect, the present application provides a preparation method of an insulating layer of a via of an interposer, the preparation method comprising: providing a substrate; wherein the substrate comprises an interposer, and the interposer comprises a plurality of vias; placing the substrate in a first reaction cavity and introducing a precursor into the first reaction cavity at a first preset temperature for vapor deposition to form a self-assembled monolayer on the sidewall of the via; wherein the precursor comprises any one of a silane compound, a thiol compound and a phosphoric acid compound; placing the deposited substrate in a second reaction cavity and alternately pulsing an insulating material and ozone into the second reaction cavity at a second preset temperature to form the insulating layer; wherein the insulating material comprises any one of hafnium oxide, aluminum oxide, zirconium oxide, titanium nitride and silicon nitride.
[0006] Optionally, the silane compound comprises any one of 3-mercaptopropyltriethoxysilane, triethylsilane and 3-(azidopropyl)triethoxysilane, the thiol compound comprises any one of propanethiol and 4-mercaptobutyric acid, and the phosphoric acid compound comprises 1-octylphosphoric acid.
[0007] Optionally, the insulating material comprises any one of hafnium dioxide, aluminum oxide, zirconium oxide, titanium nitride and silicon nitride.
[0008] Optionally, the alternately pulsing the insulating material and ozone into the second reaction cavity at the second preset temperature comprises: pulsing the insulating material into the second reaction cavity at a second preset temperature, and after the end of the pulsing, purging the reaction cavity with inert gas; pulsing the ozone into the second reaction cavity, and repeating the above steps until a preset number of times is reached.
[0009] Optionally, the preset number of times is 40-80 times.
[0010] Optionally, the first preset temperature is less than 120℃, the pressure of the first reaction cavity is 0-12 Torr, the partial pressure of the precursor is 0.3-0.6 Torr, and the preset time is 13-18 min.
[0011] Optionally, the preset temperature is 50-300℃, and the pressure of the reaction cavity is 0.01-20 Torr.
[0012] According to a second aspect of the present application, there is provided an insulating layer of a via of an interposer, which is prepared by the method for preparing an insulating layer of a via of an interposer according to the first aspect.
[0013] Optionally, the insulating layer is formed on the sidewall of the via of the interposer, and the aspect ratio of the via of the interposer is 5:1-20:1.
[0014] The method for preparing an insulating layer of a via of an interposer provided by the embodiments of the present application comprises the following steps: providing a substrate; wherein the substrate comprises an interposer, and the interposer comprises a plurality of vias; placing the substrate in a first reaction cavity, and introducing a precursor into the first reaction cavity at a first preset temperature to perform vapor deposition, so as to form a self-assembled monolayer on the sidewall of the via; wherein the precursor comprises any one of a silane compound, a mercaptan compound and a phosphoric acid compound; placing the substrate after deposition in a second reaction cavity, and alternately pulsing an insulating material and ozone into the second reaction cavity at a second preset temperature, so as to form the insulating layer; wherein the insulating material comprises any one of hafnium oxide, aluminum oxide, zirconium oxide, titanium nitride and silicon nitride. Therefore, the present application firstly deposits a self-assembled monolayer, and then deposits a protective layer by using atomic layer deposition, so as to construct a hierarchical interface, wherein the self-assembled monolayer is a silane, a mercaptan or a phosphoric acid compound, which can be combined with the Si-O dangling bond on the sidewall of the via, so as to terminate the dangling bond, thereby avoiding the problem that the dangling bond adsorbs moisture or pollutants, and weakens the adhesion of the metal filled in the sidewall of the interposer. Since the deposition of the self-assembled monolayer and the atomic layer deposition are both performed at low temperature and low pressure, the low temperature can reduce the thermal stress of the substrate, and the low pressure can enhance the diffusion capacity of the precursor in the via with high aspect ratio, so that the preparation process of the insulating layer can adapt to the brittleness of the glass interposer, and ensure that the coverage rate of the insulating layer on the bottom of the via with high aspect ratio is greater than 95%.
[0015] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description
[0016] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 A schematic diagram of the chip architecture in the related technology is shown; Figure 2 A flowchart illustrating the steps of a method for preparing an insulating layer for a via in an interposer provided in an embodiment of the present invention is shown. Figure 3 A schematic diagram of the through-hole structure in the interlayer without an insulating layer is shown. Figure 4 A schematic diagram of the structure of the insulating layer formed in the intermediate layer via of an embodiment of the present invention is shown. Detailed Implementation
[0017] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The embodiments of the present invention are described in detail below. These embodiments are implemented based on the technical solution of the present invention, and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments. Where specific experimental steps or conditions are not specified in the embodiments, they can be performed according to the conventional experimental steps or conditions described in the prior art. Reagents and other instruments used, unless otherwise specified, are all commercially available conventional reagent products.
[0018] In related technologies, a through-interposer via (TIV) generally refers to a vertical through-hole structure in an interposer, used to connect wafers or circuits on the upper and lower surfaces of the interposer, and can be applied to silicon, glass, and other substrate materials. The substrate of the interposer can be silicon, glass, or other materials. For example, using... Figure 1 For example, Figure 1 A schematic diagram of the chip architecture in the related technology is shown, such as Figure 1 As shown, the interposer layer includes multiple vias filled with metal to connect the chip to the underlying circuit board.
[0019] The via in the glass interposer includes Si-O dangling bonds, which increase with the increase of the aspect ratio of the via, and the Si-O dangling bonds easily cause the poor adhesion between the metal and the sidewall of the interposer due to the adsorption of moisture or contaminants, which affects the uniformity of the metal filling, so that the conventional insulating layer preparation method is difficult to be applied to the via with high aspect ratio, and the dangling bonds increase the leakage current and reduce the breakdown voltage, which affects the high-frequency application.
[0020] Therefore, the application provides an insulating layer of an interposer via and a preparation method thereof, a monolayer of a compound containing Si-O bonds, P-O bonds or S-O bonds is deposited on the via through self-assembled monolayer deposition, the Si-O dangling bonds are terminated by the Si-O bonds, P-O bonds or S-O bonds, so as to avoid the influence of the Si-O dangling bonds, and then an oxide or nitride insulating layer is prepared to shield the residual dangling bonds, thereby avoiding the influence of the Si-O dangling bonds on the performance of the interposer, and the self-assembled monolayer deposition and atomic layer deposition can be applied to various substrates due to the low conditions.
[0021] Reference Figure 2 , Figure 2 A step flow chart of the preparation method of the insulating layer of the interposer via provided by the embodiment of the application is shown in Figure 2 The preparation method specifically includes the following steps. S101, providing a substrate; wherein the substrate includes an interposer, and the interposer includes a plurality of vias.
[0022] In the embodiment, the substrate can be a silicon substrate, a glass substrate or other materials used for semiconductor packaging, and the substrate at least includes an interposer, which can be a silicon interposer, a glass interposer or other materials, and the interposer includes a plurality of vias, which are used to connect the wafers or lines on both sides of the interposer, and the aspect ratio of the via is 5:1-20:1. Figure 3 , Figure 3 A structural schematic diagram of the via in the embodiment of the application is shown in Figure 3 The sidewall of the via includes a plurality of Si-O dangling bonds.
[0023] S102, placing the substrate in a first reaction cavity, and introducing a precursor into the first reaction cavity at a first preset temperature to perform vapor deposition, so as to form a self-assembled monolayer on the sidewall of the via.
[0024] The precursor includes any one of a silane compound, a mercaptan compound, and a phosphoric acid compound. Specifically, the silane compound such as triethylsilane, 3-mercaptopropyl triethoxysilane, or the like can react with the Si-O dangling bond to form a Si-O-Si bond, thereby terminating the dangling bond activity. In this way, the Si-O dangling bond can be prevented from adsorbing water molecules or contaminants, and the metal adhesion can be reduced. Similarly, the mercaptan compound can react with the Si-O dangling bond to form a Si-O-S bond, and the phosphoric acid compound can react with the Si-O dangling bond to form a Si-O-P bond. All of the three can achieve the effect of terminating the dangling bond activity. It can be understood that the precursor can also include a metal affinity group. In this way, the monolayer formed by the precursor can terminate the dangling bond, and the adhesion of the metal to the interlayer can be optimized, so as to improve the filling efficiency of the metal in the via hole filling process. For example, the precursor can be triethylsilane, 3-mercaptopropyl triethoxysilane, propanethiol, or the like.
[0025] In the self-assembled monolayer deposition process, the precursor is a gas, and the precursor is introduced into the first reaction chamber for vapor deposition. In the vapor deposition process, the deposition temperature is less than 120°C, the pressure in the first reaction chamber during the deposition process is less than 12 Torr, the partial pressure of the precursor is 0.3-0.6 Torr, and the deposition time is 13-18 min.
[0026] S103, the deposited substrate is placed in the second reaction chamber, and the second reaction chamber is alternately pulsed with an insulating material and ozone at a second preset temperature to form an insulating layer.
[0027] The insulating material includes any one of hafnium oxide, aluminum oxide, zirconium oxide, titanium nitride, and silicon nitride. The metal oxide is used to further shield the residual Si-O dangling bond and enhance the insulation. In addition, the metal oxide such as hafnium oxide has a high dielectric constant, which can be used in cooperation with the self-assembled monolayer to shield the charge traps, so that the interlayer has a lower leakage current, the breakdown voltage is improved, and the via hole of the interlayer can be applied to the transmission of high-frequency signals.
[0028] In this embodiment, after the self-assembled monolayer is deposited, the substrate can be placed in the second reaction chamber, and an atomic layer deposition insulating material layer is used. Since the atomic layer deposition is atomically controllable, the coverage of the insulating material layer on the via hole can reach more than 95% at a high aspect ratio, and the process time is short, thereby improving the production efficiency of the interlayer.
[0029] The method for preparing the insulating layer of the via of the interposer provided by the embodiment of the present application adopts silane compounds, phosphoric acid compounds or thiol compounds as precursors to perform vapor deposition on the side wall of the via to form a self-assembled monolayer, the self-assembled monolayer can be combined with Si-O dangling bonds, avoiding the combination of the dangling bonds with water molecules and pollutants to reduce the adhesion of the metal, and then atomic layer deposition is used to cover the metal oxide on the side wall of the via, which can be applied to a via with a high aspect ratio, and the metal oxide deposited by atomic layer deposition is hafnium oxide or other oxides with high dielectric constant, which can shield the charge traps in cooperation with the self-assembled monolayer, so that the packaged semiconductor device can be applied to the transmission of high-frequency signals.
[0030] In an embodiment, the silane compound includes any one of 3-mercaptopropyl triethoxysilane, triethylsilane and 3-(azidopropyl) triethoxysilane, the thiol compound includes any one of propanethiol and 4-mercaptobutyric acid, and the phosphoric acid compound includes 1-octyl phosphoric acid.
[0031] In the embodiment, the silane compound includes 3-mercaptopropyl triethoxysilane, triethylsilane and 3-(azidopropyl) triethoxysilane, and of course can be other silane compounds containing metal affinity groups, and similarly, the thiol compound can include propanethiol and 4-mercaptobutyric acid, and can also include other thiol compounds containing metal affinity groups, and the phosphoric acid compound can include 1-octyl phosphoric acid, and can also include other phosphoric acid compounds containing metal affinity groups, and the silane compound / phosphoric acid compound / thiol compound containing metal affinity groups can improve the adhesion performance of the metal on the side wall of the via, and further improve the durability of the via in a high stress environment.
[0032] In an embodiment, the insulating material includes any one of hafnium dioxide, aluminum oxide, zirconium oxide, titanium nitride and silicon nitride.
[0033] Specifically, the insulating material can be a metal oxide or a metal nitride, wherein the metal oxide includes hafnium dioxide, aluminum oxide or zirconium oxide, and the metal nitride includes titanium nitride or silicon nitride. For example, taking the insulating material as hafnium dioxide as an example, atomic layer deposition is performed by using hafnium dioxide, and the obtained thin film has a high dielectric constant, so that the formed thin film can cooperate with the self-assembled monolayer to shield the charge traps, reduce the leakage current of the via of the interposer, improve the breakdown voltage and improve the reliability of signal transmission.
[0034] In an embodiment, the step S103 specifically includes: first, pulsing the insulating material into the second reaction cavity at a second preset temperature, and after the pulsing is completed, purging the reaction cavity with an inert gas. Next, ozone is pulsed into the second reaction chamber. After the pulse ends, the above steps are repeated until the preset number of times is reached.
[0035] In atomic layer deposition (ALD) processes, alternating pulse and purge cycles are required to control the thickness of the grown film. Therefore, after each pulse, an inert gas is used to purge any remaining gas from the second reaction chamber before the next pulse. The thickness of the grown insulating material layer can be controlled by adjusting the number of cycles. In this embodiment, the thickness of the film formed by ALD can be 3-6 nm.
[0036] In one embodiment, the preset number of times is 40-80.
[0037] For example, the preset number of cycles can be 40, 50, 60, 70 or 80. The thickness of the thin film formed by atomic layer deposition varies with the number of cycles, and the number of cycles can be adjusted according to the required thickness.
[0038] In one embodiment, the first preset temperature is less than 120°C, the pressure of the first reaction chamber is less than 12 Torr, the partial pressure of the precursor is 0.3-0.6 Torr, and the preset time is 13-18 min.
[0039] In this embodiment, the conditions required for self-assembled monolayer deposition are relatively low, and deposition can be achieved at temperatures below 120°C. When the substrate is a glass substrate, a reaction temperature below 120°C helps reduce the thermal stress on the glass substrate, making the preparation method suitable for relatively fragile glass interlayers. When the pressure in the first reaction chamber is less than 12 Torr, the lower pressure can enhance the diffusion ability of the precursor in the high aspect ratio via. This ensures that the self-assembled monolayer can cover the bottom of the via and that the Si-O dangling bonds at each position on the sidewall of the via can react with the self-assembled monolayer and terminate.
[0040] For example, the first preset temperature can be 30℃, 50℃, 70℃, 90℃ or 110℃, etc., the pressure of the first reaction chamber can be 1 Torr, 4 Torr, 7 Torr or 11 Torr, etc., the partial pressure of the precursor can be 0.3 Torr, 0.4 Torr, 0.5 Torr or 0.6 Torr, etc., and the preset time can be 13min, 14min, 15min, 16min, 17min or 18min, etc.
[0041] In one embodiment, the second preset temperature is 50-300°C, and the pressure in the second reaction chamber is 0.1-0.5 Torr.
[0042] For example, the second preset temperature can be 50 DEG C, 80 DEG C, 100 DEG C, 150 DEG C, 200 DEG C, 250 DEG C or 290 DEG C, and the pressure of the second reaction cavity can be 0.1 Torr, 0.2 Torr, 0.3 Torr, 0.4 Torr or 0.5 Torr.
[0043] The preparation method of the insulating layer of the via of the interposer provided by the embodiment of the present application adopts silane compounds, phosphoric acid compounds or mercaptan compounds as precursors to perform vapor deposition on the sidewall of the via to form a self-assembled monolayer, the self-assembled monolayer can be combined with Si-O dangling bonds, so that the combination of the dangling bonds with water molecules and pollutants is avoided to reduce the adhesion of the metal, and then atomic layer deposition is used to cover the metal oxide on the sidewall of the via, which can be applied to a via with a high aspect ratio, and the metal oxide deposited by atomic layer deposition is hafnium oxide or other oxides with high dielectric constant, which can be used in combination with the self-assembled monolayer to shield charge traps, so that the packaged semiconductor device can be applied to the transmission of high-frequency signals.
[0044] In the second aspect of the present application, an insulating layer of a via of an interposer is provided, which is prepared by the preparation method of the insulating layer of the via of the interposer according to the first aspect.
[0045] In the embodiment, the insulating layer includes a self-assembled monolayer deposited by the self-assembled monolayer and a protective layer deposited by atomic layer deposition, wherein the thickness of the self-assembled monolayer is 1-2 nm, and the thickness of the protective layer is 3-6 nm, for example, the thickness of the self-assembled monolayer can be 1 nm, 1.3 nm, 1.5 nm, 1.7 nm or 2 nm, and the thickness of the protective layer can be 3 nm, 4 nm, 5 nm or 6 nm.
[0046] In an embodiment, referring to Figure 4 , Figure 4 The structure of the interposer provided by the embodiment of the present application is shown in the figure, Figure 4 The insulating layer is formed on the sidewall of the via of the interposer, and the aspect ratio of the via of the interposer is 5:1-20:1.
[0047] The insulating layer is located on the sidewall of the via of the interposer, so that the self-assembled monolayer in the insulating layer can directly contact with the Si-O dangling bond to terminate the dangling bond, and the aspect ratio of the via of the interposer can be 5:1, 10:1, 15:1 or 20:1.
[0048] The insulating layer of the via of the interposer provided by the embodiment of the present application is formed by the self-assembled monolayer and the protective layer. Since the self-assembled monolayer is formed by silane compounds, phosphoric acid compounds or thiol compounds, the self-assembled monolayer can react with the Si-O dangling bonds on the sidewall of the via of the interposer, so as to terminate the dangling bonds. In addition, the metal affinity groups included in the silane compounds, the phosphoric acid compounds or the thiol compounds can improve the bonding performance between the metal and the interposer, improve the firmness of copper filling, improve the performance of the interposer and improve the durability of the via in a high stress environment.
[0049] In order to make the skilled in the art better understand the present application, the following will illustrate one kind of insulating layer of the via of the interposer and the preparation method thereof by multiple specific embodiments.
[0050] Embodiment 1 The glass interposer includes a via, the depth of the via is 100 μm, and the diameter of the via is 10 μm (aspect ratio = 10:1). The glass interposer is placed in a first reaction chamber, and a precursor is introduced into the first reaction chamber at 50°C for vapor deposition, so as to form a self-assembled monolayer on the sidewall of the via. The pressure of the first reaction chamber is 5 Torr, the partial pressure of the precursor is 0.3 Torr, and the precursor is 3-mercaptopropyltriethoxysilane. After the deposition, the substrate is placed in a second reaction chamber, and hafnium dioxide is pulsed into the second reaction chamber at 80°C. After the pulse is completed, the second reaction chamber is purged with an inert gas. Then, the second reaction chamber is pulsed with ozone, and after the pulse is completed, the above steps are repeated 50 times to form the insulating layer. The pressure of the second reaction chamber is 0.5 Torr, the insulating material is hafnium dioxide, and the duration is 13 min.
[0051] The via of the insulating layer formed by the embodiment 1 is used in the copper filling process, and the adhesion to copper can reach more than 10 MPa, and the coverage of the insulating layer in the via is greater than 95%, and the leakage current is less than 10 -9 A / cm 2 The breakdown voltage is improved by 20% compared with the via used in the related art.
[0052] Embodiment 2 The glass interposer includes a via, the depth of the via is 200 μm, and the diameter of the via is 10 μm (aspect ratio = 20:1). The glass interposer is placed in a first reaction chamber, and a precursor is introduced into the first reaction chamber at 80°C for vapor deposition to form a self-assembled monolayer on the sidewall of the via; wherein the pressure of the first reaction chamber is 10 Torr, the partial pressure of the precursor is 0.6 Torr, and the precursor is 3-mercaptopropyltriethoxysilane; The deposited substrate is placed in a second reaction chamber, and hafnium dioxide is pulsed into the second reaction chamber at 100°C, and after the pulse is over, the second reaction chamber is purged with an inert gas; Then, ozone is pulsed into the second reaction chamber, and after the pulse is over, the above steps are repeated 80 times to form the insulating layer; wherein the pressure of the second reaction chamber is 0.3 Torr, and the duration is 13 min.
[0053] The via formed by the insulating layer of the present embodiment 2 is used in a copper filling process, and the adhesion to copper can reach more than 10 MPa, and the coverage of the insulating layer in the via is greater than 95%, and the leakage current is less than 10 -9 A / cm 2 The breakdown voltage is improved by 20% compared with the via used in the related art.
[0054] Embodiment 3 A glass interposer is provided, which includes a via with a depth of 200 μm and a diameter of 10 μm (aspect ratio = 20:1) The glass interposer is placed in a first reaction chamber, and a precursor is introduced into the first reaction chamber at 80°C for vapor deposition to form a self-assembled monolayer on the sidewall of the via; wherein the pressure of the first reaction chamber is 10 Torr, the partial pressure of the precursor is 0.6 Torr, and the precursor is 3-mercaptopropyltriethoxysilane; The deposited substrate is placed in a second reaction chamber, and hafnium dioxide is pulsed into the second reaction chamber at 100°C, and after the pulse is over, the second reaction chamber is purged with an inert gas; Then, ozone is pulsed into the second reaction chamber, and after the pulse is over, the above steps are repeated 80 times to form the insulating layer; wherein the pressure of the second reaction chamber is 0.3 Torr, and the duration is 13 min.
[0055] The via formed by the insulating layer of the present embodiment 3 is used in a copper filling process, and the adhesion to copper can reach more than 10 MPa, and the coverage of the insulating layer in the via is greater than 95%, and the leakage current is less than 10 -9 A / cm 2 The breakdown voltage is improved by 20% compared with the via used in the related art.
[0056] Embodiment 4 A glass via is provided, the glass via includes a via hole, the depth of the via hole is 100 μm, the diameter of the via hole is 10 μm (aspect ratio = 10:1) The glass via is placed in a first reaction chamber, and a precursor is introduced into the first reaction chamber at 80°C for vapor deposition to form a self-assembled monolayer on the sidewall of the via hole; wherein the pressure of the first reaction chamber is 10 Torr, the partial pressure of the precursor is 0.6 Torr, and the precursor is propyl mercaptan; The deposited substrate is placed in a second reaction chamber, and silicon nitride is pulsed into the second reaction chamber at 100°C, and after the pulse is over, the second reaction chamber is purged with an inert gas; Then, ozone is pulsed into the second reaction chamber, and after the pulse is over, the above steps are repeated 80 times to form the insulating layer; wherein the pressure of the second reaction chamber is 0.3 Torr, and the duration is 13 min.
[0057] The via hole formed by the insulating layer of this embodiment 4 is used in the copper filling process, the adhesion to copper can reach more than 10 MPa, and the coverage of the insulating layer in the via hole is greater than 95%, and the leakage current is 10 -9 A / cm 2 The breakdown voltage is improved by 20% compared with the via hole used in the related art.
[0058] Embodiment 5 A glass via is provided, the glass via includes a via hole, the depth of the via hole is 100 μm, the diameter of the via hole is 10 μm (aspect ratio = 10:1) The glass via is placed in a first reaction chamber, and a precursor is introduced into the first reaction chamber at 80°C for vapor deposition to form a self-assembled monolayer on the sidewall of the via hole; wherein the pressure of the first reaction chamber is 10 Torr, the partial pressure of the precursor is 0.6 Torr, and the precursor is 1-octyl phosphonic acid; The deposited substrate is placed in a second reaction chamber, and titanium nitride is pulsed into the second reaction chamber at 100°C, and after the pulse is over, the second reaction chamber is purged with an inert gas; Then, ozone is pulsed into the second reaction chamber, and after the pulse is over, the above steps are repeated 80 times to form the insulating layer; wherein the pressure of the second reaction chamber is 0.3 Torr, and the duration is 13 min.
[0059] The via hole formed by the insulating layer of this embodiment 4 is used in the copper filling process, the adhesion to copper can reach more than 10 MPa, and the coverage of the insulating layer in the via hole is greater than 95%, and the leakage current is 10 -9 A / cm 2 The breakdown voltage is improved by 20% compared with the via hole used in the related art.
[0060] Each of the various embodiments in the present specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be mutually referred to.
[0061] Finally, it should be noted that the relational terms herein, such as first and second, and the like, are used solely to distinguish one from another entity or action, without necessarily requiring or implying any such actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.
[0062] The above describes in detail an insulating layer of a via in an interposer and a method for manufacturing the same. The principles and implementation manners of the present disclosure are described by using specific examples. The above description of the embodiments is only for the purpose of helping understand the method and core idea of the present disclosure. Meanwhile, for those skilled in the art, the specific implementation manners and application ranges can be changed according to the idea of the present disclosure. In summary, the content of the present specification should not be understood as a limitation of the present disclosure.
[0063] Other embodiments of the present disclosure will be apparent to those skilled in the art upon consideration of the specification and practice of the present disclosure. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure following, in general, the principles of the present disclosure and including such departures from the present disclosure that come within known or customary practice within the art to which the present disclosure pertains. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.
[0064] It should be understood that the present disclosure is not limited to the precise structures described herein and illustrated in the drawings and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is indicated by the appended claims, and their equivalents.
[0065] As used herein, the term "one embodiment," "an embodiment," or "one or more embodiments,” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
[0066] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
[0067] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The disclosure can be implemented by means of both hardware and software, and any combinations thereof. In a unitary claim, several devices, apparatuses and / or means can be listed, comprising means for carrying out a certain task. The use of the term "means" in a claim is intended to refer to a combination of interrelated means for performing the task. The word "comprising" does not exclude other elements being present in addition to those listed in a claim. The word "first", "second", "third", etc. does not imply any order. The mere fact that measures are recited in mutually different dependent claims does not indicate that a combination of these measures can not be used to advantage.
[0068] Finally, it should be noted that the above-mentioned embodiments are merely intended for describing and illustrating, not limiting the technical solutions of the present disclosure; even if the technical solutions of the present disclosure are described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A method for preparing an insulating layer with an intermediate through-hole, characterized in that, The preparation method includes: A substrate is provided; wherein the substrate includes an interposer layer, and the interposer layer includes a plurality of through-holes; The substrate is placed in a first reaction chamber, and a precursor is introduced into the first reaction chamber at a first preset temperature for vapor deposition to form a self-assembled monolayer on the sidewall of the through hole; wherein the precursor includes any one of silane compounds, thiol compounds, and phosphoric acid compounds. The deposited substrate is placed in a second reaction chamber, and insulating material and ozone are alternately pulsed into the second reaction chamber at a second preset temperature to form the insulating layer; wherein the insulating material includes any one of hafnium oxide, aluminum oxide, zirconium oxide, titanium nitride, and silicon nitride.
2. The method for preparing the insulating layer of the intermediate through-hole according to claim 1, characterized in that, The silane compounds include any one of 3-mercaptopropyltriethoxysilane, triethylsilane, and 3-(azidopropyl)triethoxysilane; the thiols include any one of propanethiol and 4-mercaptobutyric acid; and the phosphoric acid compounds include 1-octylphosphine.
3. The method for preparing the insulating layer of the intermediate layer through-hole according to claim 1, characterized in that, The insulating material includes any one of hafnium dioxide, aluminum oxide, zirconium oxide, titanium nitride, and silicon nitride.
4. The method for preparing the insulating layer of the intermediate through-hole according to claim 1, characterized in that, The alternating pulse of insulating material and ozone into the second reaction chamber at a second preset temperature includes: The insulating material is pulsed into the second reaction chamber at a second preset temperature. After the pulse ends, the reaction chamber is purged with inert gas. Ozone is pulsed into the second reaction chamber. After the pulse ends, the above steps are repeated until the preset number of times is reached.
5. The method for preparing the insulating layer of the intermediate layer through-hole according to claim 4, characterized in that, The preset number of times is 40-80.
6. The method for preparing the insulating layer of the intermediate layer through-hole according to claim 1, characterized in that, The first preset temperature is less than 120°C, the pressure of the first reaction chamber is 0-12 Torr, the partial pressure of the precursor is 0.3-0.6 Torr, and the preset time is 13-18 min.
7. The method for preparing the insulating layer of the intermediate through-hole according to claim 1, characterized in that, The second preset temperature is 50-300℃, and the pressure in the reaction chamber is 0.01-20 Torr.
8. An insulating layer with an intermediate through-hole, characterized in that, It is prepared by the method for preparing the insulating layer of the intermediate layer through-hole as described in any one of claims 1-8.
9. The insulating layer of the intermediate layer through-hole according to claim 8, characterized in that, The insulating layer is formed on the sidewall of the intermediate layer via, and the aspect ratio of the intermediate layer via is 5:1-20:1.