Method for forming a hybrid bonded structure and hybrid bonded wafer

Abstract

This application provides a method for forming a hybrid bonding structure and the hybrid bonding structure itself. The method for forming the hybrid bonding structure includes: forming a redistribution wafer. The redistribution wafer includes: a substrate, a second dielectric layer, a first dielectric layer, and a redistribution layer stacked sequentially; wherein, a pre-fabricated via structure is formed in the first dielectric layer. The pre-fabricated via structure penetrates the first dielectric layer. The redistribution layer of the redistribution wafer is bonded to the first wafer. The substrate of the redistribution wafer is removed. The second dielectric layer is ground to expose the surface of the pre-fabricated via structure away from the redistribution layer; wherein, the exposed pre-fabricated via structure forms a hybrid bonding structure. The first dielectric layer of the redistribution wafer is bonded to the second wafer; wherein, the hybrid bonding structure serves as the bonding point of the redistribution wafer.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a method for forming a hybrid bonding structure and a hybrid bonding wafer. Background Technology

[0002] As integrated circuit technology advances towards three-dimensional integration, hybrid bonding technology has become an important means of achieving high-density interconnects between chips. This technology, through precise alignment and connection at the wafer level, can effectively improve signal transmission efficiency and wiring flexibility in chip stacking structures, and is widely used in high-performance computing, memory expansion, and other scenarios.

[0003] In existing technologies, redistribution layers (RDLs) are typically used to provide additional wiring resources for 3D stacked structures, and electrical connections between upper and lower layers are achieved through dielectric layers and via structures. However, in actual manufacturing processes, the alignment accuracy requirements between the via structures and the redistribution layers are stringent. The traditional "via fabrication after bonding" process is prone to alignment deviations due to wafer distortion caused by bonding, making it difficult to achieve precise vertical alignment between the two, resulting in poor interconnect stability and low process yield. Furthermore, traditional processes require an additional pad fabrication step after via fabrication, increasing process complexity. Summary of the Invention

[0004] This application provides a method for forming a hybrid bonding structure and a hybrid bonding wafer. When forming a redistribution wafer, a pre-fabricated via structure is formed in advance, which avoids alignment deviations caused by wafer warping or process fluctuations after bonding, and reduces process complexity.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides a method for forming a hybrid bonding structure, the method comprising: forming a redistribution wafer; the redistribution wafer comprising: a substrate, a second dielectric layer, a first dielectric layer, and a redistribution layer stacked sequentially; wherein, a pre-fabricated via structure is formed in the first dielectric layer; the pre-fabricated via structure penetrates the first dielectric layer; bonding the redistribution layer of the redistribution wafer to the first wafer; removing the substrate of the redistribution wafer; grinding the second dielectric layer to expose the surface of the pre-fabricated via structure away from the redistribution layer; wherein, the exposed pre-fabricated via structure forms a hybrid bonding structure; bonding the first dielectric layer of the redistribution wafer to the second wafer; wherein, the hybrid bonding structure serves as the bonding point of the redistribution wafer.

[0007] In some embodiments of this disclosure, after the second dielectric layer is polished to expose the surface of the pre-fabricated via structure away from the redistribution layer, the exposed pre-fabricated via structure also forms a virtual bonding structure; the virtual bonding structure is located between two adjacent hybrid bonding structures, and the virtual bonding structure is used to balance the consistency of the bonding interface.

[0008] In some embodiments of this disclosure, the method of forming the redistribution wafer includes: sequentially depositing a second dielectric layer and a first dielectric layer on the substrate; etching along the upper surface of the first dielectric layer to form a first via penetrating the first dielectric layer; filling the first via with a metal material to form the pre-fabricated via structure; depositing a third dielectric layer on the first dielectric layer; etching the upper surface of the third dielectric layer and filling it to form the redistribution layer, thereby forming the redistribution wafer.

[0009] In some embodiments of this disclosure, the first through hole has a T-shaped cross-section; the first through hole includes: a straight hole and a groove that are interconnected in a vertical direction; wherein the width of the groove is greater than the diameter of the straight hole.

[0010] In some embodiments of this disclosure, a prefabricated through-hole structure is formed by filling the first through-hole with a double damask process.

[0011] In some embodiments of this disclosure, the pre-fabricated via structure penetrates the first dielectric layer and is partially embedded in the second dielectric layer; the method of forming the hybrid bonding structure includes: removing the second dielectric layer and the pre-fabricated via structure embedded therein by a grinding process, exposing the surface of the remaining pre-fabricated via structure away from the redistribution layer.

[0012] In some embodiments of this disclosure, the redistribution wafer further includes: a stripping modifier layer stacked sequentially; the stripping modifier layer is located between the substrate and the second dielectric layer; removing the substrate of the redistribution wafer includes: removing the stripping modifier layer by a thermal bonding process, thereby separating the substrate and the second dielectric layer.

[0013] In some embodiments of this disclosure, the redistribution wafer further includes: a buffer layer and a thin film layer stacked sequentially; the buffer layer is located between the substrate and the second dielectric layer, and the thin film layer is located between the second dielectric layer and the first dielectric layer.

[0014] In some embodiments of this disclosure, removing the substrate from the redistribution wafer further includes: thinning the substrate by a grinding process; and removing the substrate by a chemical mechanical polishing process.

[0015] In some embodiments of this disclosure, bonding the redistribution layer of the redistribution wafer to the first wafer includes: etching the upper surface of the third dielectric layer to form a second via; exposing a portion of the redistribution layer in the second via; filling the second via to form a pad; the pad contacting the redistribution layer; and bonding the redistribution layer of the redistribution wafer to the first wafer through the pad.

[0016] This disclosure also provides a hybrid bonding wafer, comprising: a first wafer, a redistribution wafer, and a second wafer; the redistribution wafer comprising: a second dielectric layer, a first dielectric layer, and a redistribution layer stacked sequentially; wherein, the first dielectric layer includes a hybrid bonding structure formed by the above method; the hybrid bonding structure is formed before the redistribution layer of the redistribution wafer is bonded to the first wafer; the hybrid bonding structure penetrates the first dielectric layer; the redistribution layer of the redistribution wafer is bonded to the first wafer; the first dielectric layer of the redistribution wafer is bonded to the second wafer; wherein, the hybrid bonding structure serves as a bonding point of the redistribution wafer.

[0017] The embodiments of this application have the following beneficial effects: When forming a redistribution wafer, a first dielectric layer is prepared in advance, and a pre-fabricated via structure is formed within the first dielectric layer. Compared to forming the first dielectric layer after the redistribution wafer is bonded to the first wafer, the surface structure of the redistribution wafer before bonding is simple, without complex functional layers, and a first dielectric layer film with good thickness consistency can be obtained through deposition processes. Simultaneously, forming the pre-fabricated via structure in advance on the first dielectric layer with good thickness consistency can avoid alignment deviations caused by wafer deformation or process fluctuations after multiple bonding processes, thus improving alignment accuracy. Furthermore, the pre-fabricated via structure penetrates the first dielectric layer, eliminating the need for additional pad connection structure preparation steps in subsequent processes; bonding can be performed simply by grinding the second dielectric layer to expose the surface of the hybrid bonding structure. The through-hole design of the pre-fabricated via structure effectively simplifies the process flow and reduces costs.

[0018] After forming the redistribution wafer, the redistribution layer of the redistribution wafer is bonded to the first wafer. Then, the substrate of the redistribution wafer is removed, leaving only the redistribution layer bonded to the surface of the first wafer. The redistribution layer provides the first wafer with high-density signal redistribution and I / O (input / output) port expansion capabilities, while avoiding the thickness redundancy, thermal resistance, and cost issues associated with the substrate. Finally, a hybrid bonding structure is used to achieve high-precision bonding between the first and second wafers, thereby improving signal transmission efficiency and interconnect reliability in the package. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0020] Figure 1 This is a schematic flowchart of the method for forming a hybrid bonding structure provided in the embodiments of this application;

[0021] Figure 2 This is a schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application. Figure 1 ;

[0022] Figure 3 This is a schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application. Figure 2 ;

[0023] Figure 4 This is a schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application. Figure 3 ;

[0024] Figure 5 Schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application Figure 4 ;

[0025] Figure 6 Schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application Figure 5 ;

[0026] Figure 7 Schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application Figure 6 ;

[0027] Figure 8 Schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application Figure 7 ;

[0028] Figure 9 Schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application Figure 8 ;

[0029] Figure 10 Schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application Figure 9 ;

[0030] Figure 11 Schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application Figure 10 ;

[0031] Figure 12 Schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application Figure 10 one;

[0032] Figure 13 Schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application Figure 10 two;

[0033] Figure 14 Schematic diagram of the method for forming a hybrid bonding structure provided in the embodiments of this application Figure 10 three. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of the invention will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate the embodiments of this application, but are not intended to limit the scope of the embodiments of this application.

[0035] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0036] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0037] In this document, when a layer / component is referred to as being "above" another layer / component, the layer / component may be directly above the other layer / component, or there may be an intermediate layer / component between them. Furthermore, in one orientation, a layer / component is "above" another layer / component; when the orientation is reversed, the layer / component may be "below" the other layer / component.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of embodiments of this application.

[0039] In conventional processes, when a redistribution layer 141 needs to be bonded to the surface of a wafer to be bonded (i.e., the first wafer 20 in this application), the following steps are performed sequentially: First, the redistribution wafer 10 is bonded to the wafer to be bonded (i.e., the first wafer 20 in this application), and the substrate 11 of the redistribution wafer 10 is removed; then, a dielectric layer is deposited on the exposed surface of the redistribution layer 141; finally, a hybrid bonding structure 123 including vias and pads is fabricated on the dielectric layer.

[0040] In this application, when preparing the redistribution wafer 10, that is, before the redistribution wafer 10 is bonded to the first wafer 20, a first dielectric layer 13 and a second dielectric layer 12 are prepared in advance, and a pre-fabricated via structure 122 is prepared in the first dielectric layer 13. The pre-fabricated via structure 122 penetrates the first dielectric layer 13 and is partially embedded in the second dielectric layer 12. In conjunction with the subsequent polishing process, a hybrid bonding structure 123 and a virtual bonding structure 124 are formed.

[0041] This application provides a method for forming a hybrid bonding structure, referring to... Figure 1 As shown, the method for forming the hybrid bonding structure includes Figure 1 Steps S101-S105 are shown. Each step will be explained in detail.

[0042] S101: Forming a redistribution wafer. The redistribution wafer includes: a substrate, a second dielectric layer, a first dielectric layer, and a redistribution layer stacked sequentially; wherein, a pre-fabricated via structure is formed in the first dielectric layer; the pre-fabricated via structure penetrates the first dielectric layer.

[0043] In this embodiment of the disclosure, reference is made to Figure 5 and Figure 6 As shown, a redistribution wafer 10 is formed. The redistribution wafer 10 includes a substrate 11, a second dielectric layer 12, a first dielectric layer 13, and a redistribution layer 141 stacked sequentially; wherein, a pre-fabricated via structure 122 is formed in the first dielectric layer 13; the pre-fabricated via structure 122 penetrates the first dielectric layer 13. When the first dielectric layer 13 is formed on the surface of the substrate 11, since the surface of the redistribution wafer 10 has no complex functional layers (such as the redistribution layer 141), the structure is simple and has high flatness, and a thin film of the first dielectric layer 13 with good thickness uniformity can be prepared by deposition process. The first dielectric layer has good uniformity, which allows for precise control of the depth, aperture, and sidewall morphology during its formation, avoiding defects such as etching residue and sidewall tilt, thereby ensuring precise alignment with the redistribution layer 141. The second dielectric layer 12 is used to protect the first dielectric layer 13 and prevent damage to the first dielectric layer 13 in the subsequent process of removing the substrate 11.

[0044] It should be noted that redistribution wafer 10 is an advanced chip packaging technology. It involves "re-fabricating" one or more new metal circuit layers on the surface of a silicon wafer using semiconductor processes. This allows the pads on the wafer, which were originally very small in pitch, to be redistributed to positions with larger pitch and a more reasonable layout, thereby facilitating electrical connections to the outside.

[0045] S102: Bond the redistribution layer of the redistribution wafer to the first wafer.

[0046] In this embodiment of the disclosure, reference is made to Figure 7 As shown, the redistribution wafer 10 is bonded to the first wafer 20 using a hybrid bonding process. This hybrid bonding process enables high-density, low-resistance, and low-latency interconnects, making it suitable for advanced packaging applications such as high-performance computing chips and memory chips.

[0047] S103: Remove the substrate from the redistribution wafer.

[0048] In this embodiment of the disclosure, combined with Figure 7 and Figure 8 As shown, the removal method can be selected according to the composite thin film structure (the thin film between the substrate 11 and the redistribution layer 141), such as grinding, chemical mechanical polishing, wet etching or thermal bonding.

[0049] S104: The second dielectric layer is ground to expose the surface of the pre-fabricated via structure away from the redistribution layer; wherein the pre-fabricated via structure exposed on the surface forms a hybrid bonding structure.

[0050] In this embodiment of the disclosure, combined with Figure 8 and Figure 9 As shown, the second dielectric layer 12 is ground to expose the surface of the pre-fabricated via structure 122 away from the redistribution layer 141. The exposed pre-fabricated via structure 122 forms a hybrid bonding structure 123. The hybrid bonding structure 123 serves as the bonding point for subsequent bonding processes and is bonded to the second wafer.

[0051] S105: Bond the first dielectric layer of the redistribution wafer to the second wafer; wherein, the hybrid bonding structure serves as the bonding point of the redistribution wafer.

[0052] In this embodiment of the disclosure, reference is made to Figure 14 As shown, the exposed hybrid bonding structure 123 serves as the bonding point for the redistribution wafer, enabling the first dielectric layer 13 of the first wafer 20 to bond with the second wafer 30.

[0053] It should be noted that the reference Figure 12 As shown, the second wafer 30 includes contact pads. The contact pads are bonded to the hybrid bonding structure 123 to achieve electrical connection and signal transmission between the two wafers.

[0054] Understandably, when forming the redistribution wafer 10, a first dielectric layer 13 is prepared in advance, and a pre-fabricated via structure 122 is formed in the first dielectric layer 13. Compared to the formation of the first dielectric layer 13 after the redistribution wafer 10 is bonded to the first wafer 20, the surface structure of the redistribution wafer 10 before bonding is simple, without complex functional layers, and a thin film of the first dielectric layer 13 with good thickness consistency can be obtained through deposition processes. At the same time, the pre-fabricated via structure 122 formed in advance on the first dielectric layer 13 with good thickness consistency can avoid alignment deviations caused by wafer deformation or process fluctuations after multiple bonding, thus improving alignment accuracy. In addition, the pre-fabricated via structure 122 penetrates the first dielectric layer 13, so that there is no need to add an additional preparation step for the pad connection structure in subsequent processes. Only the second dielectric layer 12 needs to be ground to expose the surface of the hybrid bonding structure 123 for bonding. The through-hole design of the pre-fabricated via structure 122 effectively simplifies the process flow and reduces costs.

[0055] After forming the redistribution wafer 10, the redistribution layer 141 of the redistribution wafer 10 is bonded to the first wafer 20. Then, the substrate 11 of the redistribution wafer 10 is removed, leaving only the redistribution layer 141 bonded to the surface of the first wafer 20. The redistribution layer 141 provides the first wafer 20 with high-density signal redistribution and I / O (input / output) port expansion capabilities, while avoiding the thickness redundancy, thermal resistance, and cost issues associated with the substrate 11. Finally, the first wafer 20 and the second wafer 30 are bonded with high precision using a hybrid bonding structure 123, thereby improving signal transmission efficiency and interconnect reliability in the package.

[0056] In some embodiments of this disclosure, after the second dielectric layer 12 is polished to expose the surface of the pre-fabricated via structure 122 away from the redistribution layer 141, the exposed pre-fabricated via structure 122 also forms a virtual bonding structure 124; the virtual bonding structure 124 is located between two adjacent hybrid bonding structures 123, and the virtual bonding structure 124 is used to balance the consistency of the bonding interface.

[0057] For example, refer to Figure 9 As shown, the virtual bonding structure 124 is located between two adjacent hybrid bonding structures 123 along the first direction X.

[0058] It should be noted that, referring to Figure 9 As shown, the virtual bonding structure 124, being a virtual structure, does not contact other functional structures and is used to balance the consistency of the bonding interface, reducing the problem of uneven stress distribution. The virtual bonding structure 124 is located between two adjacent hybrid bonding structures 123, which can further enhance the balancing effect of the virtual bonding structure 124 on the consistency of the bonding interface.

[0059] It should also be noted that, referring to Figure 12 As shown, the second wafer 30 also includes virtual pads. These virtual pads are bonded to the virtual bonding structure 124. The virtual pads also do not contact other functional structures, serving to balance the consistency of the bonding interface and reduce uneven stress distribution.

[0060] In some embodiments of this disclosure, such as Figures 2 to 5 As shown, the pre-fabricated via structure 122 penetrates the first dielectric layer 13 and is partially embedded in the second dielectric layer 12. The method for forming the redistribution wafer 10 includes steps S201-S205. Each step will be described in conjunction with the previous steps.

[0061] S201: Sequentially deposit the second dielectric layer and the first dielectric layer on the substrate.

[0062] In this embodiment of the disclosure, reference is made to Figure 2 As shown, a second dielectric layer 12 and a first dielectric layer 13 are sequentially deposited on a substrate 11. Both the first dielectric layer 13 and the second dielectric layer 12 are made of silicon oxide or other semiconductor insulating materials. The first dielectric layer 13 is used for subsequent fabrication of the pre-fabricated via structure 122, and the second dielectric layer 12 is used to protect the first dielectric layer 13 in subsequent processes.

[0063] S202: Etch along the upper surface of the first dielectric layer to form a first through-hole penetrating the first dielectric layer.

[0064] In this embodiment of the disclosure, reference is made to Figure 3 As shown, by selectively etching the first dielectric layer 13, a first through hole 121 for subsequent metal filling is formed on the upper surface of the first dielectric layer 13. The first through hole 121 penetrates the first dielectric layer 13.

[0065] S203: Fill the first through hole with metal material to form a prefabricated through hole structure.

[0066] In this embodiment of the disclosure, reference is made to Figure 4 As shown, a pre-fabricated through-hole structure 122 is formed by filling the first through-hole 121 with a metallic material. The filling material is typically a metal with excellent electrical conductivity, such as copper (Cu) or aluminum (Al), and is applied to the corresponding positions using an electroplating process. The pre-fabricated through-hole structure 122 can serve as a positioning reference during hybrid bonding, improving alignment accuracy and thus enhancing the overall performance after stacking.

[0067] S204: Deposit a third dielectric layer on the first dielectric layer.

[0068] In this embodiment of the disclosure, reference is made to Figure 5As shown, a third dielectric layer 14 is deposited on the first dielectric layer 13. The third dielectric layer 14 is also made of insulating material and is used for the subsequent fabrication of a redistribution layer 141 that is electrically connected to the pre-fabricated via structure 122, and serves as a support layer for the subsequent redistribution layer 141.

[0069] S205: Etch the upper surface of the third dielectric layer and fill it to form a redistribution layer, thereby forming a redistribution wafer.

[0070] In this embodiment of the disclosure, reference is made to Figure 5 As shown, wiring trenches are formed on the third dielectric layer 14 by etching, and then a redistribution layer 141 is formed by metal filling. The patterned design of the redistribution layer 141 can be flexibly adjusted according to actual wiring requirements to optimize signal paths, reduce latency, and increase wiring density. The formation process of the redistribution layer 141 can employ a dual damask process, simplifying the process flow and reducing costs and yield losses.

[0071] In some embodiments of this disclosure, combined with Figure 3 and Figure 5 As shown, the cross-section of the first through hole 121 is T-shaped. The first through hole 121 includes a straight hole and a groove that are interconnected in a vertical direction. The width of the groove along the first direction X is greater than the diameter of the straight hole.

[0072] It should be noted that, in combination Figure 3 and Figure 5 As shown, the first through-hole 121 consists of two interconnected parts: one part is a straight hole extending vertically into the first dielectric layer 13, and the other part is a groove extending laterally above the straight hole. The diameter of the straight hole is typically small, and direct alignment with the redistribution layer 141 can easily lead to alignment errors. By designing a wider groove at the end of the straight hole, the lateral dimension of the upper interface of the straight hole is enlarged, forming a "surface contact" rather than a "point contact." During subsequent alignment with the redistribution layer 141, as long as the alignment mark falls within the wider groove, electrical connection with the straight hole below can be ensured. The wider groove above the straight hole effectively improves alignment accuracy and increases the process design window.

[0073] In some embodiments of this disclosure, a pre-fabricated through-hole structure 122 is formed by filling the first through-hole 121 using a double damask process. (Refer to...) Figure 3 and Figure 4 As shown, by using the double damask process to simultaneously form straight holes and grooves in the same process flow, the process flow is simplified and costs and yield losses are reduced.

[0074] In some embodiments of this disclosure, reference is made to Figure 7As shown, the redistribution wafer 10 further includes: a stripping modification layer 16 stacked sequentially; the stripping modification layer 16 is located between the substrate 11 and the second dielectric layer 12; step S103 may specifically include step S301.

[0075] S301: The stripping modified layer is removed through a thermal bonding process, separating the substrate and the second dielectric layer.

[0076] In this embodiment of the disclosure, combined with Figure 7 and Figure 8 As shown, the release modifier layer 16 is used to achieve controlled release of the substrate 11, avoiding wafer damage caused by mechanical polishing or chemical etching. The release modifier layer 16 is typically made of silicon oxide, silicon nitride, or other composite materials with low bonding strength. Heating causes the release modifier layer 16 to thermally decompose, thereby breaking the adhesion between the release modifier layer 16 and the substrate 11, achieving physical separation of the second dielectric layer 12 from the substrate 11. The separated silicon substrate 11 can be reused in the fabrication of the redistribution wafer 10, reducing costs.

[0077] In some embodiments of this disclosure, reference is made to Figure 7 As shown, the redistribution wafer 10 further includes a buffer layer 15 and a thin film layer 17 stacked sequentially. The buffer layer 15 is located between the substrate 11 and the second dielectric layer 12, and the thin film layer 17 is located between the second dielectric layer 12 and the first dielectric layer 13. The buffer layer 15 is typically made of silicon oxide. Made of insulating materials, it possesses excellent dielectric properties and thermal stability. The buffer layer 15 absorbs and disperses interlayer stress, balancing the overall structural stress. A thin film layer 17 is deposited on the surface of the buffer layer 15 and can be made of silicon nitride (SiN) or silicon carbonitride (SiCN) thin films. The thin film layer 17 exhibits excellent chemical stability and mechanical strength, improving alignment accuracy and bonding strength in hybrid bonding processes.

[0078] In some embodiments of this disclosure, step S103 may further include steps S401-S402. These steps will be described in conjunction with the specific embodiments.

[0079] S401: The substrate is thinned through a grinding process.

[0080] In this embodiment of the disclosure, combined with Figure 7 and Figure 8 As shown, polishing is a physical processing method that typically uses polishing wheels or belts to treat the wafer surface. Polishing can be used to thin and quickly remove large amounts of substrate material, thereby improving process efficiency.

[0081] S402: Remove the substrate using a chemical mechanical polishing process.

[0082] In this embodiment of the disclosure, combined with Figure 7and Figure 8 As shown, after the grinding process, the substrate 11 is precisely removed by a chemical mechanical polishing process without damaging the underlying second dielectric layer 12.

[0083] In some embodiments of this disclosure, step S105 may specifically include steps S501-S503. These steps will be described in conjunction with the specific steps.

[0084] S501: Etch the upper surface of the third dielectric layer to form a second via. The second via exposes part of the redistribution layer.

[0085] In this embodiment of the disclosure, combined with Figure 5 and Figure 7 As shown, a second via is formed on the third dielectric layer 14 through an etching process, exposing a portion of the underlying redistribution layer 141 and providing a connection channel for the subsequent filling metal to form the pad 18. The third dielectric layer 14 serves as an isolation layer to prevent short circuits between different metal layers.

[0086] S502: Fill the second through hole to form a pad.

[0087] In this embodiment of the disclosure, combined with Figure 5 and Figure 7 As shown, a solder pad 18 is formed by electroplating and filling the second through hole with metal material. The solder pad 18 is typically made of copper, aluminum, or other metals with good electrical conductivity, and is used to achieve electrical connections.

[0088] S503: Bond the redistribution layer of the redistribution wafer to the first wafer via pads.

[0089] In this embodiment of the disclosure, reference is made to Figure 7 As shown, the redistribution wafer 10 is bonded to the first wafer 20 via the pad 18, which improves alignment accuracy and connection reliability.

[0090] In some embodiments of this disclosure, Figure 10 for Figure 8 The corresponding structural diagram of the prefabricated through-hole structure 122 is shown below. Figure 11 for Figure 9 Schematic diagrams of the corresponding hybrid bonding structure 123 and virtual bonding structure 124. Figure 12 for Figure 14 Schematic diagrams of the corresponding hybrid bonding structure 123 and virtual bonding structure 124. Figure 13 This is a schematic diagram of the structure of the second wafer 30. A pre-fabricated via structure 122 penetrates the first dielectric layer 13 and is partially embedded in the second dielectric layer 12. The method for forming the hybrid bonding structure 123 includes step S601.

[0091] S601: The second dielectric layer and the pre-fabricated via structure embedded therein are removed by a grinding process, exposing the surface of the pre-fabricated via structure away from the redistribution layer.

[0092] In this embodiment of the disclosure, reference is made to Figure 8 and Figure 9 As shown, the second dielectric layer 12 and the pre-fabricated via structure 122 embedded therein are removed by a grinding process. The second dielectric layer 12 is used to protect the first dielectric layer 13 during the thermal bonding process. After removing the substrate 11, the first dielectric layer 13 needs to be removed to reduce the wiring spacing between the redistribution layer 141 and the second wafer 30, in order to meet the requirements of high-density interconnection.

[0093] It should also be noted that the pre-fabricated through-hole structure 122 penetrates the first dielectric layer 13 and is partially embedded in the second dielectric layer 12. The fact that the pre-fabricated through-hole structure 122 is partially embedded in the second dielectric layer 12 allows the surface of the hybrid bonding structure 123 in the first dielectric layer 13 to be fully exposed during subsequent grinding processes without damaging the first dielectric layer 13, thus adapting to subsequent bonding processes.

[0094] This disclosure also provides a hybrid bonding wafer, see embodiments thereof. Figure 14 As shown, the hybrid bonding wafer includes: a first wafer 20, a redistribution wafer 10, and a second wafer 30. The redistribution wafer 10 includes: a second dielectric layer 12, a first dielectric layer 13, and a redistribution layer 141 stacked sequentially. A hybrid bonding structure 123 is formed in the first dielectric layer 13; the hybrid bonding structure 123 is formed before the redistribution layer 141 of the redistribution wafer 10 is bonded to the first wafer 20; the hybrid bonding structure 123 penetrates the first dielectric layer 13.

[0095] In this embodiment of the disclosure, reference is made to Figure 14 As shown, the redistribution layer 141 of the redistribution wafer 10 is bonded to the first wafer 20; the first dielectric layer 13 of the first wafer 20 is bonded to the second wafer 30.

[0096] It should be noted that, referring to Figure 14 As shown, the hybrid bonding structure 123 penetrates the first dielectric layer 13, and the exposed surface of the hybrid bonding structure 123 serves as a bonding point, enabling the first dielectric layer 13 of the first wafer 20 to be bonded to the second wafer 30. The second wafer 30 includes contact pads. The contact pads are bonded to the hybrid bonding structure 123, realizing the electrical connection and signal transmission between the two wafers.

[0097] Understandably, referring to Figure 14As shown, during the formation of the redistribution wafer 10, a first dielectric layer 13 is prepared in advance, and a hybrid bonding structure 123 is formed in the first dielectric layer 13. Compared to the formation of the first dielectric layer 13 after the redistribution wafer 10 is bonded to the first wafer 20, the surface structure of the redistribution wafer 10 before bonding is simple, without complex functional layers, and a thin film of the first dielectric layer 13 with good thickness consistency can be obtained through deposition process. At the same time, the hybrid bonding structure 123 is formed in advance on the first dielectric layer 13 with good thickness consistency, which can avoid alignment deviations caused by wafer deformation or process fluctuations after multiple bonding, and improve alignment accuracy. In addition, the hybrid bonding structure 123 penetrates the first dielectric layer 13, so that there is no need to add additional pad connection structures, and bonding can be performed only by exposing the surface of the hybrid bonding structure 123. The first wafer 20 and the second wafer 30 are bonded with high precision through the hybrid bonding structure 123, thereby improving the signal transmission efficiency and interconnect reliability in the package.

[0098] It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments of this application are merely for description and do not represent the superiority or inferiority of the embodiments. It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0099] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0100] The above are merely specific implementations of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application.

Claims

1. A method for forming a hybrid bonding structure, comprising: The method for forming the hybrid bonding structure includes: A redistribution wafer is formed; the redistribution wafer comprises: a substrate, a second dielectric layer, a first dielectric layer, and a redistribution layer stacked sequentially; wherein, a pre-fabricated via structure is formed in the first dielectric layer; the pre-fabricated via structure penetrates the first dielectric layer; The redistribution layer of the redistribution wafer is bonded to the first wafer; Remove the substrate from the redistribution wafer; The second dielectric layer is ground to expose the surface of the pre-fabricated via structure away from the redistribution layer; wherein the exposed pre-fabricated via structure forms a hybrid bonding structure; The first dielectric layer of the redistribution wafer is bonded to the second wafer; wherein the hybrid bonding structure serves as the bonding point of the redistribution wafer.

2. The method of forming a hybrid bonded structure of claim 1, wherein, After grinding the second dielectric layer to expose the surface of the pre-fabricated via structure away from the redistribution layer, the exposed pre-fabricated via structure also forms a virtual bonding structure; the virtual bonding structure is located between two adjacent hybrid bonding structures, and the virtual bonding structure is used to balance the consistency of the bonding interface.

3. The method of claim 1, wherein The method for forming the redistribution wafer includes: The second dielectric layer and the first dielectric layer are sequentially deposited on the substrate; Etching is performed along the upper surface of the first dielectric layer to form a first through-hole penetrating the first dielectric layer; The first through hole is filled with metal material to form the prefabricated through hole structure; A third dielectric layer is deposited on the first dielectric layer; The upper surface of the third dielectric layer is etched and filled to form the redistribution layer, thereby forming the redistribution wafer.

4. The method of claim 3, wherein The first through hole has a T-shaped cross-section; the first through hole includes: a straight hole and a groove that are interconnected in a vertical direction; wherein the width of the groove is greater than the diameter of the straight hole.

5. The method of claim 3, wherein The first through hole is filled using a double damask process to form a prefabricated through hole structure.

6. The method of forming a hybrid bonded structure of claim 1, wherein, The prefabricated through-hole structure penetrates the first dielectric layer and is partially embedded in the second dielectric layer; The method for forming the hybrid bonding structure includes: The second dielectric layer and the pre-fabricated via structure embedded therein are removed by a grinding process, exposing the surface of the remaining pre-fabricated via structure away from the redistribution layer.

7. The method of claim 1, wherein The redistribution wafer further includes: a stripping and modification layer stacked sequentially; the stripping and modification layer is located between the substrate and the second dielectric layer; The substrate from which the redistribution wafer is removed includes: The stripping modified layer is removed by a pyrolysis bonding process, separating the substrate and the second dielectric layer.

8. The method of claim 1, wherein The redistribution wafer further includes: a buffer layer and a thin film layer stacked sequentially; the buffer layer is located between the substrate and the second dielectric layer, and the thin film layer is located between the second dielectric layer and the first dielectric layer.

9. The method of claim 3, wherein The step of bonding the redistribution layer of the redistribution wafer to the first wafer includes: The upper surface of the third dielectric layer is etched to form a second via; the second via exposes a portion of the redistribution layer. The second through-hole is filled to form a pad; the pad is in contact with the redistribution layer. The redistribution layer of the redistribution wafer is bonded to the first wafer via the pads.

10. A hybrid bonding wafer, characterized in that, The hybrid bonding wafer includes: a first wafer, a redistribution wafer, and a second wafer; The redistribution wafer includes: a second dielectric layer, a first dielectric layer, and a redistribution layer stacked sequentially; wherein the first dielectric layer includes a hybrid bonding structure formed by the method according to any one of claims 1 to 9; the hybrid bonding structure is formed before the redistribution layer of the redistribution wafer is bonded to the first wafer; the hybrid bonding structure penetrates the first dielectric layer; The redistribution layer of the redistribution wafer is bonded to the first wafer; The first dielectric layer of the redistribution wafer is bonded to the second wafer; wherein the hybrid bonding structure serves as the bonding point of the redistribution wafer.

Images