A method for optimizing the energy consumption of a secure storage chip based on multi-objective optimization

Abstract

This invention discloses a method for optimizing the energy consumption of secure storage chips based on multi-objective optimization, belonging to the field of energy consumption optimization technology. The method includes: inputting the threshold voltage distribution characteristics of the secure storage chip into an aging model using a set of candidate parameters; fitting the change of the threshold voltage distribution characteristics over time under accelerated aging conditions to obtain aging model parameters; using the aging model parameters to calculate the data retention failure rate of the secure storage chip within the target lifespan; and combining this with data retention criteria to obtain an extended feasible region for immediate erasure security constraints and long-term retention security constraints; establishing a multi-objective optimization function within the extended feasible region with the optimization objectives of reducing operating energy consumption and reducing maintenance energy consumption; and obtaining a candidate solution set through a multi-objective optimization algorithm. This invention achieves data retention prediction within the lifespan, combining energy consumption optimization with long-term reliability constraints.

Description

Technical Field

[0001] This invention relates to the field of energy consumption optimization technology, and in particular to a method for optimizing the energy consumption of a secure storage chip based on multi-objective optimization. Background Technology

[0002] With the accelerating pace of informatization, data security and energy consumption control have gradually become crucial issues in integrated circuit and memory design. Secure storage chips, as a vital hardware foundation for ensuring data security, performing encrypted erasure, and ensuring long-term retention, have been widely applied in finance, government affairs, communications, and critical infrastructure. In recent years, the research and development of secure storage chips has expanded from simply focusing on storage density and transmission rate to multi-dimensional performance optimization, particularly addressing the balance between erasure energy consumption and long-term reliability, which has increasingly attracted attention from academia and industry.

[0003] However, existing research still has certain limitations. On the one hand, most methods focus on a single objective when optimizing energy consumption, such as reducing instantaneous erase current or shortening the erase pulse duration, but fail to simultaneously consider the constraints of erase intensity and long-term data retention. This can lead to risks of insufficient safe erasure or shortened lifespan while reducing energy consumption. On the other hand, in terms of combining lifetime prediction and energy consumption optimization, existing technologies mostly rely on empirical formulas or local statistical models from accelerated testing. They lack a complete path that organically combines energy consumption data from the erase process with threshold voltage distribution characteristics and extrapolates the data retention failure rate throughout the entire lifespan through aging models. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a multi-objective optimization method for power consumption optimization of secure storage chips to solve the coordination problem between power consumption control during operation and long-term data reliability assurance of secure storage chips.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] This invention provides a method for optimizing the energy consumption of a secure storage chip based on multi-objective optimization, comprising:

[0008] Collect data on the energy consumption of the erase process of the security storage chip under different erase voltage, erase pulse width, erase pulse count, junction temperature and parallelism conditions, and establish the threshold voltage distribution characteristics of the security storage chip to build a basic dataset;

[0009] The erasure intensity index is calculated based on the basic dataset, the erasure intensity threshold is obtained by combining it with the safe erasure standard, and the candidate parameter set is screened.

[0010] The threshold voltage distribution characteristics of the security storage chip are input into the aging model, and the law of the change of the threshold voltage distribution characteristics over time is fitted under accelerated aging conditions to obtain the aging model parameters.

[0011] The data retention failure rate of the security storage chip within the target life cycle is calculated using aging model parameters, and the extended feasible domain of immediate erasure security constraints and long-term retention security constraints is obtained by combining data retention judgment criteria.

[0012] In the extended feasible region, a multi-objective optimization function is established with the optimization objectives of reducing operating energy consumption and reducing maintenance energy consumption, and a candidate solution set is obtained through a multi-objective optimization algorithm.

[0013] The candidate solution set was verified and corrected in practice. The operating parameter configuration of the security storage chip that satisfies the erase strength constraint and data retention constraint and has the best energy consumption optimization effect was selected, and the energy consumption of the security storage chip was optimized.

[0014] As a preferred embodiment of the multi-objective optimization-based power consumption optimization method for secure storage chips described in this invention, the specific steps for collecting power consumption data and threshold voltage distribution characteristics of the secure storage chip during the erasure process under different erase voltages, erase pulse widths, erase pulse counts, junction temperatures, and parallelism conditions are as follows.

[0015] Based on the mass production range and reliability boundaries of the security storage chip, the range and step size of erase voltage, erase pulse width, erase pulse count, junction temperature, and parallelism are obtained to generate an acquisition execution list.

[0016] Change the parameter levels one by one according to the collection and execution list, perform the erase operation, record the energy consumption data during the erase process, and obtain the threshold voltage distribution characteristics of the security storage chip to form a single round of sampling record set.

[0017] As a preferred embodiment of the multi-objective optimization-based power consumption optimization method for secure storage chips described in this invention, the specific steps for establishing the basic dataset are as follows:

[0018] The energy consumption data of the erasure process in the dimensional sampling record set and the threshold voltage distribution characteristics of the security storage chip are unified in terms of fields and units, and a structured sample set is obtained by repeatability verification and timestamp comparison.

[0019] The energy consumption data of the erasure process after verification in the structured sample set, the threshold voltage distribution characteristics of the security storage chip, and the corresponding parameter levels are compiled into a basic dataset.

[0020] As a preferred embodiment of the multi-objective optimization-based power consumption optimization method for secure storage chips described in this invention, the specific steps of calculating the erase intensity index based on the basic dataset, obtaining the erase intensity threshold by combining it with the secure erase standard, and screening the candidate parameter set are as follows.

[0021] Extract parameter levels and corresponding security storage chip threshold voltage distribution characteristics from the basic dataset, organize them into record entries and retain the energy consumption data of the erasure process to form an input set for erasure intensity calculation;

[0022] Based on the erase intensity calculation input set, calculate the erase intensity index of the parameter level combination, sort by parameter level combination, and generate a list of erase intensity indexes.

[0023] Based on the erase intensity index list, the erase intensity threshold is obtained by querying the safe erase standard;

[0024] Based on the erase intensity index list and erase intensity threshold, filter parameter level combinations to generate a candidate parameter set.

[0025] As a preferred embodiment of the multi-objective optimization-based power consumption optimization method for secure storage chips described in this invention, the following steps are taken: The threshold voltage distribution characteristics of the secure storage chip, representing a set of candidate parameters, are input into an aging model. Under accelerated aging conditions, the variation of the threshold voltage distribution characteristics over time is fitted to obtain the aging model parameters.

[0026] Based on the candidate parameter set, an accelerated aging sampling scheme is established to obtain the temperature level sequence, time point sequence and readout order, and generate an aging test sampling list.

[0027] Accelerated aging process was carried out according to the aging test sampling list, and the threshold voltage distribution characteristics of safety storage chips were combined to form a time-labeled sequence grouped by parameter level and temperature grade.

[0028] Extract central tendency and discrete measures from time-labeled sequences to generate an aging model input table indexed by parameter level, temperature level, and time point.

[0029] Input the aging model into the aging model input table to perform the fitting task, and generate the aging model parameters through parameter solving and convergence verification.

[0030] As a preferred embodiment of the multi-objective optimization-based power consumption optimization method for secure storage chips described in this invention, the specific steps for calculating the data retention failure rate of the secure storage chip within the target lifespan using aging model parameters are as follows:

[0031] Based on the aging model parameters, target life cycle, operating temperature profile and duty cycle, the time node sequence and temperature sequence corresponding to each parameter level are obtained to form a life mapping table.

[0032] The lifespan mapping table and aging model parameters are used to extrapolate the threshold voltage distribution characteristics of the safety storage chip over time, generating the predicted mean and predicted dispersion at each time point, and summarizing them into a distribution prediction table.

[0033] Based on the distribution prediction table, for parameter levels and time points, the proportion falling outside the judgment boundary is statistically analyzed to obtain the data retention failure rate within the target life cycle.

[0034] As a preferred embodiment of the multi-objective optimization-based power consumption optimization method for secure storage chips described in this invention, the step of obtaining the extended feasible domain of immediate erasure security constraints and long-term retention security constraints by combining data retention determination criteria includes the following specific steps.

[0035] Based on the data retention failure rate and combined with the data retention judgment criteria, a set of long-term retention security constraints is selected from the parameter ranges.

[0036] Based on the erase intensity index list and the erase intensity threshold, the instant erase safety constraint result set is selected from the candidate parameter set;

[0037] The intersection of the long-term retention security constraint result set and the immediate erasure security constraint result set is used as the extended feasible region.

[0038] As a preferred embodiment of the multi-objective optimization-based energy consumption optimization method for secure storage chips described in this invention, the steps include: establishing a multi-objective optimization function in the extended feasible region with the optimization objectives of reducing operating energy consumption and reducing maintenance energy consumption, and obtaining a candidate solution set through a multi-objective optimization algorithm. The specific steps are as follows:

[0039] Establish a multi-objective optimization function in the extended feasible region with the optimization objectives of reducing operating energy consumption and reducing maintenance energy consumption;

[0040] Based on the multi-objective optimization function, the operating energy consumption per unit business cycle is calculated for the parameter level combination in the extended feasible domain, and the multi-objective optimization function input table is obtained.

[0041] Based on the input table of the multi-objective optimization function, a multi-objective optimization algorithm based on non-dominated sorting and crowding maintenance is used to search and filter within the extended feasible region to obtain a non-dominated solution with sorting and density information.

[0042] Extract the parameter range combinations and corresponding operational and maintenance energy consumption evaluation results from the non-dominated solutions with sorting and density information to generate a candidate solution set.

[0043] As a preferred embodiment of the multi-objective optimization-based power consumption optimization method for secure storage chips described in this invention, the specific steps for verifying and correcting the candidate solution set using real-world testing are as follows:

[0044] Based on the candidate solution set, list out the erase intensity verification, data retention verification, operation energy consumption measurement and maintenance energy consumption measurement that need to be performed for each parameter level combination, and generate a list of actual machine verifications;

[0045] According to the measurement caliber in the actual machine verification list, the erase and readout processes are executed item by item in the candidate solution set, and the erase intensity index is calculated. Combined with the erase intensity threshold, the erase intensity through set is obtained.

[0046] The data retention pass set is executed according to the accelerated aging time point in the actual machine verification list in the erasure intensity pass set. The data retention failure rate of the statistical parameter level combination within the target life cycle is compared with the data retention judgment criteria item by item to generate the data retention pass set.

[0047] Based on data retention, the system measures the operating energy consumption per unit business cycle according to the business load metric, calculates the data refresh frequency and wipe verification sampling size required to meet the data retention criteria, records the deviation from the input table of the multi-objective optimization function, corrects it, and generates a corrected evaluation table.

[0048] As a preferred embodiment of the multi-objective optimization-based power consumption optimization method for secure storage chips described in this invention, the specific steps for selecting the secure storage chip operating parameter configuration that satisfies the erase intensity constraint and data retention constraint and achieves the best power consumption optimization effect, and then performing power consumption optimization for the secure storage chip, are as follows:

[0049] According to the comprehensive ranking rules of operating energy consumption and maintenance energy consumption, the parameter level combination with the best energy consumption optimization effect is selected from the corrected evaluation table as the operating parameter configuration of the security storage chip.

[0050] Optimize the power consumption of the security storage chip by configuring its operating parameters.

[0051] The beneficial effects of this invention are as follows: by screening the erasure intensity index, energy consumption data and threshold voltage distribution characteristics are transformed into quantitative safety judgment criteria, ensuring that the candidate parameter set has erasure safety before optimization and avoiding residual risks; then, by fitting the time evolution law of threshold voltage distribution characteristics through the aging model, data retention prediction within the life cycle is realized, so as to combine energy consumption optimization with long-term reliability constraints. Attached Figure Description

[0052] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a flowchart of a method for optimizing the energy consumption of a secure storage chip based on multi-objective optimization.

[0054] Figure 2 A flowchart for screening erasure intensity indicators.

[0055] Figure 3 The flowchart shows the fitting of the aging model and the generation of aging model parameters.

[0056] Figure 4 A flowchart for calculating data retention failure rate and obtaining extended feasible domains. Detailed Implementation

[0057] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0058] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0059] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0060] Reference Figures 1-4 This is one embodiment of the present invention, which provides a method for optimizing the power consumption of a secure storage chip based on multi-objective optimization, including the following steps:

[0061] S1: Collect energy consumption data and threshold voltage distribution characteristics of security storage chips during the erasure process under different erasure voltages, erasure pulse widths, erasure pulse counts, junction temperatures, and parallelism conditions to establish a basic dataset;

[0062] Furthermore, based on the mass production range and reliability boundaries of the security storage chip, the erase voltage range and step size, erase pulse width range and step size, erase pulse count range and step size, junction temperature range and step size, and parallelism range and step size are respectively analyzed. The step size is determined by the minimum parameter change value corresponding to the difference in the average energy consumption data of the erase process measured at adjacent ranges or the difference in the average value of the threshold voltage distribution characteristics of the security storage chip that exceeds the minimum resolution capability of the acquisition device. The boundary of the value range is based on meeting the mass production range and reliability boundaries. All value ranges and step sizes are compiled into an acquisition execution list, which serves as the sole execution basis for subsequent sampling. The minimum resolution capability is confirmed by the metrological verification or calibration records of the acquisition device and is converted into the minimum resolvable energy change using voltage division, current division, and integral time division.

[0063] Following the data acquisition and execution list, the erase voltage level, erase pulse width level, erase pulse count level, junction temperature level, and parallelism level are changed one by one at a time, keeping the others unchanged. After each parameter setting is completed, the erase operation is executed immediately, continuously recording the energy consumption data during the erase process. After erasure, the threshold voltage distribution characteristics of the security storage chip are read out, and each complete process is recorded as an independent record. This independent record is merged with the corresponding parameter level label and time stamp for storage, accumulating to form a single-round sampling record set.

[0064] The single-round sampling record sets are merged using parameter levels as indices. First, they are aggregated by erase voltage level, then by erase pulse width level, then by erase pulse count level, then by junction temperature level, and finally by parallelism level. For each aggregation, it is confirmed that non-target parameter levels remain consistent. After confirmation, records within the same dimension are grouped into a dimensional sampling subset, and the resulting set is the dimensional sampling record set.

[0065] For the erase process energy consumption data and security storage chip threshold voltage distribution characteristics in the dimensional sampling record set, field and unit unification is performed. Fields include parameter level label, timestamp, sampling sequence number, and the erase process energy consumption data and security storage chip threshold voltage distribution characteristics. At least three independent samples are performed for the same parameter level. The standard deviation of the erase process energy consumption data and security storage chip threshold voltage distribution characteristics is calculated, with the allowable deviation range defined as twice the standard deviation. If a record differs from the mean of that parameter level by more than the allowable deviation range, the record is deemed invalid and removed. To quickly remove obvious anomalies, a preliminary judgment can be made after two independent samples; the final decision on whether to retain the record is based on the criteria obtained from at least three independent samples. Subsequently, timestamp comparison is performed. Sampling records for the same parameter level are arranged in chronological order. If the timestamp does not match the sampling sequence number or is missing, the record is deemed invalid and removed.

[0066] The energy consumption data of the erase process and the threshold voltage distribution characteristics of the security storage chip, which have been verified in the structured sample set, are checked one by one with the corresponding erase voltage level, erase pulse width level, erase pulse count level, junction temperature level, and parallelism level. The data are then compiled and a field directory, index directory, and retrieval key value are established to ensure that any record can be located by the parameter level and the corresponding energy consumption data of the erase process and threshold voltage distribution characteristics of the security storage chip can be returned. After the compilation is completed, the basic dataset is output.

[0067] It should be noted that the mass production range and reliability boundary are derived from the achievable process capabilities of the mass production batches and the stability requirements under long-term operation. For example, the mass production range was obtained by statistically analyzing key process parameters during the production of the last three batches of security storage chips, and its values ​​cover the stable range where the process capability index is greater than 1.33. The reliability boundary was determined by fitting a lifetime model based on measured data from accelerated aging and environmental stress tests, with a failure rate not exceeding 10⁻⁻⁶. 6 The parameter limits are used as boundary values. The erase voltage is used to drive charge migration in the memory cell and realize data erasure; the erase pulse width is the duration of a single erase pulse; the number of erase pulses is the number of pulses applied continuously during one erase operation; the junction temperature is the temperature of the semiconductor junction region during the erase operation; the parallelism is the number of memory cells erased simultaneously in one erase operation; the energy consumption data of the erase process is the energy consumption record obtained by comprehensively calculating the voltage and current changes; the threshold voltage distribution characteristics of the security storage chip are the distribution of the threshold voltage obtained after the erase is completed among different cells.

[0068] S2: Calculate the erasure intensity index based on the basic dataset, obtain the erasure intensity threshold by combining it with the safe erasure standard, and filter the candidate parameter set;

[0069] Furthermore, the erase voltage level, erase pulse width level, erase pulse count level, junction temperature level, and parallelism level are read one by one from the basic dataset, and the corresponding threshold voltage distribution characteristics of the security storage chip are extracted simultaneously. Each record is organized into a record entry containing parameter level labels, security storage chip threshold voltage distribution characteristics, and energy consumption data during the erase process, and stored uniformly to form the input set for erase intensity calculation.

[0070] The threshold voltage distribution characteristics of the security storage chip are extracted sequentially from the input set for erasure intensity calculation for each parameter range combination. The central tendency and dispersion measures are extracted separately, and combined with the readout judgment voltage to calculate the corresponding erasure intensity index. The expression for the erasure intensity index of the parameter range combination is as follows:

[0071] ;

[0072] in, To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels The following erase intensity index, To read the determination voltage, To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels The central tendency of the threshold voltage distribution characteristics of the low-voltage storage chip. To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels A discrete measure of the threshold voltage distribution characteristics of a low-security storage chip;

[0073] The calculated erasure intensity indices are sorted according to parameter level combinations and compiled into a unified erasure intensity index list, thus achieving the goal of generating an erasure intensity index list.

[0074] Based on the erase intensity index list, each index requirement in the secure erase standard is compared item by item. The minimum allowable level of the secure erase standard is quantified according to the ratio of readout signal to readout noise. The readout signal is defined as the difference between the central tendency of the threshold voltage distribution after erase and the judgment voltage. The readout noise is defined as the standard deviation of the readout link noise. The signal-to-noise ratio is calculated as the erase intensity threshold.

[0075] Using the erase intensity index list and erase intensity threshold as input, each parameter level combination is evaluated; parameter level combinations with erase intensity indices not lower than the erase intensity threshold are retained, while those lower are discarded. The retained parameter level combinations are then compiled into a candidate parameter set.

[0076] It should be noted that the judgment voltage is the reference voltage used to distinguish between the erase state and the programming state during readout; the safe erase standard is used to evaluate whether the erase operation meets the conditions for irreversible data recovery; the minimum allowable level is used to define the minimum value at which the erase intensity can be considered acceptable.

[0077] The Secure Erasure Standard (SEAS) is a set of technical requirements established to ensure that secure storage chips leave no recoverable information after erasure. It includes requirements for energy release during the erasure process, the range of changes in threshold voltage distribution characteristics, and the minimum safe limit of erasure intensity. These requirements are used to evaluate whether the erasure operation meets the conditions for irreversible data recovery.

[0078] The minimum allowable level in the safe erasure standard is the lower limit requirement specified in the safe erasure standard. It is used to define the minimum value at which the erasure intensity can be considered acceptable. When the actual calculated erasure intensity index is greater than or equal to the minimum allowable level, it means that the parameter combination can meet the basic requirements of safe erasure. If it is lower than the minimum allowable level, it is considered to fail to meet the requirements of safe erasure.

[0079] S3: Input the threshold voltage distribution characteristics of the security storage chip from the candidate parameter set into the aging model, and fit the law of the change of the threshold voltage distribution characteristics over time under accelerated aging conditions to obtain the aging model parameters;

[0080] Furthermore, based on the candidate parameter set, accelerated aging conditions are determined for each parameter level combination, and temperature level sequence, time point sequence and readout order are listed respectively, and a unified sampling list for aging test is generated.

[0081] The accelerated aging process was executed item by item according to the aging test sampling checklist. Each parameter combination in the candidate parameter set was kept in working condition at specified temperature levels and time points, and the threshold voltage distribution characteristics of the safety storage chip were collected. All collected results were grouped according to parameter level and temperature level and time point markers were added, and summarized into a time-labeled sequence grouped by parameter level and temperature level.

[0082] The central tendency and discrete measure of the threshold voltage distribution characteristics of the safety storage chip are extracted one by one from the time-labeled sequence, arranged in the index order of parameter level, temperature level and time point, and stored as tabular data with triple index to form the aging model input table.

[0083] Read the central tendency, dispersion measure, time point index, temperature level index and parameter range index from the aging model input table one by one, and sort the time point series under the same range according to the parameter range index and temperature level index to ensure that the time point arrangement order conforms to the time progression order of accelerated aging sampling.

[0084] The sorted aging model input table data is input into the aging model, and the variation of the central tendency with aging time is fitted and calculated. The expression is:

[0085] ;

[0086] in, To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels Down The concentrated trend after aging and evolution. To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels Down The central tendency of the threshold voltage distribution at time t. To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels Initial estimation of the aging rate parameter under the given conditions. To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels Initial estimate of the aging time constant. This refers to the aging time.

[0087] The objective function is the sum of squared residuals of the central tendency quantity and the residuals of the central tendency quantity after aging evolution. The aging rate parameter and aging time constant in the aging model expression are used as parameters to be determined. An iterative optimization method is employed to adjust the parameter values, gradually reducing the sum of squared residuals. After convergence verification, the aging rate parameter and aging time constant are output as the aging model parameters.

[0088] It should be noted that the aging model is a mathematical model used to characterize the variation of the central tendency quantity of the threshold voltage distribution in a security storage chip over aging time. By establishing a functional relationship between the central tendency quantity and aging time, it reflects the dynamic characteristics of threshold voltage drift under accelerated aging conditions. The aging model uses a predetermined functional expression, starting with the central tendency quantity, and combines the aging rate parameter and the aging time constant to describe the decay process of the central tendency quantity. In the aging model expression, the average rate of change of the central tendency quantity over a short time interval is used as the initial estimate of the aging rate parameter, and the time interval corresponding to the rate of change of the central tendency quantity decreasing to half of the initial rate of change is used as the initial estimate of the aging time constant.

[0089] S4: Use aging model parameters to calculate the data retention failure rate of the security storage chip within the target life cycle, and combine it with data retention judgment criteria to obtain the extended feasible domain of immediate erasure security constraints and long-term retention security constraints;

[0090] Furthermore, based on the aging model parameters, combined with the target life cycle length, the temperature distribution of the operating temperature profile, and the workload of the duty cycle, the discrete time nodes and matching temperature values ​​corresponding to each parameter level are calculated and summarized into a life mapping table.

[0091] Using the time nodes and temperature sequences of the lifespan mapping table as input, and combining them with aging model parameters, the threshold voltage distribution characteristics of safety storage chips at each parameter level are extrapolated over time. At each time node, the corresponding predicted mean and predicted dispersion are calculated and compiled into a distribution prediction table. The predicted dispersion is obtained by extrapolating the dispersion measure over time from the aging model parameters and is recorded under the same parameter level, temperature grade, and time point index.

[0092] Based on the distribution prediction table, for parameter levels and time points, the proportion falling outside the judgment boundary is statistically analyzed, and the data retention failure rate within the target lifespan is calculated. The expression is as follows:

[0093] ;

[0094] in, To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels Next life cycle time The cumulative data retention rate.

[0095] Based on the calculation results of the data retention failure rate, the allowable ranges in the data retention judgment criteria are compared one by one. Parameters that do not meet the judgment criteria are eliminated, while those that meet the judgment criteria are retained, and the results are summarized into a set of long-term retention security constraints.

[0096] It should be noted that the allowable range in the data retention judgment criteria refers to the cumulative failure rate calculated by the central tendency and discrete metric obtained from the aging model within the target life cycle and operating temperature profile, which does not exceed the upper limit of the data retention failure rate, and the readout signal-to-noise ratio is not lower than the threshold level converted from the judgment voltage and the standard deviation of the readout link noise. The setting method is as follows: the failure probability is calculated point-by-point according to the life mapping table, and the accumulated data retention failure rate is compared with the upper limit of the data retention failure rate. Simultaneously, the lower limit of the signal-to-noise ratio is determined based on the standard deviation of the readout link noise obtained from metrological verification and the judgment voltage. The parameter domain that both satisfy is taken as the allowable range.

[0097] Based on the erase intensity index list and the erase intensity threshold, the parameter levels in the candidate parameter set are compared and filtered, and the parameter levels that are not lower than the erase intensity threshold are retained and summarized into an instant erase safety constraint result set.

[0098] The long-term retention security constraint result set and the immediate erasure security constraint result set are compared item by item, the intersection is extracted, and the result set is summarized into an extended feasible domain.

[0099] S5: Establish a multi-objective optimization function in the extended feasible region with the optimization objectives of reducing operating energy consumption and reducing maintenance energy consumption, and obtain a candidate solution set through a multi-objective optimization algorithm;

[0100] Furthermore, using the extended feasible domain as the sole parameter source, a unit business cycle is defined as one complete erase and necessary read verification process. Maintenance energy consumption is determined by the cumulative energy required for the number of data refreshes and erase verifications within the target lifespan, under the premise of meeting the data retention criteria. The number of data refreshes and erase verifications are determined by taking the minimum value that meets the criteria threshold based on the data retention failure rate. Two types of quantitative results—operational energy consumption and maintenance energy consumption—are recorded, and weight parameters are set to establish a multi-objective optimization function, expressed as:

[0101] ;

[0102] in, To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels The multi-objective optimization function value under the following conditions For operating energy consumption weighting, To maintain energy consumption weight, To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels Maintenance energy consumption is reduced.

[0103] Based on the multi-objective optimization function, the operating energy consumption per unit business cycle is calculated for the parameter level combination in the extended feasible domain, and the multi-objective optimization function input table is obtained.

[0104] The energy consumption per unit of business cycle is calculated using the following expression:

[0105] ;

[0106] in, To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels Under the following operating energy consumption, To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels Voltage varies with the erasure process The function of change, To erase voltage setting Erasure pulse width setting Erasure pulse count settings Junction temperature setting and parallelism levels Current varies with erasure process The function of change, As an evolutionary variable in the erasure process, To erase the upper limit of integration for process variables.

[0107] When the input is a multi-objective optimization function input table, non-dominated sorting is used to hierarchically divide all parameter combinations according to the two objectives of operating energy consumption and maintenance energy consumption, while congestion maintenance is used to maintain a uniform distribution of solutions within the same level. Non-dominated relationship determination is performed and hierarchical division is completed. Within the same level, the diversity of solution distribution is maintained based on the congestion metric. The search and filtering are repeated until the convergence condition or a preset termination condition is reached. The output is a non-dominated solution containing non-dominated level and congestion metric information. The termination condition is that the non-dominated front has not changed since the previous iteration or the relative improvement of the two objectives is less than a preset improvement threshold in several consecutive iterations; the earlier one is taken.

[0108] Extract the parameter range combination on the non-dominated front from the non-dominated solution with sorting and density information, and synchronously read the corresponding operation energy consumption and maintenance energy consumption evaluation results from the multi-objective optimization function input table, and organize them into a candidate solution set.

[0109] S6: Perform on-machine verification and correction on the candidate solution set, select the operating parameter configuration of the security storage chip that satisfies the erase strength constraint and data retention constraint and has the best energy consumption optimization effect, and optimize the energy consumption of the security storage chip.

[0110] Furthermore, using the candidate solution set as the sole source, each parameter combination is listed, including the wipe intensity verification, data retention verification, operation energy consumption measurement, and maintenance energy consumption measurement. The wipe process steps, readout process steps, measurement caliber, record field names, and execution order are clearly defined, forming a unified real-machine verification checklist.

[0111] Based on the measurement specifications in the actual verification list, the erase and readout processes are executed item by item in the candidate solution set. The voltage and current trajectories of each erase process are recorded to form the energy consumption data of the erase process. At the same time, the threshold voltage distribution characteristics of the security storage chip obtained from the readout process are recorded. The erase intensity index for each parameter level combination is calculated according to the erase intensity index calculation expression, and compared with the erase intensity threshold. The parameter level combinations that are not lower than the erase intensity threshold are retained and summarized into an erase intensity pass set.

[0112] Using the erase intensity pass set as input, the read process is executed according to the accelerated aging time points listed in the actual machine verification list. The threshold voltage distribution characteristics of the security storage chip at each time point are recorded. The data retention failure rate of each parameter level combination within the target life cycle is calculated and compared item by item with the data retention judgment criteria, and then summarized into a unified data retention pass set.

[0113] Using data retention sets as input, the system measures the operational energy consumption per unit business cycle according to business load. It then calculates the data refresh frequency and wipe verification sampling size required to meet data retention criteria to quantify maintenance energy consumption. The system compares the measured operational and maintenance energy consumption for each parameter combination with the corresponding records in the multi-objective optimization function input table, records the deviation field, and updates the corresponding values ​​using the measured results. The output set of updated records serves as the corrected evaluation table.

[0114] Using the corrected evaluation table as input, all parameter combinations are sorted according to a comprehensive ranking rule for operating and maintenance energy consumption. The comprehensive ranking rule involves normalizing both operating and maintenance energy consumption separately, then calculating a weighted sum to obtain a comprehensive score. The weight parameters are non-negative, and the sum of the weights equals one. The weight values ​​are determined by the application scenario's preference for operating and maintenance energy consumption and are recorded in the implementation log. The parameter combination with the lowest comprehensive score is considered the best for energy consumption optimization. The erase voltage level, erase pulse width level, erase pulse count level, junction temperature level, and parallelism level are recorded and fixed as the operating parameter configuration for the secure storage chip.

[0115] The erase and maintenance processes are executed using the operating parameters of the secure storage chip. This includes erasure voltage control, erase pulse control, junction temperature control, and parallelism control. Simultaneously, data refresh and erase verification strategies that match the operating parameters of the secure storage chip are executed. The energy consumption performance and constraint fulfillment during the operation are recorded as implementation logs, thus completing the energy consumption optimization of the secure storage chip.

[0116] This embodiment also provides a computer device applicable to the energy consumption optimization method for secure storage chips based on multi-objective optimization, comprising: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the energy consumption optimization method for secure storage chips based on multi-objective optimization as proposed in the above embodiment.

[0117] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0118] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements the energy consumption optimization method for a secure storage chip based on multi-objective optimization as proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0119] In summary, this invention achieves the following: by using an erasure intensity index screening step, energy consumption data and threshold voltage distribution characteristics are transformed into quantitative safety judgment criteria, ensuring that the candidate parameter set has erasure safety before optimization and avoiding residual risks; then, by fitting the time evolution law of threshold voltage distribution characteristics through an aging model, data retention prediction within the life cycle is realized, thus combining energy consumption optimization with long-term reliability constraints.

[0120] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for optimizing the energy consumption of a secure storage chip based on multi-objective optimization, characterized in that: include, Collect data on the energy consumption of the erase process of the security storage chip under different erase voltage, erase pulse width, erase pulse count, junction temperature and parallelism conditions, and establish the threshold voltage distribution characteristics of the security storage chip to build a basic dataset; The erasure intensity index is calculated based on the basic dataset, the erasure intensity threshold is obtained by combining it with the safe erasure standard, and the candidate parameter set is screened. The threshold voltage distribution characteristics of the security storage chip are input into the aging model, and the law of the change of the threshold voltage distribution characteristics over time is fitted under accelerated aging conditions to obtain the aging model parameters. The data retention failure rate of the security storage chip within the target life cycle is calculated using aging model parameters, and the extended feasible domain of immediate erasure security constraints and long-term retention security constraints is obtained by combining data retention judgment criteria. In the extended feasible region, a multi-objective optimization function is established with the optimization objectives of reducing operating energy consumption and reducing maintenance energy consumption, and a candidate solution set is obtained through a multi-objective optimization algorithm. The candidate solution set was verified and corrected in practice. The operating parameter configuration of the security storage chip that satisfies the erase strength constraint and data retention constraint and has the best energy consumption optimization effect was selected, and the energy consumption of the security storage chip was optimized.

2. The energy consumption optimization method for secure storage chips based on multi-objective optimization as described in claim 1, characterized in that: The specific steps for collecting energy consumption data and threshold voltage distribution characteristics of the security storage chip during the erase process under different erase voltages, erase pulse widths, erase pulse counts, junction temperatures, and parallelism conditions are as follows. Based on the mass production range and reliability boundaries of the security storage chip, the range and step size of erase voltage, erase pulse width, erase pulse count, junction temperature, and parallelism are obtained to generate an acquisition execution list. Change the parameter levels one by one according to the collection and execution list, perform the erase operation, record the energy consumption data during the erase process, and obtain the threshold voltage distribution characteristics of the security storage chip to form a single round of sampling record set.

3. The energy consumption optimization method for secure storage chips based on multi-objective optimization as described in claim 2, characterized in that: The specific steps for establishing the basic dataset are as follows. The energy consumption data of the erasure process in the dimensional sampling record set and the threshold voltage distribution characteristics of the security storage chip are unified in terms of fields and units, and a structured sample set is obtained by repeatability verification and timestamp comparison. The energy consumption data of the erasure process after verification in the structured sample set, the threshold voltage distribution characteristics of the security storage chip, and the corresponding parameter levels are compiled into a basic dataset.

4. The energy consumption optimization method for secure storage chips based on multi-objective optimization as described in claim 3, characterized in that: The specific steps for calculating the erase intensity index based on the basic dataset, obtaining the erase intensity threshold by combining it with the secure erase standard, and filtering the candidate parameter set are as follows: Extract parameter levels and corresponding security storage chip threshold voltage distribution characteristics from the basic dataset, organize them into record entries and retain the energy consumption data of the erasure process to form an input set for erasure intensity calculation; Based on the erase intensity calculation input set, calculate the erase intensity index of the parameter level combination, sort by parameter level combination, and generate a list of erase intensity indexes. Based on the erase intensity index list, the erase intensity threshold is obtained by querying the safe erase standard; Based on the erase intensity index list and erase intensity threshold, filter parameter level combinations to generate a candidate parameter set.

5. The energy consumption optimization method for secure storage chips based on multi-objective optimization as described in claim 4, characterized in that: The process involves inputting the threshold voltage distribution characteristics of the security storage chip from the candidate parameter set into the aging model, and fitting the change of the threshold voltage distribution characteristics over time under accelerated aging conditions to obtain the aging model parameters. The specific steps are as follows: Based on the candidate parameter set, an accelerated aging sampling scheme is established to obtain the temperature level sequence, time point sequence and readout order, and generate an aging test sampling list. Accelerated aging process was carried out according to the aging test sampling list, and the threshold voltage distribution characteristics of safety storage chips were combined to form a time-labeled sequence grouped by parameter level and temperature grade. Extract central tendency and discrete measures from time-labeled sequences to generate an aging model input table indexed by parameter level, temperature level, and time point. Input the aging model into the aging model input table to perform the fitting task, and generate the aging model parameters through parameter solving and convergence verification.

6. The energy consumption optimization method for secure storage chips based on multi-objective optimization as described in claim 5, characterized in that: The specific steps for calculating the data retention failure rate of the security storage chip within the target lifespan using aging model parameters are as follows. Based on the aging model parameters, target life cycle, operating temperature profile and duty cycle, the time node sequence and temperature sequence corresponding to each parameter level are obtained to form a life mapping table. The lifespan mapping table and aging model parameters are used to extrapolate the threshold voltage distribution characteristics of the safety storage chip over time, generating the predicted mean and predicted dispersion at each time point, and summarizing them into a distribution prediction table. Based on the distribution prediction table, for parameter levels and time points, the proportion falling outside the judgment boundary is statistically analyzed to obtain the data retention failure rate within the target life cycle.

7. The energy consumption optimization method for secure storage chips based on multi-objective optimization as described in claim 6, characterized in that: The process of combining data retention criteria to obtain the extended feasible domain of immediate erasure security constraints and long-term retention security constraints involves the following steps: Based on the data retention failure rate and combined with the data retention judgment criteria, a set of long-term retention security constraints is selected from the parameter ranges. Based on the erase intensity index list and the erase intensity threshold, the instant erase safety constraint result set is selected from the candidate parameter set; The intersection of the long-term retention security constraint result set and the immediate erasure security constraint result set is used as the extended feasible region.

8. The energy consumption optimization method for secure storage chips based on multi-objective optimization as described in claim 7, characterized in that: The steps involve establishing a multi-objective optimization function within the extended feasible region, with the objectives of reducing operational and maintenance energy consumption, and obtaining a candidate solution set using a multi-objective optimization algorithm. The specific steps are as follows: Establish a multi-objective optimization function in the extended feasible region with the optimization objectives of reducing operating energy consumption and reducing maintenance energy consumption; Based on the multi-objective optimization function, the operating energy consumption per unit business cycle is calculated for the parameter level combination in the extended feasible domain, and the multi-objective optimization function input table is obtained. Based on the input table of the multi-objective optimization function, a multi-objective optimization algorithm based on non-dominated sorting and crowding maintenance is used to search and filter within the extended feasible region to obtain a non-dominated solution with sorting and density information. Extract the parameter range combinations and corresponding operational and maintenance energy consumption evaluation results from the non-dominated solutions with sorting and density information to generate a candidate solution set.

9. The energy consumption optimization method for secure storage chips based on multi-objective optimization as described in claim 8, characterized in that: The specific steps for verifying and correcting the candidate solution set using real-machine testing are as follows. Based on the candidate solution set, list out the erase intensity verification, data retention verification, operation energy consumption measurement and maintenance energy consumption measurement that need to be performed for each parameter level combination, and generate a list of actual machine verifications; According to the measurement caliber in the actual machine verification list, the erase and readout processes are executed item by item in the candidate solution set, and the erase intensity index is calculated. Combined with the erase intensity threshold, the erase intensity through set is obtained. The data retention pass set is executed according to the accelerated aging time point in the actual machine verification list in the erasure intensity pass set. The data retention failure rate of the statistical parameter level combination within the target life cycle is compared with the data retention judgment criteria item by item to generate the data retention pass set. Based on data retention, the system measures the operating energy consumption per unit business cycle according to the business load metric, calculates the data refresh frequency and wipe verification sampling size required to meet the data retention criteria, records the deviation from the input table of the multi-objective optimization function, corrects it, and generates a corrected evaluation table.

10. The energy consumption optimization method for secure storage chips based on multi-objective optimization as described in claim 9, characterized in that: The steps for selecting the optimal operating parameter configuration for the security storage chip that satisfies both erase strength and data retention constraints while achieving the best energy consumption optimization are as follows: According to the comprehensive ranking rules of operating energy consumption and maintenance energy consumption, the parameter level combination with the best energy consumption optimization effect is selected from the corrected evaluation table as the operating parameter configuration of the security storage chip. Optimize the power consumption of the security storage chip by configuring its operating parameters.

Images