Code generation method and device, electronic equipment, storage medium and program product

Abstract

Embodiments of the invention provide a code generation method and apparatus, an electronic device, a storage medium and a program product. The method comprises the steps of obtaining a circuit generation demand; inputting the circuit generation demand into a code generation model, performing N rounds of iteration through the code generation model, and generating a target circuit code corresponding to the circuit generation demand; wherein in the first round of iteration process, the circuit code is generated through the code generation model according to the circuit generation requirement, and in the ith round of iteration process, the circuit code obtained through the (i-1) th round of iteration is corrected through the code generation model according to the circuit generation requirement, the circuit code obtained through the (i-1) th round of iteration and the simulation result to generate the circuit code; the simulation result is obtained by simulating the circuit code obtained by the (i-1) th iteration through the simulation module; n and i are positive integers greater than or equal to 2. In this way, the accuracy of the finally generated target circuit code is higher, and the situation that the circuit code is manually adjusted can be reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a code generation method, apparatus, electronic device, storage medium, and program product. Background Technology

[0002] In the field of Electronic Design Automation (EDA), circuit design is a core component of chip development. In some scenarios, circuits need to be designed based on user requirements. Traditionally, circuit design involves technicians designing corresponding circuits and writing circuit code based on these requirements. With the development of artificial intelligence (AI) technology, circuit design can now be performed using AI.

[0003] Currently, deep learning models trained on static datasets can learn from a large amount of circuit diagrams, layouts, and corresponding performance data, thus acquiring the ability to generate circuit code and obtaining a well-trained model. In this way, requirements can be input into the trained model, and the model can generate circuit code.

[0004] However, due to limited training data, the accuracy of the generated circuit code is low, and manual adjustments may be required later. Summary of the Invention

[0005] This application provides code generation methods, apparatus, electronic devices, storage media, and program products, which can improve the accuracy of generated circuit code and reduce the need for manual adjustments to the circuit code.

[0006] In a first aspect, embodiments of this application provide a code generation method, including:

[0007] Obtain circuit generation requirements;

[0008] The circuit generation requirements are input into the code generation model, and the model undergoes N iterations to generate the target circuit code corresponding to the requirements. Specifically, in the first iteration, the code generation model generates circuit code based on the requirements. In the i-th iteration, the model modifies the circuit code obtained in the (i-1)-th iteration based on the requirements, the circuit code obtained in the (i-1)-th iteration, and the simulation results, generating new circuit code. The simulation results are obtained by simulating the circuit code obtained in the (i-1)-th iteration using a simulation module.

[0009] Both N and i are positive integers greater than or equal to 2.

[0010] In one possible implementation, the simulation results include feature vectors and / or reward parameters;

[0011] The circuit code obtained in the (i-1)th iteration is simulated using the simulation module, including:

[0012] The circuit code obtained in the (i-1)th iteration is simulated using the simulation module to obtain simulation data.

[0013] The simulation data is processed to obtain the feature vector and / or reward parameters corresponding to the simulation data.

[0014] In one possible implementation, the simulation data includes at least one of waveform data, text information, and performance metrics.

[0015] In one possible implementation, the simulation data is processed to obtain a feature vector corresponding to the simulation data, including:

[0016] For the waveform data in the simulation data, feature encoding processing is performed on the waveform data to obtain waveform feature vectors;

[0017] For the text information in the simulation data, feature encoding processing is performed on the text information to obtain a text feature vector;

[0018] For the performance indicators in the simulation data, the performance indicators are normalized to obtain numerical feature vectors;

[0019] The simulation data is fused to obtain the feature vector corresponding to the simulation data.

[0020] In one possible implementation, processing the simulation data to obtain the reward parameters corresponding to the simulation data includes:

[0021] For the waveform data in the simulation data, a waveform reward value corresponding to the waveform data is generated based on the waveform data and the target waveform data;

[0022] The text information in the simulation data is analyzed, and a basic reward value is generated based on the analysis results.

[0023] For the performance metrics in the simulation data, a performance reward value corresponding to the performance metrics is generated based on the performance metrics and the target performance metrics.

[0024] Based on at least one of the above-mentioned reward values ​​corresponding to the simulation data, the reward parameters corresponding to the simulation data are obtained.

[0025] In one possible implementation, generating a waveform reward value corresponding to the waveform data based on the waveform data and the target waveform data includes:

[0026] Determine the similarity between the waveform data and the corresponding target waveform data;

[0027] A waveform reward value is generated based on the similarity, and the waveform reward value is proportional to the similarity.

[0028] In one possible implementation, the step of analyzing the text information and generating a basic reward value based on the analysis results includes:

[0029] The text information is analyzed to determine the simulation completion result; the simulation completion result includes simulation success and simulation failure.

[0030] If the simulation is successful, the preset reward value will be determined as the base reward value.

[0031] If the simulation result is that the simulation is unsuccessful, then the error parameters are obtained from the text information, and a basic reward value is generated according to the error parameters and the reward value generation strategy.

[0032] In one possible implementation, generating the performance reward value corresponding to the performance indicator based on the performance indicator and the target performance indicator includes:

[0033] Determine the deviation between the performance index and the corresponding target performance index;

[0034] A performance reward value corresponding to the performance indicator is generated based on the deviation value, and the performance reward value is inversely proportional to the deviation value.

[0035] In one possible implementation, the code generation model is a multimodal large model.

[0036] In one possible implementation, the step of generating the target circuit code corresponding to the circuit generation requirement through N iterations of the code generation model includes:

[0037] The large model is iterated until the preset conditions are met, then the iteration stops and the target circuit code corresponding to the circuit generation requirements is generated.

[0038] The preset conditions include: the deviation between each performance index and the corresponding target performance index in the simulation results of the circuit code is less than the corresponding preset value, or the number of iterations reaches the preset number.

[0039] In one possible implementation, the circuit generation requirement includes at least one of the following:

[0040] The image file corresponding to the circuit;

[0041] Natural language text describing the function of the circuit;

[0042] Circuit netlist;

[0043] Target performance metrics.

[0044] Secondly, embodiments of this application provide a code generation apparatus, comprising:

[0045] The acquisition module is used to acquire circuit generation requirements;

[0046] A generation module is used to input the circuit generation requirements into a code generation model, and perform N iterations through the code generation model to generate the target circuit code corresponding to the circuit generation requirements. Specifically, in the first iteration, the code generation model generates circuit code based on the circuit generation requirements; in the i-th iteration, the code generation model corrects the circuit code obtained in the (i-1)-th iteration based on the circuit generation requirements, the circuit code obtained in the (i-1)-th iteration, and the simulation results to generate new circuit code; the simulation results are obtained by simulating the circuit code obtained in the (i-1)-th iteration through a simulation module; where N and i are both positive integers greater than or equal to 2.

[0047] In one possible implementation, the simulation results include feature vectors and / or reward parameters. Specifically, the generation module is used to simulate the circuit code obtained in the (i-1)th iteration using the simulation module to obtain simulation data; and to process the simulation data to obtain the feature vectors and / or reward parameters corresponding to the simulation data.

[0048] In one possible implementation, the simulation data includes at least one of waveform data, text information, and performance metrics.

[0049] In one possible implementation, the generation module is specifically configured to: perform feature encoding processing on the waveform data in the simulation data to obtain a waveform feature vector; perform feature encoding processing on the text information in the simulation data to obtain a text feature vector; perform normalization processing on the performance indicators in the simulation data to obtain a numerical feature vector; and perform fusion processing on at least one of the above feature vectors corresponding to the simulation data to obtain a feature vector corresponding to the simulation data.

[0050] In one possible implementation, the generation module is specifically configured to: generate a waveform reward value corresponding to the waveform data in the simulation data, based on the waveform data and the target waveform data; analyze the text information in the simulation data and generate a basic reward value based on the analysis results; generate a performance reward value corresponding to the performance index in the simulation data, based on the performance index and the target performance index; and obtain a reward parameter corresponding to the simulation data based on at least one of the above reward values ​​corresponding to the simulation data.

[0051] In one possible implementation, the generation module is specifically used to determine the similarity between the waveform data and the corresponding target waveform data; and to generate a waveform reward value corresponding to the waveform data based on the similarity, wherein the waveform reward value is proportional to the similarity.

[0052] In one possible implementation, the generation module is specifically used to analyze the text information to determine the simulation completion result; the simulation completion result includes simulation success and simulation failure; if the simulation completion result is simulation success, then the preset reward value is determined as the basic reward value; if the simulation completion result is simulation failure, then the error parameter is obtained from the text information, and the basic reward value is generated according to the error parameter and the reward value generation strategy.

[0053] In one possible implementation, the generation module is specifically used to determine the deviation value between the performance index and the corresponding target performance index; and to generate a performance reward value corresponding to the performance index based on the deviation value, wherein the performance reward value is inversely proportional to the deviation value.

[0054] In one possible implementation, the code generation model is a multimodal large model.

[0055] In one possible implementation, the generation module is specifically used to iterate through the large model until preset conditions are met, then stop the iteration and generate the target circuit code corresponding to the circuit generation requirements. The preset conditions include: the deviation between each performance indicator in the simulation results of the circuit code and the corresponding target performance indicator is less than a corresponding preset value, or the number of iterations reaches a preset number.

[0056] In one possible implementation, the circuit generation requirement includes at least one of the following:

[0057] The image file corresponding to the circuit;

[0058] Natural language text describing the function of the circuit;

[0059] Circuit netlist;

[0060] Target performance metrics.

[0061] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor;

[0062] The memory stores computer-executed instructions;

[0063] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0064] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0065] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0066] The code generation method, apparatus, electronic device, storage medium, and program product provided in this application obtain circuit generation requirements; input the circuit generation requirements into a code generation model; and perform N iterations through the code generation model to generate target circuit code corresponding to the circuit generation requirements. Specifically, in the first iteration, the code generation model generates circuit code based on the circuit generation requirements. In the i-th iteration, the code generation model corrects the circuit code obtained in the (i-1)-th iteration based on the circuit generation requirements, the circuit code obtained in the (i-1)-th iteration, and simulation results. The simulation results are obtained by simulating the circuit code obtained in the (i-1)-th iteration using a simulation module. N and i are both positive integers greater than or equal to 2. Thus, during the process of generating circuit code based on the circuit generation requirements, the simulation results are used to correct the generated circuit code, resulting in higher accuracy of the corrected code compared to the previous circuit code. This achieves dynamic adjustment based on the performance of the circuit corresponding to the generated circuit code during the circuit code generation process, resulting in higher accuracy of the final generated target circuit code and reducing the need for manual adjustments to the circuit code. Attached Figure Description

[0067] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0068] Figure 1 A flowchart illustrating a code generation method provided in an embodiment of this application;

[0069] Figure 2 This application provides a schematic flowchart of a method for simulating circuit code generated by a code generation model, as shown in the embodiments of this application.

[0070] Figure 3 This is a schematic diagram of the overall process of a code generation method provided in an embodiment of this application;

[0071] Figure 4 This is a schematic diagram of the structure of a code generation device provided in an embodiment of this application;

[0072] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0073] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0074] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0075] First, let me explain the terms used in this application:

[0076] Electronic Design Automation (EDA) is a design method that uses computer-aided design (CAD) software to complete the functional design, synthesis, verification, and physical design of very large-scale integrated circuit (VLSI) chips.

[0077] In the field of EDA (Electronic Design Automation), circuits need to be designed according to user requirements. Traditionally, circuit design involves technicians designing corresponding circuits and writing circuit code based on these requirements. However, manual circuit design is inefficient. With the development of artificial intelligence (AI) technology, circuit design can be performed using AI, effectively improving the efficiency of generating circuit code.

[0078] Currently, deep learning models trained on static datasets can learn from a large amount of circuit diagrams, layouts, and corresponding performance data, thus acquiring the ability to generate circuit code and obtaining a well-trained model. In this way, requirements can be input into the trained model, and the model can generate circuit code.

[0079] However, due to limited training data, the accuracy of the generated circuit code is low, and manual adjustments may be required later.

[0080] Based on this, embodiments of this application provide a code generation method. This method utilizes a code generation model to iteratively generate target circuit code corresponding to circuit generation requirements in multiple rounds. During each iteration, a simulation module simulates the circuit code obtained in that round and obtains the simulation results. These simulation results guide the code generation model in the next iteration. By using the actual performance of the circuit corresponding to the circuit code to guide the generation of new circuit code, the accuracy of the generated circuit code can be improved, reducing the need for manual adjustments.

[0081] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0082] Figure 1 This is a flowchart illustrating a code generation method provided in an embodiment of this application.

[0083] like Figure 1 As shown, the method includes:

[0084] S101, Obtain circuit generation requirements.

[0085] The circuit generation requirement is a user-input requirement for a desired circuit, which may include at least one of the following:

[0086] The circuit includes image files, natural language text describing the circuit's function, a circuit netlist, and target performance metrics.

[0087] The image file corresponding to the circuit can be an image file of the circuit schematic.

[0088] In this way, by acquiring circuit generation requirements in different forms and with different content, it becomes possible to generate circuit codes corresponding to those requirements based on the specific content or format of the requirements. This makes the way and content of user input requirements more flexible.

[0089] S102. Input the circuit generation requirements into the code generation model, and perform N iterations through the code generation model to generate the target circuit code corresponding to the circuit generation requirements.

[0090] In the first iteration, the code generation model generates circuit code based on the circuit generation requirements. In the i-th iteration, the code generation model corrects the circuit code obtained in the (i-1)-th iteration based on the circuit generation requirements, the circuit code obtained in the (i-1)-th iteration, and the simulation results to generate new circuit code. The simulation results are obtained by simulating the circuit code obtained in the (i-1)-th iteration using the simulation module.

[0091] Both N and i are positive integers greater than or equal to 2.

[0092] The simulation module may include SPICE simulation models, etc., but this application does not limit the simulation module.

[0093] The target circuit code includes one or more of various codes such as Verilog code, Verilog-A code, VHDL code, and SystemVerilog code. This application embodiment does not specifically limit the code.

[0094] Verilog is a hardware description language used to design and describe digital circuit systems.

[0095] For example, the code generation model can be a pre-trained multimodal large model, such as some open-source multimodal large models; or a lightweight model. This application does not specifically limit the multimodal large model.

[0096] In this way, because the multimodal large model has the ability to learn autonomously, the accuracy of adjusting the previously generated circuit code based on the simulation results is relatively high, resulting in higher accuracy of the subsequent target circuit code.

[0097] Taking a pre-trained multimodal large model as an example, the code generation model is used to perform N rounds of iteration to generate the target circuit code corresponding to the circuit generation requirements. This includes iterating through the large model until the preset conditions are met, stopping the iteration and generating the target circuit code corresponding to the circuit generation requirements.

[0098] The preset conditions include: the deviation between each performance index and the corresponding target performance index in the simulation results of the circuit code is less than the corresponding preset value, or the number of iterations reaches the preset number.

[0099] It should be understood that the simulation results include at least one performance index, and the iteration will stop only when the conditions for each performance index are met.

[0100] Performance metrics can include those obtained from circuit simulation corresponding to the circuit code, such as gain, power consumption, bandwidth, and linearity. This application does not specifically limit the performance metrics.

[0101] The target performance indicators can be the content of the circuit generation requirements input by the user, or they can be generated based on the circuit generation requirements in the user's book. This application embodiment does not specifically limit the source of the target performance indicators.

[0102] The preset values ​​for different performance indicators can be the same or different, and the specific values ​​can be limited according to the actual situation.

[0103] The preset value can be a small number, so that the performance indicators of the simulation results are closer to the corresponding performance indicators. For example, the gain of the circuit obtained from the simulation results is closer to the target gain.

[0104] The preset number of times can be set according to the actual situation of the multimodal large model, etc., and this application embodiment does not limit it in this way.

[0105] In this way, during the iterative generation of target circuit code through a multimodal large model, the iteration stops only when the performance indicators of the generated circuit code after simulation are closer to the actual target performance indicators, or when the preset number of iterations is reached. This results in higher accuracy of the generated target circuit code, reduces the need for subsequent manual adjustments to the target circuit code, and improves the efficiency of generating circuit code.

[0106] The code generation method provided in this application uses a code generation model to iteratively generate target circuit code corresponding to circuit generation requirements in multiple rounds. During the iteration process, in each round, a simulation module simulates the circuit code obtained in that round and obtains the simulation results. These simulation results are used to guide the code generation model in the next round of iteration. In this way, by using the actual performance of the circuit corresponding to the circuit code to guide the generation of new circuit code, the accuracy of the generated circuit code can be improved, making it more in line with the circuit generation requirements input by the user, reducing the need for manual adjustments to the circuit code, and improving the efficiency of circuit code generation.

[0107] Based on the embodiments described above, the circuit code obtained after each iteration needs to be simulated to test the effectiveness of the obtained circuit code. Figure 2 This is a schematic flowchart illustrating a method for simulating circuit code generated by a code generation model, as provided in an embodiment of this application.

[0108] It should be noted that the simulation results include feature vectors and / or reward parameters.

[0109] like Figure 2As shown, in this embodiment... Figure 2 Based on the embodiments, the method subject will be described in detail, which includes:

[0110] S201. Simulate the circuit code obtained in the (i-1)th iteration using the simulation module to obtain simulation data.

[0111] For example, simulation data includes at least one of waveform data, text information, and performance metrics.

[0112] The specific data types included in the simulation data are related to the actual circuit code. This application does not limit the data types included in the simulation data.

[0113] The waveform data may include, for example, curves showing the variation of voltage or current over time or frequency. The waveform data may be saved as an image or a numerical sequence (such as a CSV file). This application does not limit the waveform data used.

[0114] Text information may include error messages (such as "Node N1 floating"), warnings, or success completion messages generated in the simulation log. This application embodiment does not limit the text information.

[0115] Performance metrics may include specific performance values ​​calculated from simulation results, such as gain, power consumption, bandwidth, and linearity. This application does not limit the performance metrics.

[0116] In this way, the simulation effect can be fed back relatively accurately through at least one of waveform data, text information, and performance indicators.

[0117] S202. Process the simulation data to obtain the feature vector and / or reward parameters corresponding to the simulation data.

[0118] In this application, processing simulation data to obtain corresponding feature vectors may include: performing feature encoding on waveform data in the simulation data to obtain waveform feature vectors; performing feature encoding on text information in the simulation data to obtain text feature vectors; and performing normalization on performance indicators in the simulation data to obtain numerical feature vectors. Furthermore, at least one of the above feature vectors corresponding to the simulation data is fused to obtain the feature vector corresponding to the simulation data.

[0119] The process of feature encoding for waveform data to obtain waveform feature vectors can include: if the waveform data is an image, using a Convolutional Neural Network (CNN) (such as ResNet) to extract features; if the waveform data is time-series data, using a Long Short-Term Memory (LSTM) network or 1D-CNN to encode it into a feature vector.

[0120] Encoding text information to obtain text feature vectors can include using NLP models such as BERT to encode text information such as errors and warnings to obtain corresponding feature vectors.

[0121] For example, fusing at least one of the aforementioned feature vectors corresponding to simulation data to obtain the feature vectors corresponding to the simulation data can include: employing an advanced multimodal fusion strategy, such as inputting the feature vectors of different modalities into a large multimodal model. Through its internal self-attention and cross-attention mechanisms, the model can learn the inherent correlation between the feature vectors corresponding to different simulation data (e.g., what kind of anomaly on the waveform is associated with a specific error text), and obtain the feature vectors corresponding to the simulation data based on this inherent correlation. Alternatively, fusion processing can be achieved by concatenating at least one feature vector.

[0122] In this way, different types of simulation data are encoded separately, ensuring the accuracy of the corresponding feature vectors obtained after encoding. Furthermore, by fusing different feature vectors, the fused feature vector can more accurately represent the effect of the generated circuit code after simulation, thus guiding the subsequent iterative process of the code generation model.

[0123] In this application, processing the simulation data to obtain the corresponding reward parameters may include: for waveform data in the simulation data, generating a waveform reward value corresponding to the waveform data based on the waveform data and the target waveform data; for text information in the simulation data, analyzing the text information and generating a basic reward value based on the analysis results; for performance indicators in the simulation data, generating a performance reward value corresponding to the performance indicator based on the performance indicator and the target performance indicator. Further, the reward parameters corresponding to the simulation data are obtained based on at least one of the above reward values.

[0124] Among them, the waveform reward value is used to characterize the degree of similarity between the waveform data and the target waveform data. The closer the waveform data is to the target waveform data, the greater the waveform reward value.

[0125] The target waveform data can be generated based on the circuit generation requirements in the user's book. This application embodiment does not specifically limit the source of the target performance indicators.

[0126] The performance bonus value is used to characterize how close the performance metric is to the target performance metric. The closer the performance metric is to the target performance metric, the larger the performance bonus value.

[0127] Obtaining reward parameters corresponding to the simulation data based on at least one reward value can include: directly calculating the sum of at least one reward value, or performing a weighted average on at least one reward value to obtain reward parameters corresponding to the simulation data. In the weighted average process, the weight values ​​corresponding to different reward values ​​can be preset; this embodiment does not limit the weight values.

[0128] It should be noted that the reward parameter can be understood as the comprehensive reward value.

[0129] In this way, by calculating the reward values ​​corresponding to different types of simulation data, and based on at least one determined reward value, a comprehensive reward value, i.e., a reward parameter, is obtained. This allows the generated reward parameter to characterize the effect of the generated circuit code after simulation, thus guiding the subsequent iterative process of the code generation model.

[0130] In this application, generating a waveform reward value corresponding to the waveform data based on the waveform data and the target waveform data may include: determining the similarity between the waveform data and the corresponding target waveform data; generating a waveform reward value corresponding to the waveform data based on the similarity, wherein the waveform reward value is proportional to the similarity.

[0131] For example, a corresponding waveform reward value can be generated based on similarity and a pre-stored correspondence between similarity and reward values. Alternatively, the waveform reward value corresponding to the similarity can be calculated based on similarity and a preset calculation method. Or, the waveform reward value can be determined through other methods; this application embodiment does not specifically limit the method.

[0132] In this way, based on the similarity between the waveform data and the corresponding target waveform data, the corresponding waveform reward value is determined, so that the obtained waveform reward value can more accurately reflect the closeness between the waveform data and the target waveform data.

[0133] Analyzing text information and generating a base reward value based on the analysis results may include: analyzing text information to determine the simulation completion result; the simulation completion result includes simulation success and simulation failure; if the simulation completion result is simulation success, then the preset reward value is determined as the base reward value; if the simulation completion result is simulation failure, then the error parameters are obtained from the text information, and the base reward value is generated based on the error parameters and the reward value generation strategy.

[0134] This application does not impose specific limitations on the preset reward value.

[0135] For example, the reward value generation strategy may include: the correspondence between the size of the error parameter and the reward value, and the correspondence between the type of the error parameter and the reward value. For instance, when the error parameter includes parameter 1, the base reward value can be determined to be 2.

[0136] The specific reward value generation strategy can be set according to the actual situation, and this application embodiment does not impose specific limitations on it.

[0137] It should be understood that when the simulation succeeds, the generated base reward value is positive. When the simulation fails, the generated base reward value is negative.

[0138] In this way, for both successful and unsuccessful simulations, corresponding base reward values ​​are generated based on different generation methods. The generated base reward values ​​correspond to the success and failure of the simulation, resulting in higher accuracy.

[0139] Generating the performance reward value corresponding to the performance indicator based on the performance indicator and the target performance indicator may include: determining the deviation value between the performance indicator and the corresponding target performance indicator; generating the performance reward value corresponding to the performance indicator based on the deviation value, wherein the performance reward value is inversely proportional to the deviation value.

[0140] For example, a corresponding performance reward value can be generated based on the deviation value and a pre-stored correspondence between deviation values ​​and reward values. Alternatively, the performance reward value corresponding to the deviation value can be calculated based on the deviation value and a preset calculation method. Or, the performance reward value can be determined through other methods; this application embodiment does not specifically limit the method.

[0141] In this way, based on the deviation between the performance index and the corresponding target performance index, the corresponding performance bonus value is determined, so that the obtained performance bonus value can more accurately reflect the degree of closeness between the performance index and the corresponding target performance index.

[0142] The following describes the entire process of the code generation method in conjunction with the content of the above embodiments. Figure 3 This is a schematic diagram of the overall process of a code generation method provided in an embodiment of this application.

[0143] like Figure 3 As shown, the code generation method may include the following steps:

[0144] Step 1: Obtain the circuit generation requirements input by the user.

[0145] The user inputs the circuit design requirements, i.e., the circuit generation requirements. The input format can be multimodal, such as at least one of the following:

[0146] 1) Image file of circuit schematic.

[0147] 2) Natural language text describing the circuit function.

[0148] 3) The circuit's netlist file.

[0149] 4) Clear target performance indicators, such as gain greater than 20dB and power consumption less than 5mW.

[0150] Generating circuit code based on circuit generation requirements using a reinforcement learning model can include the following steps:

[0151] Step 2: Generate initial circuit code using a multimodal large model.

[0152] The system employs a pre-trained Multimodal Large Model (MMLM), such as the Qwen-VL series models, which is fine-tuned to understand circuit-related inputs. The MMLM receives the input from step 1 and generates initial circuit code, typically in Verilog-A.

[0153] Step 3: Automated SPICE simulation and performance evaluation.

[0154] The SPICE simulation engine is automatically invoked, and the circuit code generated in step 2 is used as input for simulation.

[0155] After the simulation is completed, the simulation results are automatically collected and analyzed. The simulation results are multimodal, including at least one of the following: waveform data, text information, and performance indicators.

[0156] For details regarding the waveform data, text information, and performance indicators, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0157] Step 4: Fusion processing of multimodal simulation feedback.

[0158] The collected multimodal simulation results are fused and converted into a unified format that MMLM can understand. The detailed process is as follows:

[0159] 1) Feature encoding:

[0160] ①Text information: Error and warning texts are encoded into feature vectors using NLP models such as BERT.

[0161] ② Waveform data: If it is an image, use CNN (such as ResNet) to extract features; if it is time series data, use LSTM or 1D-CNN to encode it into feature vectors.

[0162] ③Performance index: After normalizing the values, they are used as numerical feature vectors.

[0163] 2) Feature fusion:

[0164] By employing a multimodal fusion strategy, such as inputting the feature vectors of the different modalities mentioned above into a large multimodal model, the model can learn the intrinsic correlation between different feedback information through its internal self-attention and cross-attention mechanisms (e.g., what kind of anomaly on the waveform is associated with a specific error text).

[0165] 3) Generate a unified representation:

[0166] The fusion module ultimately outputs a unified, information-rich feature vector that comprehensively describes the simulation performance of the current circuit code.

[0167] Step 5: Design and calculation of the reward function.

[0168] Based on the simulation results from step 3 and the user-defined objectives, a quantified reward value is designed and calculated. This reward value guides the training direction of reinforcement learning. The design of the reward function may include:

[0169] 1) Basic reward: If the simulation is successful, a fixed positive reward value is given, which is the preset reward value in the above embodiment; if the simulation fails or an error occurs, a negative reward value is determined according to the content of the error.

[0170] 2) Performance Bonus: Determined based on how closely the simulated performance metrics approximate the target metrics. For example, the smaller the difference between the gain and the target gain, the higher the bonus. This can be quantified using functions such as mean squared error.

[0171] 3) Waveform reward: If the goal is to reproduce a preset target waveform, the similarity between the simulated waveform (corresponding to the waveform data in the above embodiment) and the target waveform (corresponding to the target waveform data in the above embodiment) can be used as a reward (e.g., calculating the mean square error of the two curves).

[0172] Step 6: Policy optimization based on reinforcement learning.

[0173] 1) The system uses a reinforcement learning algorithm (such as Proximal Policy Optimization (PPO)) to optimize the generation strategy of MMLM.

[0174] 2) In the RL framework:

[0175] ①State: The current circuit design requirements and the circuit code / simulation feedback from the previous round.

[0176] ②Action: Modifications made by MMLM to the circuit code (such as adjusting a resistor value, changing a connection relationship, or rewriting a piece of logic).

[0177] ③Reward: The reward value calculated in step 5.

[0178] During this process, a pre-built knowledge base (e.g., containing common circuit design rules, classic topologies, etc.) can be used. When the model explores certain specific regions, it can obtain heuristic information from the knowledge base, thereby accelerating convergence and avoiding ineffective exploration by the model.

[0179] 3) Based on the fused simulation feedback (step 4) and the calculated reward (step 5), MMLM adjusts its internal parameters and learns how to perform "actions" that will earn higher rewards, i.e., generate better circuit code.

[0180] Step 7: Iteration and convergence.

[0181] 1) The system will generate new circuit code from the optimized MMLM and send it back to step 3 for a new round of "simulation-feedback-optimization" cycle.

[0182] 2) This loop repeats continuously until the simulation results meet all target performance indicators, or the preset maximum number of iterations is reached. Finally, the system outputs a final circuit code that has undergone multiple rounds of automatic optimization and meets the performance targets.

[0183] In summary, the code generation method presented in this application deeply integrates SPICE simulation into the AI ​​model's generation loop, utilizing real circuit simulation results as dynamic feedback. This solves the problem of the disconnect between traditional AI design methods and physical reality. Because each generation step undergoes verification and feedback in a real simulation environment, the final output circuit code exhibits higher reliability and performance compliance. The circuit code generation process is modeled as a reinforcement learning problem, using simulation results as quantified reward signals to guide the large model in autonomous exploration and design optimization. It can simultaneously process and understand multiple types of feedback from simulation (waveform graphs, error text, performance values). Through multimodal fusion technology, the model can gain a more comprehensive and profound understanding of the actual behavior of the circuit, thereby enabling more precise corrections. The entire code generation process requires no manual intervention and can automatically iterate until the design goals are met. This framework has good scalability and can be applied to the design and optimization of various circuit types, including analog, digital, and mixed-signal circuits.

[0184] The method for simulating circuit code generated by a code generation model provided in this application generates feature vectors and / or reward parameters corresponding to the simulation data, so that the code generation model can directly process the simulation results.

[0185] Figure 4 This is a schematic diagram of the structure of a code generation device provided in an embodiment of this application, as shown below. Figure 4 As shown, the code generation device 40 provided in this embodiment includes:

[0186] The acquisition module 401 is used to acquire circuit generation requirements.

[0187] The generation module 402 is used to input the circuit generation requirements into the code generation model, and perform N iterations through the code generation model to generate the target circuit code corresponding to the circuit generation requirements. Specifically, in the first iteration, the code generation model generates circuit code based on the circuit generation requirements. In the i-th iteration, the code generation model corrects the circuit code obtained in the (i-1)-th iteration based on the circuit generation requirements, the circuit code obtained in the (i-1)-th iteration, and the simulation results, and then generates new circuit code. The simulation results are obtained by simulating the circuit code obtained in the (i-1)-th iteration through the simulation module. N and i are both positive integers greater than or equal to 2.

[0188] In one possible implementation, the simulation results include feature vectors and / or reward parameters. The generation module 402 is specifically used to simulate the circuit code obtained in the (i-1)th iteration using the simulation module to obtain simulation data; and to process the simulation data to obtain the feature vectors and / or reward parameters corresponding to the simulation data.

[0189] In one possible implementation, the simulation data includes at least one of waveform data, text information, and performance metrics.

[0190] In one possible implementation, the generation module 402 is specifically used to perform feature encoding processing on the waveform data in the simulation data to obtain a waveform feature vector; to perform feature encoding processing on the text information in the simulation data to obtain a text feature vector; to perform normalization processing on the performance indicators in the simulation data to obtain a numerical feature vector; and to perform fusion processing on at least one of the above feature vectors corresponding to the simulation data to obtain a feature vector corresponding to the simulation data.

[0191] In one possible implementation, the generation module 402 is specifically used to generate a waveform reward value corresponding to the waveform data based on the waveform data and the target waveform data in the simulation data; to analyze the text information in the simulation data and generate a basic reward value based on the analysis results; to generate a performance reward value corresponding to the performance index based on the performance index and the target performance index in the simulation data; and to obtain the reward parameter corresponding to the simulation data based on at least one of the above reward values ​​corresponding to the simulation data.

[0192] In one possible implementation, the generation module 402 is specifically used to determine the similarity between waveform data and the corresponding target waveform data; and to generate a waveform reward value corresponding to the waveform data based on the similarity, wherein the waveform reward value is proportional to the similarity.

[0193] In one possible implementation, the generation module 402 is specifically used to analyze the text information and determine the simulation completion result; the simulation completion result includes simulation success and simulation failure; if the simulation completion result is simulation success, then the preset reward value is determined as the basic reward value; if the simulation completion result is simulation failure, then the error parameter is obtained from the text information, and the basic reward value is generated according to the error parameter and the reward value generation strategy.

[0194] In one possible implementation, the generation module 402 is specifically used to determine the deviation value between the performance index and the corresponding target performance index; and to generate a performance bonus value corresponding to the performance index based on the deviation value, wherein the performance bonus value is inversely proportional to the deviation value.

[0195] In one possible implementation, the code generation model is a multimodal large model.

[0196] In one possible implementation, the generation module 402 is specifically used to iterate through a large model until preset conditions are met, then stop the iteration and generate the target circuit code corresponding to the circuit generation requirements. The preset conditions include: the deviation between each performance indicator in the simulation results of the circuit code and the corresponding target performance indicator is less than a corresponding preset value, or the number of iterations reaches a preset number.

[0197] In one possible implementation, the circuit generation requirement includes at least one of the following:

[0198] The image file corresponding to the circuit;

[0199] Natural language text describing the function of the circuit;

[0200] Circuit netlist;

[0201] Target performance metrics.

[0202] The code generation device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0203] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 5 As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus 504.

[0204] In a specific implementation, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.

[0205] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0206] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0207] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0208] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0209] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0210] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0211] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0212] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0213] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0214] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0215] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0216] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0217] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0218] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A code generation method characterized by, The method comprises the following steps: acquiring a circuit generation requirement; inputting the circuit generation requirement into a code generation model, and generating target circuit code corresponding to the circuit generation requirement through N rounds of iterations of the code generation model; wherein, in the first round of iteration, circuit code is generated according to the circuit generation requirement through the code generation model, and in the i th round of iteration, the circuit code obtained in the (i-1) th round of iteration is modified to generate circuit code according to the circuit generation requirement, the circuit code obtained in the (i-1) th round of iteration and simulation results through the code generation model; the simulation results are obtained by simulating the circuit code obtained in the (i-1) th round of iteration through a simulation module; N and i are both positive integers greater than or equal to 2.

2. The method of claim 1, wherein, the simulation results include a feature vector and / or a reward parameter; the simulation of the circuit code obtained in the (i-1) th round of iteration through the simulation module comprises the following steps: simulating the circuit code obtained in the (i-1) th round of iteration through the simulation module to obtain simulation data; processing the simulation data to obtain a feature vector and / or a reward parameter corresponding to the simulation data.

3. The method of claim 2, wherein, the simulation data includes at least one of waveform data, text information and performance indicators.

4. The method of claim 3, wherein, processing the simulation data to obtain a feature vector corresponding to the simulation data comprises the following steps: for the waveform data in the simulation data, performing feature coding processing on the waveform data to obtain a waveform feature vector; for the text information in the simulation data, performing feature coding processing on the text information to obtain a text feature vector; for the performance indicators in the simulation data, performing normalization processing on the performance indicators to obtain a numerical feature vector; fusing the at least one feature vector corresponding to the simulation data to obtain a feature vector corresponding to the simulation data.

5. The method of claim 3, wherein, processing the simulation data to obtain a reward parameter corresponding to the simulation data comprises the following steps: for the waveform data in the simulation data, generating a waveform reward value corresponding to the waveform data according to the waveform data and target waveform data; for the text information in the simulation data, analyzing the text information to generate a basic reward value according to the analysis result; for the performance indicators in the simulation data, generating a performance reward value corresponding to the performance indicators according to the performance indicators and target performance indicators; obtaining a reward parameter corresponding to the simulation data according to the at least one reward value corresponding to the simulation data.

6. The method of claim 5, wherein, generating a waveform reward value corresponding to the waveform data according to the waveform data and target waveform data comprises the following steps: determining the similarity between the waveform data and the corresponding target waveform data; generating a waveform reward value corresponding to the waveform data according to the similarity, wherein the waveform reward value is proportional to the similarity.

7. The method of claim 5, wherein, analyzing the text information to generate a basic reward value according to the analysis result comprises the following steps: analyzing the text information to determine a simulation completion result; the simulation completion result includes simulation success and simulation failure; if the simulation completion result is simulation success, a preset reward value is determined as the basic reward value; If the simulation completion result is that the simulation is unsuccessful, an error reporting parameter is obtained in the text information, and a strategy is generated according to the error reporting parameter and a reward value to generate a basic reward value.

8. The method of claim 5, wherein, The generating of the performance reward value corresponding to the performance index according to the performance index and the target performance index comprises: determining a deviation value of the performance index and the corresponding target performance index; generating the performance reward value corresponding to the performance index according to the deviation value, the performance reward value being inversely proportional to the deviation value.

9. The method according to any one of claims 1 to 8, characterized in that, The code generation model is a multi-modal large model.

10. The method of claim 9, wherein, The generating of the target circuit code corresponding to the circuit generation requirement through N rounds of iteration of the code generation model comprises: iterating through the large model until a preset condition is met, stopping iteration and generating the target circuit code corresponding to the circuit generation requirement; The preset condition comprises: a deviation value between each performance index in the simulation result of the circuit code and the corresponding target performance index is less than a corresponding preset value, or the number of iterations reaches a preset number.

11. The method according to any one of claims 1 to 8, characterized in that, The circuit generation requirement comprises at least one of: an image file corresponding to the circuit; a natural language text describing the function of the circuit; a circuit netlist; a target performance index.

12. A code generation apparatus characterized by comprising: comprises: an acquisition module configured to acquire a circuit generation requirement; a generation module configured to input the circuit generation requirement into a code generation model, generate a target circuit code corresponding to the circuit generation requirement through N rounds of iteration of the code generation model; wherein in the first round of iteration, the code generation model generates a circuit code according to the circuit generation requirement, and in the i-th round of iteration, the code generation model corrects the circuit code obtained in the (i-1)-th round of iteration to generate a circuit code according to the circuit generation requirement, the circuit code obtained in the (i-1)-th round of iteration, and a simulation result; The simulation result is obtained by simulating the circuit code obtained in the (i-1)-th round of iteration through a simulation module; N and i are both positive integers greater than or equal to 2.

13. An electronic device, comprising: comprises: a memory, a processor; The memory stores computer execution instructions; The processor executes the computer execution instructions stored in the memory, so that the processor executes the method of any one of claims 1-11.

14. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by the processor to implement the method of any one of claims 1-11.

15. A computer program product, characterised in that, The computer program is executed by the processor to implement the method of any one of claims 1-11.

Images