A method for timing accurate synchronization in a simulator based on shared memory

Abstract

The application discloses a kind of based on shared memory implementation simulator in timing accurate synchronization method, it is related to simulator development and cross-process communication technical field, including the construction containing head control area, annular data area, compact storage unit Standardized three-layer layout, head control area uses Rust atomic type encapsulation control parameter, annular data area cyclic access, compact storage unit binding data and timing;Through global singleton handle manager, realize cross-platform zero leakage resource management, provide interface reuse or create shared memory and map;Sending end encodes data and binds timing, atomically updates write pointer, receiving end reads data and calibrates timing, atomically updates read pointer;Timing accuracy, transmission delay, throughput and stability verification are executed.The application eliminates lock competition overhead, greatly improves cross-process data transmission efficiency, guarantees timing synchronization accuracy, adapts hardware bus fine demand.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of simulator development and cross-process communication technology, and in particular to a method for realizing timing accurate synchronization in a simulator based on shared memory. BACKGROUND

[0002] In modern simulator development, in order to realize functional modularization and flexible deployment, multi-functional modules are often split and run in the form of independent processes. These processes need to complete accurate "data transmission-time alignment" to restore the real running behavior of hardware devices, such as timing matching of peripheral register read-write, delay control of multi-module collaborative response, etc., which directly determines the simulation accuracy of the simulator. However, the current mainstream communication scheme cannot meet the dual requirements of high efficiency and strict timing of the simulator. The communication mode based on network sockets needs to pass through multiple layers of protocol stack encapsulation, and the delay is generally more than 100us, and the pipe communication delay is slightly lower but still about 50us, which cannot meet the core requirement of ns-level timing control of the simulator, resulting in deviation of hardware behavior simulation.

[0003] Although the traditional shared memory scheme reduces the transmission delay through direct memory access, it relies on mutex or semaphore to realize inter-process coordination, which causes serious lock contention problem. The lock waiting time often accounts for more than 30%, not only causing the data transmission throughput to drop by more than 40%, but also easily causing timing disorder due to lock contention, which destroys the consistency of multi-process collaboration. Some lock-free shared memory schemes only use simple pointer operations and cannot solve the two key problems of "read-write pointer competition ambiguity" and "data visibility caused by CPU cache", which frequently cause data loss or reading errors in actual application, and cannot guarantee transmission reliability. At the same time, these schemes lack a unified handle management mechanism, and the reuse rate of shared memory resources is low, with a resource leakage rate of more than 20%, increasing the system operation and maintenance cost and stability risk.

[0004] The existing technology has not formed an integrated solution of "lock-free synchronization + timing binding + cross-platform unified management", which cannot meet the comprehensive needs of the simulator for transmission efficiency, timing accuracy and system reliability. On the one hand, most schemes do not deeply bind data and timing information, which cannot adapt to the fine timing requirements of IIC, SPI, UART and other hardware buses; on the other hand, cross-platform deployment support is insufficient, and the resource creation and release mechanisms under different operating systems differ greatly, resulting in high adaptation cost and poor compatibility of the scheme. These problems jointly restrict the simulation accuracy and running stability of the simulator, and become a technical bottleneck that needs to be broken through in the field of simulator development. SUMMARY

[0005] The method for realizing timing accurate synchronization in a simulator based on shared memory proposed by the present application solves the problems mentioned in the prior art.

[0006] In order to achieve the above object, the application adopts the following technical scheme: a timing accurate synchronization method in a simulator based on shared memory, comprising the following steps:

[0007] A standardized three-layer shared memory layout is constructed: the head control area is encapsulated by a RustAtomicUsize atomic type, read_ptr, write_ptr, and buffer_size; the ring data area has a capacity consistent with buffer_size, and circular access is completed by index modulo; the compact storage unit is an EncodedEntry structure body modified by #[repr(packed)], which contains 32-bit bit_value, 8-bit status_flag, and 24-bit timing_count, and a single structure occupies ≤8 bytes;

[0008] Cross-platform zero-leak resource management is realized based on Rust: a global singleton SharedMemoryManager is defined by lazy_static!, which internally stores shared memory handles in a MutexHashMapString, Arc>; a get_or_create interface is provided, which returns after verifying capacity consistency, or creates a new instance and initializes the header parameters into the HashMap; relying on conditional compilation, resources are released by shm_unlink and munmap on Unix systems, and Drop trait is called to call munmap on Windows systems, relying on system mechanisms to recycle handles;

[0009] Cross-process lock-free data transmission and timing synchronization are realized: the sending end encodes data into EncodedEntry format, writes it into the ring buffer and synchronizes timing_count, and uses the Release memory order atomic to update write_ptr; the receiving end reads the read-write pointer by Acquire memory order, calculates the available data amount, reads the data into the read-side FIFO, and adjusts the timing based on timing_count, and uses the Release memory order to update read_ptr;

[0010] Performance verification: FPGA 1ns clock verification timing accuracy, 1GS / s oscilloscope collects transmission delay; 72-hour full-load running verifies stability, timing synchronization deviation ≤1ns, cross-process transmission delay ≤8μs, throughput ≥1.2GB / s, handle reuse rate 100%.

[0011] Further, a timing deviation dynamic compensation step is further included, the receiving end extracts the timing_count value from the EncodedEntry data as the sending end clock count, reads the local hardware clock count to calculate the count difference as the local hardware clock count minus the sending end clock count, and compensates the timing deviation by the formula Compensate the delay amount, wherein is the final compensation delay amount, is the clock cycle coefficient, is the count difference value, is the base compensation threshold value, which is preset according to the simulator timing accuracy requirement.

[0012] Further, it further includes a ring buffer state calculation step, and the sending end calculates the free space by the formula The receiving end calculates the available data amount by the formula wherein is the ring buffer free space, is the buffer size, is the current value of write_ptr, is the current value of read_ptr, is the available data amount.

[0013] Further, it further includes a multi-bus protocol adaptation step, the data to be transmitted is IIC, SPI or UART bus protocol data, the status_flag field of the EncodedEntry structure is defined differently according to the bus type, 0x01 in IIC bus protocol data represents a start condition, 0x02 represents a stop condition, 0x04 represents an ACK bit, and 0x08 represents a data bit; 0x10 in SPI bus protocol data represents a chip select signal, 0x20 represents a clock signal, 0x40 represents MOSI data, and 0x80 represents MISO data; 0x01 in UART bus protocol data represents a start bit, 0x02 represents a data bit, 0x04 represents a check bit, and 0x08 represents a stop bit, and 5-8-bit data bits and 1-2-bit stop bits are supported.

[0014] Further, it further includes a sending end free space checking step, the sending end reads the values of write_ptr and read_ptr respectively by atomic operation before data writing, calculates the free space as buffer_size minus the difference between the values of write_ptr and read_ptr, and performs data writing operation when the free space is not less than the number of bytes occupied by a single EncodedEntry structure, and after writing is completed, the number of bytes occupied by a single EncodedEntry structure is added to write_ptr by write_ptr.fetch_add, and Ordering::Release is used to complete atomic updating of the write pointer.

[0015] Further, it also includes a receiving end decoding and data distribution step. After the receiving end reads the EncodedEntry data, it first extracts the status_flag value to identify the data type, and then decodes the bit_value data to obtain the original transmission information. If it is IIC bus data, it parses the protocol according to the start condition, stop condition, ACK bit, and data bit identification. If it is SPI bus data, it reorganizes the data frame according to the chip select signal, clock signal, MOSI data, and MISO data identification. If it is UART bus data, it restores the byte stream according to the start bit, data bit, check bit, and stop bit identification.

[0016] Further, it also includes a cross-platform shared memory creation refinement step. In Unix and Unix-like operating systems, the shm_open function is called to create a named shared memory object, specifying the object name, access rights, and creation mode. Then the mmap function is called to map the shared memory object to the current process address space. In Windows operating systems, the CreateFileMapping function is called to create a file mapping object, specifying the mapping file handle, security attributes, file size high and low values, and mapping name. Then the MapViewOfFile function is called to map the file mapping object to the current process address space, setting the mapping access rights to read and write.

[0017] Further, it also includes a performance verification refinement step. Timing accuracy verification is performed by generating a 1ns period standard clock signal using FPGA, synchronously triggering the sending end timing_count counter and the receiving end verification logic, and collecting 10000 sets of the difference between the sending end timing_count value and the receiving end local clock count. Transmission delay verification is performed using a 1GS / s sampling rate high-precision oscilloscope to collect the time difference between the sending end data write completion signal and the receiving end data parsing completion signal. Throughput verification uses a fixed data amount of 10GB as the test benchmark to count the effective data amount transmitted across processes per unit time. Stability verification runs continuously for 72 hours under full load, with a cumulative transmission data amount of not less than 100GB, and a data transmission error rate of not more than 10 -6 After 1000 process restarts, the handle reuse success rate is 100%.

[0018] Further, it also includes a handle reuse consistency verification step. When the get_or_create interface queries the cache handle, it verifies the consistency of the buffer_size and the received capacity parameters, as well as the layout structure version of the shared memory, the EncodedEntry structure format, and the atomic operation memory sequence configuration. If all three key parameters are consistent, the cache handle is returned. If any of the parameters is inconsistent, the handle is considered invalid and is deleted, and a new shared memory instance that meets the current parameter requirements is created.

[0019] Further, it further comprises a simulation scenario expansion adaptation step, based on the extensible characteristics of the EncodedEntry structure, an extension field reserved is added for storing custom extension information, the get_or_create interface parameter is expanded, layout configuration parameters and timing accuracy parameters are added, the layout configuration parameter supports adjusting the bit allocation of each field of the EncodedEntry structure, the timing accuracy parameter supports setting the mapping ratio of timing_count and hardware clock period, and the simulator scene with different accuracy requirements from ns level to mu s level is adapted, while the core lock-free synchronization mechanism and cross-platform management characteristics remain unchanged.

[0020] Compared with the existing technology, the beneficial effects of the present application are:

[0021] The timing accurate synchronization method in the simulator based on shared memory of the present application solves the multiple pain points of the traditional scheme, and significantly improves the transmission efficiency, timing accuracy, system reliability, cross-platform compatibility and scalability, providing efficient and reliable core technical support for simulator development.

[0022] The transmission efficiency is fundamentally optimized, the lock competition performance loss in the traditional scheme is completely eliminated by constructing a lock-free synchronization architecture, combined with the direct access characteristics of shared memory, the intermediate link of data transmission is greatly reduced, and cross-process data transmission is more efficient. The close binding design of data and timing information avoids additional timing synchronization overhead, further improves the transmission efficiency, and can meet the demand of high-frequency data interaction of the simulator, which is significantly better than the network socket, pipe communication and traditional shared memory scheme.

[0023] The timing synchronization accuracy realizes a qualitative leap, the data bit value, state marker and timing count are integrated and packaged by a compact storage unit, ensuring that each data unit carries accurate timing information. The receiving end is calibrated based on the timing count, effectively compensating for clock deviation, making inter-process timing synchronization more accurate, and perfectly adapting to the fine timing requirements of IIC, SPI, UART and other hardware buses, providing a key guarantee for the restoration of real hardware behavior of the simulator.

[0024] The system reliability is greatly enhanced, the global singleton handle manager realizes the efficient reuse of shared memory resources, cooperates with the Arc reference counting and cross-platform resource automatic release mechanism, and eliminates the resource leakage problem. The memory safety characteristics of the Rust language avoid common errors such as wild pointers and data competition from the bottom, and after long-period full-load running verification, the system running stability is significantly improved, the failure rate is greatly reduced, and the operation and maintenance cost and potential risk are reduced.

[0025] The cross-platform compatibility advantage is prominent, relying on the conditional compilation characteristics of the Rust language, and the creation, mapping and resource release mechanism of the shared memory is customized for mainstream operating systems such as Unix and Unix-like, Windows and the like, to ensure that the scheme can run stably under different operating systems. The unified interface design reduces the cross-platform adaptation cost, so that the developer does not need to pay attention to the difference between the underlying system, and significantly improves the practicability and deployment efficiency of the scheme.

[0026] The expansibility is excellent, the standardized shared memory layout and the get_or_create interface simplify the integration process of the scheme, and facilitate the rapid integration into various simulator development scenes. The compact storage unit supports custom extension of state markers and data formats, can flexibly adapt to the transmission requirements of different hardware bus protocols, and supports flexible configuration of timing accuracy parameters, which can meet the simulator scene with different accuracy requirements from ns level to s level, and reserves sufficient space for subsequent function extension and scene adaptation. BRIEF DESCRIPTION OF DRAWINGS

[0027] Fig. 1 A schematic diagram of a method for realizing timing accurate synchronization in a simulator based on shared memory is provided.

[0028] Fig. 2 A three-layer layout flowchart of shared memory is provided.

[0029] Fig. 3 A cross-process lock-free data transmission timing flowchart is provided. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0031] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation of the present application.

[0032] In addition, the terms "first", "second", etc. are used only for the purpose of description and do not imply or indicate relative importance or imply the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited. In addition, the terms "mounting", "connecting", "connecting" should be broadly understood, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances, and the present application will be further described in detail below with reference to the accompanying drawings.

[0033] Referring to Figs. 1 to 3 A method for implementing timing accurate synchronization in a simulator based on shared memory, comprising the following steps:

[0034] A standardized three-layer layout of shared memory is constructed. The head control area uses the AtomicUsize atomic type of Rust language to encapsulate the read_ptr read pointer, write_ptr write pointer, and buffer_size buffer capacity three control parameters, respectively, to ensure the state visibility of multi-process concurrent access. The ring data area is configured with a storage capacity consistent with the buffer_size value, and the wrap-around calculation method of taking the buffer_size modulo the index value is used to realize cyclic access, maximizing memory utilization. The compact storage unit is an EncodedEntry structure with the attribute #[repr(packed)] marked, which contains 32-bit bit_value data bits, 8-bit status_flag status flag, and 24-bit timing_count timing count. The number of bytes occupied by a single structure is controlled within 8 bytes, realizing the close binding of data and timing.

[0035] Cross-platform zero-leakage resource management is implemented by defining a global singleton SharedMemoryManager using the lazy_static! macro of the Rust language, which internally sets up a Mutex structure to store a HashMap structure. The key of the HashMap is a shared memory name string, and the value is a SharedMemory handle with Arc reference counting. The get_or_create interface is provided, which receives a shared memory name parameter and a capacity parameter. First, the cached handle in the HashMap is queried. If it exists, the buffer_size is checked for consistency with the received capacity parameter. If they are consistent, the handle is returned. If it does not exist or the capacity is inconsistent, a new instance is created and mapped to the current process address space. After initializing the header control area parameters, they are stored in the HashMap and the new handle is returned. Based on the conditional compilation feature of Rust, in Unix and Unix-like operating systems, the shared memory object is deleted by the shm_unlink system call and the munmap function is called to unmap. In the Windows operating system, the munmap function is called by the Drop trait to unmap, and the resource is released relying on the operating system handle recycling mechanism.

[0036] Cross-process lock-free data transmission and timing synchronization are performed. The sender stores the data to be transmitted into the write-side FIFO buffer, encodes the buffer data according to the EncodedEntry structure format, synchronously writes the timing_count value corresponding to the hardware clock cycle 1:1, and updates the write pointer by calling the fetch_add atomic operation of write_ptr with Ordering::Release memory order to complete data writing. The receiver reads the values of read_ptr and write_ptr with Ordering::Acquire memory order, calculates the available data amount as the value of write_ptr minus the value of read_ptr, reads the EncodedEntry data from the read_ptr pointing position into the read-side FIFO buffer when the available data amount is greater than 0, performs timing calibration based on the timing_count value and the local clock, and updates the read pointer by calling the fetch_add atomic operation of read_ptr with Ordering::Release memory order.

[0037] Performance verification is performed. A 1ns period standard clock signal is generated by FPGA for timing accuracy verification, a 1GS / s sampling rate oscilloscope is used to collect transmission delay, 72-hour full-load running is performed for stability verification, timing synchronization deviation is controlled within 1ns, cross-process transmission delay is controlled within 8μs, data transmission throughput is maintained above 1.2GB / s, lock waiting time consumption ratio is 0%, handle reuse rate is 100%, and resource leakage rate is 0%.

[0038] In the application, the timing deviation dynamic compensation step is also included, the receiving end extracts the timing_count value from the EncodedEntry data as the sending end clock count, reads the local hardware clock count to calculate the count difference as the local hardware clock count minus the sending end clock count, and calculates the compensation delay through the formula The compensation delay is calculated, wherein The final compensation delay is The clock period coefficient is in a fixed proportional relationship with the hardware clock period, The count difference is The basic compensation threshold is preset according to the timing accuracy requirement of the simulator, and the receiving end data output timing is adjusted based on the compensation delay, so that the output timing deviation from the sending end timing is always controlled within 1ns, and the fine timing requirement of the hardware peripheral is adapted.

[0039] In the application, the ring buffer state calculation step is also included, the sending end calculates the idle space through the formula The receiving end calculates the available data amount through the formula The available data amount is calculated, wherein The ring buffer idle space is The buffer size is the total capacity of the buffer, The write_ptr current value is The read_ptr current value is The available data amount is calculated, so that the sending end non-blocking writing and the receiving end non-conflict reading are realized, and the data overflow or empty data reading situation is avoided.

[0040] In the application, the multi-bus protocol adaptation step is also included, the data to be transmitted is IIC, SPI or UART bus protocol data, the status_flag field of the EncodedEntry structure is defined as different identification according to the bus type, 0x01 in the IIC bus protocol data represents a start condition, 0x02 represents a stop condition, 0x04 represents an ACK bit, and 0x08 represents a data bit, 100Kbps standard mode and 400Kbps fast mode switching are supported; 0x10 in the SPI bus protocol data represents a chip select signal, 0x20 represents a clock signal, 0x40 represents MOSI data, and 0x80 represents MISO data, 1Mbps-10Mbps rate adjustment is supported; 0x01 in the UART bus protocol data represents a start bit, 0x02 represents a data bit, 0x04 represents a check bit, and 0x08 represents a stop bit, 5-8 bit data bit and 1-2 bit stop bit configuration are supported.

[0041] In the application, the sending end reads the values of write_ptr and read_ptr respectively by atomic operation before data writing, calculates the free space as buffer_size minus the difference between the values of write_ptr and read_ptr, and performs data writing operation when the free space is not less than the number of bytes occupied by a single EncodedEntry structure, and after writing is completed, the number of bytes occupied by a single EncodedEntry structure is added to write_ptr through write_ptr.fetch_add, and Ordering::Release is used to complete atomic updating of the write pointer, and when the value of write_ptr is not less than buffer_size, the value of write_ptr is reset to the starting position by taking the modulus of buffer_size, thereby ensuring the safety and continuity of the writing operation.

[0042] In the application, the receiving end first extracts the status_flag value to identify the data type after reading the EncodedEntry data, then decodes the bit_value data to obtain the original transmission information, and if it is IIC bus data, the protocol is parsed according to the identification of the start condition, stop condition, ACK bit and data bit, if it is SPI bus data, the data frame is reorganized according to the identification of the chip selection signal, clock signal, MOSI data and MISO data, if it is UART bus data, the byte stream is restored according to the identification of the start bit, data bit, check bit and stop bit, and finally the decoded original data is distributed to the corresponding simulator hardware peripheral module.

[0043] In the application, the cross-platform shared memory creation refinement step is further included, in Unix and Unix-like operating systems, the function of shm_open is called to create a named shared memory object, the object name, access permission and creation mode are specified, then the mmap function is called to map the shared memory object to the current process address space, and the mapping permission is set to read and write; in Windows operating system, the function of CreateFileMapping is called to create a file mapping object, the mapping file handle, security attribute, file size high and low values, and mapping name are specified, then the function of MapViewOfFile is called to map the file mapping object to the current process address space, the mapping access permission is set to file mapping read and write, and the consistency of shared memory creation and mapping under different operating systems is ensured.

[0044] The application also includes a performance verification refinement step. Timing accuracy verification generates a 1 ns period standard clock signal through an FPGA, synchronously triggers the sending end timing_count count and the receiving end check logic, collects 10,000 sets of the difference between the sending end timing_count value and the receiving end local clock count, and the sample proportion with a deviation of less than 1 ns is not less than 99.9%. Transmission delay verification uses a 1GS / s sampling rate high-precision oscilloscope to collect the time difference between the sending end data write completion signal and the receiving end data analysis completion signal, and the average value of repeated tests of 10,000 times is controlled to be less than 8μs. Throughput verification takes 10GB of fixed data as a test benchmark, counts the effective data amount transmitted across processes per unit time, and calculates the net throughput to maintain 1.2GB / s or more. Stability verification runs continuously for 72 hours under full load, accumulates a transmission data amount of not less than 100GB, and counts a data transmission error rate of not more than 10 -6 , and the handle reuse success rate is 100% after the process is restarted 1000 times, without resource leakage and memory exception.

[0045] The application also includes a handle reuse consistency verification step. When the get_or_create interface queries the cache handle, in addition to verifying the consistency of the buffer_size and the received capacity parameter, the layout structure version of the shared memory, the EncodedEntry structure format, and the memory sequence configuration of the atomic operation are also verified. When all the three key parameters are consistent, the cache handle is returned. If any of the three key parameters is inconsistent, the cache handle is considered invalid and is deleted, and a shared memory instance that meets the current parameter requirements is re-created, so that the reused shared memory can meet the current simulator timing synchronization requirements and avoid data transmission errors or timing deviations caused by parameter mismatch.

[0046] The application also includes a simulation scene expansion adaptation step. Based on the expandable feature of the EncodedEntry structure, an extension field reserved is added to store custom extension information, and custom attributes such as data check bits, module identifiers, and transmission priorities can be added according to different simulator scene requirements. The get_or_create interface parameters are expanded, and layout configuration parameters and timing accuracy parameters are added. The layout configuration parameters support adjusting the bit allocation of each field of the EncodedEntry structure, and the timing accuracy parameters support setting the mapping ratio of timing_count and hardware clock period, which can adapt to different precision requirements of simulator scenes from ns level to μs level, while keeping the core lock-free synchronization mechanism and cross-platform management characteristics unchanged.

[0047] The following two embodiments further illustrate the specific implementation of the system:

[0048] Embodiment 1 IIC bus peripheral simulator cross-process timing synchronization

[0049] The embodiment is applied to the development scene of IIC bus peripheral simulator, aims to realize the cross-process communication timing synchronization between the master chip and the peripheral chip, adapt the standard mode and the fast mode of the IIC bus, is deployed in the Unix operating system, accurately replicates the timing of reading and writing the peripheral register, and fully lands the technical solution of the application.

[0050] The construction of the shared memory standardized three-layer layout is the basis of the scheme implementation. The head control area adopts the AtomicUsize atomic type of the Rust language, encapsulates three core control parameters of the read pointer, the write pointer and the buffer capacity respectively, ensures the state visibility in the multi-process concurrent access, and avoids the data visibility problem caused by the CPU cache. The storage capacity of the ring data area is consistent with the buffer capacity, the circular access is realized through the ring calculation mode of the buffer capacity modulo the index value, the memory utilization is maximized, and the address overflow problem is avoided. The compact storage unit adopts the EncodedEntry structure body with the attribute of #[repr (packed)], which contains 32-bit data bit value, 8-bit state marker and timing count. The number of bytes occupied by a single structure body is strictly controlled within 8 bytes, the data and timing information are tightly bound, and the basis is provided for the subsequent timing accurate synchronization. The state marker field is defined according to the IIC bus protocol, and the start condition, the stop condition, the ACK bit and the data bit correspond to specific markers respectively, so as to ensure the accuracy of the protocol analysis.

[0051] Based on Rust, cross-platform zero-leak resource management is implemented. The global singleton SharedMemoryManager is defined by the lazy_static! macro. The Mutex structure is set inside the SharedMemoryManager to store the HashMap structure. The key of the HashMap is the shared memory name string, and the value is the SharedMemory handle with Arc reference counting. The centralized management and safe access of the handle are realized. The get_or_create interface is provided. After receiving the shared memory name parameter and the capacity parameter, the cached handle in the HashMap is queried first. If the cached handle exists, the consistency of the buffer capacity with the received capacity parameter is checked. At the same time, the layout structure version, the EncodedEntry structure format, and the atomic operation memory order configuration are also checked. When the four parameters are consistent, the cached handle is returned. If any of the parameters is inconsistent, the invalid handle is deleted. If the cached handle does not exist or has been deleted, a new shared memory instance is created. In the Unix operating system, the named shared memory object is created by the shm_open function. The object name, read-write access permission, and appropriate creation mode are specified. Then the mmap function is called to map the shared memory object to the current process address space. After the initialization of the head control area parameters, the parameters are stored in the HashMap and the new handle is returned. In the resource release stage, relying on the conditional compilation feature of Rust, the shared memory object is deleted by the shm_unlink system call, and the memory mapping is released by the munmap function. With the help of the Arc reference counting mechanism, the resource is completely released after all processes exit, and zero-leak resource management is realized.

[0052] The core link of performing cross-process lock-free data transmission and timing synchronization is to store the IIC bus protocol data to be transmitted into the write-side FIFO buffer, then traverse the buffer data, encode according to the EncodedEntry structure format, and write into the timing counter corresponding to the hardware clock cycle to ensure that each data unit carries accurate timing information. Before data writing, the sending end reads the values of the write pointer and read pointer through atomic operation, calculates the free space of the ring buffer, and when the free space is not less than the number of bytes occupied by a single EncodedEntry structure, performs data writing operation to avoid data overflow. After writing, the fetch_add atomic operation of the write pointer is updated by calling the memory sequence Ordering::Release, and when the value of the write pointer is not less than the buffer capacity, it is reset to the starting position by modulo method to ensure the safety and continuity of the writing operation. The receiving end reads the values of the read pointer and write pointer through Ordering::Acquire memory sequence, calculates the available data amount, and when the available data amount is greater than 0, reads the EncodedEntry data from the read pointer position and stores it into the read-side FIFO buffer. Based on the timing count carried in the data and the local hardware clock count, the timing is calibrated, the timing count is extracted as the sending end clock count, the local hardware clock count is read and the count difference is calculated, according to the preset clock period coefficient and the basic compensation threshold, the compensation delay is calculated, and the data output timing of the receiving end is adjusted according to the compensation delay to ensure that the timing synchronization deviation is controlled within the required range. After calibration, the fetch_add atomic operation of the read pointer is called to update the read pointer with Ordering::Release memory sequence to realize cross-process lock-free synchronization.

[0053] The receiving end decoding and data distribution step ensures accurate restoration and flow of original data. After reading the EncodedEntry data, the receiving end first extracts the state marker value to identify the data type, confirms that it is IIC bus protocol data, decodes the data bit value to get the original transmission information, then parses the protocol according to the start condition, stop condition, ACK bit and data bit identification, and finally distributes the decoded original data to the corresponding simulator hardware peripheral module to ensure that the peripheral module can accurately respond to the operation instructions of the master chip.

[0054] The simulation scenario expansion adaptation step improves the flexibility of the solution. Based on the extensible nature of the EncodedEntry structure, an extension field is added to store custom extension information. Custom attributes such as data check bits and module identification can be added according to the IIC bus simulator scenario requirements to enhance the reliability and traceability of data transmission. The get_or_create interface parameters are expanded, and layout configuration parameters and timing accuracy parameters are added. The layout configuration parameter supports adjusting the bit allocation of each field in the EncodedEntry structure, and the timing accuracy parameter supports setting the mapping ratio of timing count and hardware clock period to adapt to different accuracy requirements in this scenario while maintaining the core lock-free synchronization mechanism and cross-platform management characteristics unchanged.

[0055] The performance verification link fully tests the reliability and effectiveness of the solution. Timing accuracy verification generates a standard clock signal through professional equipment, synchronously triggers the sending end timing count and the receiving end verification logic, collects multiple sets of sending end timing count and receiving end local clock count difference, and ensures that the timing synchronization deviation meets the requirements. Transmission delay verification uses a high-precision oscilloscope to collect the time difference between the sending end data write completion signal and the receiving end data parsing completion signal, ensuring that the cross-process transmission delay is controlled within the specified range. Throughput verification takes a fixed data amount as the test benchmark, counts the effective data amount transmitted across processes per unit time, and ensures that the data transmission efficiency meets the requirements. Stability verification accumulates a large amount of data transmission through full-load continuous operation for a long period, counts the data transmission error rate, and performs multiple process restart tests to verify the handle reuse success rate and resource leakage, ensuring the stability and reliability of long-term system operation.

[0056] Table 1 Comparison of IIC bus peripheral simulation timing synchronization performance

[0057]

[0058] The data in Table 1 clearly shows that the scheme of the application has core advantages in the IIC bus simulation scene. The traditional shared memory scheme relies on mutual exclusion locks to coordinate process access, resulting in a large number of lock waiting time consumption, which not only leads to high cross-process transmission delay, but also seriously affects data transmission throughput, and the timing synchronization deviation is large, which cannot meet the fine timing requirements of the IIC bus, and the resource leakage rate is high, affecting the long-term running stability of the system. The network socket scheme is affected by the multi-layer encapsulation of the protocol stack, and the cross-process transmission delay is extremely high, the data transmission throughput is extremely low, the timing synchronization deviation is far beyond the requirement of the hardware bus, and it is difficult to adapt to the simulator scene. The scheme of the application completely eliminates the lock competition overhead through the lock-free synchronization architecture, combines the tight binding of data and timing and the dynamic compensation mechanism, realizes extremely low cross-process transmission delay and extremely small timing synchronization deviation, greatly improves the data transmission throughput, and at the same time, through the global singleton handle manager and the cross-platform resource automatic release mechanism, realizes zero resource leakage and 100% handle reuse rate, perfectly adapts to the core needs of high efficiency, precision and stability of the IIC bus peripheral simulator.

[0059] Example 2 SPI bus multi-module cooperative simulation timing synchronization

[0060] This embodiment is applied to the SPI bus multi-module cooperative simulation scene, simulates the cross-process timing synchronization between the master module and multiple peripheral modules, adapts to the multi-rate adjustment requirements of the SPI bus, is deployed in the Windows operating system, supports concurrent data interaction of multiple modules, and completely lands the technical scheme of the application.

[0061] When constructing the standardized three-layer layout of the shared memory, the head control area also uses the AtomicUsize atomic type of the Rust language to encapsulate the read pointer, the write pointer and the buffer capacity of the three control parameters, guarantee the state visibility of the multi-process concurrent access, and provide a basis for multi-module cooperative access. The storage capacity of the ring data area is consistent with the buffer capacity, and the circular access is realized by the wrap-around calculation method of the index value modulo the buffer capacity, which maximizes the memory utilization and meets the multi-module concurrent data storage requirements. The compact storage unit is the EncodedEntry structure with the attribute of #[repr (packed)], which contains 32-bit data bits, 8-bit state flags and 24-bit timing counts. The number of bytes occupied by a single structure is not more than 8 bytes, realizing the tight binding of data and timing. The state flag field defines specific identifiers according to the SPI bus protocol, and the chip select signal, the clock signal, the MOSI data and the MISO data correspond to exclusive identifiers respectively, ensuring accurate identification during multi-module data interaction.

[0062] Cross-platform zero-leak resource management is achieved through the features of the Rust language. With the help of the lazy_static! macro, a global singleton SharedMemoryManager is defined, and a Mutex<HashMap<String, Arc>> structure is set up inside to store shared memory handles. The key of the HashMap is a shared memory name string, and the value is a SharedMemory handle with Arc reference counting, which realizes efficient management of handles. When the get_or_create interface is called, the shared memory name and capacity parameters are passed in. The interface first queries the cached handle in the HashMap. If there is a cached handle, it checks the buffer capacity, shared memory layout structure version, EncodedEntry structure format, and atomic operation memory order configuration four key parameters. If all are consistent, return the handle, otherwise it is considered invalid and deleted. If the cached handle does not exist or has been deleted, a new shared memory instance is created. In the Windows operating system, the CreateFileMapping function is called to create a file mapping object, specifying the mapping file handle, security attributes, high and low values of the file size, and mapping name. Then the MapViewOfFile function is called to map the file mapping object to the current process address space, set the mapping access permission to read and write, and store the header control area parameters into the HashMap after initialization and return the new handle. In the resource release stage, the munmap function is called through the Drop trait to remove the memory mapping, relying on the handle recycling mechanism of the Windows operating system to release the shared memory resource. When the Arc reference count drops to 0, the automatic trigger cleaning logic is triggered, realizing cross-platform zero-leak resource management.

[0063] Cross-process lock-free data transmission and timing synchronization adaptation multi-module collaborative scene. The sending end is the process of simulating the master module, and the SPI bus protocol data frame is stored in the write-side FIFO buffer. The timing parameters are configured according to the current transmission rate. The buffer data is encoded according to the EncodedEntry structure format, and is written synchronously with the timing counter corresponding to the hardware clock cycle, ensuring the accuracy of the timing information of each data unit. Before writing data, the sending end reads the values of the write pointer and the read pointer through atomic operation, calculates the free space of the ring buffer, and performs the write operation when the free space is not less than the number of bytes occupied by a single EncodedEntry structure, avoiding data overflow. After writing is completed, the write pointer is updated by the fetch_add atomic operation of the Ordering::Release memory order. When the value of the write pointer is not less than the capacity of the buffer, it is reset to the starting position by modulo method to ensure the continuity of writing. Multiple receiving ends are processes simulating different peripheral modules, and the values of the read pointer and the write pointer are read through Ordering::Acquire memory order. When the available data amount is greater than 0, the EncodedEntry data is read from the read pointer position and stored in the read-side FIFO buffer of each receiving end. The receiving end extracts the timing counter in the data as the clock count of the sending end, reads the local hardware clock count and calculates the count difference. Combined with the preset clock period coefficient and the basic compensation threshold, the compensation delay is calculated, and the data output timing is adjusted according to the compensation delay to ensure that the timing synchronization deviation meets the requirements. After calibration, each receiving end updates the read pointer through Ordering::Release memory order to realize multi-process conflict-free access and lock-free synchronization.

[0064] The receiving end decoding and data distribution step ensures accurate interaction of multiple modules. After the receiving end reads the EncodedEntry data, it extracts the state marker value to identify the data type, confirms that it is SPI bus protocol data, decodes the data bit value to get the original transmission information, and reorganizes the data frame according to the chip select signal, clock signal, MOSI data and MISO data. Only the peripheral module with a matching chip select signal will respond to data interaction, ensuring the orderly progress of multi-module collaborative simulation. The reorganized original data is distributed to the corresponding peripheral module, realizing accurate collaboration of the master module and multiple peripheral modules.

[0065] The simulation scenario expansion adaptation step enhances the adaptability of the solution. Based on the extensible nature of the EncodedEntry structure, an extension field is added to store custom extension information. For SPI bus multi-module collaborative scenarios, a transmission priority field can be added to ensure priority transmission of critical data. The get_or_create interface parameters are expanded, with the addition of layout configuration parameters and timing accuracy parameters. The layout configuration parameters support adjusting the bit allocation of each field in the EncodedEntry structure, and the timing accuracy parameters support setting the mapping ratio of timing count and hardware clock period, adapting to different precision requirements of the simulator scene from ns level to μs level, while maintaining the core lock-free synchronization mechanism and cross-platform management characteristics unchanged, meeting the diversified needs of multi-module collaborative simulation.

[0066] The performance verification link fully tests the solution in multi-module scenarios. Timing accuracy verification generates a standard clock signal through professional equipment, synchronously triggers the sending end timing count and each receiving end verification logic, collects multiple sets of timing difference values, and ensures that the timing synchronization deviation is controlled within the specified range. Transmission delay verification uses a high-precision oscilloscope to collect the time difference between the sending end data write completion signal and the data analysis completion signal of each receiving end, ensuring that the cross-process transmission delay meets the requirements. Throughput verification takes a fixed data volume as the test benchmark, counts the effective data volume transmitted across processes per unit time, and meets the efficiency requirements of multi-module concurrent data interaction. Stability verification transmits a large amount of data through continuous full-load operation for a long period, counts the data transmission error rate, and performs multiple process restart tests to verify the handle reuse success rate and resource leakage, ensuring the stability and reliability of the system in multi-module concurrent access scenarios.

[0067] Table 2 SPI bus multi-module collaborative simulation performance comparison table

[0068]

[0069] The data in Table 2 directly reflects the significant advantages of the scheme of the application in the SPI bus multi-module cooperative simulation scene. The traditional shared memory scheme relies on mutual exclusion locks to coordinate multi-process access, and the lock waiting time occupies a high proportion of the time, resulting in high cross-process transmission delay, and the data transmission throughput cannot meet the multi-module concurrent demand, the timing synchronization deviation is large, which affects the multi-module cooperative precision, and the handle reuse rate is low, the resource leakage rate is high, and the system stability is insufficient. The pipe communication scheme is limited by the kernel buffer, the cross-process transmission delay is high, the data transmission throughput is medium to low, the timing synchronization deviation is large, and it is difficult to adapt to the fine timing requirements of the SPI bus high-speed transmission and multi-module cooperation. The scheme of the application completely eliminates the lock competition loss through the lock-free synchronization architecture, maximizes the memory utilization rate through the circular reuse design of the ring data area, and cooperates with the atomic operation to ensure conflict-free multi-process concurrent access, realizes extremely low cross-process transmission delay and extremely small timing synchronization deviation, greatly improves the data transmission throughput, and at the same time, through the global singleton handle manager and the cross-platform resource automatic release mechanism, realizes 100% handle reuse rate and resource zero leakage, provides efficient, accurate and stable timing synchronization support for SPI bus multi-module cooperative simulation.

[0070] Example 3 UART bus multi-rate communication timing synchronization

[0071] This embodiment is applied to the UART bus multi-rate communication simulator development scene, simulates the cross-process timing synchronization between the serial port device and the host module, adapts to different data bits and stop bits configurations of the UART bus, supports multi-rate adjustment, is deployed in a Unix-like operating system, realizes accurate simulation of serial port data transmission timing, and fully lands the technical scheme of the application.

[0072] When building a shared memory standardized three-layer layout, the head control area adopts the AtomicUsize atomic type of the Rust language, encapsulates three core control parameters of the read pointer, the write pointer and the buffer capacity, guarantees the state visibility during multi-process concurrent access, and provides a basis for cross-process data interaction. The storage capacity of the ring data area is consistent with the buffer capacity, and the circular access is realized through the wrap-around calculation mode of the buffer capacity modulo the index value, the memory utilization is improved, and address overflow is avoided. The compact storage unit is an EncodedEntry structure body with the attribute of #[repr (packed)], which internally includes 32-bit data bit value, 8-bit state flag and 24-bit timing count, and the number of bytes occupied by a single structure body is not more than 8 bytes, realizing the close binding of data and timing. The state flag field is identified according to the UART bus protocol definition, the start bit, the data bit, the check bit and the stop bit correspond to specific identifiers respectively, supporting flexible configuration of 5-8 data bits and 1-2 stop bits, meeting the multi-rate communication demand.

[0073] Cross-platform zero-leak resource management relies on the characteristics of the Rust language. The global singleton SharedMemoryManager is defined by the lazy_static! macro, and a Mutex<HashMap<String, Arc>> structure is set inside to store shared memory handles. The key of HashMap is a shared memory name string, and the value is a SharedMemory handle with Arc reference counting, which realizes centralized management of handles. When calling the get_or_create interface, the shared memory name and capacity parameters are passed in. The interface first queries the cached handle in HashMap. If there is a cached handle, it checks the buffer capacity, shared memory layout structure version, EncodedEntry structure format, and atomic operation memory order configuration four key parameters. If all are consistent, return the handle, otherwise it is considered invalid and deleted. If the cached handle does not exist or has been deleted, a new shared memory instance is created. In Unix-like operating systems, the shm_open function is called to create a named shared memory object, specify the object name, read-write access permissions and creation mode, then call the mmap function to map the shared memory object to the current process address space, and store it in HashMap after initializing the header control area parameters and return the new handle. In the resource release phase, the shared memory object is deleted by the shm_unlink system call, the memory mapping is removed by the munmap function, and the Arc reference counting mechanism is used to ensure that the resources are completely released after all processes exit, realizing zero-leak management.

[0074] Cross-process lock-free data transmission and timing synchronization guarantee efficient and accurate transmission of serial port data. The sending end stores the UART bus protocol data to be transmitted in the write-side FIFO buffer, encodes the data in the EncodedEntry structure format according to the current configured rate, data bits, and stop bits parameters, and synchronously writes it into the timing counter corresponding to the hardware clock cycle. Before writing data, the sending end reads the values of the write pointer and read pointer through atomic operations, calculates the free space of the ring buffer, and performs the write operation when the free space is not less than the number of bytes occupied by a single EncodedEntry structure, avoiding data overflow. After writing is completed, the write pointer is updated by calling the fetch_add atomic operation of the write pointer through the Ordering::Release memory order, and when the value of the write pointer is not less than the capacity of the buffer, it is reset to the starting position through the modulo method to guarantee the continuity of writing. The receiving end reads the values of the read pointer and write pointer through the Ordering::Acquire memory order, calculates the available data amount, and when the available data amount is greater than 0, reads the EncodedEntry data and stores it in the read-side FIFO buffer. The timing counter in the extracted data is used as the sending end clock count, the local hardware clock count is read and the count difference is calculated, combined with the preset clock period coefficient and the basic compensation threshold, the compensation delay is calculated, the data output timing is adjusted, and the timing synchronization deviation is ensured to meet the requirements. After calibration, the read pointer is updated through the Ordering::Release memory order to realize lock-free synchronization.

[0075] The receiving end decoding and data distribution step restores the original serial port data. After the receiving end reads the EncodedEntry data, it extracts the state marker value to identify the data type, confirms that it is UART bus protocol data, decodes the data bit value to get the original transmission information, restores the byte stream according to the identification of the start bit, data bit, check bit, and stop bit, performs verification according to the configured check bit rule to ensure the accuracy of data transmission, and finally distributes the decoded original data to the corresponding serial device simulation module to realize accurate simulation of serial communication.

[0076] The simulation scenario expansion adaptation step improves the flexibility and compatibility of the scheme. Based on the expandable nature of the EncodedEntry structure, an extension field is added to store custom extension information, and for the UART bus multi-rate scenario, a module identification field can be added to facilitate the differentiation of different serial devices. The get_or_create interface parameter is expanded, and a layout configuration parameter and a timing accuracy parameter are added. The layout configuration parameter supports adjusting the bit allocation of each field in the EncodedEntry structure, and the timing accuracy parameter supports setting the mapping ratio of the timing counter and the hardware clock period, adapting to different precision requirements of the simulator scenario from ns to μs, while maintaining the core lock-free synchronization mechanism and cross-platform management characteristics unchanged, meeting the diversified needs of multi-rate serial communication.

[0077] Performance verification link fully tests the reliability and adaptability of the scheme. The timing accuracy verification generates a standard clock signal through professional equipment, synchronously triggers the sending end timing counter and the receiving end check logic, collects multiple sets of timing difference values, and ensures that the timing synchronization deviation is controlled within the specified range. The transmission delay verification uses a high-precision oscilloscope to collect the time difference between the sending end data write completion signal and the receiving end data analysis completion signal, and ensures that the cross-process transmission delay meets the requirements. The throughput verification takes a fixed data amount as the test benchmark, counts the amount of effective data transmitted across the processes per unit time, and meets the efficiency requirements of multi-rate communication. The stability verification accumulates a large amount of data transmission through continuous full-load operation for a long period, counts the data transmission error rate, and performs multiple process restart tests to verify the handle reuse success rate and resource leakage, ensuring the stability and reliability of the system in multi-rate communication scenarios.

[0078] Table 3 UART bus multi-rate communication timing synchronization performance comparison table

[0079]

[0080] Table 3 clearly shows the core advantages of the present scheme in the UART bus multi-rate communication scenario. The traditional shared memory scheme relies on mutexes, and the lock waiting time occupies a high proportion, resulting in high cross-process transmission delay, insufficient data transmission throughput, large timing synchronization deviation, and inability to meet the fine timing requirements of UART bus multi-rate communication. In addition, the handle reuse rate is low, and the resource leakage rate is high, affecting system stability. The pipe communication scheme is limited by the transmission mechanism, resulting in high cross-process transmission delay, medium to low data transmission throughput, and large timing synchronization deviation, making it difficult to adapt to the high efficiency and precision requirements of multi-rate communication. The present scheme eliminates lock contention loss through a lock-free synchronization architecture, combines the tight binding of data and timing and a dynamic compensation mechanism, realizes extremely low cross-process transmission delay and extremely small timing synchronization deviation, greatly improves data transmission throughput, and simultaneously realizes 100% handle reuse rate and zero resource leakage through a global singleton handle manager and a cross-platform resource automatic release mechanism, perfectly adapting to the core requirements of UART bus multi-rate communication simulators and providing efficient, precise, and stable timing synchronization support for serial device simulation.

[0081] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any skilled person in the art can make equivalent replacements or changes to the technical solutions and inventive concepts of the present application within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A method for timing accurate synchronization in a simulator based on shared memory, characterized in that, Comprising the following steps: Constructing a standardized three-layer shared memory layout: the head control area encapsulates the read_ptr read pointer, write_ptr write pointer, and buffer_size buffer capacity with the AtomicUsize atomic type of the Rust language; the ring data area has the same capacity as buffer_size and is accessed cyclically through index modulo; the compact storage unit is the EncodedEntry structure with the #[repr(packed)] modifier, containing 32-bit bit_value data bits, 8-bit status_flag status flags, and 24-bit timing_count timing counts, and a single structure occupies ≤8 bytes; Implementing cross-platform zero-leak resource management based on Rust: define a global singleton SharedMemoryManager using lazy_static!, which internally stores shared memory handles in a Mutex<HashMap<String, Arc>>; provide a get_or_create interface that returns after verifying capacity consistency, or creates a new instance and initializes the header parameters into the HashMap; rely on conditional compilation to release resources through shm_unlink and munmap on Unix systems, and call munmap through the Drop trait on Windows systems, and rely on system mechanisms to recycle handles; Implementing cross-process lock-free data transmission and timing synchronization: the sender encodes the data into the EncodedEntry format, writes it to the ring buffer, and synchronizes the timing_count, and updates the write_ptr using the Release memory order; the receiver reads the read-write pointers using the Acquire memory order, calculates the available data volume, reads the data into the read-side FIFO, and adjusts the timing based on the timing_count, and updates the read_ptr using the Release memory order; Performance verification: FPGA 1ns clock verification timing accuracy, 1GS / s oscilloscope to collect transmission delay; 72-hour full-load running to verify stability.

2. The method for time-accurate synchronization in a shared memory based emulator according to claim 1, wherein, Also included is a timing offset dynamic compensation step, the receiving end extracts the timing_count value from the EncodedEntry data as the sending end clock count, reads the local hardware clock count to calculate the count difference as the local hardware clock count minus the sending end clock count, and through the formula calculates the compensation delay amount, wherein is the final compensation delay amount, is the clock cycle coefficient, is the count difference, is the base compensation threshold, which is preset according to the timing accuracy requirement of the simulator.

3. The method for time-accurate synchronization in a shared memory based emulator according to claim 1, wherein, Also included is a ring buffer status calculation step, where the sender calculates the free space by the formula and the receiver calculates the available data by the formula where is the ring buffer free space, is the total buffer size, i.e. buffer_size, is the current value of write_ptr, is the current value of read_ptr, and is the available data.

4. The method of claim 1, wherein the method is implemented in a shared memory based emulator. It also includes multi-bus protocol adaptation steps: the data to be transmitted is IIC, SPI, or UART bus protocol data; the status_flag field of the EncodedEntry structure defines different identifiers according to the bus type; in IIC bus protocol data, 0x01 represents the start condition, 0x02 represents the stop condition, 0x04 represents the ACK bit, and 0x08 represents the data bit; in SPI bus protocol data, 0x10 represents the chip select signal, 0x20 represents the clock signal, 0x40 represents the MOSI data, and 0x80 represents the MISO data; in UART bus protocol data, 0x01 represents the start bit, 0x02 represents the data bit, 0x04 represents the check bit, and 0x08 represents the stop bit, supporting 5-8-bit data bits and 1-2-bit stop bit configuration.

5. The method for time-accurate synchronization in a shared memory based emulator according to claim 1, wherein, Also includes the sending end of the idle space verification step, the sending end before writing data by atomic operation to read the value of write_ptr and read_ptr, calculate the free space for buffer_size minus the difference between the value of write_ptr and read_ptr, when the free space is not less than the number of bytes occupied by a single EncodedEntry structure, execute the data write operation, write complete by write_ptr.fetch_add the number of bytes occupied by a single EncodedEntry structure, Ordering::Release complete write pointer atomic update.

6. The method for time-accurate synchronization in a shared memory based emulator according to claim 1, wherein, Also includes the receiving end of the decoding and data distribution steps, the receiving end reads the EncodedEntry data first to extract the status_flag value to identify the data type, and then decode the bit_value data to get the original transmission information. If it is IIC bus data, it will be parsed according to the start condition, stop condition, ACK bit, and data bit identification. If it is SPI bus data, it will be reorganized into a data frame according to the chip select signal, clock signal, MOSI data, and MISO data identification. If it is UART bus data, it will be restored to a byte stream according to the start bit, data bit, check bit, and stop bit identification.

7. The method for time-accurate synchronization in a shared memory based emulator according to claim 1, wherein, Also includes the cross-platform shared memory creation refinement step, in Unix and Unix-like operating systems, call the shm_open function to create a named shared memory object, specify the object name, access rights, and creation mode, and then call the mmap function to map the shared memory object to the current process address space; In the Windows operating system, call the CreateFileMapping function to create a file mapping object, specify the mapping file handle, security attributes, file size high and low values, and mapping name, and then call the MapViewOfFile function to map the file mapping object to the current process address space, set the mapping access rights to read and write.

8. The method for time-accurate synchronization in a shared memory based emulator according to claim 1, wherein, Also includes the performance verification refinement step, timing accuracy verification generates a 1ns period standard clock signal through FPGA, synchronously triggers the sending end timing_count count and the receiving end verification logic, collects 10000 groups of sending end timing_count value and receiving end local clock count difference; Transmission delay verification uses a 1GS / s sampling rate high-precision oscilloscope to collect the time difference between the sending end data write completion signal and the receiving end data parsing completion signal; Throughput verification uses 10GB fixed data volume as the test benchmark, and counts the effective data volume transmitted across processes per unit time; Stability verification runs continuously for 72 hours under full load, accumulates transmission data volume not less than 100GB, counts data transmission error rate, and handles reuse success rate after 1000 process restarts.

9. The method for time-accurate synchronization in a shared memory based emulator according to claim 1, wherein, Also includes handle multiplex consistency check step, get_or_create interface query to the cache handle, in addition to check buffer_size and the consistency of the capacity parameter, also check the layout structure version of shared memory, EncodedEntry structure format, three key parameters of atomic operation memory sequence configuration, all consistent, return the cache handle, if any one is inconsistent, it is considered invalid handle and deleted, re-created shared memory instance that meets the current parameter requirements.

10. The method of claim 1, wherein, Also includes simulation scenario expansion adaptation step, based on the extensible characteristics of EncodedEntry structure, add new extension field reserved to store custom extension information; Expand get_or_create interface parameters, add layout configuration parameters and timing accuracy parameters, layout configuration parameters support adjusting the bit allocation of each field of EncodedEntry structure, timing accuracy parameters support setting the mapping ratio of timing_count and hardware clock period, adapt to different precision requirements of simulator scenarios from ns level to μs level, while keeping the core lock-free synchronization mechanism and cross-platform management characteristics unchanged.

Images