Cache management method and device, electronic equipment and storage medium

Abstract

The present disclosure provides a cache management method and device, electronic equipment and storage medium, which relates to the field of chips, and the main technical features include: in response to the received access request, comparing the address information in the access request with the address information stored in the cache group to obtain the hit information of the cache block; wherein the access request at least contains address information and priority information; in the case of hit information being hit, the hit cache block is determined as the selected cache block; in the case of hit information being missed, the priority comparison value is generated by combining the valid state of each cache block in the cache group, the refault prediction value and the first priority state, the replacement cache block is selected based on the priority comparison value, and the replacement cache block is determined as the selected cache block; the second priority state of the selected cache block is updated according to the priority information, and the refault prediction value of each cache block in the cache group is updated based on the updated second priority state.

Description

Technical Field

[0001] This disclosure relates to the field of chips, and more particularly to a cache management method, apparatus, electronic device, and storage medium. Background Technology

[0002] In computer systems, caching serves as an intermediate layer for data access, and its management efficiency directly impacts system performance. To improve cache utilization, various cache replacement algorithms exist, which select replacement cache blocks by prioritizing data and predicting data re-reference intervals, thereby reducing performance losses caused by cache misses.

[0003] However, when dealing with dynamic switching of multi-priority data, existing algorithms may encounter problems such as conflicting predicted values ​​due to changes in priority status, or insufficient adaptability of replacement strategies to different priority data. This makes it difficult to meet the caching needs of data of different priorities in complex access scenarios, resulting in low cache utilization. Summary of the Invention

[0004] This disclosure provides a cache management method, apparatus, electronic device, and storage medium. Its main objective is to address the problems in existing technologies where re-referenced predicted values ​​conflict during dynamic switching of multi-priority data, and where replacement strategies lack adaptability to different priority data, leading to low cache utilization.

[0005] According to a first aspect of this disclosure, a cache management method is provided, comprising:

[0006] In response to a received access request, the address information in the access request is compared with the address information stored in the cache group to obtain cache block hit information; wherein, the access request includes at least the address information and priority information;

[0007] If the hit information indicates a hit, the hit cache block is identified as the selected cache block;

[0008] If the hit information is a miss, a priority comparison value is generated by combining the effective state of each cache block in the cache group, the re-reference prediction value, and the first priority state. A replacement cache block is selected based on the priority comparison value, and the replacement cache block is determined as the selected cache block.

[0009] The second priority state of the selected cache block is updated according to the priority information, and the rereference prediction value of each cache block in the cache group is updated based on the updated second priority state.

[0010] In some embodiments, the step of generating a priority comparison value by combining the effective state of each cache block in the cache group, the re-reference prediction value, and the first priority state, and selecting a replacement cache block based on the priority comparison value, includes:

[0011] The effective state, the rereference prediction value, and the first priority state of each cache block are logically combined to generate the priority comparison value corresponding to each cache block.

[0012] The priority comparison values ​​of each cache block are compared, and the cache block corresponding to the highest priority comparison value is determined as the replacement cache block.

[0013] In some embodiments, the first priority state and the second priority state include multiple priority states, which include at least one of a high priority state, an intermediate priority state, and a normal priority state.

[0014] In some embodiments, logically combining the valid state of each cache block, the rereference prediction value, and the first priority state to generate the priority comparison value corresponding to each cache block includes:

[0015] The valid state of each cache block is inverted and used as the high-order field of the priority comparison value;

[0016] The result of the operation between the rereference prediction value of each cache block and the masking signal is used as the middle bit field of the priority comparison value; wherein, the masking signal is generated based on the first priority state and the valid state;

[0017] The distinguishing identifier generated based on the first priority state of each cache block is used as the low-order field of the priority comparison value; wherein, the distinguishing identifier takes a preset first value when the cache block is in the intermediate priority state, and takes a preset second value when the cache block is in the high priority state or the normal priority state.

[0018] The priority comparison value is obtained by concatenating the high-order field, the middle-order field, and the low-order field in that order.

[0019] In some embodiments, updating the rereference prediction value of each cache block in the cache group based on the updated second priority state includes:

[0020] Based on the updated second priority state and the hit information, determine the updated rereference prediction value of the selected cache block;

[0021] Based on the relationship between the pre-update rereference prediction value and the post-update rereference prediction value of the selected cache block, and the relationship between the pre-update rereference prediction value of each non-selected cache block and the pre-update rereference prediction value of the selected cache block and the post-update rereference prediction value of the selected cache block, the post-update rereference prediction value of each non-selected cache block is determined.

[0022] In some embodiments, the method further includes:

[0023] During cache group initialization, each cache block in the cache group is configured with a different initial rereference prediction value.

[0024] According to a second aspect of this disclosure, a cache management apparatus is provided, comprising:

[0025] A comparison unit is used to, in response to a received access request, compare the address information in the access request with the address information stored in the cache group to obtain cache block hit information; wherein, the access request includes at least the address information and priority information;

[0026] The first determining unit is configured to determine the hit cache block as the selected cache block when the hit information is a hit;

[0027] The selection unit is used to generate a priority comparison value by combining the effective state of each cache block in the cache group, the re-reference prediction value, and the first priority state when the hit information is a miss, and select a replacement cache block based on the priority comparison value.

[0028] The second determining unit is used to determine the replacement cache block as the selected cache block;

[0029] The first update unit is used to update the second priority state of the selected cache block according to the priority information;

[0030] The second update unit is used to update the rereference prediction value of each cache block in the cache group based on the updated second priority state.

[0031] In some embodiments, the selection unit includes:

[0032] The generation module is used to logically combine the valid state, the rereference prediction value and the first priority state of each cache block to generate the priority comparison value corresponding to each cache block.

[0033] The first determining module is used to compare the priority comparison values ​​of each cache block and determine the cache block corresponding to the highest priority comparison value as the replacement cache block.

[0034] In some embodiments, the first priority state and the second priority state include multiple priority states, which include at least one of a high priority state, an intermediate priority state, and a normal priority state.

[0035] In some embodiments, the generation module includes:

[0036] The first determining submodule is used to invert the valid state of each cache block and use it as the high-order field of the priority comparison value;

[0037] The second determining submodule is used to perform a calculation operation between the rereference prediction value of each cache block and the masking signal, and use the result as the middle bit field of the priority comparison value; wherein, the masking signal is generated based on the first priority state and the valid state;

[0038] The third determining submodule is used to use the distinguishing identifier generated based on the first priority state of each cache block as the low-order field of the priority comparison value; wherein, the distinguishing identifier takes a preset first value when the cache block is in the intermediate priority state, and takes a preset second value when the cache block is in the high priority state or the normal priority state.

[0039] The fourth determining submodule is used to concatenate the high-order field, the middle-order field, and the low-order field in that order to obtain the priority comparison value.

[0040] In some embodiments, the second updating unit includes:

[0041] The second determining module is used to determine the updated re-reference prediction value of the selected cache block based on the updated second priority state and the hit information.

[0042] The third determining module is used to determine the updated rereference prediction value of each non-selected cache block based on the relationship between the pre-update rereference prediction value of the selected cache block and the post-update rereference prediction value of the selected cache block, as well as the relationship between the pre-update rereference prediction value of each non-selected cache block and the pre-update rereference prediction value of the selected cache block and the post-update rereference prediction value of the selected cache block.

[0043] In some embodiments, the apparatus further includes:

[0044] A configuration unit is configured to configure different initial rereference prediction values ​​for each cache block in the cache group during the initialization of the cache group.

[0045] According to a third aspect of this disclosure, an electronic device is provided, comprising:

[0046] At least one processor; and

[0047] A memory communicatively connected to the at least one processor; wherein,

[0048] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in the first aspect above.

[0049] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform the method described in the first aspect above.

[0050] According to a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method described in the first aspect above.

[0051] In summary, the cache management method, apparatus, electronic device, and storage medium provided in this disclosure include: responding to a received access request by comparing address information in the access request with address information stored in a cache group to obtain cache block hit information; wherein the access request includes at least the address information and priority information; if the hit information is a hit, determining the hit cache block as a selected cache block; if the hit information is a miss, generating a priority comparison value by combining the valid state, rereference prediction value, and first priority state of each cache block in the cache group, selecting a replacement cache block based on the priority comparison value, and determining the replacement cache block as the selected cache block; updating the second priority state of the selected cache block according to the priority information, and updating the rereference prediction value of each cache block in the cache group based on the updated second priority state. Compared with related technologies, the solution disclosed herein can obtain cache block hit information by responding to access requests and comparing address information; when a hit occurs, the hit cache block is determined as the selected cache block; when a miss occurs, the effective state of each cache block, the re-reference prediction value, and the first priority state are combined to generate a priority comparison value, and the replacement cache block is selected as the selected cache block; the second priority state of the selected cache block is updated according to the priority information of the access request, and the re-reference prediction value of each cache block is updated based on the updated second priority state, thereby realizing dynamic management of cache block priority, improving the accuracy of cache block replacement, and thus improving cache utilization.

[0052] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0053] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0054] Figure 1 This is a flowchart illustrating a cache management method provided in an embodiment of the present disclosure;

[0055] Figure 2 This is a flowchart illustrating another cache management method provided in an embodiment of the present disclosure;

[0056] Figure 3 This is a flowchart illustrating another cache management method provided in an embodiment of the present disclosure;

[0057] Figure 4 This is a schematic diagram illustrating the sorting of cache block priority comparison values ​​provided in an embodiment of the present disclosure;

[0058] Figure 5 This is a flowchart illustrating another cache management method provided in an embodiment of the present disclosure;

[0059] Figure 6 This is a schematic diagram illustrating the state of a selected cache block switching from an intermediate priority state to a normal / high priority state, as provided in an embodiment of this disclosure.

[0060] Figure 7 This is a schematic diagram of bit vector marking and empty space search with virtual prevalues ​​provided in an embodiment of the present disclosure;

[0061] Figure 8 This is a schematic diagram illustrating the state of a selected cache block switching from a normal / high priority state to an intermediate priority state, as provided in an embodiment of this disclosure.

[0062] Figure 9 This is a schematic diagram of bit vector marking and empty space search for a virtual prevalue provided in an embodiment of the present disclosure;

[0063] Figure 10 This is a flowchart illustrating another cache management method provided in an embodiment of the present disclosure;

[0064] Figure 11 This is a schematic diagram of the structure of a cache management device provided in an embodiment of the present disclosure;

[0065] Figure 12 This is a schematic diagram of another cache management device provided in an embodiment of the present disclosure;

[0066] Figure 13 This is a schematic block diagram of an example electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0067] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0068] The cache management method, apparatus, electronic device, and storage medium of this disclosure are described below with reference to the accompanying drawings.

[0069] Figure 1 This is a flowchart illustrating a cache management method provided in an embodiment of the present disclosure.

[0070] like Figure 1 As shown, the method includes steps 101-104.

[0071] Step 101: In response to the received access request, compare the address information in the access request with the address information stored in the cache group to obtain the cache block hit information; wherein, the access request includes at least the address information and priority information.

[0072] In some embodiments, the access request is a read / write request for cached data initiated by, but not limited to, upper-layer software, processors, and other functional modules. Address information is used to locate the target data's storage position in the cache, including but not limited to physical address fragments and logical address indexes. A cache group is a collection of multiple cache blocks with identical structures. Each cache block stores a preset capacity of data and its corresponding address information. Hit information is the result information indicating whether the target data has been stored in the cache group, including both hit and miss cases. The address information in the access request is compared one by one with the address information stored in each cache block in the cache group. If a cache block with completely matching address information exists, the hit information is considered a hit; if the address information of all cache blocks does not match, the hit information is considered a miss.

[0073] The above method can be used to determine whether the target data has been cached in the cache group, providing a basis for judgment for subsequent operations.

[0074] Step 102: If the hit information indicates a hit, the hit cache block is identified as the selected cache block.

[0075] In some embodiments, the selected cache block is a specific cache block that will subsequently undergo priority status updates and rereference prediction value updates. When a hit occurs, the corresponding cache block is locked based on the address comparison result; this cache block is the hit cache block and is directly identified as the selected cache block. Locking a cache block can be implemented in ways including, but not limited to, marking the cache block's index identifier and temporarily blocking other operation requests for that cache block.

[0076] The above method clarifies which selected cache blocks need to be updated in the event of a hit.

[0077] Step 103: If the hit information is a miss, generate a priority comparison value by combining the effective state of each cache block in the cache group, the re-reference prediction value, and the first priority state. Select a replacement cache block based on the priority comparison value and determine the replacement cache block as the selected cache block.

[0078] In some embodiments, the valid state is an identifier representing whether the data stored in the cache block is valid, including two states: valid and invalid. The Reference Prediction Value (RRPV) is a value used to predict the probability that the cache block data will be accessed again later, and its value can be preset according to the cache access characteristics. The first priority state is the priority-related state of each cache block in the cache group, used to distinguish the importance of the cache block data. The priority comparison value is a value used for sorting obtained by combining the valid state, the reference prediction value, and the first priority state. The replacement cache block is the cache block selected to store new data when a cache miss occurs. The combination method includes, but is not limited to, performing logical operations and numerical transformations on each piece of information and then concatenating them to generate a unique priority comparison value. Based on the priority comparison value, the cache blocks that meet the preset rules are selected from the cache group as replacement cache blocks, and then the replacement cache block is determined as the selected cache block.

[0079] Using the above method, a cache block to be replaced can be selected when a cache miss occurs, thus providing space for new data storage.

[0080] Step 104: Update the second priority state of the selected cache block according to the priority information, and update the rereference prediction value of each cache block in the cache group based on the updated second priority state.

[0081] In some embodiments, the second priority state is the priority-related state of the selected cache block after the update. Its update is based on the priority information in the access request; that is, the original priority state of the selected cache block is adjusted according to this priority information to obtain the second priority state. The update of the rereference prediction value is based on the updated second priority state, adjusting the rereference prediction values ​​of all cache blocks in the cache group according to preset update rules. These update rules include, but are not limited to, adjusting specific values ​​according to the numerical range corresponding to the priority state, and correcting prediction values ​​based on state change trends.

[0082] The above method can be used to synchronously update the priority status and rereference prediction value of cache blocks, providing an accurate status reference for cache replacement decisions.

[0083] In summary, the cache management method provided by the embodiments of this disclosure can obtain cache block hit information by responding to access requests and comparing address information; when a hit occurs, the hit cache block is determined as the selected cache block; when a miss occurs, the effective state of each cache block, the re-reference prediction value, and the first priority state are combined to generate a priority comparison value, and a replacement cache block is selected as the selected cache block; the second priority state of the selected cache block is updated according to the priority information of the access request, and the re-reference prediction value of each cache block is updated based on the updated second priority state, thereby realizing dynamic management of cache block priority, improving the accuracy of cache block replacement, and thus improving cache utilization.

[0084] Figure 2 A flowchart illustrating a cache management method provided in an embodiment of this disclosure is further shown. Based on Figure 1 The illustrated embodiment further explains step 103. Figure 2 This may include the following steps:

[0085] Step 201: Logically combine the valid state, the rereference prediction value, and the first priority state of each cache block to generate the priority comparison value corresponding to each cache block.

[0086] In some embodiments, logical combination refers to converting the three types of information—valid state, re-referenced prediction value, and first priority state—into directly comparable numerical forms according to preset rules. The valid state can be represented in binary (e.g., 1 for valid, 0 for invalid); the re-referenced prediction value can be represented as an integer with a preset bit width, the range of which can be set according to actual needs; the first priority state can be encoded to represent different priority categories. The implementation of logical combination includes, but is not limited to: bit-extending the binary value of the valid state and concatenating it with the binary form of the re-referenced prediction value and the encoded value of the first priority state in a preset order to form a multi-bit priority comparison value; or assigning weights to the three types of information and obtaining the priority comparison value through weighted summation. Each cache block generates a unique priority comparison value through the above logical combination process to reflect its replacement priority.

[0087] Step 202: Compare the priority comparison values ​​of each cache block, and determine the cache block corresponding to the highest priority comparison value as the replacement cache block.

[0088] In some embodiments, when comparing the priority comparison values ​​of each cache block, a numerical comparison method is used, that is, the size relationship of the priority comparison values ​​is determined according to integer comparison rules. The cache block with the largest priority comparison value is determined as the replacement cache block, which means that the cache block is determined to be the most suitable object for replacement in the current cache group.

[0089] The above method can transform multi-dimensional cache block status information into quantifiable and comparable values, select replacement cache blocks based on a unified standard, and ensure the consistency and rationality of replacement decisions.

[0090] In some possible implementations of the embodiments of this disclosure, the first priority state and the second priority state include multiple priority states, and the multiple priority states include at least one of a high priority state, an intermediate priority state, and a normal priority state.

[0091] In some embodiments, the first priority state is the priority category of the cache block when participating in the priority comparison value generation, and the second priority state is the priority category of the selected cache block after the priority information is updated. Both include multiple priority states used to distinguish the importance or access characteristics of data. Among them, the high priority state (hardlock) usually corresponds to data that needs to be retained in the cache first. This type of data may have a high access frequency or a significant impact on system performance; the intermediate priority state (softlock) corresponds to data with a medium level of access frequency or importance, and its retention priority is between the high priority state and the normal priority state; the normal priority state (normal) corresponds to data with a low access frequency or relatively low importance, and is more easily replaced when cache space is insufficient.

[0092] Multiple priority states include at least one of high-priority, intermediate-priority, and normal-priority states. In practical applications, some or all of these states can be selected based on cache management needs. For example, if the system only needs to distinguish between core data and general data, it can include only high-priority and normal-priority states; if more granular management is required, all three states can be included simultaneously. The first priority state and the second priority state are consistent in type to ensure the continuity of priority update operations, that is, the priority state of the selected cache block before and after the priority update belongs to one of the preset multiple priority states.

[0093] Priority states are determined based on factors including, but not limited to, data access frequency, data importance level, and application requirements. For example, AI model parameters can be set to a high-priority state, intermediate results that are accessed repeatedly in the short term can be set to a medium-priority state, and streaming data can be set to a normal-priority state.

[0094] Figure 3 A flowchart illustrating a cache management method provided in an embodiment of this disclosure is further shown. Based on Figure 2 The illustrated embodiment further explains step 201. Figure 3 This may include the following steps:

[0095] Step 301: Invert the valid status of each cache block and use it as the high-order field of the priority comparison value.

[0096] In some embodiments, the valid state is represented by a single-bit binary value. Inverting the valid state means performing a logical NOT operation on the original binary value; that is, a valid state of 1 becomes 0 after inversion, and a valid state of 0 becomes 1. The high-order bit is the part with the highest weight in the priority comparison value, and its value directly determines the primary priority of different cache blocks in the replacement sorting. Using the inverted valid state as the high-order bit ensures that invalid cache blocks have a 1 in the high-order bit of the priority comparison value, while valid cache blocks have a 0, guaranteeing that invalid data is selected before valid data in the replacement selection. The bit width of the high-order bit is the same as the bit width of the valid state, typically 1 bit, to distinguish the primary priority.

[0097] Step 302: The result of the operation between the rereference prediction value and the masking signal of each cache block is used as the middle bit field of the priority comparison value; wherein the masking signal is generated based on the first priority state and the valid state.

[0098] In some embodiments, the re-reference prediction value is represented by a 5-bit integer, ranging from -16 to 15, and its value is related to the probability of the data being accessed again later. The mask signal is a binary signal used to control whether the re-reference prediction value participates in priority comparison; it is typically a multi-bit signal with the same bit width as the re-reference prediction value. The mask signal is generated as follows: when the first priority state of the cache block is high priority and the valid state is valid, a mask signal of all 0s is generated; otherwise, a mask signal of all 1s is generated. Operations include, but are not limited to, logical AND operations, i.e., performing a logical AND operation between each bit of the re-reference prediction value and the corresponding bit of the mask signal. A mask signal of all 0s will result in a value of 0, while a mask signal of all 1s will retain the original value of the re-reference prediction value. The middle bit field has the same bit width as the re-reference prediction value, which is 5 bits. Its value is used to further distinguish the replacement priority of the cache block when the high-order bits are the same (i.e., the valid states of the cache blocks are the same).

[0099] Step 303: The distinguishing identifier generated based on the first priority state of each cache block is used as the low-order field of the priority comparison value; wherein, the distinguishing identifier takes a preset first value when the cache block is in the intermediate priority state, and takes a preset second value when the cache block is in the high priority state or the normal priority state.

[0100] In some embodiments, the distinguishing identifier is a single-bit binary value used to further refine the replacement priority. The preset first and second values ​​are different single-bit values ​​(e.g., the first value is 1, and the second value is 0). When generating the distinguishing identifier, the first priority state category of the cache block is identified. If it is a middle priority state, the first value is output; if it is a high priority state or a normal priority state, the second value is output. The low-order bit field is the part with the lowest weight in the priority comparison value, used to finally distinguish cache blocks with different priority states when both the high-order and middle-order bits are the same.

[0101] Step 304: Concatenate the high-order field, the middle-order field, and the low-order field in that order to obtain the priority comparison value.

[0102] In some embodiments, concatenation involves combining the binary values ​​of the three fields sequentially from the most significant bit to the least significant bit to form a complete multi-bit value. For example, when the most significant bit is 1 bit, the middle bit is 5 bits, and the least significant bit is 1 bit, the concatenation results in a 7-bit priority comparison value, where the most significant bit is the value of the most significant bit, the 2nd to 6th bits are the values ​​of the middle bit, and the least significant bit is the value of the least significant bit.

[0103] The splicing process is implemented through bit splicing logic in hardware circuits or bit operations in software, ensuring that the bit order of each field is not disordered, and the generated priority comparison value can accurately reflect the overall replacement priority of the cache block.

[0104] The above method transforms the valid state, the re-referenced predicted value, and the first priority state into a structured multi-bit priority comparison value according to preset rules, thereby achieving the orderly integration of multi-dimensional information and ensuring that there is accurate numerical basis for replacement selection.

[0105] In some possible ways, Figure 4 This is a schematic diagram illustrating the sorting of cache block priority comparison values ​​provided in an embodiment of this disclosure, as shown below. Figure 4 As shown, the vertical axis represents the RRPV comparison value (i.e., the priority comparison value). The upward direction corresponds to the larger the RRPV comparison value, the higher the priority of the cache block being selected as the replacement cache block. Figure 4 Each entry represents a cache block with different state combinations, and the order of the entries is positively correlated with the size of the corresponding priority comparison value.

[0106] Figure 4In the code, "invalid" corresponds to an invalid cache block, and "valid" corresponds to a valid cache block; "RRPV=a" and "RRPV=b" represent different values ​​of the rereference prediction, and b > a; "soft lock" corresponds to an intermediate priority state, "normal" corresponds to a normal priority state, and "hard lock" corresponds to a high priority state.

[0107] Combination Figure 3 The field concatenation logic in the illustrated embodiment is as follows: Figure 4 The sorting rules for the entries are as follows:

[0108] Prioritize sorting based on the highest-order byte (the inverted valid state): when the valid state is invalid, the inverted highest-order byte is 1, and all corresponding entries are placed above those with a valid state of valid (the inverted highest-order byte is 0). Figure 4 Entries starting with "invalid" are placed above entries starting with "valid".

[0109] When the high-order fields are the same, they are sorted according to the middle field (the result of the calculation of the rereferenced predicted value and the shielding signal): Since the shielding signal is all 1s in the invalid state, the rereferenced predicted value retains the original value, and b > a, so the entry with RRPV=b is placed above the entry with RRPV=a. For example, "invalid,RRPV=b,soft lock" is above "invalid,RRPV=a,soft lock".

[0110] When the high-order and middle-order fields are the same, sorting is based on the low-order field (distinguishing identifier): the distinguishing identifier for soft lock is the preset first value, and the distinguishing identifier for normal and hard lock is the preset second value. Therefore, soft lock entries with the same valid status and the same RRPV are placed above normal entries. For example, "invalid,RRPV=b,soft lock" is above "invalid,RRPV=b,normal".

[0111] For entries that are valid and hard-locked: When the valid state is valid, the high-order bits are 0 after inversion; at the same time, the masking signal corresponding to hard lock is all 0. After re-referencing the predicted value and the masking signal, the middle bit is 0. Therefore, the priority comparison value corresponding to this type of entry is the smallest and it is placed at the bottom. For example, "valid,RRPV=a,hard lock" is located at the end of all entries.

[0112] Figure 5 A flowchart illustrating a cache management method provided in an embodiment of this disclosure is further shown. Based on Figure 1 The illustrated embodiment further explains step 104. Figure 5 This may include the following steps:

[0113] Step 401: Determine the updated rereference prediction value of the selected cache block based on the updated second priority state and the hit information.

[0114] In some embodiments, the process of determining the updated rereference prediction value includes: selecting a specific value based on the numerical range corresponding to the updated second priority state and in conjunction with the hit information. When the hit information is a hit, a first preset value is set for the selected cache block; when the hit information is a miss, a second preset value is set for the selected cache block. The specific values ​​of the first and second preset values ​​are configured according to the type of the second priority state, and different priority states may correspond to different sets of preset values. The setting method of the preset value includes, but is not limited to, using a preset mapping table, configuration registers, or through calculation logic. For example, when the second priority state is a normal priority state, the rereference prediction value is set to 0 in the case of a hit and 15 in the case of a miss; when the second priority state is an intermediate priority state, the rereference prediction value is set to -8 in the case of a hit and -1 in the case of a miss. The above is only an illustrative example and is not a limitation on the specific value of the rereference prediction value.

[0115] Step 402: Based on the relationship between the pre-update rereference prediction value of the selected cache block and the post-update rereference prediction value of the selected cache block, and the relationship between the pre-update rereference prediction value of each non-selected cache block and the pre-update rereference prediction value of the selected cache block and the post-update rereference prediction value of the selected cache block, determine the post-update rereference prediction value of each non-selected cache block.

[0116] In some embodiments, the process of determining the updated rereference prediction value for each non-selected cache block includes: comparing the rereference prediction values ​​of the selected cache block before and after the update; when the rereference prediction value before the update is greater than the rereference prediction value after the update, increasing the rereference prediction value by one step for all non-selected cache blocks whose rereference prediction values ​​before the update are between the updated and the rereference prediction values ​​of the selected cache block; when the rereference prediction value before the update is less than the rereference prediction value after the update, decreasing the rereference prediction value by one step for all non-selected cache blocks whose rereference prediction values ​​before the update are between the updated and the rereference prediction values ​​of the selected cache block; and keeping the rereference prediction values ​​of all non-selected cache blocks unchanged when the rereference prediction values ​​before the update are equal to the rereference prediction values ​​after the update. The step size is typically set to 1, but can also be configured to other integer values ​​as needed. This update process ensures that the rereference prediction values ​​of each cache block within the cache group maintain a reasonable distribution.

[0117] By using the above method, based on the state changes of selected cache blocks, the rereference prediction values ​​of all cache blocks in the cache group are systematically adjusted to maintain the dynamic balance of cache state and provide accurate state information for cache management decisions.

[0118] In some implementations, the RRPV (Reference Predicted Value) update strategy is further refined in conjunction with the priority state switching scenario of the selected cache block. The goal is to ensure that different cache blocks with the same priority state have a unique RRPV value, and the update is only related to the priority state bit of the cache block, not the valid bit. Even if the cache block data is invalid, the RRPV will still be updated according to its priority state bit to ensure that the priority comparison value (RRPV comparison value) of each cache block is unique when it is evicted.

[0119] The basic update method for non-selected cache blocks is determined based on the relationship between the RRPV values ​​of the selected cache block before and after the update: When the RRPV value of the selected cache block before the update is greater than the RRPV value after the update, if the RRPV value of the non-selected cache block before the update is between the RRPV value of the selected cache block before the update and the RRPV value before the update, then the RRPV value of the non-selected cache block after the update is increased by 1; otherwise, it remains unchanged. When the RRPV value of the selected cache block before the update is less than the RRPV value after the update, if the RRPV value of the non-selected cache block before the update is between the RRPV value of the selected cache block before the update and the RRPV value after the update, then the RRPV value of the non-selected cache block after the update is decreased by 1; otherwise, it remains unchanged. When the RRPV value of the selected cache block before the update is equal to the RRPV value after the update, the RRPV value of the non-selected cache block remains unchanged.

[0120] During actual updates, priority states include normal (N), high-priority (H), and intermediate-priority (S) states. The RRPV values ​​for normal and high-priority states are within the same range, and they use the same set of update rules.

[0121] When a selected cache block switches from a middle priority state to a normal / high priority state: the updated RRPV value of the selected cache block is `miss dsv`. Here, "dsv" is the default setting value, which varies depending on the scenario: `hit dsv` is the default setting value for a hit in the normal / high priority state, `hit soft lock dsv` is the default setting value for a hit in the middle priority state, `misssoft lock dsv` is the default setting value for a miss in the middle priority state, and `miss dsv` is the default setting value for a miss in the normal / high priority state. Figure 6 Taking the selected path (i.e., cache block) switching state as an example, Figure 6 This is a schematic diagram illustrating the state of a selected cache block switching from an intermediate priority state to a normal / high priority state, as provided in this embodiment. Before accessing the selected path (cache block 10), its priority is intermediate priority (S), and its RRPV value is -2. After access, its priority switches to normal priority (N), and the configured miss dsv is 7, so the RRPV value of the selected path after access is 7. Among the other non-selected cache blocks in normal / high priority states, the RRPV value of cache block 2 before access is 12, which is between the RRPV value before the selected path update (-2) and the updated RRPV value (7), so its RRPV value after access is updated to 13. The RRPV value of cache block 13 before access is 7, which is within this range, so its value after access is updated to 8. The RRPV values ​​of the remaining non-selected cache blocks are adjusted according to the above rules. Other non-selected cache blocks in normal / high priority states need to first pass through a range of 0 to 15. Figure 6 and Figure 7 The above virtual previous value is obtained in the manner shown, where, Figure 6 To select a route and switch its status, Figure 7 This is a schematic diagram of bit vector marking and empty space search with virtual prevalues ​​provided in an embodiment of this disclosure. Figure 7 The vertical axis represents the cache block number, and the horizontal axis represents the RRPV value. Black dots represent currently occupied RRPV values. The RRPV value of each cache block is compared with 0 to 15. The vector corresponding to cache blocks in non-normal / high priority states is all 0. After performing a logical OR operation on all vectors, the first unoccupied RRPV value is searched from 15 to 0. Figure 7The position circled in the middle is the previous virtual value, and then the RRPV value of the non-selected cache block in other intermediate priority states remains unchanged.

[0122] When a selected cache block switches from a normal / high priority state to a middle priority state: If the selected cache block is hit, the updated RRPV value is the default setting corresponding to a hit in the middle priority state (hit softlock dsv); if it is missed, it is the default setting corresponding to a miss in the middle priority state (miss soft lock dsv). Both values ​​range from -16 to -1. Figure 8 Taking the selected route switching state as an example, Figure 8 This is a schematic diagram illustrating the state transition of a selected cache block from a normal / high priority state to an intermediate priority state, provided in an embodiment of this disclosure. Before accessing the selected path (cache block 10), its priority is normal (N), and its RRPV value is 6. After access, its priority switches to an intermediate priority state (S). The configured hit soft lock dsv and miss soft lock dsv are both -10, so the RRPV value of the selected path is -10 after access. For other non-selected cache blocks in the normal / high priority state, if the RRPV value before the update is less than the RRPV value of the selected cache block before the update, it is incremented by 1 (e.g., cache block 0's value is updated from 1 to 2, and cache block 1's value is updated from 5 to 6), otherwise it remains unchanged. For other non-selected cache blocks in the intermediate priority state, they must first pass through the range [hit / miss soft lock dsv, hit / miss soft lock dsv + 15]. Figure 8 and Figure 9 The following method is used to obtain the virtual previous value: Figure 8 To select a route and switch its status, Figure 9 This is a schematic diagram of bit vector marking and empty space search for a virtual prevalue provided in an embodiment of this disclosure. Figure 9 The horizontal axis represents the RRPV value (ranging from hit / miss soft lock dsv to hit / miss soft lock dsv+15), with black dots representing the currently occupied RRPV value. The RRPV value of each cache block is compared to this range. Cache blocks that are not in the middle priority state or are outside this range have a vector of all zeros. After performing a logical OR operation on all vectors, the first unoccupied position is searched as the offset value, and then the hit / miss soft lock dsv is added. Figure 9 The value of -10 is the lower virtual previous value. Figure 9 (Circle the position in the middle), and then update it according to the basic update method based on the virtual previous value.

[0123] When a selected cache block switches from a normal / high priority state to a normal / high priority state: For the selected cache block, if the hit information is a hit, the updated RRPV value is the preset value corresponding to the hit (i.e., hit dsv, always set to 0); if the hit information is a miss, it needs to be determined in conjunction with the valid state: when the selected cache block is invalid, the updated RRPV value is the preset value corresponding to the miss (i.e., miss dsv, which can be configured by software and must be greater than 0); when the selected cache block is valid and the RRPV value before the update is between 0 and miss dsv, the updated RRPV value is its previous RRPV value minus 1; when the selected cache block is valid and the previous RRPV value is 0, this value remains unchanged; in other cases, the updated RRPV value is miss dsv. If the selected cache block switches from a high priority state to a normal priority state and a hit occurs, the updated RRPV value is also set to miss dsv. For other non-selected cache blocks in normal / high priority states, update using the basic update method; for other non-selected cache blocks in intermediate priority states, the RRPV value remains unchanged when a cache hit occurs or the selected cache block is invalid, and the RRPV value is incremented by 1 when a cache miss occurs and the selected cache block is valid. When the software indicates that the accessed data is of streaming type, the miss dsv can be configured to 15 to increase the replacement probability of this type of data; if all cache blocks in the cache group are in a valid high priority state, an error signal will be raised to report allocation failure when normal priority data access fails.

[0124] When a selected cache block switches from an intermediate priority state to an intermediate priority state: the updated RRPV value is the hit soft lock dsv when the selected cache block hits, and the miss soft lock dsv when it misses. The RRPV values ​​of other non-selected cache blocks in normal / high priority states remain unchanged; for other non-selected cache blocks in intermediate priority states, the RRPV value is updated according to the basic update method based on the smaller of the previous virtual value and the previous RRPV value of the selected cache block.

[0125] Figure 10 A flowchart illustrating a cache management method provided in an embodiment of this disclosure is further shown, such as... Figure 10 As shown, the method includes steps 501-505.

[0126] Step 501: When the cache group is initialized, configure different initial rereference prediction values ​​for each cache block in the cache group.

[0127] In some embodiments, cache group initialization refers to the configuration process performed during system startup or when the cache group is first allocated for use. The initial rereference prediction value is configured using a preset allocation algorithm, including but not limited to sequential incrementing allocation, random number generation allocation, or hash calculation allocation based on cache block location. The initial rereference prediction value for each cache block remains distinct within the numerical range corresponding to its respective priority state, ensuring that each cache block has a unique replacement priority benchmark during the initialization phase. For example, for a cache group containing 16 cache blocks, each cache block can be assigned an initial rereference prediction value from 0 to 15, or other non-repeating combinations of values. The configuration process for the initial rereference prediction value can be completed through hardware initialization circuitry or software initialization procedures, and the configuration result is stored in the status register corresponding to the cache block.

[0128] Step 502: In response to the received access request, the address information in the access request is compared with the address information stored in the cache group to obtain the cache block hit information; wherein, the access request includes at least the address information and priority information.

[0129] Step 503: If the hit information indicates a hit, the hit cache block is identified as the selected cache block.

[0130] Step 504: If the hit information is a miss, generate a priority comparison value by combining the effective state of each cache block in the cache group, the re-reference prediction value, and the first priority state. Select a replacement cache block based on the priority comparison value and determine the replacement cache block as the selected cache block.

[0131] Step 505: Update the second priority state of the selected cache block according to the priority information, and update the rereference prediction value of each cache block in the cache group based on the updated second priority state.

[0132] For explanations of steps 502 to 505, please refer to [link / reference needed]. Figure 1 The detailed description of the relevant steps will not be repeated here.

[0133] By using the above method, a unique initial rereference prediction value is configured for each cache block during the cache group initialization phase, avoiding RRPV conflicts in the initial state and providing a consistent and reliable initial state basis for subsequent cache replacement and state update strategies based on RRPV.

[0134] Corresponding to the cache management method described above, this invention also proposes a cache management device. Since the device embodiments of this invention correspond to the method embodiments described above, details not disclosed in the device embodiments can be referred to in the method embodiments described above, and will not be repeated here.

[0135] Figure 11 This is a schematic diagram of the structure of a cache management device provided in an embodiment of the present disclosure, as shown below. Figure 11 As shown, the device includes:

[0136] The comparison unit 61 is configured to, in response to a received access request, compare the address information in the access request with the address information stored in the cache group to obtain cache block hit information; wherein, the access request includes at least the address information and priority information;

[0137] The first determining unit 62 is used to determine the hit cache block as the selected cache block when the hit information is a hit;

[0138] Selection unit 63 is used to generate a priority comparison value by combining the effective state of each cache block in the cache group, the re-reference prediction value and the first priority state when the hit information is a miss, and select a replacement cache block based on the priority comparison value.

[0139] The second determining unit 64 is used to determine the replacement cache block as the selected cache block;

[0140] The first update unit 65 is used to update the second priority state of the selected cache block according to the priority information;

[0141] The second update unit 66 is used to update the rereference prediction value of each cache block in the cache group based on the updated second priority state.

[0142] The cache management device provided in this embodiment can obtain cache block hit information by responding to access requests and comparing address information; when a hit occurs, the hit cache block is determined as the selected cache block; when a miss occurs, the effective state of each cache block, the re-reference prediction value, and the first priority state are combined to generate a priority comparison value, and a replacement cache block is selected as the selected cache block; the second priority state of the selected cache block is updated according to the priority information of the access request, and the re-reference prediction value of each cache block is updated based on the updated second priority state, thereby realizing dynamic management of cache block priority, improving the accuracy of cache block replacement, and thus improving cache utilization.

[0143] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 12 As shown, the selection unit 63 includes:

[0144] The generation module 631 is used to logically combine the valid state, the rereference prediction value and the first priority state of each cache block to generate the priority comparison value corresponding to each cache block.

[0145] The first determining module 632 is used to compare the priority comparison values ​​of each cache block and determine the cache block corresponding to the highest priority comparison value as the replacement cache block.

[0146] Furthermore, in one possible implementation of the present disclosure, the first priority state and the second priority state include multiple priority states, which include at least one of a high priority state, an intermediate priority state, and a normal priority state.

[0147] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 12 As shown, the generation module 631 includes:

[0148] The first determining submodule 6311 is used to invert the valid state of each cache block and use it as the high-order field of the priority comparison value;

[0149] The second determining submodule 6312 is used to use the result of the operation between the rereference prediction value of each cache block and the masking signal as the middle bit field of the priority comparison value; wherein, the masking signal is generated based on the first priority state and the valid state;

[0150] The third determining submodule 6313 is used to use the distinguishing identifier generated based on the first priority state of each cache block as the low-order field of the priority comparison value; wherein, the distinguishing identifier takes a preset first value when the cache block is in the intermediate priority state, and takes a preset second value when the cache block is in the high priority state or the normal priority state.

[0151] The fourth determining submodule 6314 is used to concatenate the high-order field, the middle-order field, and the low-order field in that order to obtain the priority comparison value.

[0152] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 12 As shown, the second update unit 66 includes:

[0153] The second determining module 661 is used to determine the updated re-reference prediction value of the selected cache block based on the updated second priority state and the hit information.

[0154] The third determining module 662 is used to determine the updated rereference prediction value of each non-selected cache block based on the relationship between the pre-update rereference prediction value of the selected cache block and the post-update rereference prediction value of the selected cache block, and the relationship between the pre-update rereference prediction value of each non-selected cache block and the pre-update rereference prediction value of the selected cache block and the post-update rereference prediction value of the selected cache block.

[0155] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 12 As shown, the device further includes:

[0156] Configuration unit 67 is configured to configure different initial rereference prediction values ​​for each cache block in the cache group during the initialization of the cache group.

[0157] It should be noted that the foregoing explanation of the method embodiments also applies to the apparatus of the embodiments of this disclosure, and the principle is the same. Therefore, the embodiments of this disclosure are not limited thereto.

[0158] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0159] Figure 13 A schematic block diagram of an example electronic device 900 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0160] like Figure 13 As shown, the electronic device 900 includes a computing unit 901, which can perform various appropriate actions and processes based on a computer program stored in ROM (Read-Only Memory) 902 or a computer program loaded from storage unit 908 into RAM (Random Access Memory) 903. The RAM 903 can also store various programs and data required for the operation of the electronic device 900. The computing unit 901, ROM 902, and RAM 903 are interconnected via bus 904. An I / O (Input / Output) interface 905 is also connected to bus 904.

[0161] Multiple components in electronic device 900 are connected to I / O interface 905, including: input unit 906, such as keyboard, mouse, etc.; output unit 907, such as various types of displays, speakers, etc.; storage unit 908, such as disk, optical disk, etc.; and communication unit 909, such as network card, modem, wireless transceiver, etc. Communication unit 909 allows electronic device 900 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0162] The computing unit 901 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), various special-purpose AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, DSPs (Digital Signal Processors), and any suitable processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as cache management methods. For example, in some embodiments, the cache management method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 900 via ROM 902 and / or communication unit 909. When the computer program is loaded into RAM 903 and executed by the computing unit 901, one or more steps of the methods described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the aforementioned cache management method by any other suitable means (e.g., by means of firmware).

[0163] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application-Specific Standard Products), SOCs (System-on-Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0164] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0165] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, EPROM (Electrically Programmable Read-Only Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0166] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (Cathode-Ray Tube) or LCD (Liquid Crystal Display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0167] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include LANs (Local Area Networks), WANs (Wide Area Networks), the Internet, and blockchain networks.

[0168] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service system that addresses the shortcomings of traditional physical hosts and VPS (Virtual Private Server) services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0169] It's important to note that artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0170] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0171] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A cache management method, characterized in that, include: In response to a received access request, the address information in the access request is compared with the address information stored in the cache group to obtain cache block hit information; wherein, the access request includes at least the address information and priority information; If the hit information indicates a hit, the hit cache block is identified as the selected cache block; If the hit information is a miss, a priority comparison value is generated by combining the effective state of each cache block in the cache group, the re-reference prediction value, and the first priority state. A replacement cache block is selected based on the priority comparison value, and the replacement cache block is determined as the selected cache block. The second priority state of the selected cache block is updated according to the priority information, and the rereference prediction value of each cache block in the cache group is updated based on the updated second priority state; The step of generating a priority comparison value by combining the effective state, re-reference prediction value, and first priority state of each cache block in the cache group, and selecting a replacement cache block based on the priority comparison value, includes: The effective state, the rereference prediction value, and the first priority state of each cache block are logically combined to generate the priority comparison value corresponding to each cache block. The priority comparison values ​​of each cache block are compared, and the cache block corresponding to the highest priority comparison value is determined as the replacement cache block; The first priority state and the second priority state include multiple priority states, and the multiple priority states include at least one of high priority state, intermediate priority state and normal priority state. The step of logically combining the valid state of each cache block, the rereference prediction value, and the first priority state to generate the priority comparison value corresponding to each cache block includes: The valid state of each cache block is inverted and used as the high-order field of the priority comparison value; The result of the operation between the rereference prediction value of each cache block and the masking signal is used as the middle bit field of the priority comparison value; wherein, the masking signal is generated based on the first priority state and the valid state; The distinguishing identifier generated based on the first priority state of each cache block is used as the low-order field of the priority comparison value; wherein, the distinguishing identifier takes a preset first value when the cache block is in the intermediate priority state, and takes a preset second value when the cache block is in the high priority state or the normal priority state. The priority comparison value is obtained by concatenating the high-order field, the middle-order field, and the low-order field in that order.

2. The method according to claim 1, characterized in that, Updating the rereference prediction value of each cache block in the cache group based on the updated second priority state includes: Based on the updated second priority state and the hit information, determine the updated rereference prediction value of the selected cache block; Based on the relationship between the pre-update rereference prediction value and the post-update rereference prediction value of the selected cache block, and the relationship between the pre-update rereference prediction value of each non-selected cache block and the pre-update rereference prediction value of the selected cache block and the post-update rereference prediction value of the selected cache block, the post-update rereference prediction value of each non-selected cache block is determined.

3. The method according to claim 1, characterized in that, The method further includes: During cache group initialization, each cache block in the cache group is configured with a different initial rereference prediction value.

4. A cache management device, characterized in that, include: A comparison unit is used to, in response to a received access request, compare the address information in the access request with the address information stored in the cache group to obtain cache block hit information; wherein, the access request includes at least the address information and priority information; The first determining unit is configured to determine the hit cache block as the selected cache block when the hit information is a hit; The selection unit is used to generate a priority comparison value by combining the effective state of each cache block in the cache group, the re-reference prediction value, and the first priority state when the hit information is a miss, and select a replacement cache block based on the priority comparison value. The second determining unit is used to determine the replacement cache block as the selected cache block; The first update unit is used to update the second priority state of the selected cache block according to the priority information; The second update unit is used to update the rereference prediction value of each cache block in the cache group based on the updated second priority state; The step of generating a priority comparison value by combining the effective state, re-reference prediction value, and first priority state of each cache block in the cache group, and selecting a replacement cache block based on the priority comparison value, includes: The effective state, the rereference prediction value, and the first priority state of each cache block are logically combined to generate the priority comparison value corresponding to each cache block. The priority comparison values ​​of each cache block are compared, and the cache block corresponding to the highest priority comparison value is determined as the replacement cache block; The first priority state and the second priority state include multiple priority states, and the multiple priority states include at least one of high priority state, intermediate priority state and normal priority state. The step of logically combining the valid state of each cache block, the rereference prediction value, and the first priority state to generate the priority comparison value corresponding to each cache block includes: The valid state of each cache block is inverted and used as the high-order field of the priority comparison value; The result of the operation between the rereference prediction value of each cache block and the masking signal is used as the middle bit field of the priority comparison value; wherein, the masking signal is generated based on the first priority state and the valid state; The distinguishing identifier generated based on the first priority state of each cache block is used as the low-order field of the priority comparison value; wherein, the distinguishing identifier takes a preset first value when the cache block is in the intermediate priority state, and takes a preset second value when the cache block is in the high priority state or the normal priority state. The priority comparison value is obtained by concatenating the high-order field, the middle-order field, and the low-order field in that order.

5. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-3.

6. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-3.

7. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the method as described in any one of claims 1-3.

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