Display panel and driving method of display panel

Abstract

The invention discloses a display panel and a driving method of the display panel, the display panel comprises a plurality of rows of pixels, a gate driver and a discharge module, the gate driver is electrically connected with the plurality of rows of pixels, the driver is used for supplying power to each row of pixels in a unit period so that each row of pixels can present a target picture in a first time period, and the discharge module is used for discharging the target picture. The unit period comprises a first time period and a second time period; the discharging module is electrically connected with the multiple rows of pixels, and the discharging module is used for discharging each row of pixels which present the target picture in the first time period in the second time period so as to present a black frame insertion picture. Within the display time of one frame of picture, when power is supplied to the (N + 1) th row of pixels to the last row of pixels in the second time period, the pixels of the target picture displayed in the first time period, namely the pixels from the first row to the Nth row, are discharged through the discharging module, so that the display can realize black insertion while keeping the original refresh rate and complete resolution, and the display efficiency is improved. Therefore, the smear problem is effectively solved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a driving method for the display panel. Background Technology

[0002] Liquid crystal displays (LCDs) suffer from ghosting issues when displaying dynamic images because their operating principle differs from that of cathode ray tubes (CRTs). This is because liquid crystal molecules require time to align, causing a residue of the previous frame's image to remain between frames. Existing solutions involve inserting a black frame between two frames or controlling the backlight's on / off timing to achieve black insertion. However, the former affects the display's true refresh rate, and the latter is complex and costly; neither effectively solves the ghosting problem in dynamic displays. Summary of the Invention

[0003] This application provides a display panel and a driving method for the display panel that can effectively solve the ghosting problem.

[0004] In a first aspect, the display panel provided in this application includes: a multi-row pixel; a gate driver, the gate driver and the multi-row pixel are electrically connected, the gate driver is used to supply power to a target row pixel in the multi-row pixel in a unit cycle to present a target image in a first time period, the unit cycle including a first time period and a second time period; a discharge module, the discharge module and the multi-row pixel are electrically connected, the discharge module is used to discharge to the target row pixel in the second time period to present a black-and-white image.

[0005] In some feasible implementations, the display panel also includes a controller, which is electrically connected to the discharge module. The controller is used to control the discharge module to discharge the target row pixels in a second time period.

[0006] In some feasible implementations, the display panel also includes a reference voltage terminal, the discharge module includes a first switching transistor, the gate of the first switching transistor is electrically connected to the controller, the drain of the first switching transistor is electrically connected to the reference voltage terminal, the source of the first switching transistor is electrically connected to each row of pixels, and the controller is used to control the connection between the source and drain of the first switching transistor to discharge the target row of pixels.

[0007] In some feasible implementations, the display panel also includes multiple gate lines, each gate line being connected to the gate of a row of pixels. The discharge module also includes multiple second switching transistors, each second switching transistor being connected in series between a pixel and the source of a first switching transistor. Among the multiple second switching transistors, the gate of the second switching transistor connected to the current row of pixels is connected to the gate line of the current row.

[0008] In some feasible implementations, the display panel also includes an isolation module and a multi-row pixel electrical connection, the isolation module being used to isolate the current row of pixels to be powered from the previous row of pixels that have been powered.

[0009] In some feasible implementations, the display panel includes multiple data lines and multiple gate lines, multiple rows of pixels are arranged in columns, each data line is connected to the source of a column of pixels, and each gate line is connected to the gate of a row of pixels. The isolation module includes multiple third switching transistors, each third switching transistor is connected in series between the source of a pixel and its corresponding data line; among the multiple third switching transistors, the gate of the third switching transistor connected to the current row of pixels is electrically connected to the gate line of the next row.

[0010] Secondly, this application provides a driving method for a display panel, the display panel including multiple rows of pixels, a gate driver, and a discharge module, the driving method including: Within a unit cycle, power is sequentially supplied to the target row pixels in multiple rows of pixels to present the target image within a first time period. The unit cycle includes a first time period and a second time period. Discharge is applied to the target row pixels during the second time period to create a black-out image.

[0011] In some feasible implementations, the display panel also includes multiple gate lines, each gate line being connected to the gate of a row of pixels. The discharge module also includes multiple second switching transistors, each second switching transistor being connected in series between the corresponding pixel and the source of the first switching transistor. Among the multiple second switching transistors, the gate of the second switching transistor connected to the current row of pixels is connected to the gate line of the current row. Discharging the target row pixels in the second time period to present a black-insertion image includes: Obtain the number of pixel rows N of the target row pixels, where N is a preset positive integer; The gate lines corresponding to the first row of pixels to the Nth row of pixels are driven sequentially, and the second switching transistors corresponding to the first row of pixels to the Nth row of pixels are activated sequentially to turn on the first row of pixels to the Nth row of pixels and the reference voltage terminal for discharge.

[0012] In some feasible implementations, the display panel further includes an isolation module and multiple data lines. Multiple rows of pixels are arranged in columns, and each data line is connected to the source of a column of pixels. The isolation module includes a first switching transistor and multiple third switching transistors, each third switching transistor connected in series between a pixel and its corresponding data line. Among the multiple third switching transistors, the gate of the third switching transistor connected to the current row of pixels is electrically connected to the gate line of the next row. The driving method further includes: Drive the gate line where the K+1 row pixel is located, and turn off the third switching transistor corresponding to the K row pixel to isolate the K row pixel that has been powered on and the K+1 row pixel that is about to be powered on, where 1≤K≤N.

[0013] In some feasible implementations, the display panel also includes a controller, which is electrically connected to a gate driver. While the target row pixels are being discharged during the second time period, the driving method also includes: The gate driver controls the power supply to the N+1th row of pixels to the last row of pixels.

[0014] Within a unit cycle, the gate driver scans downwards from the first row of pixels, sequentially powering the pixels from the first row to the last row to display the target image. After powering the first to Nth rows of pixels in the first time period, these pixels display the target image in the first time period. In the second time period, the discharge module discharges the pixels from the first to Nth rows that displayed the target image in the first time period, i.e., the pixels that have completed charging, causing these pixels to display black bars, thus eliminating the ghosting problem on the display screen. Simultaneously, the gate driver continues to charge the pixels from the (N+1)th row to the last row. During the display time of one frame, while powering the pixels from the (N+1)th row to the last row in the second time period, the discharge module discharges the pixels that displayed the target image in the first time period, i.e., the first to Nth rows of pixels, allowing the display to achieve black bar insertion while maintaining the original refresh rate and full resolution. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0016] Figure 1 A schematic diagram of the pixel architecture of an existing display panel; Figure 2 A schematic diagram of the pixel architecture of the display panel provided in this application; Figure 3 This is a schematic diagram showing the location of parasitic capacitors in the display panel; Figure 4 A schematic diagram of another display panel provided for this application; Figure 5 A flowchart of the driving method for the display panel provided in this application; Figure 6 for Figure 2 The diagram shows the changes to the display panel. Figure 7 for Figure 2 The timing diagram of each signal in the display panel is shown.

[0017] Attached image captions: 1000 - Display panel, 100 - Pixel, 200 - Gate driver, 300 - Discharge module, 310 - First switching transistor, 320 - Second switching transistor, 400 - Isolation module, 410 - Third switching transistor, 500 - Controller, 600 - Reference voltage terminal, 700 - Parasitic capacitance. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0019] Please see Figure 1 , Figure 1 The diagram illustrates the pixel architecture of a conventional display panel. This panel includes multiple pixel units, each containing a pixel electrode and a transistor. The transistor's source is connected to a data line, its gate to a gate line, and its drain to the pixel electrode. The other end of the pixel electrode is connected to a common voltage terminal (VCM). The data line transmits voltage signals to control the pixel's brightness or color. The gate line transmits scan signals, controlling the transistor's on / off state to control the voltage signals transmitted by the data line and their writing to the pixel. Existing solutions to motion blur in displays typically involve inserting black frames between two frames or controlling backlight timing. However, inserting black frames affects the display panel's actual refresh rate, while controlling backlight timing is complex, costly, and impractical. Therefore, this application provides a highly applicable display panel and its driving method that effectively solves the motion blur problem. Please see Figure 2 The display panel 1000 provided in this application includes multiple rows of pixels 100, a gate driver 200, and a discharge module 300. The gate driver 200 is electrically connected to the multiple rows of pixels 100. The gate driver 200 is used to supply power to a target row of pixels in the multiple rows of pixels 100 in a unit cycle to present a target image in a first time period. The unit cycle includes a first time period and a second time period. The discharge module 300 is electrically connected to the multiple rows of pixels 100. The discharge module 300 is used to discharge the target row of pixels 100 in the second time period to present a black-and-white image.

[0020] A unit period refers to the display time of one frame. Within a unit period, the target row pixels are the pixels in rows 1 to N, where N is a variable positive integer, dynamically set by the parameters of the display panel 1000 and the user. The gate driver 200 scans downwards starting from the first row of pixels 100, sequentially powering the first row of pixels 100 to the Nth row of pixels 100 to display the target image.

[0021] After powering the first row of pixels 100 to the Nth row of pixels 100 is completed in the first time period, the first row of pixels 100 to the Nth row of pixels 100 presents the target image in the first time period. In the second time period, the discharge module 300 discharges the target row of pixels 100, that is, the first row of pixels 100 to the Nth row of pixels 100 that have completed charging, so that this part of the image appears as a black-and-white image. At the same time, the gate driver 200 continues to charge the N+1th row of pixels 100 to the last row of pixels 100. After all rows of pixels 100 have completed charging or discharging, the entire frame image (the first half is a black-and-white image, and the second half is the target image) will be maintained for a period of time until the next frame image begins.

[0022] During the display time of one frame, while power is supplied to pixels 100 in the (N+1)th row to the last row of pixels 100 in the second time period, the discharge module 300 discharges pixels 100 of the target image displayed in the first time period, i.e., pixels 100 in the first row to the Nth row of pixels 100. This allows the monitor to achieve black insertion while maintaining the original refresh rate and full resolution, effectively solving the ghosting problem. By controlling the ratio of the first time period to the unit cycle, the proportion of black displayed can be controlled, thereby achieving dynamic black insertion and achieving the optimal balance between image quality, clarity, and power consumption.

[0023] For further details, please see Figure 2 The display panel 1000 also includes a controller 500, which is electrically connected to the discharge module 300. The controller 500 is used to control the discharge module 300 to discharge each row of pixels 100 in a second time period. The controller 500 is a timing controller 500 or a microcontroller 500 within the display panel 1000.

[0024] The controller 500 first receives the preset black insertion ratio in the system or the black insertion ratio input by the user, and internally converts this black insertion ratio into a specific black insertion segmentation line N. For example, for a 1080-line display panel 1000, to achieve a 30% black insertion ratio, N = 324 is set, then the pixels from row 1 (100) to row 324 (100) are black, and the pixels from row 325 (100) to row 1080 (100) are displayed normally; to achieve a 75% black insertion ratio, N = 810 is set, then the pixels from row 1 (100) to row 810 (100) are black, and the pixels from row 811 (100) to row 1080 (100) are displayed normally; to achieve a 0% black insertion ratio, i.e., normal mode, N = 0 is set, in which case all lines are charged normally throughout the entire frame period.

[0025] The controller 500 controls the output of control signals to the gate driver 200 and the discharge module 300 based on the N-value. This controls the gate driver 200 to supply power to pixels 100 in the first row to the Nth row in a first time period, and controls the discharge module 300 to discharge pixels 100 in the first row to the Nth row in a second time period. Simultaneously, the controller 500 continues to supply power to pixels 100 in the (N+1)th row to the last row. This ensures that the discharge module 300 can synchronize with the scanning of the gate driver 200, precisely discharging pixels 100 in the first row to the Nth row line by line.

[0026] Since the controller 500 receives instructions and recalculates the N value frame by frame, this means that the black insertion ratio can change in real time. For example, for the first frame: the controller 500 receives an instruction for a black insertion ratio of 30%, sets N=324, and executes 30% black insertion; for the second frame: the scene changes to an intense game scene, the controller 500 receives an instruction for a black insertion ratio of 70%, immediately sets N=756, and executes 70% black insertion in the second frame.

[0027] In some feasible implementations, the controller 500 can analyze the target screen to be displayed in real time, determine whether the screen is static or dynamic, and automatically generate the interpolation ratio instruction. Users do not need to manually switch modes, and the monitor can provide itself with the best clarity and power consumption performance, which improves the intelligence of the display panel 1000 and the display system, and can also more effectively improve the ghosting problem.

[0028] Please see Figure 2 The display panel 1000 also includes a reference voltage terminal 600, and the discharge module 300 includes a first switching transistor 310. The gate of the first switching transistor 310 is electrically connected to the controller 500, the drain of the first switching transistor 310 is electrically connected to the reference voltage terminal 600, and the source of the first switching transistor 310 is electrically connected to each row of pixels 100. The controller 500 is used to control the source and drain of the first switching transistor 310 to connect so that the target row of pixels 100 discharges.

[0029] The gate of the first switching transistor 310 is connected to the controller 500 to receive control signals from the controller 500; the drain of the first switching transistor 310 is connected to the reference voltage terminal 600, which is either a common voltage terminal or ground; the source of the first switching transistor 310 is electrically connected to each row of pixels 100. When the control signal output by the controller 500 turns on the first switching transistor 310, the electrode voltage of each row of pixels 100 is equal to the reference voltage, the liquid crystal molecules do not deflect, and the liquid crystal appears black, thus achieving discharge.

[0030] Please see Figure 2The display panel 1000 also includes multiple gate lines, each gate line being connected to the gate of a row of pixels 100. The discharge module 300 also includes multiple second switching transistors 320, each second switching transistor 320 being connected in series between a pixel 100 and the source of a first switching transistor 310. Among the multiple second switching transistors 320, the gate of the second switching transistor 320 connected to the current row of pixels is connected to the gate line of the current row. It should be noted that the gate line and the gate of the pixel 100 mentioned in this application refer to the gate line and the gate of the transistor in the pixel unit.

[0031] Each pixel 100 corresponds to a second switching transistor 320. The gate of the second switching transistor 320 is connected to the gate line of the pixel 100, that is, the gate of the second switching transistor 320 corresponding to the Kth row of pixels 100 is connected to the gate line of the Kth row of pixels 100. The second switching transistor 320 is used to turn on the Kth row of pixels 100 and the first switching transistor 310. The gate of the first switching transistor 310 is connected to the controller 500 and is used to turn on the Kth row of pixels 100 and the reference voltage terminal 600 according to the control signal of the controller 500, so that the voltage of the pixel 100 located in the Kth row is equal to the voltage of the reference voltage terminal 600, thereby realizing discharge.

[0032] For example, in the first time period of a unit cycle, the controller 500 outputs a low level to the gate of the first switching transistor 310. At this time, the first switching transistor 310 is in the off state, the discharge path is cut off, and the gate driver 200 normally scans the first row of pixels 100 to the Nth row of pixels 100, supplying power to the first row of pixels 100 to the Nth row of pixels 100. In the second time period, the controller 500 outputs a high level to the gate of the first switching transistor 310, the first switching transistor 310 is turned on, and the gate driver 200, under the command of the controller 500, restarts scanning the signal from the first row. When the gate line of the first row of pixels 100 is turned on: the second switching transistors 320 of all pixels 100 in the first row are turned on, the pixels 100 in the first row are connected at the reference voltage terminal 600, the charge is released, the discharge is completed, and black insertion is achieved. When the gate line of the second row is turned on: the second switching transistor 320 of the first row is turned off, the discharge stops. The second switching transistor 320 of the second row is turned on, and the second row begins to discharge. ...and so on, until the Nth row is discharged.

[0033] The discharge operation of the discharge module 300 is completely synchronized with the scan signal of the gate driver 200. The start, end, and duration of the discharge are precisely controlled by the gate pulse, with accuracy down to the line scan cycle level. This ensures the discharge speed of the discharge module 300, thereby effectively eliminating the problems of ghosting or uneven discharge in some areas of the display panel 1000. When a row of pixels 100 is discharging, the second switching transistors 320 of all other rows are in the off state, and their discharge paths are physically completely disconnected. This prevents the drastic voltage changes of the pixels 100 undergoing black insertion from coupling to other rows that are charging or holding through the discharge path, completely eliminating crosstalk and ensuring the purity of the latter half of a frame.

[0034] Please see Figure 2 The display panel 1000 also includes an isolation module 400, which is electrically connected to the multi-row pixels 100. The isolation module 400 is used to isolate the current row pixels 100 that are about to be powered from the previous row pixels 100 that have already been powered. Please refer to [link to relevant documentation]. Figure 3 A parasitic capacitance 700 exists between pixel 100 and its corresponding data line, causing the pixel 100 electrode to be coupled by changes in the data voltage of the data line. The isolation module 400 can be multiple isolation switching transistors connected in series between the parasitic capacitance 700 and the data line, or it can be a row-level switching transistor located at the end of each data line, or it can be a row-level switching transistor connected to a common data line of an entire row of pixels 100. The isolation module 400 isolates the current row of pixels 100 about to be powered from the previous row of pixels 100 that has already been powered, preventing the drastic voltage changes during row-by-row discharge from the first row of pixels 100 to the Nth row of pixels 100 from affecting the N+1th row of pixels 100 to the last row of pixels 100. Even without black bar insertion, the isolation module 400 can isolate the Kth row of pixels 100 from the data line after the Kth row is fully charged. This eliminates the interference of voltage changes on the data line to the charged pixels 100, i.e., the data line coupling problem, improving the purity of the static image.

[0035] Please see Figure 4The display panel 1000 includes multiple data lines and multiple gate lines. Multiple rows of pixels 100 are arranged in columns. Each data line is connected to the source of a column of pixels 100, and each gate line is connected to the gate of a row of pixels 100. The isolation module 400 includes multiple third switching transistors 410. Each third switching transistor 410 is connected in series between the source of a pixel 100 and its corresponding data line. Among the multiple third switching transistors 410, the gate of the third switching transistor 410 connected to the current row of pixels is electrically connected to the gate line of the next row. It should be noted that the connection between the data line and the source of the pixel mentioned in this application refers to the connection between the data line and the source of the transistor in the pixel unit. The connection between the gate line and the gate of the pixel refers to the connection between the gate line and the gate of the transistor in the pixel unit.

[0036] For example, when the gate driver 200 supplies power to the first row of pixels 100, the gate line where the first row of pixels 100 is located is turned on. The signals of the third switching transistor 410 corresponding to the first row of pixels 100 and the third switching transistor 410 corresponding to the second row of pixels 100 are opposite to the signals of the second row of gate lines and the third row of pixels 100. At this time, the row turn-on signals of the second row of gate lines and subsequent rows are all low. Therefore, the transistors at the positions of the first column of data lines whose signals are from the third switching transistor 410 corresponding to the first row of pixels 100, the third switching transistor 410 corresponding to the second row of pixels 100, and the third switching transistor 410 corresponding to the third row of pixels 100 are all turned on, and the first row of gate lines is supplied with power. When the charging of this row is completed, the signal of the first row gate line is pulled low, and this row is turned off. The transistor on the second row gate line is turned on to charge the electrode of pixel 100 in this row. The third switching transistor 410 corresponding to pixel 100 in the first row is turned off. However, at this time, because the gate signals of other rows are all at a low level, the data lines to the second row gate line are all open and can charge normally. When the second row of pixels 100 is fully charged, the third row of pixels 100 begins to charge. At this time, the third switching transistor 410 corresponding to pixel 100 in the first row is turned on, and the third switching transistor 410 corresponding to pixel 100 in the second row is turned off, which can isolate the unpowered rows of pixels 100 from the powered rows of pixels 100.

[0037] During dynamic black insertion, when scanning reaches line N+1, the isolation module 400 ensures that pixels 100 from line 1 to line N are disconnected from the data line. This allows for complete electrical isolation between discharging pixels 100 from line 1 to line N and supplying power to pixels 100 from line N+1 to the last line, preventing interference. Even in normal mode without black insertion, when line K is fully charged, the isolation module 400 will disconnect pixels 100 in line K from the data line during line K+1 scanning. This eliminates interference from voltage changes on the data line to the charged pixels 100, thus resolving the data line coupling problem.

[0038] Please see Figure 5 This application provides a driving method for a display panel 1000, the driving method including: S101 supplies power to the target row pixels in the multi-row pixels within a unit cycle to present the target image within a first time period, the unit cycle including the first time period and the second time period.

[0039] The gate driver 200 scans line by line, starting from the first row of pixels 100 and ending at the last row of pixels 100, supplying power to only one row of pixels 100 at a time. At the instant the gate line of each row of pixels 100 is turned on, the source driver precisely sends a voltage signal representing the image content of that row to that row of pixels 100 via a data line. After powering the target row of pixels is completed, i.e., after powering the first row of pixels 100 to the Nth row of pixels 100 is completed, the target image is displayed within a first time period.

[0040] S102, discharges the target row pixels in the second time period to present a black-and-white image.

[0041] After step S101 is completed, the controller 500 activates the discharge module 300 to discharge the target row pixels that have been powered during the first time period, namely the first row pixels 100 to the Nth row pixels 100, so that the screen displays a black-and-white image during the second time period. At the same time, the gate driver 200 continues to power the N+1th row pixels 100 to the last row pixels 100 during the second time period.

[0042] Please see Figure 6 The gate driver 200 scans and supplies power to multiple rows of pixels 100 from top to bottom. First, during a first time period, it supplies power to rows 100 through N rows of pixels 100 sequentially. After supplying power to the Nth row of pixels 100, the discharge module 300 discharges power to rows 100 through N rows of pixels 100 sequentially, without affecting the gate driver 200's supply of power to rows 100 through the last row of pixels 100. Thus, while other rows of pixels 100 are being supplied power, the pixels 100 that have already been supplied are being discharged from top to bottom. This is equivalent to the display panel 1000 displaying the target image for part of the time and displaying a black-and-white image for part of the time within the display frame's display time; through the superposition of these time intervals, the black-and-white image is inserted.

[0043] The loop of steps S101 and S102 is equivalent to adding a black screen with a variable time percentage within the display cycle of one frame. This black screen resets the persistence of vision of the human eye, making each frame as clear as an independent photograph. The final synthesized dynamic image is smooth, thus eliminating the ghosting problem of the display panel 1000. The discharge operation of the discharge module 300 also clears the residual charge accumulated in the capacitor of the pixel 100 due to transistor leakage or data coupling, effectively preventing the target image of the previous frame from interfering with the target image of the next frame, ensuring the purity and fidelity of the image, especially when displaying high-contrast switching content.

[0044] Discharging the target row pixel 100 in the second time period to present a black-and-white image includes: determining the number N of the number of rows of pixels 100 to be presented in the first time period, where N is a preset positive integer; sequentially driving the gate lines corresponding to the first row pixel 100 to the Nth row pixel 100, and sequentially activating each of the second switching transistors 320 corresponding to the first row pixel 100 to the Nth row pixel 100, thereby sequentially turning on the first row pixel 100 to the Nth row pixel 100 and the reference voltage terminal 600.

[0045] The number N of 100 pixels can be dynamically calculated by the controller 500 based on the target image to be displayed, or it can be input by the user. By controlling the value of N, the black-and-white interpolation ratio of a frame can be controlled. After the gate driver 200 finishes powering the Nth row of pixels 100, under the command of the controller 500, the gate driver 200 rescans from the first row of pixels 100 to the Nth row of pixels 100, and redrives the gate lines corresponding to the first row of pixels 100 to the Nth row of pixels 100. When the gate line of the Kth row is driven, the second switching transistors 320 of all pixels 100 in that row are synchronously turned on, all pixels 100 in that row are connected to the reference voltage terminal 600, the charge of the pixels 100 is quickly released, the discharge is completed, and the pixels 100 in that row appear black.

[0046] For example, please see Figure 7Taking a display panel 1000 with 1080 rows of pixels 100 as an example, when the black insertion ratio is selected as 50%, that is, after powering on 540 rows of pixels 100, the first row of pixels 100 to the 540th row of pixels 100 are discharged. When the 541st row is turned on, the controller 500 sends a frame start signal to the gate driver 200 to rescan the first row of pixels 100. Since the 541st row of pixels 100 is turned on at this time, the third switching transistor 410 between the 541st row of pixels 100 and the 540th row of pixels 100 is in the off state. Therefore, the data lines of the first row of pixels 100 and the 540th row of pixels 100 are isolated from the data lines of the 541st row of pixels 100 to the 1080th row of pixels 100. After the first row of pixels 100 is reopened, the actions of the first row of pixels 100 and the 540th row of pixels 100 do not affect the power supply to the 541st to 1080th rows of pixels 100.

[0047] While the discharge module 300 reopens the first row of pixels 100, the controller 500 sends a high-level control signal to the first switching transistor 310, turning it on and turning off the remaining second switching transistors 320. The first switching transistor 310 is connected to the reference voltage terminal 600, pulling the data voltage of the first row of pixels 100 to the reference voltage level. Since there is no voltage difference between the pixel 100 voltage and the reference voltage at this time, the charge in the pixel 100 is released, completing the black insertion. After the black insertion of the first row of pixels 100 is completed, the black insertion of the second row of pixels 100 can be performed. At this time, the gate line of the second row of pixels 100 is turned on, the second switching transistor 320 corresponding to the second row of pixels 100 is turned on, and the second switching transistor 320 corresponding to the third row of pixels 100 is turned off. At this time, the data voltage of the second row of pixels 100 can be pulled to the reference voltage level, completing the black insertion. This process is repeated to complete the black insertion of the entire display.

[0048] By changing the N value, black insertion ratios from 0% to 100% can be achieved. The system can smoothly adjust the black insertion ratio in real time according to the movement speed of the content on the screen, finding a perfect dynamic balance between sharpness and brightness / power consumption. The process of discharging pixels 100 in the first row to the Nth row of pixels 100 completely overlaps with the process of powering pixels 100 in the N+1th row to the last row of pixels 100 in time. This means that a high black insertion ratio can be achieved without sacrificing the refresh rate, ensuring the smoothness and sharpness of the display.

[0049] The driving method further includes: driving the gate line of the (K+1)th row pixel 100 and turning off the third switching transistor 410 corresponding to the Kth row pixel 100 to isolate the Kth row pixel 100 that has been powered on and the (K+1)th row pixel 100 that is about to be powered on, where 1≤K≤N. During the process of the gate driver 200 powering multiple rows of pixels 100 row by row, when the power supply operation of the Kth row pixel 100 is completed and the power supply to the (K+1)th row pixel 100 is about to be powered on, the gate driver 200 outputs a high level to the gate line of the (K+1)th row pixel 100. Simultaneously, this high-level signal is also sent to the gate of the third switching transistor 410 corresponding to all pixels 100 in the Kth row, forcibly turning it off. This isolates the Kth row pixel 100 and the (K+1)th row pixel 100, ensuring that the stable state of the Kth row pixel 100 is not affected by any voltage changes occurring on the data line of the (K+1)th row pixel 100. This avoids the problem that the high-brightness voltage of row K+1 will couple to row K through the data line, interfering with its discharge process, causing incomplete black insertion, and resulting in bright spots or ghosting on the display screen.

[0050] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0051] Furthermore, the use of terms such as "first," "second," etc., in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0052] In this application, unless otherwise expressly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0053] Furthermore, the technical solutions of the various embodiments of this application can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this application.

[0054] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized by, The display panel comprises: a plurality of rows of pixels; a gate driver electrically connected with the plurality of rows of pixels, the gate driver being configured to supply power to target rows of pixels in the plurality of rows of pixels in a unit cycle to display a target picture in a first time period, the unit cycle comprising the first time period and a second time period; a discharging module electrically connected with the plurality of rows of pixels, the discharging module being configured to discharge the target rows of pixels in the second time period to display a black insertion picture.

2. The display panel of claim 1, wherein, The display panel further comprises a controller electrically connected with the discharging module, the controller being configured to control the discharging module to discharge the target rows of pixels in the second time period.

3. The display panel of claim 2, wherein, The display panel further comprises a reference voltage terminal, the discharging module comprises a first switch transistor, a gate of the first switch transistor being electrically connected with the controller, a drain of the first switch transistor being electrically connected with the reference voltage terminal, a source of the first switch transistor being electrically connected with the rows of pixels, and the controller being configured to control the source and the drain of the first switch transistor to be in communication to discharge the target rows of pixels.

4. The display panel of claim 3, wherein, The display panel further comprises a plurality of gate lines, each of the gate lines being connected with a gate of a row of pixels, and the discharging module further comprises a plurality of second switch transistors, each of the second switch transistors being connected in series between a pixel and the source of the first switch transistor, and a gate of a second switch transistor connected with a current row of pixels being electrically connected with a current gate line.

5. The display panel of claim 2, wherein, The display panel further comprises an isolation module electrically connected with the plurality of rows of pixels, the isolation module being configured to isolate a current row of pixels to be supplied with power from a previous row of pixels that has completed power supply.

6. The display panel of claim 5, wherein, The display panel comprises a plurality of data lines and a plurality of gate lines, the plurality of rows of pixels are arranged in columns, each of the data lines being connected with a source of a column of pixels, each of the gate lines being connected with a gate of a row of pixels, the isolation module comprises a plurality of third switch transistors, each of the third switch transistors being connected in series between a source of a pixel and a data line corresponding to the pixel, and a gate of a third switch transistor connected with a current row of pixels being electrically connected with a next gate line.

7. A driving method of a display panel, characterized by, The display panel comprises a plurality of rows of pixels, a gate driver and a discharging module, and the driving method comprises: supplying power to target rows of pixels in the plurality of rows of pixels in a unit cycle to display a target picture in a first time period, the unit cycle comprising the first time period and a second time period; discharging the target rows of pixels in the second time period to display a black insertion picture.

8. The driving method of claim 7, wherein, The display panel further comprises a plurality of gate lines, each of the gate lines being connected with a gate of a row of pixels, and the discharging module comprises a first switch transistor and a plurality of second switch transistors, each of the second switch transistors being connected in series between a corresponding pixel and a source of the first switch transistor, and a gate of a second switch transistor connected with a current row of pixels being electrically connected with a current gate line. The discharging the target rows of pixels in the second time period to display a black insertion picture comprises: obtaining a number N of pixel rows in the target rows of pixels, N being a preset positive integer; The gate lines corresponding to the first row of pixels to the Nth row of pixels are sequentially driven, and the second switch transistors corresponding to the first row of pixels to the Nth row of pixels are sequentially activated to sequentially conduct the first row of pixels to the Nth row of pixels and the reference voltage end to discharge.

9. The driving method according to claim 8, wherein The display panel further comprises an isolation module and a plurality of data lines, the plurality of rows of pixels are arranged in columns, each data line is connected with the source electrode of a column of pixels, the isolation module comprises a plurality of third switch transistors, each third switch transistor is connected in series between a pixel and the data line corresponding to the pixel; among the plurality of third switch transistors, the gate electrode of the third switch transistor connected with the current row of pixels is electrically connected with the next row of gate lines; The driving method further comprises: driving the gate line where the K+1th row of pixels is located, and closing the third switch transistor corresponding to the Kth row of pixels to isolate the Kth row of pixels which has completed power supply and the K+1th row of pixels which will be powered, wherein 1≤K≤N.

10. The driving method of claim 7, wherein, The display panel further comprises a controller, the controller and the gate driver are electrically connected, and the driving method further comprises: controlling the gate driver to supply power to the N+1th row of pixels to the last row of pixels.

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