Gate drive short-circuit protection method based on dV / dt detection

Abstract

This invention discloses a gate-driven short-circuit protection method based on dV / dt detection, belonging to the field of power electronics technology. The method includes the following steps: constructing a unified time-frequency reference baseline; performing full-phase mapping on each power device in a parallel system to reconstruct the conduction sequence; calculating the phase difference between the voltage rising edge and the sampling trigger; generating a time-frequency misalignment matrix; and determining a phase misalignment risk window. Within the phase misalignment risk window, causal playback is performed to extract the transient waveform features of the voltage rising edge, eliminate parasitic spurious peaks, obtain an effective response trajectory, and generate sampling phase verification anchor points based on this trajectory to construct a phase reference baseline. This invention achieves phase synchronization between sampling and conduction behavior by constructing a unified time-frequency baseline and a dynamic sampling mechanism. It combines feedforward vibration suppression and residual adjustment to optimize the sampling rhythm and turn-off threshold, improving the speed and accuracy of short-circuit identification. It possesses self-healing and self-correcting capabilities and is suitable for high-frequency, high-power-density scenarios.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically to a gate drive short-circuit protection method based on dV / dt detection. Background Technology

[0002] "Gate-Drive Short-Circuit Protection Based on dV / dt Detection" is a drive control technology that utilizes the voltage change characteristics of power devices during short-circuit faults to achieve rapid protection. Its core idea is that when a power semiconductor device (such as an IGBT or MOSFET) is turned on and a short-circuit fault occurs, the voltage between the collector and emitter or drain and source of the device changes drastically within a very short time, generating a significant voltage change rate (dV / dt) characteristic. This method introduces a high-speed detection unit into the gate drive circuit to monitor the device's voltage change rate in real time. When an abnormal dV / dt signal is detected, the protection logic is immediately triggered, causing the drive circuit to quickly turn off the power device or reduce the drive voltage, thereby cutting off the fault current and preventing damage to the device due to overcurrent or overheating. Compared to traditional short-circuit protection methods that rely on current detection, the dV / dt detection-based scheme has a faster response and simpler structure, enabling short-circuit fault identification and protection within nanoseconds. It is an important safety control technology in high-frequency, high-power-density power electronic systems.

[0003] The existing technology has the following shortcomings:

[0004] In existing technologies, gate drive short-circuit protection for parallel power transistors typically relies on a uniform dV / dt detection strategy for short-circuit identification. However, during dynamic operation, slight differences in the turn-on timing of each power transistor can easily lead to asynchronous conduction. When the rising edge of the voltage in a branch is out of phase with the dV / dt sampling time, the detection module's response to the actual voltage change will be delayed, causing the short-circuit signal to fail to be identified immediately. This delay can cause protection lag in high-frequency, high-power scenarios, resulting in power devices experiencing excessively high current densities and transient thermal shocks in a short period, potentially triggering thermal breakdown and severely impacting system reliability and safety.

[0005] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a gate drive short-circuit protection method based on dV / dt detection to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a gate drive short-circuit protection method based on dV / dt detection, comprising the following steps:

[0008] A unified time-frequency reference baseline is constructed, full-phase mapping is performed on each power device in the parallel system, the conduction sequence is reconstructed, the phase difference between the voltage rising edge and the sampling trigger is calculated, a time-frequency misalignment matrix is ​​generated, and the phase misalignment risk window is determined.

[0009] Within the phase misalignment risk window, causal playback is performed to extract transient waveform features of the voltage rising edge, eliminate parasitic spurious peaks, obtain an effective response trajectory, and generate sampling phase verification anchor points based on the trajectory to construct a phase reference baseline.

[0010] An adaptive migration mechanism based on phase verification anchor points is established to enable the gate drive timing and voltage detection leading edge to evolve synchronously in a unified phase space, generating a dynamic sampling reference surface.

[0011] Based on the dynamic sampling reference plane, phase conjugate write-back is performed to construct a dual-path consistency discrimination structure, correct the sampling delay, generate a feedforward vibration suppression response surface, and realize the early response and action boundary establishment of short-circuit identification.

[0012] Under stable operation of the feedforward vibration suppression response surface, the reverse diffusion gating and breathing energy regulation mechanism are activated. Based on the residual distribution results, the sampling rhythm and shut-off threshold are adaptively adjusted to eliminate the risk of sampling phase misalignment online and close the dynamic protection control loop.

[0013] Preferably, the steps for determining the phase misalignment risk window are as follows:

[0014] A unified time-frequency reference baseline is constructed. By collecting the pin voltage waveforms of each power device during the conduction process, the conduction start time point is identified, and the conduction behavior is mapped to the normalized time axis. Standardization correction and normalization processing are then performed to establish a stable time-frequency reference template.

[0015] Based on a unified time and frequency reference baseline, a full phase mapping operation is performed to sample the voltage rise edges of each power device at high density and combine them with the standard conduction position to form a relative phase distribution.

[0016] A time-frequency misalignment matrix is ​​constructed based on the relative phase distribution. The voltage rising edge is projected onto both time and frequency dimensions, and the offset distance is calculated as the unit value of the misalignment matrix to identify the maximum offset range of the conduction behavior.

[0017] Based on the high offset region in the time-frequency misalignment matrix, the key time period is determined as the time window where there is a risk of phase misalignment, and the sampling strategy and detection logic are adjusted to ensure that voltage changes can be accurately identified.

[0018] Preferably, the steps for generating phase verification anchor points are as follows:

[0019] High-resolution acquisition of voltage waveforms of each power device branch is performed within the phase misalignment risk time window to construct the transient trajectory of the conduction edge. The waveform comparability and voltage response identification are improved through time-domain synchronous correction and edge enhancement processing.

[0020] In the constructed voltage trajectory, non-spontaneous spike signals caused by parasitic coupling are identified. Pseudo-peaks are identified by combining the voltage trend comparison between branches with the driving response model. Pseudo-peaks are removed based on time position and waveform shape, and continuous waveforms are restored.

[0021] Stable feature points are extracted from the real voltage waveform after spurious peak removal to form a sampling phase verification anchor point group, which is used to calibrate the conduction start point, change inflection point and stable interval, and to establish a key identification sequence that has a constraining significance for conduction behavior;

[0022] The sampling phase verification anchor points are mapped to a unified time-frequency reference baseline, and then aligned, statistically analyzed, and homogenized to generate a continuous reference path and construct a phase reference baseline, providing a basis for subsequent sampling timing migration and detection action alignment.

[0023] Preferably, the sampling phase verification anchor points include the conduction start point, the voltage change rate mutation point during conduction, and the center point of the voltage plateau in the stable state after conduction. By statistically analyzing the anchor point overlap rate and drift range over multiple cycles, anchor points with high overlap rate and low drift range are selected as phase reference points.

[0024] Preferably, the steps for generating the dynamic sampling reference surface are as follows:

[0025] Based on the phase position of the sampling phase verification anchor point on the unified time-frequency reference baseline, the anchor point timing sequence is sorted and mapped to form the phase evolution relationship corresponding to the conduction behavior;

[0026] Based on the phase evolution relationship, an adaptive migration trajectory with a sampling time window is constructed, and the sampling window boundary is set according to the anchor point neighborhood position. The time drift pattern between anchor points is extracted to form a sampling movement path with time progressive characteristics.

[0027] Based on the sampling movement path, the trigger time of the gate drive signal is adjusted so that the driving behavior and the sampling trajectory maintain a fixed relative position in the phase space, thereby aligning the sampling action with the key section of voltage change.

[0028] The sampling trajectory is fitted to a three-dimensional sampling reference surface, which is used to configure the sampling start time, duration and interval, so as to achieve continuous adjustment of the sampling behavior under different conduction states.

[0029] Preferably, the steps for generating the feedforward vibration suppression response surface are as follows:

[0030] Based on the dynamic sampling reference plane, a phase conjugate write-back operation is performed to extract sampling trajectory data from continuous conduction cycles, identify the phase difference between the sampling point and the voltage rising edge, construct a conjugate phase plane corresponding to the sampling reference plane and superimpose them to form a phase comparison structure.

[0031] A dual-path consistency discrimination structure is established based on the phase comparison structure. A main path and an auxiliary path are set. The differences between the two paths in the time coordinate and voltage amplitude coordinate are compared. The sampling start timing and rhythm are adjusted in real time according to the degree of difference, so as to realize the dynamic tracking of the sampling trajectory to the conduction response.

[0032] Based on the output of the dual-path discrimination structure, a feedforward suppression oscillation response surface is constructed in the voltage detection channel. The phase difference and voltage change rate are mapped to a gradient field to form a predictive response boundary, thereby realizing early triggering of short-circuit identification and stable establishment of action boundary.

[0033] Preferably, the feedforward suppression oscillation response surface is generated by the density gradient field composed of the phase difference between the main path and the auxiliary path and the voltage change rate. The response surface is subjected to position averaging processing over multiple conduction cycles, and the trigger boundary position is dynamically fine-tuned according to the device's thermal capacity, current density and switching frequency to ensure that short circuit identification completes an early response before the voltage change reaches the high-risk section.

[0034] Preferably, under the stable condition of the feedforward vibration suppression response surface, the steps of activating inverse diffusion gating and breathing energy regulation based on the residual distribution, adaptively adjusting the sampling rhythm and turn-off threshold, and closing the dynamic protection control loop are as follows:

[0035] Under the premise of stable operation of the feedforward suppression oscillation response surface, the inverse diffusion gating control mechanism is activated based on the residual density distribution. The reverse adjustment drive is applied to the phase shift region in the voltage change. The convergence strength is adjusted by local gradient to limit the sampling boundary shift, and a buffer is introduced to suppress excessive gating intervention.

[0036] After the reverse diffusion gating control is completed, the breathing energy guidance regulation mechanism is activated according to the residual distribution trend. The sampling rhythm density and the cutoff threshold position are dynamically adjusted according to the residual density change. The rhythm continuous transition and voltage response matching are achieved through the rhythmic contraction and relaxation process.

[0037] Based on the combined effect of reverse diffusion gating and breathing regulation, a closed-loop protection control loop with a self-correcting path is constructed. The offset relationship between each control layer is periodically calculated, and the sampling path is corrected according to the residual micro-segment parameters to achieve synchronous maintenance of sampling timing and voltage response.

[0038] The technical effects and advantages provided by the present invention in the above technical solution are as follows:

[0039] This invention identifies critical phase offset risk windows by constructing a unified time-frequency reference baseline and misalignment matrix. It accurately reconstructs the true conduction voltage trajectory of power devices using causal playback and anchor point extraction techniques. Furthermore, through dynamic sampling window migration and phase conjugate write-back mechanisms, it achieves high synchronization between sampling and conduction behaviors in the phase space, significantly improving the timeliness and accuracy of short-circuit feature identification. Further, by combining feedforward vibration suppression control and residual-guided adjustment mechanisms, it adaptively optimizes the sampling rhythm and turn-off threshold, enabling the system to possess online self-healing and closed-loop self-correction capabilities. Ultimately, this solution not only solves the detection lag and action mismatch problems faced by dV / dt detection strategies in parallel systems but also improves the speed, accuracy, and system stability of short-circuit response, demonstrating broad applicability and engineering promotion value in high-frequency, high-power-density power electronics applications. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0041] Figure 1 This is a flowchart of the gate drive short-circuit protection method based on dV / dt detection according to the present invention. Detailed Implementation

[0042] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art.

[0043] This invention provides, for example Figure 1 The gate drive short-circuit protection method based on dV / dt detection shown includes the following steps:

[0044] A unified time-frequency reference baseline is constructed and a full-phase mapping operation is performed to reconstruct the conduction sequence of each power device in the parallel system. The phase difference between the rising edge of each branch voltage and the sampling trigger point is calculated to form a time-frequency misalignment matrix to quantify the degree of conduction timing out-of-step and determine the time window where phase misalignment risk exists.

[0045] This step focuses on the conduction behavior of each power device in a parallel system, proposing a time-frequency reconstruction method for addressing dynamic timing misalignment issues. This method aims to accurately pinpoint critical voltage change moments and determine risk windows, thus providing a foundation for subsequent synchronous correction of voltage change rate detection. The specific implementation steps are as follows:

[0046] Based on the driving triggering sequence and wiring structure of each power device in the parallel system, a unified time-frequency reference baseline is established. In the specific implementation, the pin voltage waveforms during the conduction process of each power device are actually acquired, the timing of the initial conduction edge is identified, and the conduction behavior of each device is uniformly mapped onto a normalized time axis. Considering the differences in manufacturing processes, drive signal paths, power distribution networks, capacitive loads, and drive strength among different power devices, there may be slight but measurable conduction delays. Therefore, the conduction timing of each device needs to be standardized and corrected on the reference baseline to ensure that the conduction behavior of different devices under the same load conditions can be compared within a unified time-frequency framework. To improve the stability of the reference baseline, the conduction characteristic curves of each device in different operating cycles need to be acquired multiple times, and time-domain registration and amplitude normalization processing are performed. This establishes a reusable, statistically representative time-frequency reference template that reflects the true behavior of the devices. This template can be used as the basis for subsequent phase mapping and deviation quantization.

[0047] A time-frequency reference baseline is a fundamental timing and characteristic reference system constructed for actual engineering operation. This baseline is not based on an ideal model or a single measurement result, but rather on the conduction behavior of each power device under real operating conditions. It is gradually formed through continuous acquisition and statistical analysis of the device pin voltage waveforms over multiple operating cycles. Specifically, during system operation, the voltage rise process at the moment of conduction of each power device is first meticulously observed to accurately identify its conduction initiation edge. Based on this, time-domain registration and amplitude normalization are performed on the conduction waveforms of different cycles and different devices, thereby eliminating the influence of measurement conditions, operating state fluctuations, and transient noise on the results. Through this processing, the dispersed and discrete conduction behaviors of each device can be uniformly mapped onto a normalized time axis, constructing a statistically representative and stable time-frequency reference coordinate system.

[0048] This time-frequency reference baseline, centered on a normalized time axis, implicitly incorporates information related to frequency characteristics, such as voltage change rate and transient response pattern. Therefore, it not only characterizes when conduction occurs but also reflects how conduction occurs. Its engineering significance lies in the fact that by establishing such a unified reference framework, it effectively eliminates the minute differences in conduction delay and response introduced by variations in manufacturing processes, drive signal path lengths, power distribution network structures, parasitic parameters, and load conditions among different power devices. This makes conduction behaviors, which were previously not directly comparable, alignable, quantifiable, and analyzable. Based on this, the conduction sequence, relative phase relationship, and transient characteristics of each power device can be clearly characterized within the same time-frequency framework. This provides a unified, stable, and physically meaningful reference basis for subsequent full-phase mapping, quantification of conduction timing out-of-sync degree, and accurate identification of phase misalignment risk windows. The establishment of this reference baseline is a prerequisite and key support for achieving high-precision dV / dt synchronous detection and reliable short-circuit protection strategies.

[0049] The time-frequency reference template is the concrete expression and core data carrier of the time-frequency reference baseline at the engineering implementation level. While highly consistent in technical content and functional positioning, the two differ in emphasis and level. The time-frequency reference baseline emphasizes a holistic reference system and methodological framework for describing, aligning, and comparing the conduction behavior of power devices in a parallel system. It focuses on establishing a unified time-frequency coordinate space, ensuring that different devices, despite conduction delays, path differences, and operating condition fluctuations, can still be evaluated within the same analytical dimension. The time-frequency reference template, guided by this reference system, is a specific time-frequency data model formed by statistically processing, extracting features, and solidifying parameters from voltage waveforms actually acquired over multiple operating cycles. It is used to realistically carry and reflect the timing and characteristic relationships defined by the reference baseline.

[0050] From an implementation perspective, the time-frequency reference template is obtained by repeatedly sampling and summarizing the time position, rise edge shape, voltage change rate, and transient response characteristics during the typical conduction process of power devices. It possesses a clear data structure and computable attributes. Because of this template, the time-frequency reference baseline is no longer merely an abstract concept but is solidified into an engineering benchmark that can be directly used in calculations, invoked by algorithms, and reused at different operational stages. During system operation, subsequent full-phase mapping operations, the construction of the time-frequency misalignment matrix, and the determination of the phase misalignment risk window all require this time-frequency reference template as the comparison object and calculation basis. Only by mapping real-time sampling results to the template and performing deviation analysis can the changing trend of each power device's conduction behavior relative to the reference state be accurately identified.

[0051] Therefore, the time-frequency reference template can be considered the practical implementation and functional carrier of the time-frequency reference baseline in a real system. Its role is to transform the original reference concept used to describe and align conduction behavior into an operable and scalable technical means. Supported by this template, the dV / dt detection and short-circuit protection mechanism described in this application can maintain good synchronicity, detection accuracy, and forward-looking capabilities under the complex conditions of asynchronous conduction of parallel devices, providing a key foundation for realizing a fast, reliable, and adaptive protection strategy.

[0052] After establishing a unified time-frequency reference baseline, a full-phase mapping operation is performed on the conduction behavior of each power device. In practice, high-density sampling of waveform changes before and after the voltage rise edge is performed, and combined with the standard conduction position in the aforementioned reference baseline, the sampling results are expanded in phase space to form the relative phase distribution of each power device's conduction behavior relative to the reference baseline. To accurately capture minute phase shifts, the sampling interval used must be much smaller than the effective duration of the power device's conduction transition, ensuring that the rising edge position accuracy is sufficient to reflect subtle differences in conduction timing. During phase mapping, not only the first significant change point of the rising edge needs to be recorded, but the entire rise process also needs to be continuously tracked to identify conduction mode changes caused by physical effects such as package inductance, current inrush, and drive overshoot. By expanding different conduction waveforms in the phase dimension, a multi-dimensional expression of conduction time position, rate of change, and transient response characteristics can be achieved, thus providing sufficient basic data for subsequent timing out-of-synchronization analysis.

[0053] After completing the phase mapping of each power device, a time-frequency misalignment matrix is ​​constructed based on the aforementioned relative phase distribution. This matrix is ​​constructed using a unified time-frequency reference baseline as the coordinate system, projecting the voltage rise edges during the conduction process of all devices onto both time and frequency dimensions to form a visualized two-dimensional grid structure representing the conduction timing differences between devices. In practice, for each power device, by analyzing the relative offset of its rise edge on the time axis and the spectral characteristics of the corresponding voltage change rate, its offset distance relative to the reference baseline in both the time and frequency domains is calculated and used as the unit value of the misalignment matrix. The corresponding unit values ​​of all devices form a unified matrix, where the values ​​at different positions represent the timing misalignment intensity of different devices at a specific conduction instant. By clustering and boundary extraction of high-offset regions in the matrix, the maximum offset range of conduction behavior between devices can be clearly identified, providing a precise basis for subsequent risk window delineation.

[0054] After obtaining the time-frequency misalignment matrix, the time windows with phase misalignment risks are further determined based on the high-offset regions reflected in the matrix. In implementation, firstly, several concentrated regions with high phase offset values ​​are identified in the matrix. These regions typically indicate significant asynchronous conduction of multiple devices. Secondly, by analyzing the timing boundaries of these regions, critical time periods where voltage change rate signals may be misjudged or missed are identified. Thirdly, based on the typical range of power device turn-on times under high-frequency operating conditions, the aforementioned time periods are locally magnified for analysis, and phase offset boundaries with overlapping trends are extracted to construct a unified time window range. Finally, this range is designated as the sensitive period that must be monitored in subsequent dV / dt detection processes, and the sampling strategy and detection logic are adjusted based on this window to ensure accurate identification of voltage changes and rapid response to short-circuit faults even when devices are asynchronously conducting. Thus, the complete process of establishing a time-frequency reference baseline, full-phase mapping, misalignment matrix construction, and risk window determination is completed, providing a quantifiable, traceable, and forward-looking timing support foundation for subsequent voltage change rate-based protection mechanisms.

[0055] Within the time window, the causal playback process is executed to extract the transient voltage waveform characteristics of the voltage rise edge of each branch, eliminate the spurious peak signals caused by parasitic coupling, obtain the effective response trajectory that reflects the actual voltage change, and generate sampling phase verification anchor points based on the response trajectory to construct the phase reference baseline.

[0056] This step, focusing on the established phase misalignment risk time window, proposes a causal playback method for accurate identification of transient behavior. This method reconstructs the actual voltage change trajectory of each power device during the conduction process and extracts high-confidence verification anchor points to construct a unified sampling phase reference baseline. The specific implementation steps are as follows:

[0057] Within the previously identified phase misalignment risk time window, high-resolution time-domain backtracking acquisition is performed on the voltage change process of each power device branch to construct a complete transient trajectory of the conduction edge. In practice, by continuously sampling the voltage waveforms before and after the power devices are turned on, a sampling configuration with a sampling frequency significantly higher than the device turn-on time constant is selected, thus enabling the complete capture of the voltage rise edge change process within an extremely short time scale. To further enhance the waveform discernibility, time-domain synchronous correction is performed simultaneously during sampling to ensure that the waveforms of each branch have comparability and temporal consistency during the playback analysis stage. During the construction of the waveform trajectory, edge enhancement processing is performed on the acquired signals. By identifying the transition positions between the steep voltage change segment and the stable segment, the true dynamic voltage response profile of each power device during the conduction process is depicted, laying the foundation for subsequent pseudo-peak identification and anchor point extraction.

[0058] After obtaining the complete rising edge waveforms of each power device branch, spurious peak removal is performed to ensure signal purity within the transient waveforms. Specifically, firstly, by comparing the voltage change trends of the branch containing the power device with those of neighboring branches within the same time window, non-spontaneous fluctuations introduced by parasitic capacitance, inductive coupling, and drive circuit interference are identified. Then, a known drive response model is used to fit and compare the voltage change pattern that should be exhibited during normal conduction, identifying spike waveforms that deviate from the physical response model characteristics as spurious peak signals. Next, based on the time location, duration, and amplitude range of the spurious peak signals, their physical causes are analyzed in conjunction with the branch topology, and they are removed from the original sampled waveforms or replaced with gradual transition waveforms that conform to physical expectations. Finally, waveform smoothing restores signal continuity, ensuring that the ultimately retained voltage rising edge trajectory reflects the true device conduction process.

[0059] Based on the waveform trajectory after spurious peak removal, sampling phase verification anchor points with stable timing significance and morphological characteristics are extracted. The core of this step is to screen out key feature points from the real waveform that can be reproduced across multiple cycles or multiple power devices and have a constraining effect on the subsequent sampling rhythm. In the actual extraction process, firstly, the starting point where the voltage change rate reaches the initial critical value is determined in the steep transition section of the waveform to calibrate the leading behavior of the conduction event; then, the voltage change curve is tracked backward, and secondary feature points such as slope inflection points and amplitude inflection points are extracted before the rising edge reaches the stable plateau. These points usually correspond to the sudden change in device conduction speed or the turning point of gate control behavior; further, the center point of the region with the smallest fluctuation is found in the gradually changing range of the waveform as the representative position of the stable conduction state; finally, the set of the above multiple feature points is used as the sampling phase verification anchor point group to characterize the key nodes of the global behavior of the power device during the conduction process and to standardize the sampling rhythm and detection boundary.

[0060] The extracted sampling phase verification anchor points are projected back onto a unified time-frequency reference baseline to construct a complete phase reference baseline, which serves as the core basis for subsequent sampling window migration and detection timing adjustment. In the specific construction process, firstly, according to the unified baseline's time-frequency coordinate system, each anchor point is remapped onto a unified phase axis, forming a cross-branch, cross-cycle anchor point alignment sequence. Next, frequency statistics and morphological clustering are performed on the distribution of various anchor points, selecting the anchor point with the maximum overlap rate and minimum drift interval as the phase reference point, and generating a continuous reference path accordingly. Then, the reference path undergoes time interval homogenization to adapt to the differences in conduction rhythms of different devices, improving the uniformity of sampling rhythms and the synchronization accuracy of the detection leading edge. Finally, through the registration relationship between this phase reference baseline and the real-time sampling signal, a dynamic timing compensation mechanism is established to ensure that subsequent voltage change rate detection actions and the actual conduction behavior of the devices achieve precise alignment in terms of phase consistency, trajectory consistency, and response consistency. At this point, the causal replay process based on the risk window is complete, and a phase reference baseline with both physical credibility and synchronization adaptability has been established, providing a solid foundation for subsequent sampling migration and short-circuit protection response mechanisms.

[0061] Based on the sampling phase verification anchor point, an adaptive migration mechanism for the sampling time window is established to adjust the trigger timing of the gate drive signal and the voltage detection front edge to evolve synchronously in a unified phase space, so that the sampling action is aligned with the key time period of the voltage rising edge, and a continuously traceable dynamic sampling reference surface is generated.

[0062] This step, based on the constructed sampling phase verification anchor point group, further proposes an adaptive migration mechanism for the sampling time window that evolves with the conduction behavior. This ensures that the sampling action continuously aligns with the key change range of the voltage rising edge, forming a continuous, stable, and traceable dynamic sampling reference surface. The specific implementation steps are as follows:

[0063] After obtaining a complete set of sampling phase verification anchor points, these anchor points need to be time-series ordered and phase-mapped according to a unified time-frequency reference baseline to form a time correspondence between the anchor point sequence and the power device conduction process. Specifically, firstly, based on the physical time position of the anchor points during the conduction process of each power device, and in conjunction with the aforementioned constructed reference baseline, all anchor points are repositioned in a unified phase space coordinate system, so that each anchor point not only corresponds to a physical moment but also has a clear phase identifier. On this basis, by varying the time intervals between anchor points, the relative rhythm differences of conduction behavior in different conduction cycles are extracted, and a dynamic time-series curve describing the sampling evolution trend is constructed. This curve serves as the dominant trajectory for subsequent sampling window migration, guiding how the sampling moment evolves synchronously with the conduction behavior and enabling flexible sampling scheduling under different operating states.

[0064] Based on the established dynamic timing curve, an adaptive migration system for the sampling time window is constructed, using anchor points as reference nodes. During implementation, the boundary determination method of the sampling window must first be clarified, i.e., the preceding and following neighborhoods of the anchor point are used as the start and end positions of the window, ensuring that the sampling range covers the main change segments of the voltage rise edge. When constructing the migration mechanism, the distribution characteristics of the anchor points over multiple cycles need to be compared to extract their time drift patterns, and a sampling interval movement trajectory with time-gradient characteristics is established accordingly. This trajectory should have dynamic adjustment capabilities; that is, when the power device turns on earlier or later, the sampling window can correspondingly move forward or backward along the time axis to adapt to the new conduction rhythm. Furthermore, to enhance the stability of this migration mechanism under frequent switching conditions, the trajectory change trend needs to be smoothed to avoid frequent jumping of the sampling window due to conduction jitter, thereby maintaining the consistency and continuity of sampling.

[0065] Based on the constructed adaptive migration sampling trajectory, the trigger timing of the gate drive signal is adjusted to maintain strict phase consistency with the detection leading edge of the voltage change. This step is a crucial link in the deep coupling between the sampling migration mechanism and the drive control strategy. It requires adjusting the starting trigger point of the drive signal to maintain a constant relative position with the sampling anchor point group in the phase space. In the actual implementation, firstly, the anchor point distribution of the current conduction cycle is reviewed and analyzed based on the dynamic sampling trajectory to confirm the relative phase difference between the starting position of the gate drive signal and the voltage rising edge. Subsequently, the trigger time of the drive signal is adjusted according to this phase difference so that the rising edge of the drive waveform falls exactly in the center segment of the sampling window. Furthermore, by dynamically compensating the phase relationship between the drive starting position and the voltage response over multiple operating cycles, the drive behavior always closely follows the migration path of the sampling window in the phase space, thereby ensuring that the sampling action can accurately fall on the critical segment of rapid voltage change.

[0066] After the driving signal and sampling window complete synchronous evolution, the aforementioned dynamic migration path is transformed into a continuously trackable sampling reference surface, used to guide the precise deployment of sampling behavior throughout the entire conduction cycle and under different operating states. To this end, the sampling trajectory within each conduction cycle needs to be fitted with discrete points, and a three-dimensional surface model is constructed through staggered projection of the time plane and phase surface. Each contour line of this model corresponds to the sampling rhythm distribution under a specific conduction state. Subsequently, this surface is used as the main control surface for dynamic sampling behavior, guiding the fine configuration of the sampling start time, duration, and sampling interval, thereby achieving a high degree of fit between sampling behavior and conduction behavior in the phase space. Through the continuous evolution of this reference surface, not only can the online adjustment of the sampling strategy be achieved, but the sampling rhythm can also be adaptively adjusted according to changes in operating conditions, ultimately forming a stable, predictable, and responsive dynamic sampling control structure. At this point, the entire process of the adaptive migration mechanism for the sampling time window is completed, the dynamic sampling reference surface is successfully constructed, and the voltage change detection action achieves precise alignment during the critical time period of physical behavior.

[0067] Based on the dynamic sampling reference plane, a phase conjugate write-back operation is performed to construct a dual-path consistency discrimination structure for detection timing correction. The sampling delay caused by asynchronous conduction is corrected in real time, and a suppression oscillation response surface with feedforward characteristics is generated in the voltage detection channel, so that short circuit identification is executed in advance and a stable action boundary is established.

[0068] This step, based on the constructed dynamic sampling reference surface, further proposes a phase conjugate write-back operation to address the sampling delay problem caused by asynchronous conduction of power devices. It constructs a dual-path consistency discrimination structure and establishes a feedforward characteristic-based oscillation suppression response surface, thereby achieving early response for short-circuit identification and stable establishment of action boundaries. The specific implementation steps are as follows:

[0069] Based on the generated dynamic sampling reference plane, a phase soft write-back operation is performed to trace and recover key voltage rising edge features that were not accurately captured in the previous cycle, and use them as a reference for correcting sampling deviations in the current cycle. In practice, sampling trajectory data from multiple consecutive conduction cycles needs to be extracted from the dynamic sampling reference plane, and the sampling point closest to the voltage rising edge within each sampling window needs to be identified, thus establishing an actual phase difference distribution map between the sampling point and the actual rising edge. Subsequently, this map is written back, mapping each phase difference value back to the original position of the corresponding sampling path, thereby constructing a symmetrical phase surface opposite to the sampling reference plane, called the conjugate phase surface. This conjugate phase surface is not simply a copy of the sampling trajectory, but is constructed in reverse, combining the actually measured phase difference and voltage waveform evolution trend, and can present the dynamic phase offset characteristics between the ideal sampling trajectory and the actual response. After forming the conjugate surface, this surface is superimposed on the sampling reference plane of the current conduction cycle, forming a set of mutually referential phase comparison structures to reveal and quantify the degree of offset of the sampling action relative to the voltage response.

[0070] Based on the phase comparison structure, a dual-path consistency discrimination structure is constructed for timing correction detection. This structure identifies the synchronization error between sampling deviation and conduction rhythm in real time and performs timing adjustment operations on the sampling window accordingly. In implementation, a primary sampling path is first defined as the main track, taken from the sampling trajectory generated based on anchor points in the current cycle. An auxiliary track is then defined, derived from the ideal sampling trajectory reconstructed through phase conjugate write-back in the previous cycle. Subsequently, the sampling positions of the main and auxiliary tracks within the same time period are extracted, and their corresponding voltage response feature points are compared item by item to calculate the degree of difference in time and voltage amplitude coordinates. If the difference between the two paths at multiple consecutive key sampling positions exceeds a preset threshold, the current sampling path is considered to have a significant offset. Next, based on the local difference function of the two paths, the starting timing and sampling rhythm of the main path in subsequent cycles are deduced to achieve phase alignment with the auxiliary track. During the adjustment process, the sampling step size should be kept continuous to avoid abrupt changes, and a time smoothing strategy should be used to suppress high-frequency jitter, ultimately achieving dynamic tracking of the main path to the actual conduction response. This dual-path discrimination mechanism not only enables early identification of sampling timing drift, but also provides real-time feedback on the degree of coordination between the sampling trajectory and the voltage response, providing reliable data support for short-circuit response strategies.

[0071] Based on the real-time output of the dual-path discrimination structure, a feedforward-characteristic oscillation suppression response surface is constructed in the voltage detection channel as an early triggering basis for the short-circuit protection mechanism. In implementation, the phase difference between the main rail and the auxiliary rail, along with the voltage change rate distribution, is first jointly mapped to a unified phase space, and a density gradient field reflecting this difference trend is constructed. This gradient field reveals the changing trend of the sampling behavior's response to the voltage rise edge at different conduction stages. Subsequently, a feedforward response boundary curve is constructed centered on the high-density change region in the gradient field to indicate the time position when the voltage change enters the high-risk range. Extending this boundary curve forward by a certain time length forms a feedforward response surface with time-series prediction capabilities, used to predict the critical critical point that the voltage change will reach in advance. Based on this, by dynamically aligning this response surface with the main rail sampling path, the early warning time for short-circuit protection is adjusted, so that the protection mechanism no longer relies on passive judgment after an event occurs, but rather actively responds based on the prediction of the voltage response trend. To ensure the stability of the response surface, the position of the response surface should be averaged over multiple conduction cycles, and a threshold adjustment mechanism should be introduced. The position of the response surface should be fine-tuned in real time based on operating parameters such as equipment heat capacity, current density, and switching frequency to ensure that the protection boundary is neither lagging nor premature. Through this method, a predictive, stable, and real-time response control mechanism is established, enabling accurate identification of short-circuit faults before they cause device impact and prompting protection actions before voltage changes approach high-risk areas. This achieves true high-frequency, fast short-circuit response closed-loop control.

[0072] Under the condition that the feedforward suppression oscillation response surface is continuously stable, a dual dynamic response mechanism including inverse diffusion gating control and breathing energy guidance regulation is activated. Based on the residual distribution results of the suppression oscillation response surface output, the sampling rhythm and turn-off threshold of the time grid array are adaptively adjusted to realize the online elimination of the sampling phase misalignment risk in short-circuit identification and close the dynamic protection control loop containing the self-correction path.

[0073] This step, based on the constructed feedforward-suppressed oscillation response surface, proposes a dual dynamic response mechanism integrating inverse diffusion gating control and breathing-type energy-guided regulation. It also combines residual distribution to achieve adaptive linkage control of sampling rhythm and turn-off threshold, ultimately constructing a closed-loop protection control loop with online self-correction capability. The specific implementation steps are as follows:

[0074] Under the premise of stable operation of the feedforward suppression oscillation response surface, the inverse diffusion gating control mechanism is activated to actively reverse the abnormal evolution trend that may induce sampling phase misalignment during voltage changes. This mechanism identifies potential regions of abnormal voltage change rate accumulation based on the residual density distribution exhibited by the feedforward response surface during continuous conduction cycles. In practice, residual data in different phase segments of the feedforward response surface must first be extracted; this residual refers to the relative deviation between the sampling trajectory and the actual voltage change. Regions with high residual density usually indicate nonlinear shifts in the voltage rise edge or abrupt changes in device conduction characteristics, potentially causing sampling behavior to deviate from critical detection points. To prevent such offset accumulation, the inverse diffusion gating control mechanism applies an opposite adjustment drive in the residual density peak region. This adjustment does not rely on responding after a voltage abrupt change but actively converges the sampling boundary inward before the voltage change trend enters the critical region, thus preemptively suppressing phase slippage on the signal propagation path. This convergence process dynamically adjusts the response intensity according to the local gradient of the residual curve, enabling differentiated gating in different regions based on their disturbance levels, thereby achieving the dual goals of local stability and overall consistency. During execution, it is also necessary to prevent the gating action from excessively interfering with the normal conduction waveform. To this end, a controllable buffer should be introduced at the gating edge to avoid secondary loss of synchronization caused by hard truncation and to ensure that the reverse diffusion action has good adaptability to the sampling timing.

[0075] After the reverse diffusion gating action is completed, a breathing-style energy guidance and regulation mechanism is further introduced to dynamically adjust the sampling rhythm density and the trigger threshold of the voltage turn-off action, achieving an adaptive adjustment strategy that matches the voltage response pattern. This mechanism is based on the residual distribution map. By extracting the trend of residual density evolution with the conduction cycle over different time periods, it determines whether the current sampling rhythm meets the coverage requirements for key voltage change points. If the residual distribution shows a periodic expansion or local accumulation trend in a certain phase segment, it indicates insufficient sampling point coverage. Therefore, the sampling interval is shortened to improve resolution and achieve denser sampling of key change segments. Conversely, if the residual density remains below the preset range, it indicates stable voltage changes in the current region. Therefore, the sampling rhythm is appropriately widened to release detection resources and improve overall response efficiency. During the adjustment process, to avoid detection discontinuity caused by rhythm changes, a breathing-style rhythmic structure is introduced. This involves setting two phases, contraction and relaxation, within each sampling cycle to achieve rhythmic fluctuations within micro-cycles, flexibly adapting to the nonlinear changes in voltage response. In addition to the sampling rhythm, the breathing-style adjustment also affects the setting of the turn-off threshold. The threshold position is adjusted based on the location of the residual peak distribution, ensuring that the turn-off action depends not only on the absolute voltage change amplitude but also on the dynamic phase of the voltage change relative to the sampling trajectory. This improves the accuracy and foresight of the protection action. This process completes a reassessment within each conduction cycle, ensuring that the system maintains coverage of critical change areas and timely response even under response offsets caused by external load disturbances, device aging, or drive changes.

[0076] Based on the dynamic control foundation formed by inverse diffusion gating and breathing-like regulation, a closed-loop protection control loop including a self-correcting path is constructed to achieve online closed-loop correction of sampling phase misalignment risk in short-circuit identification. In specific implementation, information such as the feedforward response surface, residual density field, inverse diffusion gating curve, and breathing rhythm sampling trajectory are first integrated into a multi-layer control reference set. The offset relationship between each layer of information is calculated through periodic iteration to identify whether the current control behavior deviates from the true voltage change path. When a persistent deviation trend is detected between the sampling path and the true trajectory, the system triggers the activation of the self-correcting path. This path retrieves the sampling parameters of the smallest residual density segment in the previous conduction cycle as a reference standard, and adjusts the sampling interval, start time, and turn-off position in the current cycle in reverse, continuously tracking the correction effect during execution. If the residual density decreases significantly after correction, the path is set as the priority benchmark for the next cycle, forming a positive compensation feedback loop; if the correction is ineffective or the deviation increases, path replacement is performed, retrieving successful sampling modes from other cycles for reconstruction. Through repeated execution of this dynamic path reconstruction and deviation feedback, the sampling behavior and voltage response remain highly coupled, maintaining the timeliness and accuracy of short-circuit protection triggering even under complex load fluctuations, high-temperature drift, or aging conditions. Ultimately, this closed loop completes the online elimination of sampling phase misalignment throughout the entire process, maintaining the continuity and robustness of the control strategy under a multi-cycle collaborative mechanism, ensuring stable gate protection response and overall system operational safety under high-frequency drive environments.

[0077] This invention identifies critical phase offset risk windows by constructing a unified time-frequency reference baseline and misalignment matrix. It accurately reconstructs the true conduction voltage trajectory of power devices using causal playback and anchor point extraction techniques. Furthermore, through dynamic sampling window migration and phase conjugate write-back mechanisms, it achieves high synchronization between sampling and conduction behaviors in the phase space, significantly improving the timeliness and accuracy of short-circuit feature identification. Further, by combining feedforward vibration suppression control and residual-guided adjustment mechanisms, it adaptively optimizes the sampling rhythm and turn-off threshold, enabling the system to possess online self-healing and closed-loop self-correction capabilities. Ultimately, this solution not only solves the detection lag and action mismatch problems faced by dV / dt detection strategies in parallel systems but also improves the speed, accuracy, and system stability of short-circuit response, demonstrating broad applicability and engineering promotion value in high-frequency, high-power-density power electronics applications.

[0078] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A gate drive short-circuit protection method based on dV / dt detection, characterized in that, Includes the following steps: A unified time-frequency reference baseline is constructed, full-phase mapping is performed on each power device in the parallel system, the conduction sequence is reconstructed, the phase difference between the voltage rising edge and the sampling trigger is calculated, a time-frequency misalignment matrix is ​​generated, and the phase misalignment risk window is determined. Within the phase misalignment risk window, causal playback is performed to extract transient waveform features of the voltage rising edge, eliminate parasitic spurious peaks, obtain an effective response trajectory, and generate sampling phase verification anchor points based on the trajectory to construct a phase reference baseline. An adaptive migration mechanism based on phase verification anchor points is established to enable the gate drive timing and voltage detection leading edge to evolve synchronously in a unified phase space, generating a dynamic sampling reference surface. Based on the dynamic sampling reference plane, phase conjugate write-back is performed to construct a dual-path consistency discrimination structure, correct the sampling delay, generate a feedforward vibration suppression response surface, and realize the early response and action boundary establishment of short-circuit identification. Under stable operation of the feedforward vibration suppression response surface, the reverse diffusion gating and breathing energy regulation mechanism are activated. Based on the residual distribution results, the sampling rhythm and shut-off threshold are adaptively adjusted to eliminate the risk of sampling phase misalignment online and close the dynamic protection control loop.

2. The gate drive short-circuit protection method based on dV / dt detection according to claim 1, characterized in that, The steps for determining the phase misalignment risk window are as follows: A unified time-frequency reference baseline is constructed. By collecting the pin voltage waveforms of each power device during the conduction process, the conduction start time point is identified, and the conduction behavior is mapped to the normalized time axis. Standardization correction and normalization processing are then performed to establish a stable time-frequency reference template. Based on a unified time and frequency reference baseline, a full phase mapping operation is performed to sample the voltage rise edges of each power device at high density and combine them with the standard conduction position to form a relative phase distribution. A time-frequency misalignment matrix is ​​constructed based on the relative phase distribution. The voltage rising edge is projected onto both time and frequency dimensions, and the offset distance is calculated as the unit value of the misalignment matrix to identify the maximum offset range of the conduction behavior. Based on the high offset region in the time-frequency misalignment matrix, the key time period is determined as the time window where there is a risk of phase misalignment, and the sampling strategy and detection logic are adjusted to ensure that voltage changes can be accurately identified.

3. The gate drive short-circuit protection method based on dV / dt detection according to claim 2, characterized in that, The steps for generating phase verification anchor points are as follows: High-resolution acquisition of voltage waveforms of each power device branch is performed within the phase misalignment risk time window to construct the transient trajectory of the conduction edge. The waveform comparability and voltage response identification are improved through time-domain synchronous correction and edge enhancement processing. In the constructed voltage trajectory, non-spontaneous spike signals caused by parasitic coupling are identified. Pseudo-peaks are identified by combining the voltage trend comparison between branches with the driving response model. Pseudo-peaks are removed based on time position and waveform shape, and continuous waveforms are restored. Stable feature points are extracted from the real voltage waveform after spurious peak removal to form a sampling phase verification anchor point group, which is used to calibrate the conduction start point, change inflection point and stable interval, and to establish a key identification sequence that has a constraining significance for conduction behavior; The sampling phase verification anchor points are mapped to a unified time-frequency reference baseline, and then aligned, statistically analyzed, and homogenized to generate a continuous reference path and construct a phase reference baseline, providing a basis for subsequent sampling timing migration and detection action alignment.

4. The gate drive short-circuit protection method based on dV / dt detection according to claim 3, characterized in that, The sampling phase verification anchor points include the conduction start point, the voltage change rate mutation point during conduction, and the center point of the voltage plateau in the stable state after conduction. By statistically analyzing the anchor point overlap rate and drift range over multiple cycles, anchor points with high overlap rate and low drift range are selected as phase reference points.

5. The gate drive short-circuit protection method based on dV / dt detection according to claim 3, characterized in that, The steps for generating a dynamic sampling reference surface are as follows: Based on the phase position of the sampling phase verification anchor point on the unified time-frequency reference baseline, the anchor point timing sequence is sorted and mapped to form the phase evolution relationship corresponding to the conduction behavior; Based on the phase evolution relationship, an adaptive migration trajectory with a sampling time window is constructed, and the sampling window boundary is set according to the anchor point neighborhood position. The time drift pattern between anchor points is extracted to form a sampling movement path with time progressive characteristics. Based on the sampling movement path, the trigger time of the gate drive signal is adjusted so that the driving behavior and the sampling trajectory maintain a fixed relative position in the phase space. The sampling trajectory is fitted to a three-dimensional sampling reference surface, which is used to configure the sampling start time, duration and interval.

6. The gate drive short-circuit protection method based on dV / dt detection according to claim 5, characterized in that, The steps for generating the feedforward damping response surface are as follows: Based on the dynamic sampling reference plane, a phase conjugate write-back operation is performed to extract sampling trajectory data from continuous conduction cycles, identify the phase difference between the sampling point and the voltage rising edge, construct a conjugate phase plane corresponding to the sampling reference plane and superimpose them to form a phase comparison structure. A dual-path consistency discrimination structure is established based on the phase comparison structure. A main path and an auxiliary path are set. The differences between the two paths in the time coordinate and voltage amplitude coordinate are compared. The sampling start sequence and rhythm are adjusted in real time according to the degree of difference. Based on the output of the dual-path discrimination structure, a feedforward suppressed oscillation response surface is constructed in the voltage detection channel, and the phase difference and voltage change rate are mapped to a gradient field to form a predictive response boundary.

7. The gate drive short-circuit protection method based on dV / dt detection according to claim 6, characterized in that, The feedforward suppression oscillation response surface is generated by the density gradient field formed by the phase difference between the main path and the auxiliary path and the voltage change rate. The response surface is subjected to position averaging processing over multiple conduction cycles, and the trigger boundary position is dynamically fine-tuned according to the device's thermal capacity, current density and switching frequency to ensure that short circuit identification completes an early response before the voltage change reaches the high-risk section.

8. The gate drive short-circuit protection method based on dV / dt detection according to claim 6, characterized in that, Under the stable condition of the feedforward vibration suppression response surface, the following steps are taken to activate inverse diffusion gating and breathing-type energy regulation based on the residual distribution, adaptively adjust the sampling rhythm and turn-off threshold, and close the dynamic protection control loop: Under the premise of stable operation of the feedforward suppression oscillation response surface, the inverse diffusion gating control mechanism is activated based on the residual density distribution. The reverse adjustment drive is applied to the phase shift region in the voltage change. The convergence strength is adjusted by local gradient to limit the sampling boundary shift, and a buffer is introduced to suppress excessive gating intervention. After the reverse diffusion gating control is completed, the breathing energy guidance regulation mechanism is activated according to the residual distribution trend. The sampling rhythm density and the cutoff threshold position are dynamically adjusted according to the residual density change. The rhythm continuous transition and voltage response matching are achieved through the rhythmic contraction and relaxation process. Based on the combined effect of reverse diffusion gating and breathing regulation, a closed protection control loop containing a self-correcting path is constructed. The offset relationship between each control layer is periodically calculated, and the sampling path is corrected according to the residual micro-segment parameters.

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