Charge activation circuit and photovoltaic charging system

Abstract

The embodiments of the present disclosure disclose a charging activation circuit and a photovoltaic charging system, the charging activation circuit comprising a controller, which is configured to set an activation control signal when the controller is about to shut down a device to be charged, and send the activation control signal to a signal holding circuit to hibernate; the signal holding circuit is configured to hold the activation control signal; a voltage detection circuit is configured to output a valid level when a voltage of a first voltage source meets a first condition; an activation signal generation circuit is configured to generate an activation signal according to the activation control signal held by the signal holding circuit and send the activation signal to the controller when the voltage detection circuit outputs the valid level; and the controller is further configured to wake up every time the activation signal is received, determine that a charging condition is not met, and prepare to hibernate again, set the activation control signal again, and send the activation control signal to the signal holding circuit to hibernate. The charging activation circuit and the photovoltaic charging system can enable the controller to be activated when the voltage of the first voltage source meets a predetermined condition after each hibernation.

Description

Technical Field

[0001] This disclosure relates to the field of photovoltaic charging technology, and more specifically, to a charging activation circuit and a photovoltaic charging system. Background Technology

[0002] Solar panels absorb sunlight and convert it into electrical energy. Once this energy is converted, it needs to be stored in an energy storage system or power supply. During operation, the voltage output of solar panels can be unstable due to factors such as shade from trees or clouds, or during nighttime operation. For example, in the early morning or on cloudy days, the solar panel outputs a weak voltage. This voltage can activate the energy storage system, but the actual output power is insufficient to charge the system, leading to energy depletion within the storage system. In more severe cases, the energy storage system may be completely depleted and rendered unusable. Therefore, there is an urgent need for a charging activation circuit capable of handling complex weather conditions. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a charging activation circuit and a photovoltaic charging system.

[0005] This disclosure provides a charging activation circuit, applied to a device to be charged, comprising:

[0006] The controller is configured to set an activation control signal when the device to be charged is turned off, and then go into sleep mode after sending the activation control signal to the signal holding circuit;

[0007] The signal holding circuit is connected to the controller and is configured to hold the active control signal;

[0008] The voltage detection circuit is configured to acquire the voltage of a first voltage source, and output an effective level when the voltage of the first voltage source meets a first condition; the effective level refers to the level that enables the activation signal generation circuit to operate.

[0009] The activation signal generation circuit is connected to the voltage detection circuit and the signal holding circuit respectively, and is configured to generate an activation signal and send it to the controller when the voltage detection circuit outputs an effective level, based on the activation control signal held by the signal holding circuit.

[0010] The controller is further configured to wake up whenever it receives the activation signal, and when it determines that the charging conditions are met, control the first voltage source to charge the device to be charged; when it determines that the charging conditions are not met and prepares to hibernate again, it sets the activation control signal again, and sends the newly set activation control signal to the signal holding circuit before hibernating.

[0011] In one exemplary embodiment, the activation control signal includes a timing duration control signal; the timing duration control signal is M bits; and M is a natural number.

[0012] The activation signal generation circuit includes a frequency division circuit and a channel selection circuit; the channel selection circuit has... One channel;

[0013] The frequency division circuit is connected to the voltage detection circuit and the channel selection circuit respectively, and is configured to output N square wave signals with different frequencies when the voltage detection circuit outputs an effective level; where N is a natural number.

[0014] The channel selection circuit is connected to the frequency division circuit and the signal holding circuit respectively, and is configured to select the corresponding channel according to the timing duration control signal, and output the square wave signal transmitted by the selected channel as the activation signal.

[0015] Among them, when When N, the Each of the N channels in the channel corresponds one-to-one with the N square wave signals;

[0016] when When N, the Each channel and one of the N square wave signals Each square wave signal corresponds to one other.

[0017] In one exemplary embodiment, the activation control signal further includes a circuit enable control signal;

[0018] The circuit enable control signal is used to control whether the channel selection circuit is working or not.

[0019] In one exemplary embodiment, the first condition includes the voltage of the first voltage source increasing to be greater than or equal to a first threshold voltage, and the voltage of the first voltage source decreasing to be less than the first threshold voltage but greater than a second threshold voltage.

[0020] The voltage detection circuit is further configured to output an invalid level when the voltage of the first voltage source meets a second condition; the second condition includes the voltage of the first voltage source increasing to be greater than the second threshold voltage and less than the first threshold voltage, and the voltage of the first voltage source decreasing to be less than the second threshold voltage; the invalid level refers to the level that makes the activation signal generation circuit not work.

[0021] In one exemplary embodiment, the voltage detection circuit includes a voltage comparison circuit, which includes a first resistor, a second resistor, a third resistor, a fourth resistor, and an AND gate.

[0022] The first end of the first resistor is used to connect to the second voltage source, and the second end of the first resistor is connected to the first node;

[0023] The first end of the second resistor is connected to the first node, and the second end of the second resistor is grounded.

[0024] The first end of the third resistor is used to connect to the first voltage source, and the second end of the third resistor is connected to the second node;

[0025] The first end of the fourth resistor is connected to the second node; the second end of the fourth resistor is grounded.

[0026] The first input terminal of the AND gate is connected to the first node, the second input terminal of the AND gate is connected to the second node, and the output terminal of the AND gate is the output terminal of the voltage comparison circuit.

[0027] In one exemplary embodiment, the voltage detection circuit includes a voltage comparison circuit, which includes a first resistor, a second resistor, a third resistor, a fourth resistor, a diode, and an AND gate.

[0028] The first end of the first resistor is used to connect to the second voltage source, and the second end of the first resistor is connected to the first node;

[0029] The first end of the second resistor is connected to the first node, and the second end of the second resistor is grounded.

[0030] The anode of the diode is connected to the first voltage source, and the cathode of the diode is connected to the first end of the third resistor;

[0031] The second end of the third resistor is connected to the second node;

[0032] The first end of the fourth resistor is connected to the second node; the second end of the fourth resistor is grounded.

[0033] The first input terminal of the AND gate is connected to the first node, the second input terminal of the AND gate is connected to the second node, and the output terminal of the AND gate is the output terminal of the voltage comparison circuit.

[0034] In one exemplary embodiment, the voltage comparison circuit further includes a Zener diode;

[0035] The anode of the Zener diode is grounded, and the cathode of the Zener diode is connected to the second node.

[0036] In one exemplary embodiment, the output circuit includes a fifth resistor, a sixth resistor, and a first transistor;

[0037] The first end of the fifth resistor is used to connect to the second voltage source, and the second end of the fifth resistor is connected to the third node;

[0038] The first end of the sixth resistor is connected to the output terminal of the voltage comparison circuit, and the second end of the sixth resistor is connected to the fourth node;

[0039] The control electrode of the first transistor is connected to the fourth node; the first electrode of the first transistor is connected to the third node; and the second electrode of the first transistor is grounded.

[0040] The third node is connected to the activation signal generation circuit.

[0041] In one exemplary embodiment, the output circuit further includes a seventh resistor and a first capacitor;

[0042] The first end of the seventh resistor is connected to the fourth node, and the second end of the seventh resistor is grounded.

[0043] The first plate of the first capacitor is connected to the fourth node, and the second plate of the first capacitor is grounded.

[0044] In one exemplary embodiment, the frequency divider circuit is a frequency divider chip.

[0045] In one exemplary embodiment, the timing duration control signal is multi-bit;

[0046] The signal holding circuit includes multiple signal holding units;

[0047] Each of the plurality of signal holding units corresponds one-to-one with each bit of the timing duration control signal.

[0048] In one exemplary embodiment, the signal holding unit includes an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a second transistor, a second capacitor, a third capacitor, and a third transistor.

[0049] The first end of the eighth resistor is connected to the fifth node, and the second end of the eighth resistor is connected to the sixth node; the fifth node is configured to receive the timing duration control signal.

[0050] The first end of the ninth resistor is connected to the sixth node, and the second end of the ninth resistor is grounded.

[0051] The first plate of the second capacitor is connected to the sixth node, and the second plate of the second capacitor is grounded.

[0052] The control electrode of the second transistor is connected to the sixth node, the first electrode of the second transistor is connected to the first terminal of the tenth resistor, and the second electrode of the second transistor is grounded.

[0053] The second end of the tenth resistor is connected to the eighth node;

[0054] The control electrode of the third transistor is connected to the eighth node; the first electrode of the third transistor is connected to the seventh node; the second electrode of the third transistor is connected to the ninth node; the seventh node is configured to be connected to a third voltage source.

[0055] The first end of the eleventh resistor is connected to the seventh node, and the second end of the eleventh resistor is connected to the eighth node;

[0056] The first plate of the third capacitor is connected to the seventh node, and the second plate of the third capacitor is connected to the eighth node;

[0057] The first end of the twelfth resistor is connected to the ninth node, and the second end of the twelfth resistor is grounded;

[0058] The first end of the thirteenth resistor is connected to the ninth node; the second end of the thirteenth resistor is connected to the fifth node;

[0059] The ninth node is connected to the channel selection circuit as the output terminal of the signal holding unit.

[0060] This disclosure also provides a photovoltaic charging system, including:

[0061] Photovoltaic input source;

[0062] Device to be activated;

[0063] The charging activation circuit described in any of the above embodiments; the photovoltaic input source serves as the first voltage source in the charging activation circuit.

[0064] The charging activation circuit described in this embodiment enables the controller to be activated after each sleep cycle when the voltage of the first voltage source meets the first condition, thereby overcoming the problem that the single-pulse activation circuit can only be activated once and cannot cope with complex weather changes.

[0065] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0066] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0067] Figure 1 This is one of the schematic diagrams of a charging activation circuit according to an embodiment of the present disclosure;

[0068] Figure 2 This is one of the schematic diagrams of a voltage detection circuit according to an embodiment of the present disclosure;

[0069] Figure 3 This is a second schematic diagram of a voltage detection circuit according to an embodiment of the present disclosure;

[0070] Figure 4 This is a second schematic diagram of the charging activation circuit according to an embodiment of the present disclosure;

[0071] Figure 5 This is a schematic diagram of a frequency divider circuit according to an embodiment of the present disclosure;

[0072] Figure 6 This is a schematic diagram of a channel selection circuit according to an embodiment of the present disclosure;

[0073] Figure 7 This is a schematic diagram of a signal holding unit according to an embodiment of the present disclosure. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0075] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0076] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0077] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0078] Figure 1 This is one schematic diagram of a charging activation circuit according to an embodiment of this disclosure. It is applied to a device to be charged. Figure 1 As shown, the charging activation circuit includes a voltage detection circuit, an activation signal generation circuit, a signal holding circuit, and a controller.

[0079] The controller is configured to set an activation control signal when the device to be charged is turned off, and then go into sleep mode after sending the activation control signal to the signal holding circuit;

[0080] The signal holding circuit is connected to both the controller and the activation signal generation circuit, and is configured to hold the activation control signal.

[0081] The voltage detection circuit is connected to the activation signal generation circuit and is configured to acquire the voltage of the first voltage source. When the voltage of the first voltage source meets the first condition, it outputs an effective level. The effective level refers to the level that enables the activation signal generation circuit to work.

[0082] The activation signal generation circuit is configured to generate an activation signal and send it to the controller when the voltage detection circuit outputs an effective level, based on the activation control signal held by the signal holding circuit.

[0083] The controller is further configured to wake up whenever it receives the activation signal, and when it determines that the charging conditions are met, control the first voltage source to charge the device to be charged; when it determines that the charging conditions are not met and prepares to go into sleep mode again, it sets the activation control signal again, and sends the newly set activation control signal to the signal holding circuit before going into sleep mode.

[0084] The charging activation circuit of this embodiment sets an activation control signal and sends it to a signal holding circuit when it is determined that the charging conditions are not met. The signal holding circuit holds the activation control signal. When the voltage detection circuit outputs a valid level, it generates an activation signal based on the held activation control signal. The controller is activated from the sleep state based on the generated activation signal, so that the controller can be activated after each sleep state when the voltage of the first voltage source meets the first condition. This overcomes the problem that the single-pulse activation circuit can only be activated once and cannot cope with complex weather changes.

[0085] For example, the device to be charged can be a portable energy storage product.

[0086] For example, the first voltage source is a photovoltaic power source (i.e., a photovoltaic power source, also known as a PV source).

[0087] For example, the effective level refers to the signal that enables the activation signal generation circuit to operate. The effective level can be low or high, depending on the actual needs.

[0088] For example, a situation where charging conditions are not met could be that the circuit is considered unable to sustain charging until the light intensity increases when the battery level of the device being charged falls below a certain value. For instance, it could be set that the circuit cannot sustain charging until the light intensity increases when the battery level of the device being charged falls below 2% of its capacity. This value is determined based on the capacity of the device being charged. If the capacity of the device being charged is large, this value can be set smaller, such as 1%. If the capacity of the device being charged is small, this value can be set larger, such as 5%.

[0089] For example, the charging conditions can also be set as follows: When the device is started to be charged by a photovoltaic power source, the power supply voltage provided by the external photovoltaic panel will decrease. When the voltage of the photovoltaic panel after the decrease is greater than the minimum charging voltage of the device to be charged, the charging conditions are considered to be met; otherwise, the charging conditions are considered not met. For example, when the external charging voltage is 12~28V, the charging conditions are met, and the circuit charging power is 5~100W. When a 14V photovoltaic power source is connected, the circuit will start charging. At this time, the 14V voltage will start to drop. When charging with 100W, the voltage drops to 10V, which no longer meets the charging conditions. At this time, the circuit will gradually reduce the charging power. For example, when it drops to 30W, the voltage can be maintained above 12V, and the circuit considers the charging conditions to be met. If the charging power continues to decrease, even if it is reduced to 5W, the voltage of the external photovoltaic panel is still lower than 12V, then the circuit considers the charging power not met.

[0090] In one exemplary embodiment, the first condition includes the voltage of the first voltage source increasing to be greater than or equal to a first threshold voltage, and the voltage of the first voltage source decreasing to be less than the first threshold voltage but greater than a second threshold voltage.

[0091] The voltage detection circuit is further configured to output an invalid level when the voltage of the first voltage source meets a second condition; the second condition includes the voltage of the first voltage source increasing to be greater than the second threshold voltage and less than the first threshold voltage, and the voltage of the first voltage source decreasing to be less than the second threshold voltage.

[0092] This embodiment prevents the activation signal generation circuit from being repeatedly activated by setting a voltage hysteresis.

[0093] Clearly, the first threshold voltage is greater than the second threshold voltage. Here, the invalid level refers to a signal that can cause the activation signal generation circuit to stop working.

[0094] For example, the first threshold voltage is 10V, and the second threshold voltage is 3V. Assume that when the PV source voltage is higher than 10V, the voltage detection circuit output changes from low to high. Without hysteresis, in weak photovoltaic conditions, when the PV starts charging, the voltage will be pulled down below 10V, the voltage detection circuit will output a low level, the PV source will stop charging, and then the PV source voltage will rise above 10V again, causing the voltage detection circuit to continuously switch between high and low levels. If hysteresis is set, when the PV output voltage is higher than 10V, the voltage detection circuit outputs a high level. After the voltage detection circuit outputs a high level, the PV source input voltage remains high between 3V and 10V. Only when the PV source input voltage falls below 3V will the voltage detection circuit output change from high to low. For the voltage detection circuit to change from low to high again, the PV source input voltage needs to rise above 10V.

[0095] For example, the activation control signal has only one bit and is used to control the activation signal generation circuit. In some other embodiments, the activation control signal can have multiple bits, which can not only control the activation signal generation circuit but also control the timing duration.

[0096] In one exemplary embodiment, the voltage detection circuit includes a voltage comparison circuit;

[0097] In one exemplary embodiment, the voltage comparison circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, and an AND gate;

[0098] The voltage comparison circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, and an AND gate;

[0099] The first end of the first resistor is used to connect to the second voltage source, and the second end of the first resistor is connected to the first node;

[0100] The first end of the second resistor is connected to the first node, and the second end of the second resistor is grounded.

[0101] The first end of the third resistor is used to connect to the first voltage source, and the second end of the third resistor is connected to the second node;

[0102] The first end of the fourth resistor is connected to the second node; the second end of the fourth resistor is grounded.

[0103] The first input terminal of the AND gate is connected to the first node, the second input terminal of the AND gate is connected to the second node, and the output terminal of the AND gate is the output terminal of the voltage comparison circuit.

[0104] The first transistor can be turned on or off by its own control electrode. The control electrode of the first transistor can be the gate, the first electrode of the first transistor can be the drain, and the second electrode of the first transistor can be the source; or the first electrode of the first transistor can be the source, and the second electrode of the first transistor can be the drain. For example, the first transistor can be an N-type transistor, with the first electrode being the drain and the second electrode being the source.

[0105] In one exemplary embodiment, the voltage detection circuit includes a voltage comparison circuit;

[0106] The voltage comparison circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a diode, and an AND gate;

[0107] The first end of the first resistor is used to connect to the second voltage source, and the second end of the first resistor is connected to the first node;

[0108] The first end of the second resistor is connected to the first node, and the second end of the second resistor is grounded.

[0109] The anode of the diode is connected to the first voltage source, and the cathode of the diode is connected to the first end of the third resistor;

[0110] The second end of the third resistor is connected to the second node;

[0111] The first end of the fourth resistor is connected to the second node; the second end of the fourth resistor is grounded.

[0112] The first input terminal of the AND gate is connected to the first node, the second input terminal of the AND gate is connected to the second node, and the output terminal of the AND gate is the output terminal of the voltage comparison circuit.

[0113] In this embodiment, the diode is used to prevent the positive and negative terminals of the first voltage source from being reversed.

[0114] In one exemplary embodiment, the voltage comparison circuit further includes a Zener diode;

[0115] The anode of the Zener diode is grounded, and the cathode of the Zener diode is connected to the second node.

[0116] In this embodiment, the Zener diode is used to prevent excessively high input voltage from damaging the input pins of the AND gate.

[0117] In one exemplary embodiment, the voltage detection circuit further includes an output circuit;

[0118] The output circuit includes a fifth resistor, a sixth resistor, and a first transistor;

[0119] The first end of the fifth resistor is used to connect to the second voltage source, and the second end of the fifth resistor is connected to the third node;

[0120] The first end of the sixth resistor is connected to the output terminal of the voltage comparison circuit, and the second end of the sixth resistor is connected to the fourth node;

[0121] The control electrode of the first transistor is connected to the fourth node; the first electrode of the first transistor is connected to the third node; and the second electrode of the first transistor is grounded.

[0122] The third node is connected to the activation signal generation circuit.

[0123] In one exemplary embodiment, the output circuit further includes a seventh resistor and a first capacitor;

[0124] The first end of the seventh resistor is connected to the fourth node, and the second end of the seventh resistor is grounded.

[0125] The first plate of the first capacitor is connected to the fourth node, and the second plate of the first capacitor is grounded.

[0126] In this embodiment, the seventh resistor and the first capacitor are used to prevent interference signals from causing the first transistor to malfunction.

[0127] Figure 2 One of the circuit diagrams of the voltage detection circuit in this disclosure is shown below. Figure 2 As shown, the voltage detection circuit includes a voltage comparison circuit 10 and an output circuit 20.

[0128] The voltage comparator circuit 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and an AND gate Q1;

[0129] The first end of the first resistor R1 is used to connect to the second voltage source U2, and the second end of the first resistor R1 is connected to the first node N1.

[0130] The first end of the second resistor R2 is connected to the first node N1, and the second end of the second resistor R2 is grounded.

[0131] The first end of the third resistor R3 is used to connect to the first voltage source, and the second end of the third resistor R3 is connected to the second node N2.

[0132] The first terminal of the fourth resistor R4 is connected to the second node N2; the second terminal of the fourth resistor R4 is grounded.

[0133] The first input terminal of AND gate Q1 is connected to the first node N1, the second input terminal of AND gate Q1 is connected to the second node N2, and the output terminal of AND gate Q1 is the output terminal of the voltage comparison circuit.

[0134] The output circuit 20 includes a fifth resistor R5, a sixth resistor R6, and a first transistor T1;

[0135] The first end of the fifth resistor R5 is connected to the second voltage source U2, and the second end of the fifth resistor R5 is connected to the third node N3;

[0136] The first end of the sixth resistor R6 is connected to the output of the voltage comparator circuit, and the second end of the sixth resistor R6 is connected to the fourth node N4.

[0137] The control electrode of the first transistor T1 is connected to the fourth node N4, the first electrode of the first transistor T1 is connected to the third node N3, and the second electrode of the first transistor T1 is grounded.

[0138] The third node N3 is connected to the activation signal generation circuit as the output terminal of the output circuit.

[0139] Figure 3 This is a second circuit diagram of the voltage detection circuit according to an embodiment of the present disclosure, as follows: Figure 3 As shown, the voltage detection circuit includes a voltage comparison circuit 10 and an output circuit 20. (The last sentence appears to be incomplete and possibly refers to a different circuit.) Figure 2 The difference in the circuit shown is that diode D1, Zener diode Z1, first capacitor C1, and seventh resistor R7 are added.

[0140] The circuit connections change as follows:

[0141] The anode of diode D1 is connected to the first voltage source, and the cathode of diode D1 is connected to the first terminal of the third resistor R3.

[0142] The anode of Zener diode Z1 is grounded, and the cathode of Zener diode Z1 is connected to the second node N2;

[0143] The first end of the third resistor R3 is connected to the cathode of the diode D1, and the second end of the third resistor R3 is connected to the second node N2.

[0144] The first terminal of the seventh resistor R7 is connected to the fourth node N4, and the second terminal of the seventh resistor R7 is grounded.

[0145] The first plate of the first capacitor C1 is connected to the fourth node N4, and the second plate of the first capacitor C1 is grounded.

[0146] In this embodiment, the diode D1 is used to prevent the input positive and negative terminals of the first voltage source from being reversed.

[0147] The third resistor R3 and the fourth resistor R4 are used to control the voltage threshold for activating the first voltage source.

[0148] The function of Zener diode Z1 is to prevent excessively high input voltage from damaging the input pin of AND gate Q1.

[0149] The first resistor R1 and the second resistor R2 control one of the input pins of the AND gate Q1 to be at a high voltage by dividing the voltage.

[0150] The sixth resistor, R6, serves to limit the current.

[0151] The seventh resistor R7 and the first capacitor C1 are to prevent interference signals from causing the first transistor T1 to malfunction. The first transistor T1 and the fifth resistor R5 are used to control the high and low levels of the subsequent circuits.

[0152] Figure 3 The working mechanism of the circuit shown is as follows: Assume that the high-level voltage threshold of the input signal of AND gate Q1 is U. H The low-level voltage threshold of the input signal to AND gate Q1 is U. L The voltage of the first voltage source U1 is U1, when

[0153] ;

[0154] The input terminal of AND gate Q1, connected to the fourth resistor R4, is high; when

[0155] ;

[0156] The input terminal of AND gate Q1, which is connected to the fourth resistor R4, is at a low level;

[0157] make Where U2 is the voltage of the second voltage source U2, therefore, the input of the AND gate Q1 connected to the first resistor R1 is always high. According to the logic of the AND gate Q1, when the voltage U1 of the first voltage source U1 satisfies... When the AND gate Q1 outputs a high level, the first transistor T1 is turned on, and the voltage detection circuit outputs a low level, which enables the activation signal generation circuit to work. Therefore, the low level output at this time is an effective level. When the voltage U1 of the first voltage source U1 satisfies... When the AND gate Q1 outputs a low level, the first transistor T1 is turned off, and the voltage detection circuit outputs a high level, which can disable the activation signal generation circuit. Therefore, the high level output at this time is an invalid level.

[0158] when The output at this moment is determined by the output of the previous voltage detection circuit. If the output of the previous voltage detection circuit was high, then the output at this moment is high; if the output of the previous voltage detection circuit was low, then the output at this moment is low.

[0159] Figure 4 This is a second schematic diagram of the charging activation circuit according to an embodiment of the present disclosure, as shown below. Figure 4As shown, the charging activation circuit includes a voltage detection circuit, an activation signal generation circuit, a signal holding circuit, and a controller. Figure 1 The charging activation circuit shown is different. Figure 4 The activation signal generation circuit shown includes a frequency divider circuit and a channel selection circuit.

[0160] The activation control signal includes a timing duration control signal; the timing duration control signal is M bits; and M is a natural number.

[0161] The activation signal generation circuit includes a frequency division circuit and a channel selection circuit; the channel selection circuit has... One channel;

[0162] The frequency division circuit is connected to the voltage detection circuit and the channel selection circuit respectively, and is configured to output N square wave signals with different frequencies when the voltage detection circuit outputs an effective level; where N is a natural number.

[0163] The channel selection circuit is connected to the frequency division circuit and the signal holding circuit respectively, and is configured to select the corresponding channel according to the timing duration control signal, and output the square wave signal transmitted by the selected channel as the activation signal.

[0164] Among them, when When N, the Each of the N channels corresponds one-to-one with the N square wave signals;

[0165] when When N, the Each channel and one of the N square wave signals Each square wave signal corresponds to one other.

[0166] The activation control signal also includes a circuit enable control signal;

[0167] The circuit enable control signal is used to control whether the channel selection circuit is working or not.

[0168] The frequency divider circuit first generates a square wave with a fixed frequency of f1 using an RC circuit. The frequency divider circuit then divides f1 to generate... The purpose of frequency division is twofold: First, ordinary hardware circuits cannot generate a square wave with a long period. Frequency division can generate a square wave with a very low frequency. The lower the frequency, the longer the period, and the longer the timing time. For example, a square wave with a period of one hour can be set to delay waking up the device, which ordinary hardware circuits cannot achieve. Second, it generates multiple square waves with different periods. A channel selection circuit can be used to select the required square wave frequency, thereby setting the delay wake-up time.

[0169] For example, the frequency divider circuit is a frequency divider chip. The frequency divider chip may include a static frequency divider, a dynamic frequency divider, a Miller frequency divider, and an injection-locked frequency divider.

[0170] For example, the frequency divider chip can be a CD4060. The CD4060 is a static frequency divider. Figure 5 As shown, the CD4060 frequency divider chip has 16 pins. Pin 16 is connected to the power supply (a photovoltaic power source can be used), pin 12 is for reset, pin 8 is grounded, and pin 11 is connected to a resistor. One end is connected, and pin 10 is connected to the resistor. One end is connected, and pin 9 is connected to the capacitor. One plate connection, resistor At the other end, the resistor The other end is connected to the capacitor. The other electrode is connected. Pin 1 (Q12) is connected to channel A8; pin 2 (Q13) is connected to channel A9 in the channel selection circuit; pin 3 (Q14) is connected to channel A10 in the channel selection circuit; pin 4 (Q6) is connected to channel A3 in the channel selection circuit; pin 5 (Q5) is connected to channel A2 in the channel selection circuit; pin 6 (Q7) is connected to channel A4 in the channel selection circuit; pin 13 (Q9) is connected to channel A6 in the channel selection circuit; pin 14 (Q8) is connected to channel A5 in the channel selection circuit; and pin 15 (Q10) is connected to channel A7 in the channel selection circuit. The frequency divider chip CD4060 is connected via... , , To generate a square wave, where The resistance value is Two to ten times that of the square wave, producing a period of... The square wave period output by pin 7 (Q4) of the frequency divider chip is... The square wave period output by pin 5 (Q5) of the frequency divider chip is... Similarly, the square wave period output by pin 3 (Q14) of the frequency divider chip is... Ten square wave signals with different periods can be generated by a frequency divider circuit. These square wave signals with different periods are then sent to a channel selection circuit, which selects one of them as the activation signal, thereby controlling the wake-up time.

[0171] When the reset pin is high, the frequency divider circuit does not output a square wave signal; when the reset pin is low, it outputs a square wave signal.

[0172] For example, a channel selection circuit is a circuit with multiple inputs and one output. It can be configured to select one of the multiple inputs as the output signal, thereby achieving the purpose of setting different delay times. For example... Figure 6 The channel selection circuit shown is a gating chip. A photovoltaic source (corresponding to the first voltage source mentioned above) can be used as the power supply for the channel selection circuit. Channels A1 to A10 of the gating chip are respectively connected to square wave signals of different frequencies from the frequency divider circuit. Channel selection signals S0 to S3 control which specific signal is sent to the activation signal. Table 1 shows the correspondence between the channel selection signal and the activation signal. Table 1 uses an example where the timing duration control signal has 4 bits and the channel selection circuit has 10 channels. Channel selection signals S0 to S3 correspond to each bit of the timing duration control signal, and the enable signal EN of the channel selection circuit corresponds to the circuit enable control signal. These five signals are all controlled by the activation control signal output by the controller.

[0173] Table 1

[0174]

[0175] In one exemplary embodiment, the timing duration control signal is a multi-bit signal;

[0176] Since the controller output pin cannot output high or low levels after the product enters sleep mode, a circuit is needed to maintain the signal sent by the controller before it entered sleep mode.

[0177] The signal holding circuit includes multiple signal holding units;

[0178] Each of the plurality of signal holding units corresponds one-to-one with each bit of the timing duration control signal.

[0179] That is, each signal holding unit corresponds to one bit in the timing duration control signal.

[0180] Figure 7 This is a schematic diagram of the signal holding unit according to an embodiment of the present disclosure, as shown below. Figure 7 As shown, the signal holding unit includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a second transistor T2, a second capacitor C2, a third capacitor C3, and a third transistor T3.

[0181] The first end of the eighth resistor R8 is connected to the fifth node N5, and the second end of the eighth resistor R8 is connected to the sixth node N6; the fifth node N5 is configured to receive the timing duration control signal.

[0182] The first terminal of the ninth resistor R9 is connected to the sixth node N6, and the second terminal of the ninth resistor R9 is grounded.

[0183] The first plate of the second capacitor C2 is connected to the sixth node N6, and the second plate of the second capacitor C2 is grounded.

[0184] The control electrode of the second transistor T2 is connected to the sixth node N6; the first electrode of the second transistor T2 is connected to the first end of the tenth resistor R10; and the second electrode of the second transistor T2 is grounded.

[0185] The second terminal of the tenth resistor R10 is connected to the eighth node N8;

[0186] The control electrode of the third transistor T3 is connected to the eighth node N8; the first electrode of the third transistor T3 is connected to the seventh node N7; and the second electrode of the third transistor T3 is connected to the ninth node N9.

[0187] The first end of the eleventh resistor R11 is connected to the seventh node N7, and the second end of the eleventh resistor R11 is connected to the eighth node N8.

[0188] The first plate of the third capacitor C3 is connected to the seventh node N7, and the second plate of the third capacitor C3 is connected to the eighth node N8.

[0189] The first end of the twelfth resistor R12 is connected to the ninth node N9, and the second end of the twelfth resistor R12 is grounded.

[0190] The first terminal of the thirteenth resistor R13 is connected to the ninth node N9; the second terminal of the thirteenth resistor R13 is connected to the fifth node N5.

[0191] The ninth node is connected to the channel selection circuit as the output terminal of the signal holding unit.

[0192] Taking the channel selection circuit S0 in the channel selection circuit as an example, the working mechanism of the above signal holding unit is explained. Assume that the second transistor T2 is an N-type transistor, with its control electrode as the gate, its first electrode as the drain, and its second electrode as the source. The third transistor T3 is a P-type transistor, with its control electrode as the gate, its first electrode as the source, and its second electrode as the drain. Before the controller enters sleep mode, the timing duration control signal corresponding to channel selection S0 is at a high level, so the third transistor T3 and the second transistor T2 are turned on, and channel selection S0 becomes high. After the controller enters sleep mode, the controller's control signal pin becomes high-impedance. Since channel selection S0 was already high before the controller entered sleep mode, the high level is fed back to the gate of the second transistor T2 through the thirteenth resistor R13. Even if the controller's control signal disappears, channel selection S0 will still maintain a high level. Similarly, before the controller enters sleep mode, the timing duration control signal corresponding to channel selection S0 is low, and when the controller enters sleep mode, channel selection S0 still maintains a low level.

[0193] For example, the third voltage source U3 can obtain electrical energy from the first voltage source.

[0194] This disclosure also provides a photovoltaic charging system, including:

[0195] Photovoltaic input source;

[0196] Device to be activated;

[0197] The charging activation circuit described in any of the above embodiments; the photovoltaic input source serves as the first voltage source in the charging activation circuit.

[0198] The controller in the charging activation circuit can be a control chip. This control chip can be a microcontroller (MCU), a microprocessor (MPU), a system-on-a-chip (SoC), a motion control chip, or other dedicated control chips such as digital signal processors or industrial control chips.

[0199] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0200] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0201] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0202] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0203] In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0204] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0205] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0206] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0207] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A charging activation circuit, applied to a device to be charged, characterized in that, include: The controller is configured to set an activation control signal when the device to be charged is turned off, and then go into sleep mode after sending the activation control signal to the signal holding circuit; The activation control signal includes a timing duration control signal; the timing duration control signal is used to set the delayed wake-up time. The signal holding circuit is connected to the controller and is configured to hold the active control signal; The voltage detection circuit is configured to acquire the voltage of a first voltage source, and output an effective level when the voltage of the first voltage source meets a first condition; the effective level refers to the level that enables the activation signal generation circuit to operate. The activation signal generation circuit is connected to the voltage detection circuit and the signal holding circuit respectively, and is configured to generate an activation signal and send it to the controller when the voltage detection circuit outputs an effective level, based on the activation control signal held by the signal holding circuit. The controller is further configured to wake up whenever it receives the activation signal, and when it determines that the charging conditions are met, control the first voltage source to charge the device to be charged; when it determines that the charging conditions are not met and prepares to hibernate again, it sets the activation control signal again, and sends the newly set activation control signal to the signal holding circuit before hibernating.

2. The charging activation circuit as described in claim 1, characterized in that, The timing duration control signal is M bits; where M is a natural number. The activation signal generation circuit includes a frequency division circuit and a channel selection circuit; the channel selection circuit has... One channel; The frequency division circuit is connected to the voltage detection circuit and the channel selection circuit respectively, and is configured to output N square wave signals with different frequencies when the voltage detection circuit outputs an effective level; where N is a natural number. The channel selection circuit is connected to the frequency division circuit and the signal holding circuit respectively, and is configured to select the corresponding channel according to the timing duration control signal, and output the square wave signal transmitted by the selected channel as the activation signal. Among them, when When N, the Each of the N channels corresponds one-to-one with the N square wave signals; when When N, the Each channel and one of the N square wave signals Each square wave signal corresponds to one other.

3. The charging activation circuit as described in claim 2, characterized in that, The activation control signal also includes a circuit enable control signal; The circuit enable control signal is used to control whether the channel selection circuit is working or not.

4. The charging activation circuit as described in claim 1 or 2, characterized in that, The first condition includes the voltage of the first voltage source increasing to be greater than or equal to the first threshold voltage, and the voltage of the first voltage source decreasing to be less than the first threshold voltage but greater than the second threshold voltage. The voltage detection circuit is further configured to output an invalid level when the voltage of the first voltage source meets a second condition; the second condition includes the voltage of the first voltage source increasing to be greater than the second threshold voltage and less than the first threshold voltage, and the voltage of the first voltage source decreasing to be less than the second threshold voltage; the invalid level refers to the level that makes the activation signal generation circuit not work.

5. The charging activation circuit as described in claim 4, characterized in that, The voltage detection circuit includes a voltage comparison circuit; The voltage comparison circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, and an AND gate; The first end of the first resistor is used to connect to the second voltage source, and the second end of the first resistor is connected to the first node; The first end of the second resistor is connected to the first node, and the second end of the second resistor is grounded. The first end of the third resistor is used to connect to the first voltage source, and the second end of the third resistor is connected to the second node; The first end of the fourth resistor is connected to the second node; the second end of the fourth resistor is grounded. The first input terminal of the AND gate is connected to the first node, the second input terminal of the AND gate is connected to the second node, and the output terminal of the AND gate is the output terminal of the voltage comparison circuit.

6. The charging activation circuit as described in claim 4, characterized in that, The voltage detection circuit includes a voltage comparison circuit; The voltage comparison circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a diode, and an AND gate; The first end of the first resistor is used to connect to the second voltage source, and the second end of the first resistor is connected to the first node; The first end of the second resistor is connected to the first node, and the second end of the second resistor is grounded. The anode of the diode is connected to the first voltage source, and the cathode of the diode is connected to the first end of the third resistor; The second end of the third resistor is connected to the second node; The first end of the fourth resistor is connected to the second node; the second end of the fourth resistor is grounded. The first input terminal of the AND gate is connected to the first node, the second input terminal of the AND gate is connected to the second node, and the output terminal of the AND gate is the output terminal of the voltage comparison circuit.

7. The charging activation circuit as described in claim 5 or 6, characterized in that, The voltage comparison circuit also includes a Zener diode; The anode of the Zener diode is grounded, and the cathode of the Zener diode is connected to the second node.

8. The charging activation circuit as described in claim 5 or 6, characterized in that, The voltage detection circuit also includes an output circuit; The output circuit includes a fifth resistor, a sixth resistor, and a first transistor; The first end of the fifth resistor is used to connect to the second voltage source, and the second end of the fifth resistor is connected to the third node; The first end of the sixth resistor is connected to the output end of the voltage comparison circuit, and the second end of the sixth resistor is connected to the fourth node; The control electrode of the first transistor is connected to the fourth node; the first electrode of the first transistor is connected to the third node; and the second electrode of the first transistor is grounded. The third node is connected to the activation signal generation circuit.

9. The charging activation circuit as described in claim 8, characterized in that, The output circuit also includes a seventh resistor and a first capacitor; The first end of the seventh resistor is connected to the fourth node, and the second end of the seventh resistor is grounded. The first plate of the first capacitor is connected to the fourth node, and the second plate of the first capacitor is grounded.

10. The charging activation circuit as described in claim 2, characterized in that, The frequency divider circuit is a frequency divider chip.

11. The charging activation circuit as described in claim 2, characterized in that, The timing duration control signal is multi-bit; The signal holding circuit includes multiple signal holding units; Each of the plurality of signal holding units corresponds one-to-one with each bit of the timing duration control signal.

12. The charging activation circuit as described in claim 11, characterized in that, The signal holding unit includes an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a second transistor, a second capacitor, a third capacitor, and a third transistor; The first end of the eighth resistor is connected to the fifth node, and the second end of the eighth resistor is connected to the sixth node; the fifth node is configured to receive the timing duration control signal. The first end of the ninth resistor is connected to the sixth node, and the second end of the ninth resistor is grounded; The first plate of the second capacitor is connected to the sixth node, and the second plate of the second capacitor is grounded. The control electrode of the second transistor is connected to the sixth node, the first electrode of the second transistor is connected to the first terminal of the tenth resistor, and the second electrode of the second transistor is grounded. The second end of the tenth resistor is connected to the eighth node; The control electrode of the third transistor is connected to the eighth node; the first electrode of the third transistor is connected to the seventh node; the second electrode of the third transistor is connected to the ninth node; the seventh node is configured to be connected to a third voltage source. The first end of the eleventh resistor is connected to the seventh node, and the second end of the eleventh resistor is connected to the eighth node; The first plate of the third capacitor is connected to the seventh node, and the second plate of the third capacitor is connected to the eighth node; The first end of the twelfth resistor is connected to the ninth node, and the second end of the twelfth resistor is grounded; The first end of the thirteenth resistor is connected to the ninth node; the second end of the thirteenth resistor is connected to the fifth node; The ninth node is connected to the channel selection circuit as the output terminal of the signal holding unit.

13. A photovoltaic charging system, characterized in that, include: Photovoltaic input source; Device to be activated; The charging activation circuit as described in any one of claims 1-12; The photovoltaic input source serves as the first voltage source in the charging activation circuit.

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