A boost circuit based on COT modulation

Abstract

The application discloses a BOOST voltage boosting circuit based on COT modulation and belongs to the field of switching power supplies and power management integrated circuits. In view of the problem that low equivalent series resistance of an output capacitor leads to low-frequency oscillation of COT control, a ripple injection compensation scheme is provided, a compensation triangular wave is generated by filtering a switching node signal and is injected into a feedback node to stabilize the control loop. Meanwhile, an LDO gate drive cooperative startup scheme is designed, input voltage is used to supply power for gate drive in a pass-through mode in a startup stage, and reliable startup of the system is ensured. In addition, two switching node oscillation compensation schemes are provided, a next conduction period is triggered in time through detection of a falling edge or voltage comparison, oscillation is effectively inhibited, and the load capacity and transient response of the system are optimized. The application significantly improves the stability and reliability of the BOOST circuit in the COT architecture under the condition of low ESR.

Description

Technical Field

[0001] This invention relates to the field of power management integrated circuit technology, and in particular to a BOOST boost circuit based on COT modulation. Background Technology

[0002] Boost-type switching power supplies are widely used in power management units (PMUs) to boost low-voltage inputs to high-voltage outputs to drive subsequent circuits. Constant On-Time (COT) control is widely adopted due to its fast response and simple control structure. However, COT control relies on output voltage ripple as the basis for determining turn-on and turn-off. When the equivalent series resistance (ESR) of the output capacitor is low, the resistive ripple of the ESR at the feedback node is covered by capacitive ripple, resulting in phase lag. The controller cannot correctly determine the turn-off time, thus generating low-frequency oscillations, manifested as periodic fluctuations in the output voltage.

[0003] In discrete power supplies, this problem can be eliminated by selecting capacitors with appropriate ESR. However, in integrated circuit designs, output capacitors are often low-ESR ceramic capacitors, which are difficult to provide resistive ripple of sufficient amplitude. Therefore, traditional methods are prone to instability under COT modulation, and existing solutions such as analog slope compensation or pseudo-ripple injection are often complex, power-consuming, or difficult to adapt.

[0004] Furthermore, there are generally two approaches to powering the BOOST driver module. One is to directly use the BOOST input as the driver power supply. This approach is simple and easy to implement, but when the input voltage varies significantly, it has a large impact on the on-resistance of the power transistor. The other approach is to use the BOOST output to generate a suitable power supply via an LDO. In this approach, during the BOOST startup phase, the power transistor gate requires a drive voltage to turn on, but the output voltage has not yet been established, making it difficult to achieve a stable power supply and easily leading to startup failure. In addition, the traditional approach of using an external driver increases system cost and complexity, making it unsuitable for integrated implementation.

[0005] Meanwhile, due to parasitic capacitance and inductance, the SW node will generate high-frequency oscillation after the falling edge ends during the switching instant. In CCM mode, this affects the transient response and load capacity, and in the startup phase, it affects the system power-on completion time. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a BOOST boost circuit based on COT modulation to suppress low-frequency oscillations under low ESR conditions and reduce the impact of SW node oscillations on the system.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] A BOOST boost circuit based on COT modulation includes: a reference and voltage / current bias module BG / BIAS, a soft-start module SS, an error amplifier EA, a comparator CMP, a control module CTRLER, a timing module Timer, a power transistor drive module DRIVER, a feedback module FB, a ripple injection module Rippie injection module LDO, a node detection module SWER, an overcurrent detection module OCP, and an output circuit.

[0009] The reference and voltage / current bias module BG / BIAS is connected to the soft-start module SS. The output of the soft-start module SS is connected to the non-inverting input of the error amplifier EA. The inverting input of the error amplifier EA is connected to the output of the feedback module FB. The output of the error amplifier EA is connected to the non-inverting input of the comparator CMP. The inverting input of the comparator CMP is connected to the output of the feedback module FB. The output of the comparator CMP is connected to the first input of the control module CTRLER and the first input of the timing module Timer. The second input of the timing module Timer is connected to the output of the overcurrent detection module OCP. The first and second outputs of the timing module Timer are correspondingly connected to the second and third inputs of the control module CTRLER. The output of the control module CTRLER is connected to the first input of the power transistor driver module DRIVER. The output of the power transistor driver module DRIVER is connected to the first terminal of the output circuit.

[0010] The second terminal of the output circuit is used to output voltage VOUT, and is also connected to the first input terminal of the drive power supply module LDO and the first input terminal of the feedback module FB. The second input terminal of the drive power supply module LDO is connected to the input voltage terminal VIN. The third terminal of the output circuit is the SW node, which is connected to the input terminal of the node detection module SWER and the input terminal of the ripple injection module Rippie injection. The first output terminal of the node detection module SWER is connected to the input terminal of the overcurrent detection module OCP. The second, third, and fourth output terminals of the node detection module SWER are respectively connected to the fourth, fifth, and sixth input terminals of the control module CTRLER. The output terminal of the ripple injection module Rippie injection is connected to the second input terminal of the feedback module FB.

[0011] Furthermore, the feedback module FB includes a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

[0012] The first voltage divider resistor and the second voltage divider resistor are connected in series. The other end of the first voltage divider resistor is connected to the output voltage VOUT, and the other end of the second voltage divider resistor is grounded. The fourth capacitor is connected in parallel across the first voltage divider resistor. The first capacitor and the third voltage divider resistor are connected in series. The other end of the first capacitor is connected to the SW node, and the other end of the third voltage divider resistor is grounded. The second capacitor is connected in parallel across the third voltage divider resistor. One end of the third capacitor is connected to the connection node VBF between the first and second voltage divider resistors, and the other end of the third capacitor is connected between the third voltage divider resistor and the first capacitor.

[0013] Furthermore, the output circuit includes a power transistor, a diode, an inductor, and a capacitor;

[0014] The gate of the power transistor is connected to the output terminal of the power transistor driver module (DRIVER), the source of the power transistor is grounded, the drain of the power transistor is connected to the SW node, the SW node is also connected to the anode of the diode and one end of the inductor, the other end of the inductor is connected to the input voltage terminal VIN, and the cathode of the diode is grounded through a capacitor; the cathode of the diode is used for the output voltage VOUT, which is connected to the first input terminal of the drive power supply module (LDO) and the first input terminal of the feedback module (FB).

[0015] Furthermore, when the LDO drive power supply module starts up, since the VOUT voltage is low, VIN is used to power the LDO drive power supply module. The LDO drive power supply module outputs VIN directly to the power transistor drive module DRIVER in a pass-through mode to power the power transistor drive, thus passing the input voltage VIN of the LDO drive power supply module directly to the output. As the output voltage continues to increase, when it reaches the set value, VOUT powers the LDO drive power supply module, and the LDO outputs a normal voltage of 5V to power the power transistor drive module DRIVER.

[0016] Furthermore, in the direct-through mode, the power transistor is a native transistor, a PMOS transistor, or a Schottky diode.

[0017] Furthermore, the node detection module SWER includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first resistor, a second resistor, a third resistor, a capacitor C1, a first inverter, a second inverter, a first comparator, a second comparator, a first AND gate, and a second AND gate;

[0018] The drains of the first and second PMOS transistors are both connected to the sw node. The source of the first PMOS transistor is connected to the drain of the third PMOS transistor, the inverting input of the first comparator, and one end of the first resistor. The source of the second PMOS transistor is connected to the drain of the fourth PMOS transistor and the non-inverting input of the second comparator. The sources of the third and fourth PMOS transistors and the other end of the first resistor are all grounded. The gate of the first PMOS transistor is connected to the gate of the fourth PMOS transistor, the gate of the first NMOS transistor, and the second input of the first AND gate. The gate of the second PMOS transistor is connected to the gate of the third PMOS transistor and the second input of the second AND gate.

[0019] One end of capacitor C1 is connected to the sw node, and the other end of capacitor C1 is connected to one end of the second resistor and one end of the third resistor. The other end of the second resistor is connected to the power supply, and the other end of the third resistor is connected to the drain of the fifth PMOS transistor and the drain of the second NMOS transistor. The gate and source of the fifth PMOS transistor are interconnected and also connected to the power supply and the source of the first NMOS transistor. The gate and source of the second NMOS transistor are interconnected and grounded. The drain of the first NMOS transistor is connected to the drain of the fifth PMOS transistor and the input terminal of the first inverter. The output terminal of the first inverter is connected in series with the second inverter to output the first voltage LGC_SWCR.

[0020] The output of the first comparator is connected to the first input of the first AND gate, and the output of the first AND gate outputs the second voltage LGC_SWL. The output of the second comparator is connected to the first input of the second AND gate, and the output of the second AND gate outputs the third voltage LGC_SWH.

[0021] The beneficial effects of this invention are:

[0022] The BOOST circuit of this invention can achieve stable operation of COT control under low ESR load capacitance, significantly improving the low-frequency oscillation phenomenon of output voltage caused by low ESR load capacitance; the cooperative startup scheme of LDO gate drive ensures gate drive power supply during startup; the oscillation compensation scheme of SW node optimizes the system's load capacity, transient response and startup time. Attached Figure Description

[0023] Figure 1 This is a system block diagram of a BOOST boost circuit based on COT modulation;

[0024] Figure 2 Schematic diagram of the ripple injection compensation circuit for the feedback module FB;

[0025] Figure 3 A schematic diagram showing the two operating modes of the LDO (Low-Density Logic Controller) power supply module;

[0026] Figure 4 This is the circuit schematic of the SWER node detection module. Detailed Implementation

[0027] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] See Figures 1-4 The present invention provides a technical solution:

[0029] A BOOST boost circuit based on COT modulation is shown in the system block diagram below. Figure 1 As shown, it includes: a reference and voltage / current bias module BG / BIAS, a soft-start module SS, an error amplifier EA, a comparator CMP, a control module CTRLER, a timing module Timer, a power transistor drive module DRIVER, a feedback module FB, a ripple injection module Rippie injection module LDO, a node detection module SWER, an overcurrent detection module OCP, and an output circuit. Figure 1 The area within the dashed box represents the on-chip design, while the area outside the dashed box represents off-chip components.

[0030] The chip includes: a reference and voltage / current bias module (BG / BIAS) providing a reference voltage (VREF) and voltage and current bias (IREF) for the entire chip; a soft-start module (SS) to prevent excessive inrush current during BOOST startup and provide a reference (VREF_SS) for the BOOST feedback signal; an error amplifier (EA) to amplify the error of the BOOST loop feedback signal (VFB); a comparator (CMP) to compare the output (EAO) of EA with the feedback signal (VFB); a control module (CTRLER) to provide logic control for the BOOST loop; a timing module (Timer) in the COT control, generating the on-time signal (Ton) and the minimum off-time signal (Toff_min); an overcurrent detection module (OCP) to report an overcurrent and use it as the logic control input for the timing module; and a ripple injection module to compensate for ripple and stabilize the control loop.

[0031] Specifically, the reference and voltage / current bias module BG / BIAS is connected to the soft-start module SS. The output of the soft-start module SS is connected to the non-inverting input of the error amplifier EA. The inverting input of the error amplifier EA is connected to the output of the feedback module FB. The output of the error amplifier EA is connected to the non-inverting input of the comparator CMP. The inverting input of the comparator CMP is connected to the output of the feedback module FB. The output of the comparator CMP is connected to the first input of the control module CTRLER and the first input of the timing module Timer. The second input of the timing module Timer is connected to the output of the overcurrent detection module OCP. The first and second outputs of the timing module Timer are correspondingly connected to the second and third inputs of the control module CTRLER. The output of the control module CTRLER is connected to the first input of the power transistor drive module DRIVER. The output of the power transistor drive module DRIVER is connected to the first terminal of the output circuit.

[0032] The second terminal of the output circuit is used to output voltage VOUT, and is also connected to the first input terminal of the drive power supply module LDO and the first input terminal of the feedback module FB. The second input terminal of the drive power supply module LDO is connected to the input voltage terminal VIN. The third terminal of the output circuit is the SW node, which is connected to the input terminal of the node detection module SWER and the input terminal of the ripple injection module Rippie injection. The first output terminal of the node detection module SWER is connected to the input terminal of the overcurrent detection module OCP. The second, third, and fourth output terminals of the node detection module SWER are respectively connected to the fourth, fifth, and sixth input terminals of the control module CTRLER. The output terminal of the ripple injection module Rippie injection is connected to the second input terminal of the feedback module FB.

[0033] The schematic diagram of the feedback module FB ripple injection compensation circuit in this embodiment is as follows: Figure 2 As shown, the feedback module FB includes a first voltage divider resistor RF1, a second voltage divider resistor RF2, a third voltage divider resistor R1, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4.

[0034] The first voltage divider resistor and the second voltage divider resistor are connected in series. The other end of the first voltage divider resistor is connected to the output voltage VOUT, and the other end of the second voltage divider resistor is grounded. The fourth capacitor is connected in parallel across the first voltage divider resistor. The first capacitor and the third voltage divider resistor are connected in series. The other end of the first capacitor is connected to the SW node, and the other end of the third voltage divider resistor is grounded. The second capacitor is connected in parallel across the third voltage divider resistor. One end of the third capacitor is connected to the connection node VBF between the first and second voltage divider resistors, and the other end of the third capacitor is connected between the third voltage divider resistor and the first capacitor.

[0035] Traditional feedback modules consist only of voltage dividers RF1 and RF2. In this embodiment, the feedback module FB introduces ripple injection compensation, the specific principle of which is as follows: Capacitor C4 is connected in parallel across the first voltage divider resistor RF1 to feed the ripple phase of VOUT forward to the VFB node, compensating for the ripple phase lag caused by capacitive ripple; the square wave of the SW node is divided by capacitors C1 and C2 to obtain a square wave of appropriate amplitude, and then the triangular AC component in phase with the resistive ripple is coupled to the VFB node through capacitor C3. In addition, the first resistor of the third voltage divider is a large-value resistor, the purpose of which is to ensure that the DC voltage component of the node between C1 and C2 is 0V, thus compensating for the ripple phase of the VFB node and ensuring the stability of COT modulation.

[0036] This invention utilizes the SW node signal of BOOST for filtering, and filters the square wave into a triangular wave with the same phase as the ESR resistive ripple by passing it through an RC filter (composed of the third voltage divider, the first resistor, and the first capacitor C1). The AC component is injected into the feedback node to compensate for the lack of resistive ripple, ensuring that no low-frequency oscillation occurs in COT mode.

[0037] In this embodiment, the output circuit includes a power transistor (POWERMOS), a diode, an inductor, and a capacitor. The gate of the power transistor is connected to the output terminal of the power transistor driver module (DRIVER), the source of the power transistor is grounded (POWERGND), the drain of the power transistor is connected to the SW node, the SW node is also connected to the anode of the diode and one end of the inductor, the other end of the inductor is connected to the input voltage terminal (VIN), and the cathode of the diode is grounded through a capacitor. The cathode of the diode is used for the output voltage (VOUT), which is connected to the first input terminal of the drive power supply module (LDO) and the first input terminal of the feedback module (FB).

[0038] The operating mode of the LDO drive power supply module is as follows Figure 3 As shown in the figure, there are two working scenarios. In the embodiment, the input voltage VIN of the BOOST circuit is set to 3.7V, and the output voltage VOUT is 30V. When the LDO driver power supply module starts up, since the VOUT voltage is low, VIN is used to power the LDO driver power supply module. The LDO driver power supply module outputs VIN directly to the DRIVER power transistor driver module in a pass-through mode to power the power transistor. The input voltage VIN of the LDO driver power supply module is directly passed to the output terminal POWER. As the output voltage continues to increase, when it reaches the set value, VOUT powers the LDO driver power supply module. The output terminal POWER of the LDO normally outputs a 5V voltage to power the DRIVER power transistor driver module.

[0039] Optionally, in the direct-through mode, the power transistor is a native transistor, a PMOS transistor, or a Schottky diode.

[0040] The node detection module SWER structure is as follows: Figure 4 As shown, it includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first resistor R1, a second resistor R2, a third resistor R3, a capacitor C1, a first inverter, a second inverter, a first comparator, a second comparator, a first AND gate, and a second AND gate.

[0041] The drains of the first and second PMOS transistors are both connected to the sw node. The source of the first PMOS transistor is connected to the drain of the third PMOS transistor, the inverting input of the first comparator, and one end of the first resistor. The source of the second PMOS transistor is connected to the drain of the fourth PMOS transistor and the non-inverting input of the second comparator. The sources of the third and fourth PMOS transistors and the other end of the first resistor are all grounded. The gate of the first PMOS transistor is connected to the gate of the fourth PMOS transistor, the gate of the first NMOS transistor, and the second input of the first AND gate. The gate of the second PMOS transistor is connected to the gate of the third PMOS transistor and the second input of the second AND gate.

[0042] One end of capacitor C1 is connected to the sw node, and the other end of capacitor C1 is connected to one end of the second resistor and one end of the third resistor. The other end of the second resistor is connected to the power supply, and the other end of the third resistor is connected to the drain of the fifth PMOS transistor and the drain of the second NMOS transistor. The gate and source of the fifth PMOS transistor are interconnected and also connected to the power supply and the source of the first NMOS transistor. The gate and source of the second NMOS transistor are interconnected and grounded. The drain of the first NMOS transistor is connected to the drain of the fifth PMOS transistor and the input terminal of the first inverter. The output terminal of the first inverter is connected in series with the second inverter to output the first voltage LGC_SWCR.

[0043] The output of the first comparator is connected to the first input of the first AND gate, and the output of the first AND gate outputs the second voltage LGC_SWL. The output of the second comparator is connected to the first input of the second AND gate, and the output of the second AND gate outputs the third voltage LGC_SWH.

[0044] Reference Figure 4The circuit principle of the SWER node detection module is as follows: VGATE is the gate drive voltage of the power transistor, and VGATEB is inverted compared to VGATE. When the gate drive voltage of the power transistor is low, the SW node voltage is VOUT + Vdiode, that is, the output voltage plus the forward voltage drop of the diode. At this time, the transistor in the SWL branch is turned on, and the voltage of the SWL node is the same as that of the SW node. When the gate drive voltage of the power transistor is high, the SW node voltage is 0V. At this time, the transistor in the SWH branch is turned on, and the voltage of the SWH node is the same as that of the SW node. When the SW node is on the falling edge, the SWCR node goes low, and then LGC_SWCR is pulled low, and the control module CTRLER enters the next working cycle in time. In addition, the SWL node is compared with VTHSWL at the comparator terminal. When the SWL voltage is lower than VTHSWL, and VGATEB is high, LGC_SWL is pulled high, and the control module CTRLER enters the next working cycle in time. These two methods can reduce the impact of SW node oscillation on the system. In addition, the CTRLER circuit includes an optional counter that allows LGC_SWL and LGC_SWCR to be modulated using several high and low level pulses. The SWER circuit incorporates an overcurrent detection function, implemented by comparing SWH with a preset threshold VTHSWH. When SWH exceeds VTHSWH, LGC_SWH is pulled high, and an overcurrent signal is reported to the OCP module.

[0045] Since the oscillation of the SW node generates negative current, reducing the load-carrying capacity of the BOOST, and voltage oscillation also generates interference, the design of the SWER node detection module can provide two compensation schemes to address the oscillation of the SW node:

[0046] The first method is an edge detection scheme. When a falling edge is detected at the SW node, the control signal LGC_SWCR is pulled low to enable the power transistor to enter the next Ton time in a timely manner. This reduces the impact of the oscillation after the falling edge of the SW node on the load capacity and transient response. In addition, through a configurable counter module, the number of oscillations after the falling edge of the SW node can be controlled to enable the power transistor to enter the next Ton time.

[0047] The second method is a level detection scheme, which directly uses a comparator to detect the voltage of the SW node. When the voltage of the SW node is lower than the threshold voltage VTHSWL, the signal LGC_SWL is pulled high, so that the power transistor enters the next Ton time in time, thereby reducing the impact of the oscillation after the falling edge of the SW node on the load capacity and transient response.

[0048] This invention addresses the problem of low-frequency oscillations in COT control caused by the low equivalent series resistance of the output capacitor. It proposes a ripple injection compensation scheme, which generates a compensation triangular wave by filtering the switching node signal (sw) and injecting it into the feedback node to stabilize the control loop. Simultaneously, an LDO gate drive collaborative startup scheme is designed, utilizing the input voltage to power the gate drive during the startup phase in a pass-through mode, ensuring reliable system startup. Furthermore, two switching node oscillation compensation schemes are provided, which promptly trigger the next conduction cycle by detecting the falling edge or voltage comparison, effectively suppressing oscillations and optimizing the system's load capacity and transient response.

[0049] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A BOOST boost circuit based on COT modulation, comprising: The reference and voltage / current bias module BG / BIAS, the soft-start module SS, the error amplifier EA, the comparator CMP, the control module CTRLER, the timing module Timer, and the power transistor drive module DRIVER are characterized by further including a feedback module FB, a ripple injection module Rippie injection module LDO, a drive power supply module SWER, an overcurrent detection module OCP, and an output circuit. The reference and voltage / current bias module BG / BIAS is connected to the soft-start module SS. The output of the soft-start module SS is connected to the non-inverting input of the error amplifier EA. The inverting input of the error amplifier EA is connected to the output of the feedback module FB. The output of the error amplifier EA is connected to the non-inverting input of the comparator CMP. The inverting input of the comparator CMP is connected to the output of the feedback module FB. The output of the comparator CMP is connected to the first input of the control module CTRLER and the first input of the timing module Timer. The second input of the timing module Timer is connected to the output of the overcurrent detection module OCP. The first and second outputs of the timing module Timer are correspondingly connected to the second and third inputs of the control module CTRLER. The output of the control module CTRLER is connected to the first input of the power transistor driver module DRIVER. The output of the power transistor driver module DRIVER is connected to the first terminal of the output circuit. The second terminal of the output circuit is used to output voltage VOUT, and is also connected to the first input terminal of the drive power supply module LDO and the first input terminal of the feedback module FB. The second input terminal of the drive power supply module LDO is connected to the input voltage terminal VIN. The third terminal of the output circuit is the SW node, which is connected to the input terminal of the node detection module SWER and the input terminal of the ripple injection module Rippie injection. The first output terminal of the node detection module SWER is connected to the input terminal of the overcurrent detection module OCP. The second, third, and fourth output terminals of the node detection module SWER are respectively connected to the fourth, fifth, and sixth input terminals of the control module CTRLER. The output terminal of the ripple injection module Rippie injection is connected to the second input terminal of the feedback module FB.

2. The BOOST boost circuit based on COT modulation according to claim 1, characterized in that: The feedback module FB includes a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The first voltage divider resistor and the second voltage divider resistor are connected in series. The other end of the first voltage divider resistor is connected to the output voltage VOUT, and the other end of the second voltage divider resistor is grounded. The fourth capacitor is connected in parallel across the first voltage divider resistor. The first capacitor and the third voltage divider resistor are connected in series. The other end of the first capacitor is connected to the SW node, and the other end of the third voltage divider resistor is grounded. The second capacitor is connected in parallel across the third voltage divider resistor. One end of the third capacitor is connected to the connection node VBF between the first and second voltage divider resistors, and the other end of the third capacitor is connected between the third voltage divider resistor and the first capacitor.

3. The BOOST boost circuit based on COT modulation according to claim 1, characterized in that: The output circuit includes a power transistor, a diode, an inductor, and a capacitor; The gate of the power transistor is connected to the output terminal of the power transistor driver module (DRIVER), the source of the power transistor is grounded, the drain of the power transistor is connected to the SW node, the SW node is also connected to the anode of the diode and one end of the inductor, the other end of the inductor is connected to the input voltage terminal VIN, and the cathode of the diode is grounded through a capacitor; the cathode of the diode is used for the output voltage VOUT, which is connected to the first input terminal of the drive power supply module (LDO) and the first input terminal of the feedback module (FB).

4. The BOOST boost circuit based on COT modulation according to claim 3, characterized in that: When the LDO driver module starts up, since the VOUT voltage is low, VIN is used to power the LDO driver module. The LDO driver module outputs VIN directly to the power transistor driver module (DRIVER) in a pass-through mode to power the power transistors. The input voltage VIN of the LDO driver module is passed directly to the output. As the output voltage increases, when it reaches the set value, VOUT powers the LDO driver module. The LDO outputs a normal voltage of 5V to power the power transistor driver module (DRIVER).

5. A BOOST boost circuit based on COT modulation according to claim 4, characterized in that: In the direct-through mode, the power transistor is a native transistor, a PMOS transistor, or a Schottky diode.

6. A BOOST boost circuit based on COT modulation according to claim 1, characterized in that: The node detection module SWER includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first resistor, a second resistor, a third resistor, a capacitor C1, a first inverter, a second inverter, a first comparator, a second comparator, a first AND gate, and a second AND gate; The drains of the first and second PMOS transistors are both connected to the sw node. The source of the first PMOS transistor is connected to the drain of the third PMOS transistor, the inverting input of the first comparator, and one end of the first resistor. The source of the second PMOS transistor is connected to the drain of the fourth PMOS transistor and the non-inverting input of the second comparator. The sources of the third and fourth PMOS transistors and the other end of the first resistor are all grounded. The gate of the first PMOS transistor is connected to the gate of the fourth PMOS transistor, the gate of the first NMOS transistor, and the second input of the first AND gate. The gate of the second PMOS transistor is connected to the gate of the third PMOS transistor and the second input of the second AND gate. One end of capacitor C1 is connected to the sw node, and the other end of capacitor C1 is connected to one end of the second resistor and one end of the third resistor. The other end of the second resistor is connected to the power supply, and the other end of the third resistor is connected to the drain of the fifth PMOS transistor and the drain of the second NMOS transistor. The gate and source of the fifth PMOS transistor are interconnected and also connected to the power supply and the source of the first NMOS transistor. The gate and source of the second NMOS transistor are interconnected and grounded. The drain of the first NMOS transistor is connected to the drain of the fifth PMOS transistor and the input terminal of the first inverter. The output terminal of the first inverter is connected in series with the second inverter to output the first voltage LGC_SWCR. The output of the first comparator is connected to the first input of the first AND gate, and the output of the first AND gate outputs the second voltage LGC_SWL. The output of the second comparator is connected to the first input of the second AND gate, and the output of the second AND gate outputs the third voltage LGC_SWH.

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