Local oscillator output circuit and short-wave superheterodyne receiver

Abstract

The invention belongs to the technical field of local oscillator signal output, and particularly discloses a local oscillator output circuit and a short-wave superheterodyne receiver. A single crystal oscillator harmonic generation architecture is adopted to replace a traditional multi-PLL scheme, all local oscillator signals are from a reference clock of the same high-frequency crystal oscillator and harmonic waves of the reference clock, the homologous characteristic ensures frequency coherence between the signals, and stray and phase noise generated by mutual traction of a plurality of independent PLLs are eliminated fundamentally. The fundamental frequency higher than 30MHz is selected and the higher harmonics of the fundamental frequency are utilized, so that the fundamental frequency and the output frequency of each stage of local oscillator are located outside the short wave receiving frequency band, and the sensitivity of the receiver is not influenced by any circuit leakage. Meanwhile, the three-stage local oscillator signal naturally forms a frequency interval of more than two octaves based on the harmonic relation, so that the inter-stage mirror image interference frequency is far away from each other and can be effectively suppressed through simple filtering. According to the scheme, dual suppression of local oscillator leakage and mirror image interference is systematically realized while the circuit structure is simplified finally.

Description

Technical Field

[0001] This application belongs to the field of local oscillator signal output technology, specifically relating to a local oscillator output circuit and a shortwave superheterodyne receiver. Background Technology

[0002] Shortwave communication refers to wireless communication using radio waves in the 3MHz to 30MHz frequency band, primarily relying on ionospheric reflection for long-distance transmission. This communication technology boasts significant advantages such as wide coverage, simple equipment, and strong resilience, playing an irreplaceable role in military, emergency communications, and maritime and aviation fields. The main technical challenges facing shortwave communication include ionospheric instability, narrowband interference, and multipath effects. Solutions include adaptive frequency hopping, digital signal processing (DSP) filtering, and diversity reception technologies.

[0003] A shortwave superheterodyne receiver is a classic radio receiving device widely used in shortwave communications. Its core operating principle involves mixing the received radio frequency (RF) signal with the local oscillator signal using a mixer, converting it into a fixed intermediate frequency (IF) signal (typically 455 kHz or 9 MHz). This IF signal is then amplified and filtered by an IF amplifier. The main advantage of this architecture is that a highly selective filter can be designed using a fixed IF, significantly improving the receiver's sensitivity and interference immunity.

[0004] Modern shortwave superheterodyne receivers commonly employ phase-locked loop (PLL) frequency synthesis technology to provide a stable local oscillator signal. The key advantages of this receiver architecture include excellent selectivity, high sensitivity, and good overload resistance, making it particularly suitable for operation in complex electromagnetic environments. However, due to its three-channel architecture, it suffers from drawbacks such as local oscillator leakage, image interference, slow frequency switching speed, and insufficient frequency resolution. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide a local oscillator output circuit and a shortwave superheterodyne receiver, aiming to solve the problems of local oscillator leakage and image interference caused by the common use of three-channel PLL frequency synthesis technology in modern shortwave superheterodyne receivers to generate local oscillator signals.

[0006] The first aspect of this application relates to a local oscillator output circuit, comprising: a crystal oscillator amplification module, a first local oscillator output module, a second local oscillator output module, and a third local oscillator output module; the output terminal of the crystal oscillator amplification module is respectively connected to the input terminal of the first local oscillator output module, the input terminal of the second local oscillator output module, and the input terminal of the third local oscillator output module; the crystal oscillator amplification module is used to drive, enhance, and amplify the harmonics of the original crystal oscillator signal with a frequency greater than 30MHz to obtain a reference clock signal, and provides the reference clock signal to the first local oscillator output module, the second local oscillator output module, and the third local oscillator output module; The first local oscillator output module is configured to generate an adjustable frequency first local oscillator signal using the eighth harmonic frequency of the reference clock signal as the base frequency; the second local oscillator output module is configured to generate a second local oscillator signal using the second harmonic frequency of the reference clock signal as the base frequency; and the third local oscillator output module is configured to generate a third local oscillator signal using the fundamental frequency of the reference clock signal as the base frequency.

[0007] In one embodiment, the crystal oscillator amplification module includes: a first crystal oscillator, a first driver, and a first amplifier connected in sequence; the output terminal of the first crystal oscillator is connected to the input terminal of the first driver; the output terminal of the first driver is connected to the input terminal of the first amplifier; and the output terminal of the first amplifier is connected to each local oscillator output module.

[0008] In one embodiment, the first local oscillator output module is configured to receive a reference clock signal and generate an adjustable frequency first local oscillator signal via a first direct digital frequency synthesizer, using the eighth harmonic frequency of the reference clock signal as the base frequency; the third local oscillator output module is configured to receive a reference clock signal and generate a third local oscillator signal via a second direct digital frequency synthesizer, using the original frequency of the reference clock signal as the base frequency.

[0009] In one embodiment, the first local oscillator output module includes: a first bandpass filter, a second amplifier, a first high-pass filter, a first direct digital frequency synthesizer, a first low-pass filter, a third amplifier, an adjustable bandpass filter unit, a fourth amplifier, a second low-pass filter, and a fifth amplifier; the input terminal of the first bandpass filter is connected to the output terminal of the crystal oscillator amplifier module, and the output terminal of the first bandpass filter is connected to the input terminal of the second amplifier; the output terminal of the second amplifier is connected to the input terminal of the first high-pass filter; the output terminal of the first high-pass filter is connected to the input terminal of the first direct digital frequency synthesizer; and the output terminal of the first direct digital frequency synthesizer is connected to the input terminal of the first low-pass filter. The output of the first low-pass filter is connected to the input of the third amplifier; the output of the third amplifier is connected to the input of the adjustable band-pass filter unit; the output of the adjustable band-pass filter unit is connected to the input of the fourth amplifier, and the output of the fourth amplifier is connected to the input of the second low-pass filter; the output of the second low-pass filter is connected to the input of the fifth amplifier; the output of the fifth amplifier is connected to an external first mixer; the adjustable band-pass filter unit is configured to filter the output signal of the first direct digital frequency synthesizer after amplification by the third amplifier, and the passband frequency of the adjustable band-pass filter unit is dynamically adjusted according to the target frequency output by the first direct digital frequency synthesizer.

[0010] In one embodiment, the adjustable bandpass filter unit includes: a first switch, a second bandpass filter, and a second switch connected in sequence; and a third switch, a third bandpass filter, and a fourth switch connected in sequence; wherein the first switch is connected to the first switch and the output of the third amplifier respectively; the second switch is connected to the first switch and the input of the fourth amplifier respectively; the first switch and the second switch are configured to operate synchronously; the third switch and the fourth switch are configured to operate synchronously.

[0011] In one embodiment, the second local oscillator output module includes: a fourth bandpass filter, a sixth amplifier, and a third low-pass filter; the input terminal of the fourth bandpass filter is connected to the output terminal of the crystal oscillator amplifier module; the output terminal of the fourth bandpass filter is connected to the input terminal of the sixth amplifier; the output terminal of the sixth amplifier is connected to the input terminal of the third low-pass filter; and the output terminal of the third low-pass filter is connected to an external second mixer.

[0012] In one embodiment, the third local oscillator output module includes: a seventh amplifier, a second direct digital frequency synthesizer, a fourth low-pass filter, and the seventh amplifier; the input terminal of the seventh amplifier is connected to the output terminal of the crystal oscillator amplifier module; the output terminal of the seventh amplifier is connected to the input terminal of the second direct digital frequency synthesizer; the output terminal of the second direct digital frequency synthesizer is connected to the input terminal of the fourth low-pass filter; the output terminal of the fourth low-pass filter is connected to the input terminal of the eighth amplifier; and the output terminal of the eighth amplifier is connected to an external third mixer.

[0013] In one embodiment, the frequency stability of the first crystal oscillator is less than 0.5 ppm; the first driver is an NPN transistor, and the first amplifier is a broadband amplifier.

[0014] In one embodiment, the first direct digital frequency synthesizer is a voltage output type; the second direct digital frequency synthesizer is a current output type.

[0015] The second aspect of this application relates to a shortwave superheterodyne receiver, which includes: a local oscillator output circuit as described in the first aspect; the local oscillator output circuit is configured to output a first local oscillator signal, a second local oscillator signal, and a third local oscillator signal.

[0016] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art: The local oscillator output circuit of this application generates a high-frequency reference clock and enhances its harmonic energy through the crystal oscillator amplification module. This allows the first, second, and third local oscillator output modules to directly utilize the eighth, second, and first harmonics of the signal as the fundamental frequency, respectively. This design ensures that the three-stage local oscillator signals originate from a highly stable reference, guaranteeing frequency coherence and fundamentally avoiding the additional spurious noise and phase noise generated by the mutual attraction of multiple independent PLLs, thereby reducing the spectral impurity of the local oscillator signal. More importantly, by reasonably selecting a reference frequency higher than 30MHz and utilizing its higher harmonics, the fundamental frequency and output signal frequency of each stage of the local oscillator circuit are set outside the shortwave receiving frequency band. This characteristic ensures that even if circuit leakage occurs, its energy will not fall within the receiver's sensitive frequency band, thus fundamentally avoiding the impact of local oscillator leakage on receiver sensitivity.

[0017] Meanwhile, the three local oscillator signals naturally form a huge frequency gap of more than two octaves based on harmonic relationships. This huge difference makes the image interference frequency of any signal to the other far apart, so it can be easily and effectively suppressed by a simple filtering circuit, significantly reducing inter-stage crosstalk. Finally, the whole scheme replaces the traditional multi-PLL frequency synthesis with a single crystal oscillator harmonic generation architecture, and simultaneously achieves effective suppression of local oscillator leakage and image interference at the system level. Attached Figure Description

[0018] Figure 1 This is one of the structural block diagrams of the local oscillator output circuit provided in the embodiments of this application; Figure 2 This is a circuit topology diagram of the crystal oscillator amplifier module provided in the embodiments of this application; Figure 3 This is a second structural block diagram of the local oscillator output circuit provided in the embodiments of this application; Figure 4This is a circuit topology diagram of the first local oscillator output module provided in the embodiments of this application; Figure 5 This is a circuit topology diagram of the second local oscillator output module provided in the embodiments of this application; Figure 6 This is a circuit topology diagram of the third local oscillator output module provided in the embodiments of this application.

[0019] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein: 10 is the crystal oscillator amplifier module; X1 is the first crystal oscillator; BUFF1 is the first driver; AMP1 is the first amplifier; 20 is the first local oscillator output module; BPF1 is the first bandpass filter; AMP2 is the second amplifier; HPF1 is the first high-pass filter; DDS1 is the first direct digital frequency synthesizer; LPF1 is the first low-pass filter; AMP3 is the third amplifier; 21 is the adjustable bandpass filter unit; AMP4 is the fourth amplifier; LPF2 is the second low-pass filter; AMP5 is the fifth amplifier; BPF2 is the second bandpass filter; BPF3... SW1 is the third bandpass filter; SW2 is the first switch; SW3 is the second switch; SW4 is the fourth switch; MIXER1 is the first mixer; 30 is the second local oscillator output module; BPF4 is the fourth bandpass filter; AMP6 is the sixth amplifier; LPF3 is the third low-pass filter; MIXER2 is the second mixer; 40 is the third local oscillator output module; AMP7 is the seventh amplifier; DDS2 is the second direct digital frequency synthesizer; LPF4 is the fourth low-pass filter; AMP8 is the eighth amplifier; MIXER3 is the third mixer. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] In this application, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. In this application, the symbol " / " indicates that the related objects are in an "or" relationship, for example, A / B means A or B.

[0022] In this application, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages. The term "connection" can refer to a direct circuit connection or signal transmission via a communication protocol.

[0023] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0024] Furthermore, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0025] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0026] In zero-IF or low-IF receivers, typically only one local oscillator (LO) signal is needed. However, in modern shortwave superheterodyne receivers requiring high integration and multi-band support, a three-PLL scheme is widely used to generate three key LO signals. These three key LO signals are: the main conversion LO, used to downconvert the RF signal to a fixed IF; the image rejection LO, used to eliminate image frequency interference in the image rejection mixer; and the carrier recovery LO, used to downconvert the IF signal to the baseband I / Q signal.

[0027] Specifically, three PLLs mean three local oscillator sources, each a potential leakage point. Leakage can occur through power supply, ground, substrate coupling, and parasitic capacitance between PCB traces. Simultaneously, during mixing, two input signals of different frequencies, the useful signal and the image signal, are down-converted to the same intermediate frequency. The receiver cannot distinguish them, resulting in interference signals at the image frequency being received as well.

[0028] To address image interference, image rejection mixers are typically used, which usually require a second local oscillator signal to generate orthogonal I / Q channels. One of the local oscillators in a three-PLL architecture serves this purpose. However, the image rejection ratio of this solution heavily depends on the amplitude and phase balance of the I / Q channels. Any mismatch will lead to a decrease in image rejection performance, and the inconsistent phase noise and jitter characteristics of the three PLLs further exacerbate this imbalance.

[0029] Based on this, this application proposes an embodiment of a local oscillator output circuit. Please refer to... Figure 1 , Figure 1 This is one of the structural block diagrams of the local oscillator output circuit provided in the embodiments of this application.

[0030] In this embodiment, the local oscillator output circuit includes: a crystal oscillator amplifier module 10, a first local oscillator output module 20, a second local oscillator output module 30, and a third local oscillator output module 40. The output terminal of the crystal oscillator amplifier module 10 is connected to the input terminals of the first local oscillator output module 20, the second local oscillator output module 30, and the third local oscillator output module 40, respectively.

[0031] It should be noted that the crystal oscillator amplifier module 10 is used to drive, enhance and amplify the original crystal oscillator signal with a frequency greater than 30MHz to obtain a reference clock signal, and provides the reference clock signal to the first local oscillator output module 20, the second local oscillator output module 30 and the third local oscillator output module 40.

[0032] Understandably, choosing a primary crystal oscillator signal outside the 3MHz to 30MHz band for shortwave communication is a design aimed at fundamentally avoiding interference. Specifically, the circuit selects a signal with a frequency greater than 30MHz as the primary crystal oscillator signal f1. This means that the fundamental frequencies of the reference clock signal generated by it and its various harmonics (such as the second harmonic 2×f1 and the eighth harmonic 8×f1) are far from the shortwave band. The primary advantage of this design is that even if there is local oscillator leakage in the circuit, the frequency components of these leaked signals fall entirely outside the receiver's operating frequency band, thus preventing them from entering the signal channel and causing interference, fundamentally ensuring that the receiver's sensitivity remains unaffected.

[0033] Understandably, the high-frequency raw signal facilitates the generation of higher harmonic components. For example, to generate a local oscillator signal in the Very High Frequency (VHF) band, extracting its eighth harmonic from a fundamental frequency above 30MHz is far more efficient and practical than frequency doubling from a fundamental frequency in the shortwave band, ensuring the feasibility of the harmonic generation scheme. Furthermore, since all local oscillator signals originate from the same high-frequency reference, the frequency spacing between them is naturally increased, creating favorable conditions for subsequent use of filtering circuits to effectively separate the signals and suppress interstage image interference.

[0034] Understandably, driving and amplifying the original crystal oscillator signal with a frequency greater than 30MHz to generate a reference clock signal is to simultaneously address the two key issues of signal integrity and harmonic availability. Driving enhancement significantly improves the signal's current output capability and voltage swing, ensuring that the reference clock can stably and reliably drive three parallel local oscillator output modules simultaneously, overcoming signal attenuation caused by load effects. Simultaneously, the harmonic amplification process specifically enhances the energy level of higher harmonic components in the signal, particularly providing sufficient energy for the subsequent first local oscillator output module that directly utilizes the eighth harmonic. This makes it possible to replace traditional PLL frequency multiplication with a harmonic extraction scheme, fundamentally avoiding the phase noise and mutual interference introduced by multi-PLL architectures.

[0035] Specifically, this embodiment provides a feasible implementation of the crystal oscillator amplification module 10. Please refer to... Figure 2 , Figure 2 This is a circuit topology diagram of the crystal oscillator amplifier module provided in the embodiments of this application.

[0036] exist Figure 2 In the crystal oscillator amplification module 10, there are: a first crystal oscillator X1, a first driver BUFF1 and a first amplifier AMP1 connected in sequence; the output terminal of the first crystal oscillator X1 is connected to the input terminal of the first driver BUFF1; the output terminal of the first driver BUFF1 is connected to the input terminal of the first amplifier AMP1; and the output terminal of the first amplifier AMP1 is connected to each local oscillator output module.

[0037] The crystal oscillator has a frequency greater than 30MHz and a frequency stability of less than 0.5ppm. Since the first and second local oscillator signals originate from the eighth and second harmonics of the crystal oscillator, respectively, any frequency drift of the crystal oscillator will be amplified exponentially during the harmonic process. For example, if the crystal oscillator frequency drifts by 1kHz, the drift of its eighth harmonic will be as high as 8kHz. Such a large error will cause severe inaccuracy of the local oscillator frequency, making normal mixing and demodulation impossible. The extremely high stability of less than 0.5ppm ensures that even after eight harmonic multiplications, the final local oscillator signal frequency can still be precisely controlled within the system's required tolerance, which is the prerequisite for the entire harmonic architecture to function.

[0038] Specifically, the first crystal oscillator X1 can be a surface-mount crystal oscillator of model XTCJH32M000TJEB4P0, with a clock frequency of 32MHz and a frequency stability of ±0.3ppm. This means that within an industrial temperature range of -40 to +85 degrees Celsius, the frequency fluctuation of the 32MHz crystal oscillator will not exceed ±9.6Hz, and the frequency error of its eighth harmonic will not exceed ±76.8Hz. Such accuracy fully meets the requirements of high-performance communication systems for local oscillator frequency stability.

[0039] The first driver, BUFF1, uses an NPN transistor of model 2SC2714 to enhance the driving capability of the crystal oscillator clock signal. Although the crystal oscillator output signal has a precise frequency, its driving capability is very weak. Directly connecting multiple loads can lead to frequency instability or even oscillation failure. The first driver, BUFF1, significantly reduces the output impedance through its current amplification characteristics, providing a low-impedance signal source for subsequent circuits. This ensures that it can simultaneously drive three local oscillator modules without causing signal attenuation or waveform distortion.

[0040] The first amplifier, AMP1, is a broadband amplifier of model UPC2709T, which enhances the energy of the crystal oscillator harmonic signal. Although the driving capability of the signal output by the first driver, BUFF1, is enhanced, the relative energy of the higher harmonic components is still insufficient. The broadband amplifier provides nearly uniform gain for all frequency components, including the fundamental frequency and all harmonics, within its passband, especially effectively amplifying high-frequency components such as the eighth harmonic. This ensures that these higher harmonics have sufficient energy amplitude, creating the necessary conditions for the subsequent first local oscillator output module to directly extract the eighth harmonic.

[0041] It should be noted that the first local oscillator output module 20 is configured to generate an adjustable frequency first local oscillator signal using the eighth harmonic frequency of the reference clock signal as the base frequency; the second local oscillator output module 30 is configured to generate a second local oscillator signal using the second harmonic frequency of the reference clock signal as the base frequency; and the third local oscillator output module 40 is configured to generate a third local oscillator signal using the fundamental frequency of the reference clock signal as the base frequency.

[0042] Understandably, the configuration of the first local oscillator output module 20 is to obtain a high-frequency fundamental frequency by extracting the eighth harmonic of the reference clock signal, thereby achieving an eighth-fold frequency expansion. This high-order harmonic extraction technology enables a single crystal oscillator to support the local oscillator requirements of multiple frequency bands. Based on this, the frequency selection mechanism introduced by this module uses the high-frequency signal generated by the aforementioned eighth harmonic as a precise reference. The target frequency band can be switched simply by making a selection. This collaborative solution perfectly solves the engineering requirements of frequency tunability while maintaining the low phase noise advantage brought by the harmonic extraction technology.

[0043] Understandably, the second local oscillator output module 30 extracts the second harmonic component of the reference clock signal as its fundamental frequency, completely avoiding the additional phase noise and spurious interference introduced by traditional active frequency multiplier circuits. The third local oscillator output module 40 directly uses the frequency of the reference clock signal as its operating fundamental frequency. This design fully utilizes the inherent high stability and low phase noise characteristics of the crystal oscillator source signal, providing the purest and most reliable frequency reference for the entire system.

[0044] Specifically, harmonic extraction can be achieved using a bandpass filter. A bandpass filter is a passive linear network. Unlike the VCO and frequency divider in a PLL, the bandpass filter's filtering process does not introduce additional phase noise. The phase noise of the output signal is largely inherited from the crystal oscillator itself, with only the thermal noise from the filter's own minor insertion loss added, thus achieving extremely high spectral purity.

[0045] Specifically, after extracting the harmonics, the sine wave output from the bandpass filter typically has a small amplitude and insufficient driving capability, and may also contain a small amount of spurious signals, making it unsuitable for direct use as the local oscillator signal. Therefore, further processing is required using amplifiers, buffers, and possibly additional filters and fixed attenuators to ultimately obtain the local oscillator signal.

[0046] In this embodiment, since the crystal oscillator amplification module generates a high-frequency reference clock and enhances its harmonic energy, the first, second, and third local oscillator output modules can directly use the eighth, second, and first harmonics of the signal as the fundamental frequency, respectively. This hierarchical harmonic utilization architecture ensures that the three-level local oscillator signals originate from a highly stable reference, guaranteeing frequency coherence and fundamentally avoiding the additional spurious noise and phase noise caused by the mutual attraction of multiple independent PLLs, thereby reducing the spectral impurity of the local oscillator signal.

[0047] Crucially, by strategically selecting a reference frequency higher than 30MHz and utilizing its higher harmonics, the fundamental frequency and output signal frequency of each stage of the local oscillator circuit are set outside the shortwave receiving band. This characteristic ensures that even if circuit leakage occurs, its energy will not fall within the receiver's sensitive frequency band, thus fundamentally avoiding the impact of local oscillator leakage on receiver sensitivity. Simultaneously, the three stages of local oscillator signals naturally form a large frequency interval of more than two octaves based on harmonic relationships. This significant difference means that the image interference frequencies of any signal to the others are far apart, allowing for easy and effective suppression by simple filtering circuits, significantly reducing inter-stage crosstalk.

[0048] Compared with existing technologies, the entire solution replaces the traditional multi-PLL frequency synthesis with a single crystal oscillator harmonic generation architecture, and simultaneously achieves effective suppression of local oscillator leakage and image interference at the system level.

[0049] Furthermore, this application proposes improvements based on the above embodiments to increase the frequency switching speed. Specifically, please refer to... Figure 3 , Figure 3 This is the second structural block diagram of the local oscillator output circuit provided in the embodiments of this application.

[0050] In this embodiment, the first local oscillator output module 20 is configured to receive a reference clock signal and use the eighth harmonic frequency of the reference clock signal as the base frequency to generate an adjustable frequency first local oscillator signal via a first direct digital frequency synthesizer (DDS1); the third local oscillator output module 40 is configured to receive a reference clock signal and use the original frequency of the reference clock signal as the base frequency to generate a third local oscillator signal via a second direct digital frequency synthesizer (DDS2).

[0051] Understandably, a Direct Digital Synthesizer (DDS) achieves frequency switching by changing the step size of its internal phase accumulator. This is a purely numerical calculation process that can be completed in an extremely short time, typically on the order of nanoseconds to microseconds, thus achieving a frequency agility far exceeding that of traditional PLLs.

[0052] Understandably, while DDS offers significant advantages in frequency agility and resolution, its inherent drawbacks are equally apparent: First, there is spurious interference; due to digital processes such as phase truncation and amplitude quantization, the DDS output spectrum contains a large number of spurious components. Second, there is in-band phase noise; the phase noise of its output signal increases at low frequency offsets, resulting in performance inferior to high-quality analog oscillators. Finally, there is output frequency limitation; constrained by the Nyquist criterion, its useful output frequency is typically much lower than the reference clock frequency.

[0053] Based on this, this application uses DDS only for the first and third local oscillators, which have the largest frequency difference. The first and third local oscillators themselves differ in frequency by several octaves. When they are generated by the first direct digital frequency synthesizer DDS1 and the second direct digital frequency synthesizer DDS2, respectively, due to the limited output bandwidth of the DDS and the fact that its main spurious and phase noise energy is usually concentrated near the output frequency and near the various division points of the reference clock, the spurious products generated by the two DDSs are far apart in the spectrum. Therefore, the possibility of their spurious products overlapping and intersecting in each other's output frequency bands and causing serious intermodulation interference is minimized.

[0054] Understandably, the second local oscillator does not use DDS, but instead continues to be generated through a pure passive filtering extraction method. This ensures that at least one of the three local oscillators is a nearly pure analog signal. This crucial local oscillator signal will not be contaminated by the inherent spurious signals of DDS, providing the receiver system with a highly reliable down-conversion channel.

[0055] In this embodiment, when a high-frequency, agile local oscillator signal is required, DDS is selected, and spurious emissions are a necessary trade-off. However, by using DDS only for specific paths and spacing these paths apart in the frequency domain, this trade-off is controlled within a manageable and acceptable range. The system trades acceptable, localized spurious emissions for the globally crucial fast frequency switching capability.

[0056] Based on the above embodiments, this application provides a specific implementation method for achieving the above functions.

[0057] In this embodiment, please refer to Figure 4 , Figure 4 This is a circuit topology diagram of the first local oscillator output module provided in the embodiments of this application. The first local oscillator output module 20 includes: a first bandpass filter BPF1, a second amplifier AMP2, a first high-pass filter HPF1, a first direct digital frequency synthesizer DDS1, a first low-pass filter LPF1, a third amplifier AMP3, an adjustable bandpass filter unit 21, a fourth amplifier AMP4, a second low-pass filter LPF2, and a fifth amplifier AMP5.

[0058] The input of the first bandpass filter BPF1 is connected to the output of the crystal oscillator amplifier module 10, and the output of the first bandpass filter BPF1 is connected to the input of the second amplifier AMP2. The output of the second amplifier AMP2 is connected to the input of the first high-pass filter HPF1. The output of the first high-pass filter HPF1 is connected to the input of the first direct digital frequency synthesizer DDS1. The output of the second direct digital frequency synthesizer DDS2 is connected to the input of the first low-pass filter LPF1. The output of the first low-pass filter LPF1 is connected to the input of the third amplifier AMP3. The output of the third amplifier AMP3 is connected to the input of the adjustable bandpass filter unit 21. The output of the adjustable bandpass filter unit 21 is connected to the input of the fourth amplifier AMP4. The output of the fourth amplifier AMP4 is connected to the input of the second low-pass filter LPF2. The output of the second low-pass filter LPF2 is connected to the input of the fifth amplifier AMP5. The output of the fifth amplifier AMP5 is connected to the external first mixer MIXER1.

[0059] It should be noted that the adjustable bandpass filter unit 21 is configured to filter the output signal of the first direct digital frequency synthesizer DDS1 after it has been amplified by the third amplifier AMP3. The passband frequency of the adjustable bandpass filter unit 21 is dynamically adjusted according to the target frequency output by the first direct digital frequency synthesizer DDS1.

[0060] Specifically, the frequency range of the first local oscillator signal is 67.455MHz to 94.455MHz, and the eighth harmonic of the first crystal oscillator X1 is used as the fundamental frequency. The first bandpass filter, BPF1, is a third-order bandpass filter with a center frequency of 256MHz. The second amplifier, AMP2, is a wideband amplifier of model UPC2709T, which improves the clock signal energy. The first high-pass filter, HPF1, is a second-order high-pass filter that filters out low-frequency spurious signals. The first direct digital frequency synthesizer, DDS1, uses AD9951, which supports a main clock input signal frequency of 256MHz, has a 14-bit DAC resolution, and outputs a current-type signal with a frequency range of 67.455MHz to 94.455MHz. The first low-pass filter, LPF1, is a third-order low-pass filter that filters out high-frequency spurious signals. The third amplifier, AMP3, is a wideband amplifier of model UPC2710T, which improves the clock signal energy. The fourth amplifier, AMP4, uses an NPN transistor of model 2SC3357-T1, which has low noise and wide dynamic range characteristics. The second low-pass filter, LPF2, is a second-order low-pass filter with a cutoff frequency of 94.455MHz, which filters out high-frequency spurious signals.

[0061] Understandably, in the signal generation and initial conditioning stage, this link begins with the first bandpass filter BPF1. This third-order bandpass filter, with its center frequency of 256MHz, accurately extracts the eighth harmonic from the rich harmonic signal provided by the crystal oscillator amplifier module 10 as the fundamental frequency of the entire first local oscillator. Subsequently, the second amplifier AMP2 is responsible for boosting the power level of this harmonic signal. Immediately afterwards, the first high-pass filter HPF1 acts as a frequency guarantee, filtering out any possible low-frequency spurious signals and noise, providing a relatively clean high-frequency reference clock for the subsequent first direct digital frequency synthesizer DDS1 circuit.

[0062] Understandably, during the core frequency synthesis and dynamic filtering stage, the purified 256MHz signal is input to the first direct digital frequency synthesizer (DDS1). This DDS chip utilizes its high-resolution DAC and fast frequency switching capabilities to generate the target frequency signal within the range of 67.455MHz to 94.455MHz. The DDS output contains a significant amount of high-frequency spurious signals, which are immediately suppressed by the first low-pass filter (LPF1). Subsequently, the third amplifier (AMP3) compensates for the insertion loss introduced by the filtering.

[0063] In one embodiment, the adjustable bandpass filter unit 21 includes: a first switch SW1, a second bandpass filter BPF2, and a second switch SW2 connected in sequence; and a third switch SW3, a third bandpass filter BPF3, and a fourth switch SW4 connected in sequence; wherein, the first end of the first switch SW1 is connected to the first end of the third switch SW3 and the output end of the third amplifier AMP3 respectively; the tail end of the second switch SW2 is connected to the first end of the fourth switch SW4 and the input end of the fourth amplifier AMP4 respectively; the first switch SW1 and the second switch SW2 are configured to operate synchronously and are controlled by a first path control switch SWA; the third switch SW3 and the fourth switch SW4 are configured to operate synchronously and are controlled by a second path control switch SWB.

[0064] Alternatively, a first-path control switch SWA and a second-path control switch SWB can be used instead of the other four switches. Both the first-path control switch SWA and the second-path control switch SWB use a pair of diodes of model 1SV308 with opposite connection directions. When operating, the first path is open and the second path is closed, allowing the signal path to pass through the second bandpass filter BPF2, or the first path is closed and the second path is open, allowing the signal path to pass through the third bandpass filter BPF3.

[0065] Specifically, the second bandpass filter BPF2 and the third bandpass filter BPF3 are both third-order bandpass filters with passband ranges of 67.455MHz to 79.455MHz and 79.455MHz to 94.455MHz, respectively.

[0066] It is understandable that the adjustable bandpass filter unit 21 is not a fixed filter, but rather comprises two parallel filters with different passbands, which are dynamically switched through a switching network. This design allows the filter's passband to be dynamically adjusted according to the target frequency of the DDS output, ensuring optimal passband performance and out-of-band rejection across the entire output frequency band, thereby accurately filtering out high-order spurious signals such as image frequencies and clock feedpasses generated by the DDS.

[0067] Understandably, in the final signal purification and output drive stage, the dynamically filtered signal is amplified by the fourth amplifier AMP4, which uses a low-noise NPN transistor to minimize the degradation of the system noise figure. Subsequently, the second low-pass filter LPF2 serves as the final purification stage, using its 94.455MHz cutoff frequency to filter out residual high-frequency noise and newly generated high-frequency noise from the amplifier. Finally, the fifth amplifier AMP5 serves as the output buffer stage, its primary function being to provide sufficient drive capability to ensure that the local oscillator signal can stably drive the subsequent first mixer MIXER1. Through this cascaded structure, the entire link gradually boosts the signal to the power level required by the system while maintaining signal quality.

[0068] In this embodiment, please refer to Figure 5 , Figure 5 This is a circuit topology diagram of the second local oscillator output module provided in an embodiment of this application. The second local oscillator output module 30 includes: a fourth bandpass filter BPF4, a sixth amplifier AMP6, and a third low-pass filter LPF3.

[0069] The input of the fourth bandpass filter BPF4 is connected to the output of the crystal oscillator amplifier module 10; the output of the fourth bandpass filter BPF4 is connected to the input of the sixth amplifier AMP6; the output of the sixth amplifier AMP6 is connected to the input of the third low-pass filter LPF3; and the output of the third low-pass filter LPF3 is connected to the external second mixer MIXER2.

[0070] Specifically, the frequency of the secondary local oscillator signal is 64MHz, using the second harmonic of the first crystal oscillator X1 as the fundamental frequency. The fourth bandpass filter BPF4 is a third-order bandpass filter with a center frequency of 64MHz; the sixth amplifier AMP6 is a broadband amplifier of model UPC2709T, which amplifies the 64MHz frequency signal to an energy range of -10dBm to 0dBm; the third low-pass filter LPF3 is a second-order low-pass filter that filters out high-frequency spurious signals.

[0071] Understandably, the fourth bandpass filter, BPF4, is used as the input, with its center frequency set to 64MHz, to extract the second harmonic component from the output signal of the crystal oscillator amplifier module. This third-order bandpass filter effectively suppresses the fundamental frequency and other harmonic components, ensuring the spectral purity of the output signal. The filtered 64MHz signal is then fed into the sixth amplifier, AMP6, for amplitude amplification. This broadband amplifier boosts the signal power to an operating level of -10dBm to 0dBm, providing sufficient drive capability for subsequent circuits. The amplified signal undergoes final processing through the third low-pass filter, LPF3. The main function of this second-order low-pass filter is to filter out high-frequency spurious and harmonic components that may be generated by the amplifier, further improving the spectral characteristics of the output signal.

[0072] Understandably, the processed 64MHz second local oscillator signal is ultimately output to the external second mixer MIXER2. The entire signal path employs a simple filtering, amplification, and filtering structure, achieving simplified circuit design while ensuring signal quality. It is suitable for generating a fixed 64MHz local oscillator signal, avoiding complex frequency synthesis circuits and improving the system's reliability and stability.

[0073] In this embodiment, please refer to Figure 6 , Figure 6 This is a circuit topology diagram of the third local oscillator output module provided in an embodiment of this application. The third local oscillator output module 40 includes: a seventh amplifier AMP7, a second direct digital frequency synthesizer DDS2, a fourth low-pass filter LPF4, and an eighth amplifier AMP8.

[0074] The input of the seventh amplifier AMP7 is connected to the output of the crystal oscillator amplifier module 10; the output of the seventh amplifier AMP7 is connected to the input of the second direct digital frequency synthesizer DDS2; the output of the second direct digital frequency synthesizer DDS2 is connected to the input of the fourth low-pass filter LPF4; the output of the fourth low-pass filter LPF4 is connected to the input of the eighth amplifier AMP8; and the output of the eighth amplifier AMP8 is connected to the external third mixer MIXER3.

[0075] Specifically, the frequency of the third-stage local oscillator signal is 419kHz, using the fundamental frequency of the first crystal oscillator X1 as the fundamental frequency. The seventh amplifier AMP7 uses an inverter of model SN74AHC1GU04 to improve signal driving capability; the second direct digital frequency synthesizer DDS2 uses an AD5932, with a main clock supporting a signal frequency input of 32MHz, 10-bit DAC resolution, and a voltage output signal with an output frequency of 419kHz. The fourth low-pass filter LPF4 is a second-order low-pass filter to filter out high-frequency spurious signals; the eighth amplifier AMP8 uses an inverter of model SN74AHC1GU04 to improve signal driving capability.

[0076] Understandably, the 32MHz reference clock signal from the crystal oscillator amplifier module 10 is first input to the seventh amplifier AMP7, which uses an inverter to shape the signal and enhance its driving capability. The amplified signal is then used as a reference clock input to the second direct digital frequency synthesizer (DDS2), which generates a 419kHz output signal based on the 32MHz reference clock. The 419kHz signal output from the second DDS2 contains high-frequency spurious components and needs to be filtered by the fourth low-pass filter LPF4. This second-order low-pass filter effectively suppresses high-frequency spurious components and clock feedthrough products, improving the spectral purity of the output signal. The filtered signal is finally buffered and amplified by the eighth amplifier AMP8 to enhance its driving capability before being output to the external third mixer MIXER3. This design utilizes the characteristics of DDS technology to ensure excellent frequency accuracy and stability while maintaining a fixed output frequency. Through a simplified signal processing chain, a high-quality 419kHz local oscillator signal is generated, meeting the system's performance requirements for the third local oscillator signal.

[0077] It should be noted that the first direct digital frequency synthesizer (DDS1) in this application uses a current output type while the second direct digital frequency synthesizer (DDS2) uses a voltage output type. This is a performance optimization choice based on different operating frequencies. The DDS1 of the first local oscillator output module 20 operates in the high-frequency range, outputting 67-94MHz, with a reference clock of 256MHz. The current output architecture can provide faster settling time, better dynamic performance, and higher spurious-free dynamic range at this frequency, which is crucial for the spectral purity of the RF-grade local oscillator signal.

[0078] It should be noted that the DDS2 of the third local oscillator output module 40 operates in the low-frequency range (output 419kHz, reference clock 32MHz). The voltage output architecture can meet the performance requirements at this frequency, and has advantages such as low output impedance, simple interface, and no need for external load resistors. This achieves circuit simplification and cost optimization, and realizes the effect of precise optimization for different performance requirements in system design.

[0079] In the specific implementation process, a high-frequency crystal oscillator in the shortwave band, outside of 3MHz to 30MHz, with a frequency of 32MHz, is selected. The driving capability of the crystal oscillator is enhanced and the harmonic signal energy is increased through a driving amplifier circuit. The eighth harmonic signal of the crystal oscillator, 256MHz, is used as the fundamental frequency to generate the first local oscillator signal with a frequency range of 67.455MHz to 94.455MHz. The second harmonic signal of the crystal oscillator, 64MHz, is used as the fundamental frequency, filtered and amplified to generate the second local oscillator signal of 64MHz. The original frequency of the crystal oscillator, 32MHz, is used as the fundamental frequency to generate the third local oscillator signal of 419KHz.

[0080] Understandably, the base frequency and local oscillator signal of each local oscillator output circuit are outside the shortwave band, avoiding the impact of local oscillator leakage on receiver sensitivity. At the same time, the frequency difference between each local oscillator circuit is more than 2 octaves, and the image interference between each local oscillator output circuit is reduced by the filtering circuit. The variable frequency first-stage local oscillator signal and third-stage local oscillator signal are generated by driving the DDS chip with the base frequency, which improves the frequency switching speed and frequency resolution.

[0081] Understandably, the above methods address the shortcomings of existing shortwave superheterodyne receivers that employ PLL frequency synthesis technology, such as local oscillator leakage, image interference, slow frequency switching speed, and insufficient frequency resolution.

[0082] In addition to the above-described local oscillator output circuit embodiment, this application proposes a shortwave superheterodyne receiver. This receiver integrates the aforementioned local oscillator output circuit, which outputs three independent local oscillator signals with strict frequency coherence, providing a core excitation source for the receiver's multi-stage frequency conversion architecture. Specifically, this shortwave superheterodyne receiver simultaneously obtains a first local oscillator signal, a second local oscillator signal, and a third local oscillator signal through the local oscillator output circuit.

[0083] The first local oscillator signal, generated based on the eighth harmonic and DDS technology, provides a variable frequency output in the high-frequency band to realize the down-conversion of the radio frequency signal to the first intermediate frequency signal; the second local oscillator signal, generated based on the second harmonic extraction technology, provides a fixed intermediate frequency local oscillator to suppress the image frequency or further frequency conversion; and the third local oscillator signal, generated based on the original frequency and DDS technology, provides the final local oscillator output to complete the signal to baseband conversion.

[0084] Understandably, this design derives all the required local oscillator signals from a single, highly stable crystal oscillator source, fundamentally ensuring the phase coherence between the various local oscillator signals. This effectively avoids the local oscillator leakage and phase noise degradation problems caused by the mutual attraction of multiple independent frequency sources in traditional multi-PLL architectures. Simultaneously, the harmonic extraction-based generation method significantly reduces the phase noise of the local oscillator signal, while the introduction of DDS technology provides the necessary frequency agility while maintaining frequency accuracy. This receiver architecture systematically improves the overall receiver sensitivity and anti-interference performance by employing an innovative local oscillator generation scheme at the signal chain source.

[0085] Compared with the prior art, the beneficial effects of the shortwave superheterodyne receiver provided in this application are the same as the beneficial effects of the local oscillator output circuit provided in the above embodiments, and will not be repeated here.

[0086] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A local oscillator output circuit, characterized in that, include: Crystal oscillator amplifier module, first local oscillator output module, second local oscillator output module and third local oscillator output module; The output terminal of the crystal oscillator amplifier module is connected to the input terminal of the first local oscillator output module, the input terminal of the second local oscillator output module, and the input terminal of the third local oscillator output module, respectively. The crystal oscillator amplification module is used to drive, enhance, and amplify the original crystal oscillator signal with a frequency greater than 30MHz to obtain a reference clock signal, and to provide the reference clock signal to the first local oscillator output module, the second local oscillator output module, and the third local oscillator output module. The first local oscillator output module is configured to generate an adjustable frequency first local oscillator signal using the eighth harmonic frequency of the reference clock signal as the base frequency; the second local oscillator output module is configured to generate a second local oscillator signal using the second harmonic frequency of the reference clock signal as the base frequency; and the third local oscillator output module is configured to generate a third local oscillator signal using the fundamental frequency of the reference clock signal as the base frequency.

2. The local oscillator output circuit as described in claim 1, characterized in that, The crystal oscillator amplification module includes: a first crystal oscillator, a first driver, and a first amplifier connected in sequence; The output terminal of the first crystal oscillator is connected to the input terminal of the first driver; the output terminal of the first driver is connected to the input terminal of the first amplifier; and the output terminal of the first amplifier is connected to each of the local oscillator output modules.

3. The local oscillator output circuit as described in claim 1, characterized in that, The first local oscillator output module is configured to receive the reference clock signal and generate an adjustable frequency first local oscillator signal via a first direct digital frequency synthesizer, using the eighth harmonic frequency of the reference clock signal as the base frequency. The third local oscillator output module is configured to receive the reference clock signal and generate the third local oscillator signal via a second direct digital frequency synthesizer using the original frequency of the reference clock signal as the base frequency.

4. The local oscillator output circuit as described in claim 3, characterized in that, The first local oscillator output module includes: a first bandpass filter, a second amplifier, a first high-pass filter, a first direct digital frequency synthesizer, a first low-pass filter, a third amplifier, an adjustable bandpass filter unit, a fourth amplifier, a second low-pass filter, and a fifth amplifier; The input terminal of the first bandpass filter is connected to the output terminal of the crystal oscillator amplifier module; the output terminal of the first bandpass filter is connected to the input terminal of the second amplifier; the output terminal of the second amplifier is connected to the input terminal of the first high-pass filter; the output terminal of the first high-pass filter is connected to the input terminal of the first direct digital frequency synthesizer; the output terminal of the first direct digital frequency synthesizer is connected to the input terminal of the first low-pass filter; the output terminal of the first low-pass filter is connected to the input terminal of the third amplifier; the output terminal of the third amplifier is connected to the input terminal of the adjustable bandpass filter unit; the output terminal of the adjustable bandpass filter unit is connected to the input terminal of the fourth amplifier; the output terminal of the fourth amplifier is connected to the input terminal of the second low-pass filter; the output terminal of the second low-pass filter is connected to the input terminal of the fifth amplifier. The output of the fifth amplifier is connected to an external first mixer. The adjustable bandpass filter unit is configured to filter the output signal of the first direct digital frequency synthesizer after it has been amplified by the third amplifier. The passband frequency of the adjustable bandpass filter unit is dynamically adjusted according to the target frequency output by the first direct digital frequency synthesizer.

5. The local oscillator output circuit as described in claim 4, characterized in that, The adjustable bandpass filter unit includes: a first switch, a second bandpass filter, and a second switch connected in sequence; and a third switch, a third bandpass filter, and a fourth switch connected in sequence. The first switch is connected to the first end of the third switch and the output end of the third amplifier; the second switch is connected to the first end of the fourth switch and the input end of the fourth amplifier. The first switch and the second switch are configured to operate synchronously; the third switch and the fourth switch are configured to operate synchronously.

6. The local oscillator output circuit as described in claim 1, characterized in that, The second local oscillator output module includes: a fourth bandpass filter, a sixth amplifier, and a third low-pass filter; The input terminal of the fourth bandpass filter is connected to the output terminal of the crystal oscillator amplifier module; the output terminal of the fourth bandpass filter is connected to the input terminal of the sixth amplifier; the output terminal of the sixth amplifier is connected to the input terminal of the third low-pass filter. The output of the third low-pass filter is connected to an external second mixer.

7. The local oscillator output circuit as described in claim 3, characterized in that, The third local oscillator output module includes: a seventh amplifier, a second direct digital frequency synthesizer, a fourth low-pass filter, and an eighth amplifier; The input terminal of the seventh amplifier is connected to the output terminal of the crystal oscillator amplifier module; the output terminal of the seventh amplifier is connected to the input terminal of the second direct digital frequency synthesizer; the output terminal of the second direct digital frequency synthesizer is connected to the input terminal of the fourth low-pass filter; the output terminal of the fourth low-pass filter is connected to the input terminal of the eighth amplifier. The output of the eighth amplifier is connected to an external third mixer.

8. The local oscillator output circuit as described in claim 2, characterized in that, The frequency stability of the first crystal oscillator is less than 0.5 ppm; the first driver is an NPN transistor; and the first amplifier is a broadband amplifier.

9. The local oscillator output circuit as described in claim 3, characterized in that, The first direct digital frequency synthesizer is a voltage output type; the second direct digital frequency synthesizer is a current output type.

10. A shortwave superheterodyne receiver, characterized in that, The shortwave superheterodyne receiver includes: a local oscillator output circuit as described in any one of claims 1 to 9; The local oscillator output circuit is configured to output a first local oscillator signal, a second local oscillator signal, and a third local oscillator signal.

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