Programmable domestic broadband signal generation method and device

Abstract

The invention provides a programmable domestic broadband signal generation method and device. According to the programmable broadband signal generation method provided by the embodiment of the invention, the coverage of an ultra-wide frequency band from 30MHz to 20GHz and the maximum instantaneous bandwidth output of 2GHz are realized, the flexibility and spurious suppression capability of signal generation are effectively improved by adopting a full-localization digital-analog hybrid architecture, and the requirements of complex modulation, rapid frequency switching and extreme environment adaptability are met.

Description

Technical Field

[0001] This invention relates to the field of communication testing equipment technology, and in particular to a programmable, domestically produced broadband signal generation method and apparatus. Background Technology

[0002] In modern communications, radar, satellite navigation, and electronic warfare, signal source equipment serves as a core support for system testing and verification, widely used in signal simulation, parameter modulation, and performance evaluation under complex electromagnetic environments. Related technologies utilize the collaborative operation of digital modulation and analog RF links to construct a complete signal generation system from intermediate frequency generation to high-frequency output. Specifically, this technology covers the entire process from signal waveform design, digital processing, analog up-conversion to power regulation, including key aspects such as FPGA digital modulation, DAC analog output, mixer frequency conversion, filter bank bandwidth control, and RF switch path selection. As communication systems evolve towards higher frequencies and wider bandwidths, higher demands are placed on the frequency coverage, instantaneous bandwidth, spurious emission suppression capabilities, and environmental adaptability of signal sources, driving the coordinated evolution of mixed-signal architectures and the integration of domestically produced components.

[0003] However, existing signal source technologies, either by directly using a single analog link or limited by the performance of imported components, struggle to simultaneously satisfy ultra-wideband (30MHz–20GHz) and high instantaneous bandwidth (≥2GHz), and exhibit significant shortcomings in key indicators such as spurious suppression and phase noise. Specifically, domestically produced signal sources generally have phase noise levels worse than -120dBc / Hz in high-frequency bands (e.g., 6–18GHz), instantaneous bandwidths are mostly below 1GHz, and multi-band signal generation requires multiple devices, making seamless single-unit coverage impossible. Due to the nonlinear characteristics of mixers, parasitic frequency components are easily introduced, and existing technologies lack effective dynamic frequency planning and filter bank collaborative control mechanisms, leading to decreased signal purity and increased system complexity. Therefore, there is an urgent need to construct a hybrid digital-analog architecture that integrates the flexibility of digital and the low latency advantages of analog links to achieve a balance between high performance, high domestic production rate, and miniaturization. Summary of the Invention

[0004] The present invention aims to at least partially solve one of the technical problems in the related art.

[0005] Therefore, the first objective of this invention is to propose a programmable, domestically produced broadband signal generation method.

[0006] The second objective of this invention is to propose a programmable, domestically produced broadband signal generation device.

[0007] The third objective of this invention is to provide an electronic device.

[0008] The fourth objective of this invention is to provide a computer-readable storage medium.

[0009] The fifth objective of this invention is to provide a computer program product.

[0010] To achieve the above objectives, the first aspect of this invention proposes a programmable domestically produced broadband signal generation method, including: a programmable intermediate frequency signal generation method, a programmable multi-channel radio frequency signal generation method, a programmable frequency synthesizer signal agility generation method, and a fully domestically produced broadband signal generation method.

[0011] To achieve the above objectives, a second aspect of the present invention provides a programmable domestically produced broadband signal generation device, comprising: an intermediate frequency output unit for generating a customized intermediate frequency signal using a software-defined radio method; a radio frequency channel unit for converting the intermediate frequency signal to a radio frequency broadband signal; and a data control interface for communicating with a host computer and receiving control from the host computer according to a UDP protocol loading method.

[0012] To achieve the above objectives, a third aspect of the present invention provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of the first aspects.

[0013] To achieve the above objectives, a fourth aspect of the present invention provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of the first aspects.

[0014] To achieve the above objectives, a fifth aspect of the present invention provides a computer program product that, when executed by a processor, implements the method described in any one of the first aspects.

[0015] The technical solutions and apparatus provided by the embodiments of the present invention bring at least the following beneficial effects: A complete signal generation system from intermediate frequency generation to high frequency output has been constructed, promoting the coordinated evolution of mixed digital-analog architecture and integration of domestically produced devices. It prioritizes the adoption of software-defined radio concepts, providing new ideas for electronic countermeasures strategy design, equipment miniaturization design, and functional upgradeable design in modern communication, radar, satellite navigation and other fields.

[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a flowchart illustrating a programmable broadband signal generation method provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of a programmable broadband signal generation system provided in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the classification of devices used in the radio frequency channel according to an embodiment of the present invention; Figure 4 This is a block diagram of a radio frequency channel system provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the frequency selection logic provided in an embodiment of the present invention; Figure 6 This is a structural design diagram of the filter bank 2 RF switch group provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of a filter bank design provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structural logic of a programmable domestically produced broadband signal generation device provided in an embodiment of the present invention; Figure 9 This is a structural design diagram of a programmable domestically produced broadband signal generation device provided in an embodiment of the present invention; Figure 10 This is a physical image of a programmable, domestically produced broadband signal generation device provided in an embodiment of the present invention. Detailed Implementation

[0018] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0019] Figure 1 This is a flowchart illustrating a programmable broadband signal generation method provided in an embodiment of the present invention. Figure 2 The example shown is implemented using a programmable broadband signal generation system.

[0020] like Figure 2As shown, this programmable broadband signal generation system consists of a programmable intermediate frequency (IF) board, an RF channel, RF ports, a power supply module, and a host computer. The host computer is directly connected to the IF board and can simultaneously program and control the IF board, RF channel, and RF ports. The IF board is responsible for digital signal modulation, performing convolution in the FPGA, and outputting an IF analog signal through a DAC. The analog signal then passes through the programmed RF channel and RF ports to dynamically output the signal's frequency and power. The RF analog link has advantages such as low latency, ultra-high bandwidth, and adaptability to extreme environments. This device adopts a mixed-signal architecture, which improves flexibility and intelligence.

[0021] like Figure 1 As shown, the method includes the following steps: S1, the host computer sends configuration commands to the RAM of the intermediate frequency board via an Ethernet interface. The configuration commands include the frequency, power, waveform parameters of the intermediate frequency signal, and control parameters of the radio frequency channel. Specifically, sending configuration commands from the host computer to the intermediate frequency board's RAM via an Ethernet interface is a crucial step in achieving flexible control and rapid response of the programmable broadband signal generator. This step is based on the TCP / IP protocol stack and communicates with the intermediate frequency board through a standard RJ45 Ethernet interface. The intermediate frequency board has a built-in IP address and supports both remote network control and local independent operation modes. In some implementations, the host computer encapsulates the user-defined intermediate frequency signal frequency, power, waveform parameters, and RF channel control parameters (such as switch status, filter selection, attenuator settings, etc.) into standard TCP data packets, sends them to the FPGA control unit on the intermediate frequency board via the Ethernet interface, and the FPGA writes the relevant parameters into its onboard RAM as the basis for subsequent signal generation and processing.

[0022] In terms of parameter specifications, the intermediate frequency (IF) signal frequency configuration accuracy can reach 0.1MHz, the power adjustment range is -30dBm to +10dBm, and the step accuracy is 0.1dB. Waveform parameters support multiple modulation formats (such as AM, FM, PM, pulse modulation, etc.), and custom waveforms can be generated using tools such as Matlab and sent to the IF board via a host computer. RF channel control parameters, including the LO frequency selection of the frequency synthesizer (1MHz step), the on / off state of the RF switch group, and the channel switching of the filter bank, must all be explicitly specified in the configuration instructions to ensure the correct establishment of the signal path and the stability of signal quality.

[0023] This step is widely used in practical applications such as communication testing, radar simulation, and satellite navigation signal simulation. For example, when simulating BeiDou signals, the host computer can dynamically adjust the carrier frequency and modulation parameters output by the intermediate frequency board to achieve high-precision signal reproduction. In interference signal generation, by quickly switching the RF channel configuration, real-time output of multi-band and multi-style interference signals can be achieved.

[0024] In terms of technical effectiveness, this step enables remote real-time configuration of signal parameters, improving the system's flexibility and automation. By directly writing the configuration parameters into the intermediate frequency board's RAM, the low-speed bottleneck of traditional serial communication is avoided, meeting the fast response requirements of 2GHz instantaneous bandwidth and a frequency coverage range of 30MHz to 20GHz. Simultaneously, this design aligns with the trends of domestic production and miniaturization, providing a solid foundation for building a high-performance, low-cost, and scalable signal generation system.

[0025] Furthermore, embodiments of the present invention also support the generation of custom modulation waveforms using Matlab software, and the transmission of the waveform data to the RAM of the intermediate frequency board via an Ethernet interface for caching, so that it can be called in real time when the signal is transmitted.

[0026] Specifically, generating a custom modulation waveform using Matlab software and transmitting the waveform data to the intermediate frequency board's RAM for caching via an Ethernet interface is a key step in achieving flexible signal configuration and real-time transmission in this programmable, domestically produced broadband signal generation device. In some implementations, this step utilizes Matlab's signal processing toolbox (such as the Communications Toolbox or Signal Processing Toolbox) to model and generate the waveform, supporting various modulation methods including QAM, OFDM, FM, AM, and PM. Users can define signal parameters, such as carrier frequency, symbol rate, modulation order, pulse shape, and filter type (e.g., root-raised cosine filter), through Matlab scripts or a GUI interface to generate baseband waveform data that conforms to specific communication standards or custom requirements.

[0027] The generated waveform data is quantized in floating-point or fixed-point format, typically with 12-bit or 14-bit precision, to match the input requirements of the DAC on the intermediate frequency (IF) board. Subsequently, the waveform data is encapsulated into TCP packets and transmitted to the IF board's RAM via an Ethernet interface (RJ45). In terms of specifications, Ethernet communication uses the TCP / IP protocol, with data transmission rates reaching 1Gbps or higher, ensuring waveform data loading is completed within milliseconds. The IF board has a built-in IP address, supporting remote control and networking operations, and complies with the IEEE 802.3 standard.

[0028] In application scenarios, this step is suitable for situations requiring rapid switching and high-precision modulation, such as radar testing, satellite navigation signal simulation, and electronic warfare jamming signal generation. By caching waveform data to RAM, real-time retrieval during signal transmission is possible, avoiding signal distortion or timing deviations caused by external storage read delays. This technical solution improves system flexibility and response speed, providing a reliable data loading mechanism for domestically produced, miniaturized, and high-performance signal source equipment.

[0029] Furthermore, S1 includes: S11, the configuration command is encapsulated via TCP / IP protocol and transmitted to the DAC and FPGA modules of the intermediate frequency board at a rate of 15Gbps via the RJ45 interface.

[0030] Specifically, in some implementations, the configuration commands are encapsulated via TCP / IP protocol and transmitted to the DAC and FPGA modules of the intermediate frequency board at a rate of 15Gbps through an RJ45 interface. This technology is based on a collaborative design of high-speed Ethernet communication and digital signal processing architecture. The core of this step lies in achieving efficient and reliable data interaction between the host computer and the intermediate frequency board through standardized network protocols, thereby enabling real-time configuration and control of signal generation parameters.

[0031] At the technical implementation level, configuration commands are first encapsulated in the host computer according to the TCP / IP protocol, including fields such as IP address, port number, data packet header, and checksum, to ensure data integrity and reachability during transmission. The encapsulated data packet is then connected to the Ethernet controller on the intermediate frequency board via an RJ45 interface. This controller is typically integrated into an FPGA or dedicated communication chip, supporting Ethernet communication rates of 10 / 100 / 1000Mbps or even 10Gbps. In this device, a high-speed transmission rate of 15Gbps is used, primarily relying on the collaborative operation of the high-speed SerDes interface within the FPGA and the JESD204B interface of the CX8144 RF transceiver to achieve rapid data parsing and storage.

[0032] In terms of specifications, the transmission rate of the configuration command is set to 15Gbps, which meets the subclass 1 rate requirements of the JESD204B standard. It supports 8B / 10B encoding and decoding mechanisms to ensure low bit error rate and high reliability of data transmission. The IP address built into the intermediate frequency board supports static or dynamic allocation, facilitating remote network control. The frequency setting accuracy of the configuration command is 0.1MHz, the power adjustment range is 0.5dB to 31.5dB, and it supports programmable configuration of multi-stage attenuators.

[0033] In application scenarios, this step is widely used in remote signal configuration, multi-channel parallel control, and automated testing systems. Through the Ethernet interface, users can remotely program the intermediate frequency board without physical contact, improving the maintainability and deployment flexibility of the equipment. Simultaneously, this configuration method supports parallel control of multiple intermediate frequency boards, making it suitable for multi-channel signal generation systems.

[0034] From a technical perspective, this step enables real-time, high-precision configuration of the FPGA and DAC modules in the intermediate frequency board, ensuring the flexibility and stability of signal generation. High-speed data transmission shortens the configuration response time, improves the overall real-time performance and dynamic adjustment capabilities of the system, and lays a solid foundation for subsequent RF up-conversion and signal output.

[0035] S12, the intermediate frequency board has a built-in IP address, supports remote network control, and returns a configuration success status code after receiving a configuration command.

[0036] Specifically, in some implementations, the intermediate frequency board has a built-in IP address, supports remote network control, and returns a configuration success status code after receiving a configuration command. Its technical implementation is based on Ethernet communication protocol and embedded control architecture. The intermediate frequency board achieves remote communication with the host computer by integrating an Ethernet controller and a TCP / IP protocol stack. Specifically, the intermediate frequency board is equipped with an RJ45 Ethernet interface, supporting 10 / 100 / 1000Mbps adaptive rates, and connects to the external network via a standard Ethernet cable. At the hardware level, the intermediate frequency board uses the Fudan Microelectronics FMQL45T900 FPGA development board as the main control unit, which integrates an Ethernet MAC unit and achieves physical layer communication through an external domestically produced JEM88E1111HV chip. At the software level, the intermediate frequency board runs a lightweight embedded operating system or bare-metal program, supporting the reception and processing of remote control commands based on UDP or TCP protocols.

[0037] When the host computer sends configuration commands (such as frequency, power, waveform, etc.) via Ethernet, the intermediate frequency board identifies the target device through its IP address and parses the received TCP data packets. Configuration parameters are stored in the onboard RAM for subsequent real-time access by the digital modulation module. After parameter loading and verification, the intermediate frequency board controls the DAC (such as the CityCore CX8144) via FPGA logic to output the intermediate frequency analog signal, and simultaneously configures the frequency synthesizer, RF switch group, and programmable attenuator in the RF channel. If the configuration process is successful, the intermediate frequency board will return a standard status code (such as HTTP 200 OK or 0x01 in a custom protocol indicating successful configuration) via the Ethernet interface to confirm that the device has entered the expected operating state.

[0038] This step plays a crucial role in the system, realizing a closed-loop mechanism for remote control and status feedback, and improving the intelligence and maintainability of the equipment. Its technical value lies in supporting multi-device network control, reducing manual intervention, improving configuration efficiency, and meeting the design goals of localization, miniaturization, and high integration.

[0039] S2, the intermediate frequency board uses the FPGA to complete digital modulation processing according to the configuration instructions, and converts the digital signal into an analog intermediate frequency signal output through the DAC.

[0040] Specifically, in some implementations, the intermediate frequency board, according to the configuration instructions, uses an FPGA to perform digital modulation processing and converts the digital signal into an analog intermediate frequency signal output via a DAC. This is one of the core steps in realizing programmable broadband signal generation in this device. This step, based on the collaborative mechanism of digital baseband signal processing and analog intermediate frequency signal conversion, ensures that the signal has high fidelity, high bandwidth, and low distortion characteristics before entering the radio frequency channel.

[0041] In terms of technical implementation, the intermediate frequency (IF) board design uses the Fudan Microelectronics FMQL45T900 FPGA chip as the digital modulation processing unit. It integrates high-performance logic resources and a DSP module, supporting real-time computation of complex modulation algorithms (such as QAM, OFDM, FM, AM, etc.). The FPGA extracts configuration parameters (such as IF frequency, modulation method, waveform data, etc.) by parsing TCP data packets sent from the host controller, and performs digital modulation processing on the baseband signal based on these parameters. The modulated digital signal is transmitted to the DAC module via the JESD204B high-speed interface, realizing the conversion from the digital domain to the analog domain. The DAC uses the CityCore Technology CX8144 RF transceiver, supporting 14-bit precision and a 12GSPS sampling rate, and can directly output analog IF signals with a frequency range from DC to 6GHz, meeting the processing requirements of a 2GHz instantaneous bandwidth.

[0042] In terms of specifications, the FPGA's clock source needs to have high stability and low phase noise, typically using a 100MHz crystal oscillator with a frequency setting accuracy of 0.1MHz. The DAC's output bandwidth, sampling rate, and dynamic range (SNR, SFDR) directly affect the fidelity and spurious rejection capability of the intermediate frequency signal; its SFDR should be better than 70dBc to ensure the purity of the output signal. Furthermore, the JESD204B interface uses Subclass 1 mode and supports 8B / 10B encoding / decoding, ensuring reliable data transmission and low latency.

[0043] In terms of application scenarios, this step is widely used in radar testing, satellite communication signal simulation, and electronic warfare jamming signal generation. Through the programmability of FPGAs, users can flexibly configure modulation methods and waveform content to achieve rapid generation and switching of complex signals. The high-quality output of the intermediate frequency (IF) signal provides a stable foundation for subsequent RF upconversion, especially in multi-stage mixing architectures, where the bandwidth and spectral purity of the IF signal have a decisive impact on the performance of the final output signal.

[0044] In terms of technical effectiveness, this step achieves efficient integration of digital modulation and analog intermediate frequency signal generation, improving the flexibility and real-time performance of signal generation. At the same time, by selecting domestically produced components, it enhances the system's autonomy, controllability, and environmental adaptability, laying a solid foundation for the high-performance output of subsequent RF links.

[0045] Furthermore, S2 includes: S21, the FPGA uses the Fudan Microelectronics FMQL45T900 chip to execute the convolution modulation algorithm to generate a high-precision intermediate frequency signal.

[0046] Specifically, in this step, the FPGA uses the Fudan Microelectronics FMQL45T900 chip to execute a convolution modulation algorithm to generate a high-precision intermediate frequency signal. This step is the core processing stage of the entire programmable broadband signal generation device. Its technical implementation is based on the efficient collaboration between digital signal processing (DSP) and field-programmable gate array (FPGA), aiming to achieve real-time generation and output of complex modulation signals.

[0047] In some implementations, the FMQL45T900 chip serves as the main control unit of the intermediate frequency (IF) board, possessing high parallel computing capabilities and low latency, making it suitable for real-time processing of broadband signals. The convolution modulation algorithm is implemented within the FPGA using a hardware description language (such as Verilog or VHDL), utilizing its internal DSP slice and block RAM resources to construct a multi-channel parallel processing structure. This algorithm achieves precise modulation of the IF signal by convolving the baseband signal with the modulation waveform, thereby improving the signal's spectral purity and modulation accuracy.

[0048] In terms of specifications, the FPGA's operating clock frequency is typically configured from 125MHz to 300MHz to meet the real-time processing requirements of the intermediate frequency (IF) signal bandwidth (up to 2GHz). The number of taps for convolution operations is generally set to 64 to 256 to balance computational complexity and modulation accuracy. The IF signal output frequency range is 10MHz to 6GHz, with a frequency setting accuracy of 0.1MHz, meeting the high-precision requirements for multi-band signal generation. Furthermore, high-speed data transmission between the FPGA and DAC is achieved via the JESD204B interface, using Subclass 1 mode, supporting 8B / 10B encoding and decoding, and achieving a data rate of up to 15Gbps, ensuring signal real-time performance and integrity.

[0049] In practical applications, this step is mainly used to generate standard communication signals, analog modulated signals, and jamming signals, suitable for scenarios such as radar, satellite communication, and electronic warfare. Through convolutional modulation, FPGAs can flexibly support multiple modulation formats (such as QPSK, OFDM, etc.) and achieve high-fidelity signal output. In the context of miniaturization and domestic production, this step effectively improves the autonomy and controllability of signal generation and the degree of system integration, providing a high-quality intermediate frequency signal source for subsequent RF up-conversion and output, demonstrating significant technical value and engineering practicality.

[0050] S22, the DAC uses the CX8144 RF transceiver from Citychip Technology, which supports 14-bit, 12GSPS sampling rate and enables direct analog signal output at frequencies below 6GHz.

[0051] Specifically, the DAC uses the CX8144 RF transceiver from Citychip Technology, supporting 14 bits and a 12GSPS sampling rate to achieve direct analog signal output at frequencies below 6GHz. This step is a crucial link in the digital generation of the intermediate frequency signal and the connection between the RF analog link in this device, and its technical implementation is based on the principles of high-precision digital-to-analog conversion and broadband signal reconstruction.

[0052] At the technical implementation level, the CX8144, as a highly integrated RF direct sampling device, features 14-bit resolution and a sampling rate of 12 GSPS. It can directly convert digital baseband or intermediate frequency (IF) signals into analog RF signals, covering the analog output band up to 6 GHz without the need for an additional up-conversion module. This DAC interacts with the FPGA (Fudan Microelectronics FMQL45T900) via a JESD204B high-speed serial interface, employing subclass 1 mode and supporting 8B / 10B encoding / decoding to ensure data transmission integrity and a low bit error rate. In this device, the DAC's output signal serves as an IF analog signal, directly entering the RF channel for subsequent up-conversion processing.

[0053] In terms of specifications, the CX8144's 14-bit precision provides approximately 160dB of dynamic range, meeting the requirements for high-fidelity signal output. Its 12GSPS sampling rate enables the DAC to support Nyquist frequencies up to 6GHz while ensuring a signal bandwidth of up to 2GHz, meeting the instantaneous bandwidth design requirements of this device. Furthermore, the DAC's output signal exhibits excellent harmonic suppression, typically exceeding -40dBc, ensuring signal purity. Its output impedance of 50Ω provides good matching with the SMA interface of subsequent RF links, facilitating signal transmission.

[0054] In application scenarios, this DAC module is widely used for signal generation in the C and X bands, and is particularly suitable for test scenarios requiring rapid frequency switching and complex modulation. By programming the DAC's output parameters, such as frequency, phase, and amplitude, it can generate various modulation formats (such as AM, FM, and PM) and custom waveforms. In fields such as satellite navigation signal simulation, radar testing, and communication system simulation, this module can provide high-precision, low-latency analog signal output, improving test efficiency and signal accuracy.

[0055] The technical value of this step lies in achieving full independent control of the signal source by adopting domestically produced high-performance DAC devices. Simultaneously, the integration of the JESD204B high-speed interface technology enhances the overall system integration and signal processing capabilities. The CX8144's high sampling rate and wide output bandwidth provide a solid foundation for the subsequent multi-stage mixing and filtering design of the RF channels, making it a core supporting module for achieving the device's wideband, low-spurious, and high dynamic range output.

[0056] S3, the radio frequency channel, according to the control parameters of the radio frequency channel, controls the radio frequency switch group and frequency synthesizer through dynamic frequency selection logic to generate a radio frequency signal covering the frequency band from 30MHz to 20GHz after multi-stage mixing and filtering of the analog intermediate frequency signal.

[0057] Because the intermediate frequency board's output frequency cannot reach the design requirement of a maximum frequency of 20GHz, an upconversion link needs to be designed. The components mainly consist of analog devices, utilizing both passive and active components. Among the active components, the RF switch group and frequency synthesizer are programmable control devices. For a classification of components used in the RF channel, see [link to relevant documentation]. Figure 3 .

[0058] Specifically, based on the control parameters of the RF channel, the RF channel uses dynamic frequency selection logic to control the RF switch group and frequency synthesizer, generating an RF signal covering the 30MHz to 20GHz frequency band after multi-stage mixing and filtering of the analog intermediate frequency signal. This step is the core link in realizing broadband signal upconversion and frequency band switching, and its technical implementation is based on a superheterodyne structure and a programmable control mechanism.

[0059] At the technical implementation level, the RF channel adopts a multi-stage mixing architecture, and the RF channel system block diagram is as follows: Figure 4 As shown, the frequency selection logic for broadband signals is as follows: Figure 5 As shown. Figure 5 In the process, logic 1 is the output frequency logic of the intermediate frequency board; logic 2 is the low-frequency / high-frequency selection logic; logic 3 is the frequency point selection logic of the frequency synthesizer; and logic 4 is the filter channel selection logic. First, the analog intermediate frequency (IF) signal output from the intermediate frequency board is mixed with the local oscillator signal generated by the frequency synthesizer (LO) to generate a higher frequency RF signal. According to the frequency point selection logic of the frequency synthesizer, the frequency of the LO signal is programmable, with a step accuracy of 1MHz and an operating range of 8-26.5GHz. In the high-frequency section, a two-stage mixing structure is adopted. After the first-stage mixing, spurious emissions are suppressed by bandpass filter bank 1 (passband 2GHz). The second-stage mixing is then combined with filter bank 2 (passband also 2GHz) to further improve signal purity and frequency band coverage. The mixer selected is the domestically produced double-balanced mixer HGC518, with an RF input / output range of DC-18GHz, an LO input of 18-40GHz, an IF input of DC-18GHz, an isolation of ≥30dB at each port, and an input P1dB of 11dBm, ensuring high linearity and low phase noise during the mixing process.

[0060] In terms of specifications, the RF channel must meet the following requirements: spurious rejection ratio (ACLR) ≥ -40dBc, output power stability ≤ 3dB, and instantaneous bandwidth ≥ 2GHz. The frequency synthesizer has an output power of 16dBm and a frequency stability of 0.5ppm, ensuring the accuracy and stability of frequency switching. The RF switch assembly uses domestically produced components such as HGC101 (0.1-6GHz), HGC103L (0.5-18GHz), and HGC120A (0.3-20GHz), and achieves path switching through level control, ensuring seamless signal transition between different frequency bands.

[0061] At the application level, this step is widely used in radar testing, satellite communication, and electronic warfare jamming signal generation. Through dynamic frequency selection logic, the system can quickly switch to the required frequency band, such as C-band (4-8GHz), X-band (8-12GHz), or Ku-band (12-18GHz), and optimize signal quality in conjunction with filter banks. The RF port integrates a 6-digit digitally controlled attenuator (HGC212LC5), supporting power adjustment from 0.5dB to 31.5dB to meet output requirements in different testing environments.

[0062] The technical value of this step lies in achieving efficient generation and spurious suppression of ultra-wideband signals through the coordinated control of multi-stage mixing and filtering. At the same time, relying on domestically produced devices and programmable logic, it significantly improves the system's flexibility, miniaturization, and domestic substitution capabilities, providing reliable technical support for signal simulation and testing in complex electromagnetic environments.

[0063] Furthermore, S3 includes: S31, the dynamic frequency selection logic includes logic 2a and logic 2b, wherein logic 2a divides the signal into a low-frequency part (0.1-6GHz) and a high-frequency part (6-20GHz), and logic 2b integrates the low-frequency and high-frequency signals to the same output port through an RF switch group. Specifically, refer to Figure 6 The dynamic frequency selection logic (logic 2a and logic 2b) in this step is a key component in realizing the multi-band signal integration and output of the programmable domestic broadband signal generator. In some implementations, logic 2a is responsible for dividing the analog signal output from the intermediate frequency board into a low-frequency part (0.1-6GHz) and a high-frequency part (6-20GHz) according to its frequency characteristics, so that it can be processed through different RF links. This division is based on the spectral distribution of the signal and the device characteristics of the RF channel, ensuring that the low-frequency signal can be directly output after power adjustment by a low-noise amplifier (such as HGC329, HGC180-5) and a fixed attenuator (such as HGC191 series), while the high-frequency signal needs to be processed by a two-stage mixing architecture (such as HGC518 dual-balanced mixer) and a custom cavity bandpass filter (passband 2GHz) for spurious suppression and frequency up-conversion.

[0064] Furthermore, Logic 2b integrates low-frequency and high-frequency signals to the same output port through RF switch groups (such as HGC101, HGC103L, HGC120A, and HGC182-4). Since the gain of low-frequency signals in low-noise amplifiers is typically higher than that of high-frequency signals, and high-frequency signals experience greater path loss after multiple mixing and filtering stages, low-noise amplifiers with different gain configurations are required for compensation during integration to ensure that the power stability of the output signal is within 3dB. The RF switch groups employ level control and support various switch types such as SPDT, SP4T, SP6T, and SP8T, covering an operating frequency range of 0.1-20GHz, with insertion loss less than 0.5dB and isolation greater than 20dB, meeting the requirements for high linearity and low phase distortion in broadband signal path switching.

[0065] This step acts as a bridge in the overall system, enabling the device to switch flexibly between C, X, and Ku bands and achieve seamless signal integration through a unified output port. Its technical value lies in improving the continuity, stability, and programmability of signal output, while effectively reducing system complexity and size, meeting the design goals of miniaturization and domestic production.

[0066] S32, the frequency synthesizer adopts a "fixed plus dynamic" frequency selection method, wherein the fixed frequency is used for the first stage of mixing, and the dynamic frequency is adjusted according to the bandwidth range of the intermediate frequency signal to avoid harmonics falling into the filter passband.

[0067] Specifically, in the RF channel design of this device, the frequency synthesizer adopts a "fixed plus dynamic" frequency selection method. Its technical implementation principle is based on a multi-stage mixing strategy in a superheterodyne structure, aiming to optimize signal spurious suppression performance and improve frequency coverage flexibility. Specifically, the first-stage mixer uses a fixed-frequency local oscillator (LO) signal to upconvert the analog intermediate frequency (IF) signal output from the intermediate frequency board to an intermediate RF band. The selection of this fixed frequency point must meet the matching relationship with the IF signal bandwidth, and is usually set within a range with a fixed offset from the IF signal center frequency. For example, when the IF signal is 1GHz, the first-stage LO can be set to 3GHz to achieve an initial RF output of 4GHz. The second-stage mixer uses a dynamic frequency point, whose frequency is adjusted in real time according to the instantaneous bandwidth range of the IF signal to ensure that the frequency of the final output signal accurately falls into the target frequency band (e.g., 6-18GHz), while avoiding harmonics generated during the mixing process (such as integer multiples of the LO frequency) from falling into the filter passband, thereby reducing spurious signal interference to the target signal.

[0068] Regarding parameter settings, the frequency synthesizer has a fixed frequency step of 1MHz, while the dynamic frequency step is dynamically planned based on the intermediate frequency signal bandwidth (maximum 2GHz). The LO frequency range covers 8-26.5GHz, the output power is 16dBm, and the frequency stability is 0.5ppm. The mixer uses the domestically produced double-balanced mixer HGC518, with an LO input range of 18-40GHz, an IF input of DC-18GHz, port isolation of up to 30dB, and an input P1dB of 11dBm, ensuring linearity and spurious suppression during the mixing process. Furthermore, as... Figure 7 As shown, both filter bank 1 and filter bank 2 are designed as custom cavity bandpass filters with a passband of 2 GHz. Their transition band characteristics are matched with the adjustment logic of the dynamic LO frequency point to achieve effective suppression of harmonics and image frequencies.

[0069] This step plays a crucial role in practical applications, especially in the generation of broadband signals in the C, X, and Ku bands. Through the coordinated control of fixed and dynamic frequency points, the system can quickly switch between different frequency bands while maintaining high signal purity and low spurious characteristics. In scenarios such as satellite communication testing, radar signal simulation, and electronic warfare jamming signal generation, this design can effectively improve the adaptability and stability of the signal source, meeting the testing requirements in complex electromagnetic environments. Its technical value lies in significantly reducing harmonic interference and improving signal quality through a dynamic frequency adjustment mechanism, while also enhancing the system's programmability and domestic substitution capabilities.

[0070] S4 adjusts the output signal power through the programmable attenuation module of the RF port to achieve adjustable signal output power within the range of -3dBm to 15.5dBm and power stability within 3dB.

[0071] Specifically, adjusting the output signal power via a programmable attenuation module on the RF port is a crucial step in achieving adjustable output power within the range of -3dBm to 15.5dBm with power stability within 3dB. This module is typically implemented using a Digital Step Attenuator (DSA), with its core component being the HGC212LC5 six-digit DSA chip. This chip supports attenuation adjustment within a frequency range of 0.1–18GHz, with a step accuracy of 0.5dB and an attenuation range of 0.5dB to 31.5dB. This chip operates via SPI or I / O. 2 The system communicates with the host computer via a digital interface such as C, receives power adjustment commands from the control software, and dynamically adjusts the internal attenuation levels according to the commands, thereby achieving precise control of the RF output signal.

[0072] At the technical implementation level, this module is embedded at the output of the RF channel, located between the low-noise amplifier (LNA) and the SMA output connector. By introducing a programmable attenuator into the RF link, the final output signal can be linearly adjusted without changing the output power of the signal source, avoiding nonlinear distortion or phase noise degradation caused by directly adjusting the signal source. Furthermore, the attenuator's high isolation (>30dB) and low insertion loss (<0.5dB) characteristics help maintain signal purity and stability.

[0073] In terms of specifications, this module needs to meet the following requirements: output power adjustment range of -3dBm to 15.5dBm, corresponding to a maximum attenuation of 18.5dB. Power stability is required to be within 3dB, mainly depending on the temperature stability, voltage stability of the attenuator, and timing consistency of the control signal. At extreme temperatures (-40°C)... Up to +85 Under conditions of voltage fluctuation (±5%), the temperature coefficient of the attenuator should be less than ±0.05dB / This is to ensure the long-term stability of output power.

[0074] In application scenarios, this module is widely used in communication testing, radar simulation, and satellite navigation signal simulation. For example, when simulating satellite signals, the transmit power needs to be dynamically adjusted according to the receiver sensitivity to simulate signal strength at different distances. In interference signal generation, the programmable attenuation module can be combined with different interference patterns to achieve multi-level power control, improving the flexibility and realism of the test.

[0075] The technical value of this step lies in the fact that by introducing a domestically produced programmable attenuation module, high-precision and wide-range adjustment of the signal output power is achieved, while ensuring the stability and consistency of the output signal. This provides important support for the localization, miniaturization, and intelligentization of the entire signal generation device.

[0076] The programmable broadband signal generation method of this invention realizes dynamic generation and high-precision frequency control of ultra-wideband signals. Through the integration of a mixed-signal architecture and domestically produced components, it effectively improves the flexibility, bandwidth performance and environmental adaptability of signal output, and meets the needs of multi-band communication and testing.

[0077] To achieve the above embodiments, the present invention also proposes a programmable domestically produced broadband signal generation device. Figure 8 This is a schematic diagram of a programmable, domestically produced broadband signal generation device provided in an embodiment of the present invention. Figure 8 As shown, the device includes: The configuration instruction sending module 100 is used to send configuration instructions to the RAM of the intermediate frequency board via the host control computer through the Ethernet interface. The configuration instructions include the frequency, power, waveform parameters of the intermediate frequency signal and the control parameters of the radio frequency channel. The digital modulation processing module 200 is used by the intermediate frequency board to perform digital modulation processing using the FPGA according to the configuration instructions, and to convert the digital signal into an analog intermediate frequency signal output through the DAC; The radio frequency signal generation module 300 is used to generate a radio frequency signal covering the 30MHz to 20GHz frequency band by controlling the radio frequency switch group and frequency synthesizer through dynamic frequency selection logic according to the control parameters of the radio frequency channel. After the analog intermediate frequency signal is mixed and filtered through multiple stages, the radio frequency channel generates a radio frequency signal. The power adjustment module 400 is used to adjust the power of the output signal through the programmable attenuation module of the RF port, so as to achieve adjustable signal output power in the range of -3dBm to 15.5dBm and power stability within 3dB.

[0078] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0079] To implement the above embodiments, the present invention also proposes an electronic device, comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory to implement the method provided in the foregoing embodiments.

[0080] To implement the above embodiments, the present invention also proposes a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the methods provided in the foregoing embodiments.

[0081] To implement the above embodiments, the present invention also proposes a computer program product, including a computer program that, when executed by a processor, implements the methods provided in the foregoing embodiments.

[0082] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in this invention all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0083] It should be noted that personal information collected from users should be used for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. Furthermore, such collection / sharing should only be conducted after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization that includes authorization of relevant user information before the user uses the function. In addition, any necessary steps must be taken to protect and safeguard access to such personal information data and ensure that others with access to personal information data comply with their privacy policies and procedures.

[0084] This invention is intended to provide implementation schemes for users to selectively prevent the use or access to personal information data. That is, this disclosure is intended to provide hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, risks can be minimized by restricting data collection and deleting data. Furthermore, where applicable, such personal information can be de-identified to protect user privacy.

[0085] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0086] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0087] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of the invention pertain.

[0088] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0089] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any of the following techniques known in the art, or a combination thereof: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0090] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiments.

[0091] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0092] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

[0093] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0094] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A programmable, domestically produced broadband signal generation method, characterized in that, This is achieved through a programmable broadband signal generation system, and the methods include: S1, the host controller sends configuration instructions to the RAM of the intermediate frequency board via an Ethernet interface. The configuration instructions include the frequency, power, waveform parameters of the intermediate frequency signal and the control parameters of the radio frequency channel. S2, the intermediate frequency board performs digital modulation processing using the FPGA according to the configuration instructions, and converts the digital signal into an analog intermediate frequency signal output through the DAC; S3, the radio frequency channel, according to the control parameters of the radio frequency channel, controls the radio frequency switch group and frequency synthesizer through dynamic frequency selection logic to generate a radio frequency signal covering the 30MHz to 20GHz frequency band after multi-stage mixing and filtering of the analog intermediate frequency signal; S4 adjusts the output signal power through the programmable attenuation module of the RF port to achieve adjustable signal output power within the range of -3dBm to 15.5dBm and power stability within 3dB.

2. The method as described in claim 1, characterized in that, The step of sending configuration commands to the RAM of the intermediate frequency board via an Ethernet interface from the host controller also includes: The configuration instructions are encapsulated via TCP / IP protocol and transmitted to the DAC and FPGA modules of the intermediate frequency board at a rate of 15Gbps through the RJ45 interface. The intermediate frequency board has a built-in IP address, supports remote network control, and returns a configuration success status code after receiving a configuration command.

3. The method as described in claim 1, characterized in that, The intermediate frequency board, according to the configuration instructions, utilizes the FPGA to perform digital modulation processing, and further includes: The FPGA uses the Fudan Microelectronics FMQL45T900 chip to execute a convolution modulation algorithm to generate a high-precision intermediate frequency signal. The DAC uses the CX8144 RF transceiver from Citychip Technology, which supports 14-bit, 12GSPS sampling rate and enables direct analog signal output at frequencies below 6GHz.

4. The method as described in claim 1, characterized in that, The radio frequency channel, based on its control parameters, controls the radio frequency switch group and frequency synthesizer via dynamic frequency selection logic, and also includes: The dynamic frequency selection logic includes logic 2a and logic 2b, wherein logic 2a divides the signal into a low-frequency part and a high-frequency part, and logic 2b integrates the low-frequency and high-frequency signals to the same output port through an RF switch group. The frequency synthesizer employs a fixed and dynamic frequency selection method, where the fixed frequency is used for the first-stage mixing, and the dynamic frequency is adjusted according to the bandwidth range of the intermediate frequency signal to prevent harmonics from falling into the filter passband.

5. The method as described in claim 1, characterized in that, Also includes: A custom modulation waveform is generated using Matlab software, and the waveform data is transmitted to the RAM of the intermediate frequency board via an Ethernet interface for caching, so that it can be called in real time when the signal is transmitted.

6. A programmable, domestically produced broadband signal generation device, characterized in that, This is achieved through a programmable broadband signal generation system, and the device includes: The configuration instruction sending module is used to send configuration instructions to the RAM of the intermediate frequency board via the host control computer through the Ethernet interface. The configuration instructions include the frequency, power, waveform parameters of the intermediate frequency signal and the control parameters of the radio frequency channel. The digital modulation processing module is used by the intermediate frequency board to perform digital modulation processing using the FPGA according to the configuration instructions, and to convert the digital signal into an analog intermediate frequency signal output through the DAC; The radio frequency signal generation module is used to control the radio frequency switch group and frequency synthesizer through dynamic frequency selection logic according to the control parameters of the radio frequency channel, and generate a radio frequency signal covering the frequency band from 30MHz to 20GHz after multi-stage mixing and filtering of the analog intermediate frequency signal. The power adjustment module is used to adjust the output signal power through the programmable attenuation module of the RF port, so as to achieve adjustable signal output power in the range of -3dBm to 15.5dBm and power stability within 3dB.

7. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-5.

9. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method of any one of claims 1-5.

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