Packet caching method, apparatus and device

Abstract

The application provides a message caching method, device and equipment in a forwarding process, and is used for solving the technical problems of cache fragmentation and low message forwarding efficiency caused by cache management in a high bandwidth scenario. The application caches message fragment groups based on logical cache areas, combines a plurality of logical cache areas into a logically continuous cache space, effectively manages the cache through the combination of an idle logical cache area chain table and a message descriptor, and simultaneously uses a dynamic hash function to store the message fragments in a dispersed manner on a plurality of banks, so as to reduce the formation of cache access hot spots, improve the access performance and the utilization rate of the cache.

Description

Technical Field

[0001] This application relates to the field of data communication technology, and in particular to a message caching method, apparatus and device. Background Technology

[0002] With the rapid development of communication technologies such as 5G (5th Generation Mobile Communication Technology) and cloud computing, network traffic is growing exponentially, leading to increasingly stringent demands on packet forwarding rates. For example, the single-port forwarding rate of switches within data centers has evolved from 100Gbps (Gigabits Per Second) to 400Gbps and even 800Gbps. During packet forwarding, due to the suddenness and volatility of input traffic (such as a 3-5 fold increase in traffic during peak periods), network devices (such as switches and routers) need to temporarily store the packet data to be forwarded in a cache (such as Static Random-Access Memory, SRAM) before reading, processing, and sending the packet data based on forwarding rules. Therefore, the efficiency of address management after packet storage and the utilization rate of the stored packet space directly determine the processing latency and resource consumption of the entire forwarding system, becoming key factors restricting the improvement of packet forwarding rates.

[0003] In existing technologies, mainstream memory management schemes are based on MMU (Memory Management Unit), with the "descriptor pool + bitmap management" approach being the most widely used. The core implementation logic of this scheme is as follows: First, the SRAM used to store packets is divided into fixed-size cache blocks (e.g., 1MB of SRAM is divided into 256B / block cache blocks, totaling 4096 cache blocks); second, a bitmap (with the same number of bits as the number of cache blocks, such as a 4096-bit bitmap) is used to mark the free / occupied status of each cache block (e.g., "1" indicates free, "0" indicates occupied), while maintaining a descriptor pool (stored in another SRAM block). Each descriptor is used to record the storage information of a single packet (including start address, end address, packet length, etc.).

[0004] When a message arrives, the MMU's specific operation procedure is as follows:

[0005] (1) Calculate the required number of buffer blocks n based on the message length L (n = ceil (L / buffer block size), e.g., when L = 500B, n = 2);

[0006] (2) Find n consecutive free blocks marked "1" in the bitmap;

[0007] (3) If a consecutive free buffer block that meets the conditions is found, the corresponding block's marker in the bitmap is updated (from "1" to "0"), and the start address (first block address), end address (last block address), and message length L of the message are written into the corresponding descriptor. At the same time, the valid bit of the descriptor is set to "1".

[0008] (4) Write the message data into the allocated n buffer blocks.

[0009] After the message forwarding is complete, the memory release process is as follows:

[0010] (1) Locate the corresponding cache block based on the address information in the descriptor;

[0011] (2) Change the flags of these cache blocks in the bitmap from "0" back to "1";

[0012] (3) Set the valid position of the descriptor to "0" to complete the reclamation of the cache block and descriptor.

[0013] However, the existing "descriptor pool + bitmap management" solution has significant technical flaws:

[0014] Because this solution requires allocating contiguous cache blocks based on message size, and since message sizes vary and message caching operations are very frequent, frequent writing and releasing of cache blocks occupied by small messages will continuously reduce the large contiguous cache space, disrupting the continuity of the cache space and leading to cache fragmentation. This problem directly reduces cache utilization. To avoid further deterioration of memory fragmentation, existing solutions require additional defragmentation algorithms (such as periodically merging contiguous free blocks) and supporting hardware logic (such as block migration control modules). This not only increases hardware design complexity and chip area overhead, but also introduces "processing latency" (usually in the μs / microsecond range) during the defragmentation process, which in turn restricts the improvement of message forwarding rate and cannot meet the requirements of "low latency and high resource utilization" in high-bandwidth scenarios. Summary of the Invention

[0015] This application provides a message caching method, apparatus, and device during the forwarding process to solve the technical problems of cache fragmentation and low message forwarding efficiency caused by cache management in high-bandwidth scenarios.

[0016] Based on one aspect of the embodiments of this application, this application provides a message caching method, the method comprising:

[0017] In response to a message caching request, the address of one or more logical buffers for caching messages is obtained from the free logical buffer list; each logical buffer includes the same number of cache blocks belonging to different banks.

[0018] The message is written sequentially into one or more logical buffers in units of fragment groups, and a message descriptor for the message is created; the fragments in the fragment group are mapped and written into different buffer blocks in the logical buffers through a hash function; the message descriptor provides the addresses of all logical buffers storing the message and the message length information.

[0019] Based on the embodiments of this application, the method further includes:

[0020] In response to a message read request, the message fragments are read sequentially from each logical buffer according to the logical buffer address and message length provided by the message descriptor. During reading, the same hash function as during writing is used to read fragments from the buffer blocks in the logical buffer.

[0021] After a successful read, the address of one or more logical buffers storing the message is returned to the free logical buffer list and the message descriptor is deleted.

[0022] Based on the embodiments of this application, the logical cache area is further composed of cache blocks on the same row in the same cache (SRAM), and the size of the cache block is the same as that of the packet fragment;

[0023] The hash function that maps fragments in a message fragment group to cache blocks in a logical buffer includes at least a partition factor and a fragmentation factor, and may further include a constant factor; the value of the partition factor is determined by the address or index of the logical buffer; the value of the fragmentation factor is determined by the address or index of the fragments within the fragment group.

[0024] Which cache block in the logical cache is written to by a shard mapping in a shard group is determined at least by the partition factor, the shard factor, and the number of banks.

[0025] Based on the embodiments of this application, the process of sequentially writing the message into the one or more logical buffers in units of fragment groups further includes:

[0026] The number of message fragments is determined based on the message length, and the message fragments are then divided into multiple fragment groups in sequence.

[0027] After obtaining the address of a free logical cache from the free logical cache linked list, the mapping write interface is called according to the order of the shard groups to write the shards in the current shard group to be written into the cache blocks in the free logical cache.

[0028] After successfully writing the first fragment group, a message descriptor is created for the message. The message descriptor records the message length and the address of the first logical buffer. After successfully writing subsequent fragment groups, the addresses of subsequent logical buffers are recorded in a linked list based on the message descriptor.

[0029] The process of sequentially reading the fragments of a message based on its message descriptor includes:

[0030] Obtain the address of the first logical buffer and the message length based on the message descriptor, and calculate the number of fragment groups based on the message length;

[0031] Based on the address of the first logical cache and the addresses of subsequent logical caches recorded in a linked list, the mapping read interface is called to read each shard group from the corresponding logical cache in sequence; during reading, the same hash function as during writing is used to read the shards in the shard group from the cache blocks in the logical cache.

[0032] Based on the embodiments of this application, further, during initialization, all free logical cache areas in the cache space are traversed, and the addresses of the free logical cache areas are added to the free logical cache area linked list;

[0033] After successfully reading the message, the address of the released logical buffer is added to the end of the free logical buffer list.

[0034] Based on the embodiments of this application, the cache space storing the free logical cache area linked list and the message descriptor of the message belongs to a different physical cache (e.g., SRAM1 and SRAM2) from the cache space storing the logical cache area.

[0035] Based on another aspect of the embodiments of this application, this application also provides a message buffering device, the device comprising:

[0036] The message receiving module is used to respond to message caching requests by requesting the address management module for the address of one or more free logical buffers (buffers) for caching the message; each logical buffer includes the same number of cache blocks belonging to different banks;

[0037] The address management module is used to manage the free logical buffer list and message descriptors. It allocates the address of a free logical buffer for the message from the free logical buffer list and creates a message descriptor for the message. The message descriptor provides the addresses of all logical buffers storing the message and the message length information.

[0038] The message storage module is used to cache messages and write the messages sequentially into one or more requested logical buffers in units of fragment groups; the fragments in the fragment group are mapped and written into different cache blocks in the logical buffers through a hash function.

[0039] Based on the embodiments of this application, the apparatus further includes:

[0040] The message reading module is used to respond to message reading requests and, based on the message descriptor, call the interface provided by the message storage module to read the cached message;

[0041] The message storage module is also used to read the fragment group of the message sequentially from each logical buffer according to the logical buffer address and message length provided by the message descriptor. When reading, the same hash function as when writing is used to read the fragments in the fragment group from the cache block in the logical buffer.

[0042] The address management module is also used to put the address of one or more logical buffers storing the message back into the free logical buffer list after a successful read.

[0043] Based on the embodiments of this application, the logical cache area is further composed of cache blocks on the same row in the same cache (SRAM), and the size of the cache block is the same as that of the packet fragment;

[0044] The hash function that maps fragments in a message fragment group to cache blocks in a logical buffer includes at least a partition factor and a fragmentation factor, and may further include a constant factor; the value of the partition factor is determined by the address or index of the logical buffer; the value of the fragmentation factor is determined by the address or index of the fragments within the fragment group.

[0045] Which cache block in the logical cache area a shard mapping in a shard group is written to is determined at least by the partition factor, shard factor, and number of memory blocks.

[0046] Based on the embodiments of this application, the message receiving module further determines the number of message fragments according to the message length and divides the message fragments into multiple fragment groups in sequence; after obtaining the address of an idle logical buffer from the idle logical buffer linked list managed by the address management module, the module calls the mapping write interface provided by the message storage module to map and write the fragments in the current fragment group to be written into the cache block in the idle logical buffer according to the order of the fragment groups;

[0047] After successfully writing the first fragment group, the message storage module instructs the address management module to create a message descriptor for the message. The message descriptor records the message length and the address of the first logical buffer. After successfully writing subsequent fragment groups, the address management module records the addresses of subsequent logical buffers in a linked list based on the message descriptor.

[0048] After receiving the message descriptor from the message reading module, the message storage module calculates the number of fragment groups based on the message length, according to the logical buffer address and message length provided by the message descriptor. Based on the address of the first logical buffer and the addresses of subsequent logical buffers recorded in a linked list, the module calls the mapping read interface to read each fragment group sequentially from the corresponding logical buffer according to the number of fragment groups. During reading, the same hash function as during writing is used to read fragments from the cache blocks in the logical buffer.

[0049] Based on another aspect of the embodiments of this application, this application also provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is executed by the processor to perform the aforementioned message caching method.

[0050] The technical solutions provided in the embodiments of this specification may include the following beneficial effects:

[0051] This application caches message fragments based on logical buffers, combining multiple logical buffers into a logically contiguous cache space. It effectively manages the cache by combining a list of free logical buffers and message descriptors. At the same time, it uses a dynamic hash function to distribute and map message fragments across multiple banks, thereby reducing the formation of cache access hotspots and improving access performance and cache utilization.

[0052] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of a cache structure used in an embodiment of this application;

[0054] Figure 2This is a schematic diagram of the message caching process after receiving a message caching request in one embodiment of this application;

[0055] Figure 3 This is a schematic diagram of the structure of a message buffer device in one embodiment of this application;

[0056] Figure 4 This is a schematic diagram of the cache data structure used by the message caching device in one embodiment of this application;

[0057] Figure 5 This is a schematic diagram of a network device structure that uses a message caching device in one embodiment of this application. Detailed Implementation

[0058] The exemplary embodiments will now be described in detail. When the description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification; they are merely exemplary embodiments of apparatuses and methods consistent with some aspects of this specification.

[0059] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” used in this specification are also intended to include the plural forms unless the context clearly indicates otherwise. This specification may use terms such as “first,” “second,” “third,” etc., to describe various information or structural modules for the purpose of more clearly describing the scheme, and should not be construed as indicating or implying relative importance or implicitly specifying the number, order, or position of the indicated technical features. Thus, a feature defined with “first,” “second,” “third,” etc., may explicitly or implicitly include one or more of that feature. In the description of this specification, unless otherwise stated, “multiple” means two or more; “if” can be interpreted as “when,” “when,” or “in response to a determination.” In this specification, “and / or” is used to describe the relationship between related objects, indicating that three relationships may exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural.

[0060] In message forwarding scenarios, compared to main memory, caches (such as SRAM) with faster read / write speeds are the basic hardware storage carriers. They consist of multiple banks (memory banks). The number and bit width of each cache bank are related to the specific hardware and application scenario. Each bank is an independently accessible unit with its own address lines and control lines. By reading / writing cache blocks in multiple banks in parallel, data read / write efficiency can be significantly improved.

[0061] Figure 1 Schematic diagram of the cache structure used in an embodiment of the present application. In the figure, the cache includes 4 Banks, the bit width of each Bank is n (for example, n can be 8 bytes, 16 bytes, etc.), and each Bank is divided into m cache blocks with a bit width of n (the index numbers range from 0 to m-1). In an embodiment of the present application, the cache blocks on the same index, that is, the same row, in each Bank are divided into a group to form a logical buffer memory (referred to as buffer for short). The logical buffer memory is distributed across multiple Banks, which can not only meet the requirements of functional partitioning but also meet the requirements of low latency and high utilization in high-bandwidth scenarios based on the multi-Bank parallel access feature. Figure 1 The 4 cache blocks blk with row index 0 in Banks 0 to Bank3 in the SRAM cache 0,0 、blk 1,0 、blk 2,0 、blk 3,0 are combined to form a logical buffer memory Buffer0, and blk 1,0 represents the cache block with index 0 on bank1. In an embodiment of the present application, each logical buffer memory can also include multiple rows of cache blocks. For example, the i rows (1 < i < m-1) of cache blocks in each Bank can be combined to form a logical buffer memory to meet the needs in the large cache block scenario.

[0062] Figure 2 Schematic diagram of the message caching process after receiving a message caching request in an embodiment of the present application. The message caching method provided by the present application is applied to devices that need to perform high-speed forwarding and / or processing of messages. The method includes the following steps:

[0063] S201. In response to the message caching request, obtain the addresses of one or more logical buffer memories for caching the message from the free logical buffer memory linked list;

[0064] Taking the switching device in the data center as an example, when the switching device receives a large number of messages through the port in a short time and cannot process them in time, it is necessary to first cache the messages in the local SRAM cache. The efficiency of message caching directly affects the overall performance of the device.

[0065] After receiving a message caching request, the device needs to obtain the cache location information first. This application uses a free logical buffer list to manage and maintain the addresses of free logical buffers (buffers) that can be used to cache message data. Each linked unit of the free logical buffer list stores the address of a free logical buffer. The logical buffer is the basic unit for caching messages, and each logical buffer includes the same number of cache blocks belonging to different banks.

[0066] S202. The message is sequentially written into one or more logical buffers in units of fragment groups, and a message descriptor for the message is created; the fragments in the fragment group are mapped and written into different buffer blocks in the logical buffers through a hash function; the message descriptor provides information on the addresses of all logical buffers storing the message and the message length.

[0067] In forwarding devices, packets are typically divided into packet fragments (i.e., flow control units flit) for internal transmission. In this embodiment, packets are written sequentially into one or more available free logical buffers, in fragment groups, according to the order of the fragment groups. The maximum number of fragments in a fragment group is the same as the number of buffer blocks in the logical buffer, and each buffer block stores one fragment.

[0068] The purpose of using a hash function to write the fragment mapping in the fragment group to the logical buffer is to distribute the message fragments into different storage banks, and to use the parallel access characteristics of multiple banks in the cache to distribute bank hotspots, improve bank utilization, and thus improve message caching performance.

[0069] After the device writes a message to the cache, when resources are available to process or forward the cached message, it will read the cached message from the cache through an interface. The reading process includes:

[0070] S203. In response to the message read request, according to the logical buffer address and message length provided by the message descriptor, read the fragment group of the message in sequence from each logical buffer. When reading, the same hash function as when writing is used to read the fragments in the fragment group from the buffer block in the logical buffer.

[0071] Based on the message length in the message descriptor, the number of message fragments can be calculated, thus determining the number of fragment groups. The hash function used determines the location of the cache block where each fragment is stored based on information such as the logical cache index and the fragment sequence number within the fragment group, thereby retrieving the message from the cache.

[0072] S204. After successful reading, the address of one or more logical buffers storing the message is put back into the free logical buffer list and the message descriptor of the message is deleted.

[0073] After a cached message is successfully read, the occupied logical buffer area needs to be released in a timely manner. Therefore, the address of the used logical buffer area needs to be put back into the free logical buffer area linked list and the message descriptor of the message needs to be deleted from the cache.

[0074] This embodiment stores message fragment groups based on logical buffers, combining multiple logical buffers into a logically contiguous cache space. It effectively manages the cache by combining a list of free logical buffers and message descriptors. At the same time, it uses a dynamic hash function to distribute and map message fragments to multiple banks, thereby reducing the formation of cache access hotspots and improving access performance and cache utilization.

[0075] Figure 3 This is a schematic diagram of a message caching device in one embodiment of this application. The device is applied in a network device in the form of software or a combination of software and hardware. When the network device receives a message and needs to cache it, the upper-layer software / hardware of the network device can call the message caching device 300 to cache the message. The device mainly consists of a message receiving module 310, a message storage module 320, an address management module 330, and a message reading module 340.

[0076] Figure 4 This is a schematic diagram of the cache data structure used by the message caching device in one embodiment of this application. The message caching device can be based on... Figure 4 The data structure manages and utilizes the cache space to achieve efficient packet caching. To improve caching efficiency, the cached packet data and cached management control information can be located in different physical caches, such as... Figure 4 For example, Cache 2 (SRAM2) caches message data and is mainly used by the message storage module 320. Cache 1 (SRAM1) caches the free logical buffer list and management control information such as message descriptors. Assuming that the number of banks in SRAM2 is 4, i.e., K=4, then each logical buffer in SRAM2 includes 4 cache blocks belonging to different banks. For example, the 4 cache blocks blk in logical buffer buffer1. 0,1 blk 1,1 blk 2,1 blk 3,1These are four cache blocks in SRAM2, each with an uplink index of 1 for each of the four banks. This application separates message data and cache management control information, enabling parallel processing of message data reading / writing and cache management control information reading / writing. Furthermore, through the structural design of the logical cache area, it fully leverages the parallel access characteristics of multiple cache banks, thereby improving the overall read / write and utilization efficiency of the cache.

[0077] like Figure 4 In the example, the free logical buffer list in cache 1 records the addresses of all unused free logical buffers in cache 2. During system initialization, all free logical buffers in cache 2 are traversed, and their addresses are added to the free logical buffer list of cache 1 for use in subsequent packet caching.

[0078] The Message Descriptor List (PDL) records all message descriptors cached in SRAM2. Each message descriptor includes at least the message length and the address of the logical buffer storing the first fragment group (or it can be an index of the logical buffer, which can be converted to a physical address). Figure 4 For example, the list cells in the message descriptor list include a message length field and a header index field. The header index field stores the logical buffer index of the first cached message data. The structural cells in the message linked list structure (PCStru) correspond one-to-one with the logical buffers in SRAM2. The index (idx) of the structural cell in the message linked list structure can be considered as the index of the logical buffer, which is equivalent to an address mapping relationship between the logical buffer and the structural cells in the message linked list structure. Based on the base address and the index, the access address of the logical buffer can be quickly calculated. For example, the logical buffer buffer buffer0 with index 0 in SRAM2 corresponds to the structural cell with index 0 in PCStru, buffer1 corresponds to the structural cell with index 1 in PCStru, and so on. The structural cells in the message linked list structure (PCStru) store the index of the logical buffer corresponding to the next cached message data, forming a linked list through the recorded indices. For example, assuming that the length of message 1, Pkg1Len, calculates that message 1 requires three logical buffers, buffer0, buffer1, and buffer3, to cache its fragments, then the header index field of the message descriptor of message 1 stores the index of buffer0, i.e., the value of idx being 0. In the message linked list structure, the index value of the structure unit with index idx=0 is filled with 1, representing that the logical buffer following buffer0 is buffer1. The index value of the structure unit with index idx=1 is filled with 3, representing that the logical buffer following buffer1 is buffer3. This index-based linked list structure allows for efficient recording of the logical buffer addresses of messages.

[0079] The following combination Figure 3 and Figure 4 The example provides a detailed description of the process of writing messages to and reading messages from the cache.

[0080] The process from when a message enters the message buffer 300 to when the message is written to the buffer includes:

[0081] S401. After receiving the message caching request, the message receiving device 310 requests the address of one or more free logical buffer areas for caching the message from the address management module 330 through the interface provided by the address management module 330.

[0082] S402. After receiving the request, the address management module obtains the address of the required logical buffer for the packet from the managed free logical buffer list and creates a packet descriptor for the packet.

[0083] like Figure 4 For example, suppose the message length field and header index field values ​​of message descriptor for message 1 are Pkg1Len and buffer0Ptr, respectively. Pkg1Len represents 9-12 fragments (buffer blocks), divided into 3 fragment groups. The 3 fragment groups of message 1 are cached sequentially in buffer0, buffer1, and buffer3. The logical buffer index recorded in buffer0Ptr is idx=0. The index value recorded in the header index field, together with the index values ​​1 and 3 recorded in the two structural units with indices 0 and 1 in the message linked list structure (corresponding to logical buffers buffer1 and buffer3 respectively), form a linked list structure that records the addresses of all logical buffers caching message 1. The index idx can be regarded as the offset address of the logical buffer relative to the base address. The actual physical address of the buffer can be easily obtained by multiplying the index by the memory block size and adding the base address.

[0084] S403. After obtaining the address of one or more logical buffers of the cached message, the message receiving device 310 calls the interface provided by the message storage module 320, and the message storage module 320 writes the message sequentially into the one or more logical buffers in units of fragment groups.

[0085] In this application, messages are grouped into fragments in a fragmentation order, with the number of fragments in each fragment group being the same as the number of banks in the cache. Fragmentation is also known as a flow control unit (flit). In specific scenarios of forwarding chips (such as NoC communication), a flit is the smallest granularity for data transmission and flow control after further segmentation of a message / data packet.

[0086] The message storage module writes the fragment mappings in the fragment group to different cache blocks in the logical cache area based on a preset hash function. The hash function includes at least a partition factor and a fragment factor, and may further include a constant factor. The value of the partition factor is determined by the address or index of the logical cache area; the value of the fragment factor is determined by the address or index of the fragment within the fragment group. Which cache block in the logical cache area a fragment mapping in the fragment group is written to is determined at least by the partition factor, the fragment factor, and the number of storage banks.

[0087] The hash function used in one embodiment of the application is as follows:

[0088] bank_index = (buffer_idx % N + flit_offset % N + C) % N (Formula 1)

[0089] Wherein, the partition factor is the logical buffer index `buffer_idx`, the fragment factor is the fragment number `flit_offset` within the fragment group (or the fragment's sequence number within the packet), and the number of banks in the SRAM is N. `C` is a constant and optional. `bank_index` is the bank index in the logical buffer, i.e., the index of the packet fragment in the write buffer block within the logical buffer. `%` is the modulo operator.

[0090] refer to Figure 4 For example, suppose message 1 includes 11 fragments (fragment indices or sequence numbers within the message are 0~10), and the number of buffer banks is 4. These 11 fragments will be divided into 3 fragment groups and cached sequentially in buffer0, buffer1, and buffer3 (logical buffer indices are 0, 1, and 3 respectively). Based on formula 1, the 11th fragment should be written to buffer3, where buffer_idx is 3, the fragment's sequence number within the fragment group is flit_offset, and C is 1. Therefore, the final mapped write location is:

[0091] bank_index = (3 % 4 + 2 % 4 + 1) % 4 = 2

[0092] That is, the 11th fragment is mapped and written to blk within buffer3. 2,3 In the cache block.

[0093] This application improves the data distribution in the cache and enhances the parallel access efficiency of the bank by introducing partitioning and fragmentation factors into the hash function. To illustrate the effect, assume an extreme case where all message packets are small (the size of a single fragment). Since this application allocates cache space at the logical buffer level, each fragment occupies a buffer. Without hash mapping, all message fragments would be distributed across bank0. However, with hash mapping, the effect after hash mapping is shown in the following example:

[0094] The fragments of message 1 are buffered in Bank1 of Buffer0;

[0095] The fragments of message 2 are buffered in Bank2 of Buffer1;

[0096] The fragments of message 3 are buffered in Bank 3 of Buffer 2;

[0097] The fragments of message 4 are buffered in Bank0 of Buffer3;

[0098] This not only improves the distribution of message data in the cache, but also eliminates hotspots on the bank as much as possible, thereby improving cache performance.

[0099] In one embodiment of this application, the message receiving module 310, upon obtaining the address of a free logical buffer from the free logical buffer linked list of the address management module 330, calls the mapping write interface provided by the message storage module 320 to map and write the fragments in the current fragment group to be written into the cache block in the free logical buffer according to the order of the fragment groups. The mapping write interface determines the writing position of the fragments in the logical buffer within the fragment group based on the hash function of formula one.

[0100] In another embodiment of this application, in order to improve writing efficiency, the message receiving module 310 can also obtain the addresses of all the required free logical buffers at once through the address management module 330, and then provide them to the message storage module 320 through the interface. The message storage module 320 writes the message fragments into the corresponding free logical buffers in sequence based on the mapping write interface. After successful writing, it responds to the message receiving module 310 and the address management module 330, thereby completing a complete message caching transaction.

[0101] After successful message caching, the message receiving module 310 provides the message descriptor to the message scheduling module, which then processes the message. When the device is capable of processing the message, the message processing / forwarding module in the device retrieves the message from the cache via the message reading module 340. Since the message scheduling module and message processing / forwarding module are not directly related to the solution in this application, therefore... Figure 3 Not shown in the image.

[0102] The following combination Figure 3 and Figure 4 The following example provides a detailed description of the process of reading a message from a buffer:

[0103] S403. When the message reading module 340 receives a message reading request, it calls the mapping reading interface provided by the message storage module 320 to read the cached message from the cache according to the logical buffer address and message length provided by the message descriptor.

[0104] In one embodiment of this application, after receiving a message reading request, the message reading module 340 extracts the message descriptor index from the request, then calls the interface of the address management module 330 to obtain the message descriptor corresponding to the message descriptor index, and then calls the mapping reading interface provided by the message storage module 320 to read the cached message from the cache based on the logical buffer address provided by the message descriptor and the message length.

[0105] by Figure 4 For example, the message storage module 320 can calculate the number of fragments and the number of logical buffers occupied based on the message length Pkg1Len of message 1. Then, based on the index of the first logical buffer recorded in the header index field and the index of the subsequent logical buffers recorded in the linked list in the message linked list structure, all logical buffers for caching message 1 can be obtained as buffer0, buffer1 and buffer3. Then, using the same hash function as when mapping and writing, the message fragments are read from each logical buffer in the order of message fragment groups, i.e. the order of logical buffers. After successful reading, the complete message can be assembled.

[0106] S404. After the message reading module 340 successfully reads the message, the message reading module 340 instructs the address management module 330 to put the address of one or more logical buffers storing the message back into the free logical buffer list and delete the message descriptor of the message.

[0107] This concludes the description of a complete message caching process and the process of reading messages from the cache.

[0108] It should be noted that the use of a linked list structure to manage the address of the free logical cache area in the above embodiments of this application is only a preferred method. In addition to the linked list structure, other data structure forms can also be used, such as lists, tree structures, queues, etc. Under the same purpose, there may be some differences in management efficiency, but these should all fall within the protection scope of this application, and this application will not elaborate further.

[0109] This application, based on structural innovations in the logical buffer area and effective management of the free logical buffer area, can efficiently traverse and utilize the entire SRAM cache space, making more effective use of the cache and avoiding memory fragmentation and waste. Furthermore, based on an efficient indexing structure using packet descriptors, a packet can be quickly read by knowing only the address of the first buffer, effectively improving the cache performance of network devices.

[0110] Figure 3 The modules in the example message buffering device 300 can be implemented in software or through a combination of hardware and software. Taking the message storage module as an example, it includes both the software portion that implements the interfaces with other modules and the hardware cache SRAM portion. As a logical device, its software implementation can be formed by the processor of the device loading the corresponding computer program instructions from the non-volatile memory into memory for execution.

[0111] Figure 5 This is a schematic diagram of a network device structure using a packet caching device in one embodiment of this application. The network device includes a processor 510, main memory 530, cache 520, and non-volatile memory 540. The software part of the packet caching device 300 provided in this embodiment can be formed by the processor 510 reading the corresponding computer program instructions from the non-volatile memory 540 and running them in the main memory 530. Depending on the actual function of the network device, other hardware may also be included, which will not be described in detail here.

[0112] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the solution in this specification according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0113] The foregoing has described exemplary embodiments of this specification. It should be understood that in some cases, the modules described in this specification may be divided in a manner different from that in the embodiments, and the described actions or steps may be performed in a different order than that in the embodiments, while still achieving the desired result. Furthermore, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0114] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A message caching method, characterized in that, The method includes: In response to a message caching request, the addresses of one or more logical buffers for caching messages are obtained from the free logical buffer list; each logical buffer contains the same number of cache blocks belonging to different memory banks; The message is sequentially written into one or more logical buffers in units of fragment groups, creating a message descriptor for the message. Fragments in each fragment group are mapped and written to different cache blocks in the logical buffers using a hash function. The message descriptor provides information about the addresses of all logical buffers storing the message and the message length. The hash function includes at least a partition factor and a fragment factor. The value of the partition factor is determined by the address or index of the logical buffer. The value of the fragment factor is determined by the address or index of the fragment within the fragment group. Which cache block in the logical buffer a fragment in a fragment group is mapped to is determined at least by the partition factor, the fragment factor, and the number of memory blocks. In response to a message read request, the message fragments are read sequentially from each logical buffer according to the logical buffer address and message length provided by the message descriptor. During reading, the same hash function as during writing is used to read fragments from the buffer blocks in the logical buffer. After a successful read, the address of one or more logical buffers storing the message is returned to the free logical buffer list and the message descriptor is deleted.

2. The method according to claim 1, characterized in that, The logical buffer area is composed of cache blocks on the same line in the same cache, and the size of the cache block is the same as that of the message fragment. The hash function also includes a constant factor.

3. The method according to claim 1, characterized in that, The process of sequentially writing the message into the one or more logical buffers in units of fragment groups includes: The number of message fragments is determined based on the message length, and the message fragments are then divided into multiple fragment groups in sequence. After obtaining the address of a free logical cache from the free logical cache linked list, the mapping write interface is called according to the order of the shard groups to write the shards in the current shard group to be written into the cache blocks in the free logical cache. After successfully writing the first fragment group, a message descriptor is created for the message. The message descriptor records the message length and the address of the first logical buffer. After successfully writing subsequent fragment groups, the addresses of subsequent logical buffers are recorded in a linked list based on the message descriptor. The process of sequentially reading the fragments of a message based on its message descriptor includes: Obtain the address of the first logical buffer and the message length based on the message descriptor, and calculate the number of fragment groups based on the message length; Based on the address of the first logical cache and the addresses of subsequent logical caches recorded in a linked list, the mapping read interface is called to read each shard group from the corresponding logical cache in sequence; during reading, the same hash function as during writing is used to read the shards in the shard group from the cache blocks in the logical cache.

4. The method according to claim 1, characterized in that, During initialization, all free logical cache areas in the cache space are traversed, and the addresses of the free logical cache areas are added to the free logical cache area linked list. After successfully reading the message, the address of the released logical buffer is added to the end of the free logical buffer list.

5. The method according to claim 1, characterized in that, The cache space storing the free logical buffer linked list and the message descriptor of the message belongs to a different physical cache from the cache space storing the logical buffer.

6. A message buffering device, characterized in that, The device includes: The message receiving module is used to respond to message caching requests by requesting the address management module for the address of one or more free logical cache areas for caching the message; each logical cache area includes the same number of cache blocks belonging to different memory banks; The address management module is used to manage the free logical buffer list and message descriptors. It allocates the address of a free logical buffer for the message from the free logical buffer list and creates a message descriptor for the message. The message descriptor provides information on the addresses of all logical buffers storing the message and the message length. A message storage module is used to cache messages and sequentially write the messages into one or more requested logical caches in units of fragment groups. Fragments within a fragment group are mapped and written to different cache blocks in the logical cache using a hash function. The hash function includes at least a partition factor and a fragment factor. The value of the partition factor is determined by the address or index of the logical cache. The value of the fragment factor is determined by the address or index of the fragment within the fragment group. Which cache block in the logical cache a fragment within a fragment group is mapped to is determined at least by the partition factor, the fragment factor, and the number of memory blocks. The message reading module is used to respond to message reading requests and, based on the message descriptor, call the interface provided by the message storage module to read the cached message; The message storage module is also used to read the fragment group of the message sequentially from each logical buffer according to the logical buffer address and message length provided by the message descriptor. When reading, the same hash function as when writing is used to read the fragments in the fragment group from the cache block in the logical buffer. The address management module is also used to put the address of one or more logical buffers storing the message back into the free logical buffer list after a successful read.

7. The apparatus according to claim 6, characterized in that, The logical buffer area is composed of cache blocks on the same line in the same cache, and the size of the cache block is the same as that of the message fragment. The hash function also includes a constant factor.

8. The apparatus according to claim 6, characterized in that, The message receiving module determines the number of message fragments based on the message length and divides the message fragments into multiple fragment groups in sequence. After obtaining the address of an idle logical buffer from the idle logical buffer linked list managed by the address management module, the module calls the mapping write interface provided by the message storage module to map and write the fragments in the current fragment group to be written into the cache block in the idle logical buffer according to the order of the fragment groups. After successfully writing the first fragment group, the message storage module instructs the address management module to create a message descriptor for the message. The message descriptor records the message length and the address of the first logical buffer. After successfully writing subsequent fragment groups, the address management module records the addresses of subsequent logical buffers in a linked list based on the message descriptor. After receiving the message descriptor provided by the message reading module, the message storage module calculates the number of fragment groups based on the message length, according to the logical buffer address and message length provided by the message descriptor. Based on the address of the first logical cache and the addresses of subsequent logical caches recorded in a linked list, the mapping read interface is called to read each shard group from the corresponding logical cache in sequence according to the number of shard groups; during reading, the same hash function as during writing is used to read the shards in the shard groups from the cache blocks in the logical cache.

9. A computer device, characterized in that, The device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being executed by the processor to perform the method as described in any one of claims 1 to 5.

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