Method for optimizing LDNMOS layout design
By adjusting the LDNMOS layout, increasing the drift region width, and shortening the effective channel length, the hot carrier injection failure problem of LDNMOS was solved, improving device performance and reliability.
Patent Information
- Application Number
- CN202511759683.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-02-17
AI Technical Summary
Existing laterally diffused N-type metal-oxide-semiconductor transistors (LDNMOS) suffer from hot carrier injection failure, leading to device parameter degradation such as threshold voltage drift, reduced transconductance, and increased leakage current.
By adjusting the LDNMOS layout, increasing the drift region width and shortening the effective channel length, the layout design is optimized. Fine-tuning is then performed using the DPO algorithm in DOE while keeping the gate length constant.
It effectively increases driving capability, improves carrier mobility, reduces substrate current and drain saturation current, and improves product reliability.
Smart Images
Figure CN121548112A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and specifically to a method for optimizing LDNMOS layout design. Background Technology
[0002] Laterally diffused metal-oxide-semiconductor transistors (LDMOS) are mainly used in power integrated circuits, such as RF power amplifiers for mobile phone base stations, and can also be used in high-frequency, ultra-high-frequency and super-high-frequency broadcast transmitters, as well as microwave radar and navigation systems.
[0003] The existing structure of laterally diffused N-type metal-oxide-semiconductor transistors (LDNMOS) is as follows: Figure 1 As shown, partially overlapping P-wells (IOPW) and N-wells (IONW) are formed in the substrate. A polysilicon gate G covers part of the P-well, part of the N-well, and part of the STI isolation structure near the drain D. The source S and drain D are separated by the STI isolation structure. The width of the overlap between the gate G and the P-well is A, the width of the overlap between the active region (AA) and the N-well is C, the width of the overlap between the P-well and the N-well is B, the width of the overlap between the gate G and the STI isolation structure is D, and the width of the STI isolation structure is E. This LDNMOS suffers from hot carrier injection (HCI) failure, leading to device parameter degradation such as threshold voltage drift, reduced transconductance, and increased leakage current. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for optimizing LDNMOS layout design to solve the problem of hot carrier injection failure in existing LDNMOS.
[0005] To achieve the above and other related objectives, this application provides a method for optimizing LDNMOS layout design by adjusting the LDNMOS layout, increasing the drift region width, and shortening the effective channel length while keeping the gate length unchanged.
[0006] Preferably, the drift region width is increased to 0.4-0.5 micrometers, and the effective channel length is shortened to 0.3-0.5 micrometers.
[0007] Preferably, the drift region width is increased to 0.46 micrometers, and the effective channel length is shortened to 0.4 micrometers.
[0008] Preferably, the LDNMOS layout includes a gate, a source, a drain, an STI isolation structure, and P-wells and N-wells in the substrate, with the source and drain separated by the STI isolation structure.
[0009] Preferably, when adjusting the LDNMOS layout, the width of the overlapping portion of the P-well and N-well, the width of the overlapping portion of the gate and the STI isolation structure, and the width of the STI isolation structure remain unchanged.
[0010] Preferably, the LDNMOS layout is adjusted by the DPO algorithm in DOE, so that the channel width and channel length are adjustable and the number of fingers are adjustable, provided that the ratio of channel width to channel length is fixed.
[0011] Preferably, the gate is a polysilicon gate.
[0012] As described above, the method for optimizing LDNMOS layout design provided in this application has the following beneficial effects: by fine-tuning the layout to increase the drift region width and shortening the effective channel length while keeping the gate length unchanged, the driving capability can be effectively increased, the carrier mobility can be improved, and the substrate current (ISUB) / drain saturation current (IDSAT) can be reduced, thereby improving product reliability. Attached Figure Description
[0013] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0014] Figure 1 The diagram shows an adjustment of an existing LDNMOS layout according to the method for optimizing LDNMOS layout design provided in this application;
[0015] Figure 2 The diagram shows the decrease in substrate current (ISUB) / drain saturation current (IDSAT) after shortening the effective channel length.
[0016] Figure 3 The diagram illustrates how shortening the effective channel length improves hot carrier injection (HCI). Detailed Implementation
[0017] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.
[0018] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0019] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0020] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0021] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0022] Please see Figure 1 The existing LDNMOS layout is fine-tuned by increasing the drift region width C while shortening the effective channel length A (the red portion changes) without changing the gate (Poly) length. For example, the drift region width C is increased to 0.4-0.5 micrometers, preferably 0.46 micrometers, and the effective channel length A is shortened to 0.3-0.5 micrometers, preferably 0.4 micrometers. The width B of the overlap between the P-well and N-well, the width D of the overlap between the gate G and the STI isolation structure, and the width E of the STI isolation structure remain unchanged.
[0023] As an example, by fine-tuning the LDNMOS layout using the DPO algorithm in DOE (Design of Experiment), the channel width and channel length can be adjusted while the ratio of channel width to channel length is fixed, and the number of gate segments connected in parallel (finger number) can also be adjusted.
[0024] like Figure 2As shown, when the effective channel length is shortened to 0.3-0.5 μm, the substrate current (ISUB) / drain saturation current (IDSAT) decreases significantly. This can significantly improve carrier mobility by approximately 40%, while maintaining the same leakage current.
[0025] like Figure 3 As shown, as the effective channel length shortens, the drain saturation current (IDSAT) increases, and hot carrier injection is significantly improved.
[0026] The above fine-tuning can significantly improve carrier mobility by approximately 40%, while maintaining the same leakage current. The only change in the LDPMOS layout is the number of protection diodes, which does not affect the electrical parameters.
[0027] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0028] In summary, the method for optimizing LDNMOS layout design provided in this application increases the drift region width by fine-tuning the layout, while shortening the effective channel length without changing the gate length. This effectively increases the driving capability, improves carrier mobility, and reduces substrate current / drain saturation current, thereby improving product reliability. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0029] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.
Claims
1. A method for optimizing LDNMOS layout design, characterized in that, The method adjusts the LDNMOS layout, increases the drift region width, and shortens the effective channel length while keeping the gate length unchanged.
2. The method according to claim 1, characterized in that, The drift region width is increased to 0.4-0.5 micrometers, and the effective channel length is shortened to 0.3-0.5 micrometers.
3. The method according to claim 2, characterized in that, The drift region width is increased to 0.46 micrometers, and the effective channel length is shortened to 0.4 micrometers.
4. The method according to claim 1, characterized in that, The LDNMOS layout includes a gate, a source, a drain, an STI isolation structure, and P-wells and N-wells in the substrate, wherein the source and the drain are separated by the STI isolation structure.
5. The method according to claim 4, characterized in that, When adjusting the LDNMOS layout, the width of the overlapping portion of the P-well and the N-well, the width of the overlapping portion of the gate and the STI isolation structure, and the width of the STI isolation structure remain unchanged.
6. The method according to claim 1, characterized in that, The LDNMOS layout is adjusted using the DPO algorithm in DOE, allowing for adjustable channel width and channel length, and adjustable finger count, provided that the ratio of channel width to channel length is fixed.
7. The method according to claim 1, characterized in that, The gate is a polysilicon gate.