Solar cell

Abstract

The solar cell comprises a plurality of first doping structures which are arranged at intervals and are diffusion regions formed by inward diffusion of doping sources from the back surface of a silicon substrate; the second doping structure and the first doping structure are alternately arranged, the second doping structure is located in an area sunken from the back face of the silicon substrate to the front face of the silicon substrate, the second doping structure is a tunneling passivation contact structure, and the doping type of the tunneling passivation contact structure is opposite to that of the diffusion area; the spacer region is located between the first doping structure and the second doping structure; the first electrode is positioned on the back surface of the first doping structure; the second electrode is positioned on the back surface of the tunneling passivation contact structure; the tunneling passivation contact structure comprises n tunneling layers and doped polycrystalline silicon layers located on the sides, away from the silicon substrate, of the tunneling layers, n is larger than or equal to 2, the second electrode makes contact with at least one of the second doped polycrystalline silicon layer and the nth doped polycrystalline silicon layer in the direction from the silicon substrate to the back face, the doping types of the different doped polycrystalline silicon layers are the same, and n is larger than or equal to 2. The battery efficiency can be improved; and the method is suitable for industrial promotion.

Description

[0001] Cross-references to related applications

[0002] This application is a divisional application of Chinese invention patent application filed on August 29, 2024, with application number 202411209958.1 and invention title "Solar Cell". Technical Field

[0003] This invention relates to the field of photovoltaics, and more particularly to a solar cell. Background Technology

[0004] Back contact (BC) batteries have both positive and negative electrodes located on the back of the battery, which reduces the current transmission path and lowers resistance; in addition, the absence of grid lines on the front improves light absorption efficiency and enhances battery performance.

[0005] However, despite the obvious advantages of BC batteries over other battery technologies, the structural design of the batteries affects the mass production process.

[0006] In view of this, it is necessary to provide an improved solar cell to solve the above-mentioned technical problems. Summary of the Invention

[0007] This invention provides a solar cell with an improved structural design on the back of the cell, which is beneficial for industrialization.

[0008] To achieve one of the above-mentioned objectives, the present invention adopts the following technical solution:

[0009] A solar cell, comprising:

[0010] A plurality of first doped structures are spaced apart, wherein the first doped structure is a diffusion region formed by the diffusion of dopant from the back side of the silicon substrate inward;

[0011] A second doped structure is alternately disposed with the first doped structure. The second doped structure is located in a region recessed from the back side to the front side of the silicon substrate. The second doped structure is a tunneling passivation contact structure, and the doping type of the tunneling passivation contact structure is opposite to that of the diffusion region.

[0012] The spacer region is located between the first doped structure and the second doped structure;

[0013] The first electrode is located on the back side of the first doped structure;

[0014] The second electrode is located on the back side of the tunneling passivation contact structure;

[0015] The tunneling passivation contact structure includes n tunneling layers and a doped polysilicon layer located on the side of each tunneling layer facing away from the silicon substrate; wherein, n≥2, and in the direction from the silicon substrate to the back side, the second electrode is in contact with at least one of the 2nd to nth doped polysilicon layers, and the doping type of the different doped polysilicon layers is the same.

[0016] In an optional embodiment, the first doped structure is a diffusion region formed by boron diffusion from the back side of the silicon substrate inward, wherein the diffusion depth of boron is 0.5 μm to 1.0 μm.

[0017] In one optional embodiment, one of the first doped structure and the second doped structure forms a PN junction with the silicon substrate, and the other forms a high-low junction with the silicon substrate, wherein the area of ​​the PN junction region is larger than the area of ​​the high-low junction region.

[0018] In one optional embodiment, the spacer region is recessed from the back side to the front side of the silicon substrate, and the recess depth at the location of the second doped structure and / or the spacer region is not less than the diffusion depth of the diffusion region. In another optional embodiment, the recess depth at the location of the second doped structure is less than the recess depth of the spacer region.

[0019] In one optional embodiment, the width of the interval region is 10 μm to 150 μm.

[0020] In one optional embodiment, the spacer region is recessed from the back side of the silicon substrate toward the front side, and the distance from the back surface of the spacer region to the back surface of the first doped structure is 1 μm to 20 μm.

[0021] In one optional embodiment, the distance from the back surface of the second doped structure to the front surface of the silicon substrate is not greater than the distance from the back surface of the first doped structure to the front surface of the silicon substrate.

[0022] In one optional embodiment, the dimension of the second doped structure in the thickness direction of the silicon substrate is not greater than the recess depth of the spacer region.

[0023] In one optional embodiment, the distance between the back surface of the first doped structure and the back surface of the second doped structure in the thickness direction of the silicon substrate is 1 μm to 10 μm.

[0024] In one optional embodiment, the diffusion region includes a gate line region and a non-gate line region, wherein the doping concentration of the gate line region is greater than the doping concentration of the non-gate line region, and the first electrode is in contact with the gate line region.

[0025] In one optional embodiment, the sheet resistance of the gate region is 80 ohm / sq to 130 ohm / sq, and the sheet resistance of the non-gate region is 200 ohm / sq to 400 ohm / sq.

[0026] In one optional embodiment, the first doped structure is a P-type diffusion region, and the doped polysilicon layer is an N-type doped polysilicon layer; or

[0027] The first doped structure is an N-type diffusion region, and the doped polysilicon layer is a P-type doped polysilicon layer.

[0028] The beneficial effects of this invention are as follows: The solar cell of this invention, by placing both the first and second electrodes on the back side, eliminates the obstruction of the front side by metal electrodes, resulting in a large light-receiving area, high light conversion efficiency, and improved cell efficiency. Furthermore, the first doped structure is a diffusion region formed by the diffusion of dopant from the back side of the silicon substrate inwards, while the second doped structure is located in a region recessed from the back side of the silicon substrate towards the front side. The second doped structure is a tunneling passivation contact structure, which allows for the first doped structure to be formed first, followed by the removal of a portion of the diffusion junction, and then the deposition of the tunneling passivation contact structure. This design exhibits high compatibility with the TOPCon cell process flow and is suitable for industrialization. In addition, the multilayer tunneling layer effectively hinders the inward diffusion of the material forming the second electrode, preventing it from contacting the silicon substrate and forming an alloy. Moreover, the second electrode does not reach the innermost doped polycrystalline silicon layer, thus avoiding direct contact between the second electrode and the silicon substrate. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0034] Figure 6 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0035] Figure 7 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0036] Figure 8 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0037] Figure 9 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0038] Figure 10 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0039] Figure 11 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0040] Figure 12 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention.

[0041] Among them, 100-solar cell, 1-silicon substrate, 2-first doped structure, 21-gate region, 22-non-gate region, 3-second doped structure, 31-tunneling layer, 32-doped polycrystalline silicon layer, 4-spacer region, 5-back passivation layer, 6-back antireflection layer, 7-front passivation layer, 8-front antireflection layer, 91-first electrode, 92-second electrode. Detailed Implementation

[0042] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0043] In the various figures of this invention, for ease of illustration, some dimensions of structures or parts may be exaggerated relative to other structures or parts; therefore, only the basic structure of the subject matter of this invention is used to illustrate the invention.

[0044] Please refer to Figures 1-12 As shown, a solar cell 100 according to a preferred embodiment of the present invention includes a silicon substrate 1, a first doped structure 2 located on the back side of the silicon substrate 1, a second doped structure 3 located on the back side of the silicon substrate 1, a spacer region 4 located between the first doped structure 2 and the second doped structure 3, a first electrode 91 located on the back side of the first doped structure 2, and a second electrode 92 located on the back side of the second doped structure 3.

[0045] The first doped structure 2 and the second doped structure 3 have opposite doping types, one being a P-type doped structure and the other an N-type doped structure. The first doped structure 2 and the second doped structure 3 are alternately arranged, and the two regions are separated by a spacer region 4. By placing both the first doped structure 2 and the second doped structure 3 on the back side of the solar cell, the current transport path between the P-type and N-type doped structures can be reduced, thus lowering the resistance. Furthermore, by placing both the first electrode 91 and the second electrode 92 on the back side, there are no metal electrodes obstructing the front side, resulting in a larger light-receiving area and improved battery efficiency.

[0046] The silicon substrate 1 is selected from N-type silicon wafers with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 2 Ω·cm to 3.5 Ω·cm. In an optional embodiment, the front side of the silicon substrate 1 has a textured structure, which has a good light-limiting effect and can further improve the light utilization rate.

[0047] The first doped structure 2 is a diffusion region formed by the diffusion of dopant sources directly inward from the back side of the silicon substrate 1. When the first doped structure 2 is a P-type doped structure, it is formed by the diffusion of P-type dopant sources inward from the back side of the silicon substrate 1; P-type dopant sources include, but are not limited to, boron, aluminum, gallium, etc. In this case, the PN junction is located inside the silicon substrate 1, which is beneficial for the separation and collection of charge carriers and can improve the battery efficiency. When the first doped structure 2 is an N-type doped structure, it is formed by the diffusion of N-type dopant sources inward from the back side of the silicon substrate 1; N-type dopant sources include, but are not limited to, phosphorus, arsenic, antimony, etc.

[0048] The diffusion depth of the dopant source along the thickness direction of the silicon substrate 1 is called the junction depth. The diffusion depth H1 of the first doped structure 2 is related to the dopant source and the diffusion process, and can be adjusted as needed.

[0049] like Figure 2 , Figure 4 , Figure 6 , Figure 8 As shown, the first doped structure 2 includes a gate line region 21 and a non-gate line region 22, wherein the doping concentration of the gate line region 21 is greater than the doping concentration of the non-gate line region 22.

[0050] The high doping concentration of the gate region 21 forms an ohmic contact with the first electrode 91, reducing the series resistance of the battery and increasing the fill factor FF. Conversely, the low doping concentration of the non-gate region 22 reduces the probability of carrier surface recombination, decreasing the reverse saturation current and thus increasing the open-circuit voltage Voc and short-circuit current Isc. Furthermore, the gate region 21 and the non-gate region 22 can create a P++ / P+ or N++ / N+ high-low junction laterally, which is beneficial for improving carrier collection and further increasing the short-circuit current Isc.

[0051] In an optional embodiment, the doping concentration of the gate region 21 is 5E18cm⁻¹. -3 ~1E20cm -3 The sheet resistance is 80 ohm / sq to 130 ohm / sq; the sheet resistance of the non-gate region 22 is 200 ohm / sq to 400 ohm / sq.

[0052] The second doped structure 3 is located in a region recessed from the back side to the front side of the silicon substrate 1, and the second doped structure 3 is a tunneling passivation contact structure. The tunneling passivation contact structure includes at least one tunneling layer 31 and a doped polysilicon layer 32 located on the side of each tunneling layer 31 facing away from the silicon substrate 1. The second electrode 92 is in contact with the doped polysilicon layer 32.

[0053] In one embodiment, the passivation contact structure includes a tunneling layer 31 and a doped polysilicon layer 32. The second electrode 92 is in contact with the doped polysilicon layer 32, thereby avoiding direct contact between the second electrode 92 and the silicon substrate 1 and improving battery efficiency.

[0054] The tunneling layer 31 is selected from silicon oxide (SiOx) or silicon carbide (SiC), with a thickness of 1 nm to 3 nm, preferably 1 nm to 2.5 nm, more preferably 1 nm to 2 nm or 1.5 nm to 2.5 nm. The thickness of the tunneling layer 31 is optimized according to its density. When the tunneling layer 31 is SiOx, the thickness is between 1.4 nm and 2.3 nm; when the tunneling layer 31 is SiC, the film is more dense, with a thickness of 1 nm to 1.8 nm.

[0055] The doped polysilicon layer 32 is an N-doped polysilicon layer; the following explanation will use phosphorus doping as an example. The doping concentration is 1E19cm⁻¹. -3 ~1E21cm -3 1E20cm is preferred -3 ~9E20cm -3 The thickness is 80nm to 120nm, and can be set to 90nm, 85nm, 100nm, 105nm, 110nm, or 115nm.

[0056] In another embodiment, the tunneling passivation contact structure includes n tunneling layers 31 and a doped polycrystalline silicon layer 32 located on the side of each tunneling layer 31 facing away from the silicon substrate 1, where n ≥ 2. The multiple tunneling layers 31 can hinder the inward diffusion of metallic silver, preventing it from contacting the silicon substrate and forming a silicon-silver alloy.

[0057] In the direction from the silicon substrate 1 toward the back side, the second electrode 92 is in contact with at least one of the second to nth doped polysilicon layers 32; that is, the second electrode 92 is in contact with some or all of the other doped polysilicon layers except the one closest to the silicon substrate 1, and will not reach the innermost doped polysilicon layer, thus avoiding direct contact between silver and the silicon substrate.

[0058] In one embodiment, the passivation contact structure includes two doped polysilicon layers, and the second electrode 92 contacts only the doped polysilicon layer 32 furthest from the silicon substrate 1.

[0059] In another embodiment, the passivation contact structure includes three doped polysilicon layers 32, and the second electrode 92 is in contact only with the outermost doped polysilicon layer 32, or the second electrode 92 is in contact only with the first and second doped polysilicon layers 32 counted from the outside in.

[0060] Also, please refer to Figures 1 to 8 As shown, the first doped structure 2 is a P-type diffusion region, and the doped polysilicon layer 32 is an N-type doped polysilicon layer. Alternatively, please refer to... Figures 9-12 As shown, the first doped structure 2 is an N-type diffusion region, and the doped polysilicon layer 32 is a P-type doped polysilicon layer.

[0061] The width W1 of the P-type doped structure is greater than the width W2 of the N-type doped structure, and the area of ​​the PN junction region is greater than the area of ​​the N-N+ region. This is beneficial for the generation, separation and collection of photogenerated carriers, which can improve battery efficiency.

[0062] Also, please refer to Figures 1-10 As shown, along the direction from the front to the back of the silicon substrate 1, the first doped structure 2 is higher than the second doped structure 3. By having the first doped structure 2 higher than the second doped structure 3, on the one hand, the surface area of ​​the entire back side is increased, thus expanding the light-receiving area; on the other hand, the back and sides of the first doped structure 2 are exposed outward, increasing the light-absorbing area of ​​the first doped structure 2, enabling it to generate and successfully collect more charge carriers, thereby improving battery efficiency.

[0063] Of course, such as Figures 11-12 As shown, along the direction from the front to the back of the silicon substrate 1, the second doped structure 3 is higher than the first doped structure 2, which can also increase the back surface area, increase the back light-receiving area in the bifacial module, and improve the battery efficiency.

[0064] The spacer 4 separates the first doped structure 2 and the second doped structure 3 to prevent leakage problems caused by contact between the two.

[0065] In one embodiment, the width W3 of the spacer region 4 is 10 μm to 150 μm. Under the premise of isolating leakage current, the narrower the width W3 of the spacer region 4, the less recombination of charge carriers in that region, and the higher the battery efficiency. Preferably, the width W3 is 50 μm to 100 μm.

[0066] In this invention, the spacer region 4 is recessed from the back side of the silicon substrate 1 towards the front side, and the recess depth H2 at the location of the second doped structure 3 and / or the recess depth H3 of the spacer region 4 is not less than the diffusion depth H1 of the diffusion region. This design ensures that the spacer region 4 completely isolates the first doped structure 2 and the second doped structure 3. For example, on the one hand, if the recess depth H2 at the location of the second doped structure 3 is not less than the diffusion depth H1 of the diffusion region, the first doped structure 2 and the second doped structure 3 can be isolated in the thickness direction, and the back surface area can be effectively increased. This optimizes the back stepped design, improves optical utilization, and enhances short-circuit current, thus achieving both electrical and optical improvements. On the other hand, based on the spacer region 4 being located between the first doped structure 2 and the second doped structure 3, the recess depth H2 at the location of the second doped structure 3 is designed to be not less than the diffusion depth H1 of the diffusion region, so that the first doped structure 2 and the second doped structure 3 are isolated in the extension direction of the silicon substrate 1. Thus, the combination of "the recess depth H2 at the location of the second doped structure 3 is not less than the diffusion depth H1 of the diffusion region" and "spacer region 4" completely isolates different types of doped structures in the extension and thickness directions of the silicon substrate 1 to avoid back leakage, while increasing the back surface area and improving optical utilization.

[0067] In one embodiment, the recess depth H2 at the location of the second doped structure 3 is less than the recess depth H3 of the spacer region 4, completely isolating the diffusion region and the passivation contact structure in both the extension and thickness directions of the silicon substrate 1, resulting in good isolation. Specifically, not only is the recess depth H3 of the spacer region 4 greater than the recess depth H2 at the location of the second doped structure 3, but the recess depth H2 at the location of the second doped structure 3 is also not less than the diffusion depth H1 of the diffusion region. This facilitates both complete electrical isolation of the first doped structure 2 and the second doped structure 3 in both the thickness and planar directions through structural design to maximize leakage current suppression, and simultaneously increases the effective surface area on the back of the battery and forms a stepped structure that facilitates multiple reflections of light, thereby improving the optical utilization rate of the battery and ultimately obtaining higher short-circuit current and open-circuit voltage. In other words, a three-dimensional isolation and optical enhancement structure can be constructed to achieve dual and thorough physical and electrical isolation of the first doped structure 2 and the second doped structure 3 in the thickness and extension directions of the silicon substrate 1, while simultaneously optimizing the back-side stepped design, improving optical utilization, and increasing short-circuit current, thereby achieving both electrical and optical improvements.

[0068] The distance from the back surface of the spacer region 4 (the wall of the spacer region 4 facing the front side of the silicon substrate 1) to the back surface of the first doped structure 2 is called the depth H4 of the spacer region 4, which is 1 μm to 20 μm. This depth H4 preferably exceeds the diffusion depth H1 of the diffusion region. Alternatively, this depth is preferably 5 μm to 10 μm. In this way, a defined step structure with a specific height (1 μm to 20 μm) is formed between the first doped structure 2 and the bottom of the recessed spacer region 4. This step structure physically ensures insulation between different electrodes during subsequent metallization, preventing short circuits.

[0069] In one embodiment, the distance from the back surface of the second doped structure 3 to the front surface of the silicon substrate 1 is not greater than the distance from the back surface of the first doped structure 2 to the front surface of the silicon substrate 1. Alternatively, the dimension of the second doped structure 3 in the thickness direction of the silicon substrate 1 is not greater than the recess depth H3 of the spacer region 4. With this design, the first doped structure 2 and the second doped structure 3 form a height difference on the back side of the silicon substrate 1, increasing the surface area of ​​the back side, i.e., increasing the light-absorbing area, which can improve the efficiency of the solar cell.

[0070] In one embodiment, the distance between the back surface of the first doped structure 2 and the back surface of the second doped structure 3 in the thickness direction of the silicon substrate 1 is 1 μm to 10 μm. This not only increases the surface area of ​​the back surface but also creates a stepped shape, allowing light to undergo multiple reflections on the back surface, which is more conducive to light absorption. Preferably, the height difference is 4 μm to 10 μm.

[0071] Alternatively, the surface of the spacer region 4 facing the silicon substrate 1 is planar, which provides good passivation and can improve the cell efficiency by 0.1 to 0.2% while keeping other structures unchanged. Or, the surface of the spacer region 4 facing the silicon substrate 1 can have a textured surface.

[0072] In addition, the back side of the solar cell 100 is provided with a back passivation layer 5 and a back anti-reflection layer 6. The first electrode 91 passes through the back anti-reflection layer 6 and the back passivation layer 5 and contacts the grid line region 21. The second electrode 92 passes through the back anti-reflection layer 6 and the back passivation layer 5 and contacts the doped polycrystalline silicon layer 32.

[0073] The back passivation layer 5 is preferably an alumina layer, providing excellent field passivation for the first doped structure 2 and excellent interface passivation for the second doped structure 3. In this invention, the thickness of the back passivation layer 5 is preferably 3 nm to 6 nm.

[0074] The back antireflection layer 6 is selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60nm to 130nm, which reduces reflectivity and improves light utilization.

[0075] In an optional embodiment, the solar cell 100 further includes a front passivation layer 7 and a front antireflection layer 8 sequentially disposed on the front side of the silicon substrate 1 to passivate surface defects on the front side. In this invention, the front passivation layer 7 and the back passivation layer 5 are made of the same material and have the same thickness, and can be deposited together; the front antireflection layer 8 and the back antireflection layer 6 are made of the same material and have the same thickness, and can also be deposited in the same process.

[0076] In the solar cell 100 of the present invention, the first doped structure 2 is a diffusion region formed by the diffusion of dopant from the back side of the silicon substrate 1 inward, and the second doped structure 3 is located in a region recessed from the back side to the front side of the silicon substrate 1, and the second doped structure 3 is a tunneling passivation contact structure. This structural design allows for the first doped structure 2 to be formed by diffusion on the back side of the silicon substrate, followed by the removal of a portion of the diffusion junction, and then the deposition of the tunneling passivation contact structure. It exhibits high compatibility with the process flow of TOPCon cells and is suitable for industrialization.

[0077] The following example, using boron-doped P-type diffusion region as the first doped structure 2 and phosphorus-doped N-type tunneling passivation contact structure as the second doped structure, provides a method for fabricating a solar cell for illustration.

[0078] S1 uses a boron diffusion process to form a diffusion region (boron junction) and BSG on the back side of silicon substrate 1.

[0079] S11 First, a boron source is formed on the entire back side of the silicon substrate 1. The silicon substrate 1 is fixed in a quartz boat and placed in a tube furnace. The boron source and oxygen are introduced to deposit a layer of boron source (or a through-source) on the back side of the silicon substrate 1. The boron source is boron trichloride (BCl3), with a flow rate of 90 sccm to 150 sccm, an oxygen flow rate of 100 sccm to 500 sccm reacting with BCl3, and an oxygen flow rate of 1 slm to 10 slm for forming the oxide layer; or, the boron source is boron tribromide (BBr3), with a boron trichloride flow rate of 90 sccm to 150 sccm, an oxygen flow rate of 100 sccm to 500 sccm reacting with BBr3, and an oxygen flow rate of 1 slm to 10 slm for forming the oxide layer.

[0080] S12 forms a heavily doped gate region 21 by laser scanning in the gate region of the first doped structure 2. Laser parameters: laser gas power is 120W, using 63% power for wafer fabrication; laser frequency is 100kHz, and scan speed is 25m / s.

[0081] S13 then diffuses in the non-gate region.

[0082] In one optional embodiment, the heavily doped silicon substrate 1 is placed in a tube furnace, and oxygen is introduced into the tube furnace at a temperature of 950°C to 1000°C and an oxygen flow rate of 10 slm to 15 slm. At the high temperature, the boron source in the non-gate region diffuses inward to form a non-gate region 22, while BSG is formed on the entire surface.

[0083] In one optional embodiment, the sheet resistance after depositing the boron source is 120 ohm / sq to 170 ohm / sq; after laser scanning, the doping concentration of the gate region 21 is 5E18cm. -3 ~1E20cm -3 The sheet resistance is 80 ohm / sq to 130 ohm / sq; after high-temperature oxidation, the sheet resistance of the non-gate region 22 is 200 ohm / sq to 400 ohm / sq.

[0084] In an optional embodiment, the first doped structure 2 is a diffusion region formed by boron directly diffusing inward from the back side of the silicon substrate 1, forming an NP junction inside the silicon substrate 1, which is beneficial for carrier separation and transport; furthermore, referring to Table 1, the diffusion depth of boron is 0.5 μm to 1.0 μm, which optimizes the passivation effect of the diffusion region, making the dark saturation current density J0 of the diffusion region 2 fA / cm 2 ~4fA / cm 2 This allows for a balanced passivation effect with the second doped structure 3, and the junction depth results in less parasitic light absorption, thus comprehensively improving the battery efficiency. Furthermore, the dark saturation current density J0 of the second doped structure 3 is 1 fA / cm². 2 ~3fA / cm 2 When this optimal passivation level is reached, a roughly fixed junction depth level will appear.

[0085] Table 1: Diffusion depth of boron and its corresponding diffusion depth, minority carrier lifetime, and dark saturation current density.

[0086] It should be noted that, in the batteries corresponding to Examples 1 to 3, Comparative Examples 1 and 2, the structural features are the same except for the diffusion depth of boron.

[0087] As shown in Table 1, excessively deep boron junctions increase Auger recombination and reduce silicon wafer lifespan; conversely, shallow junctions pose a risk of Ag puncturing the PN junction region during metal electrode fabrication. Therefore, a boron diffusion depth of 0.5 μm to 1.0 μm was designed, resulting in advantages in both bifaciality and efficiency of the battery.

[0088] S2 removes the BSG and boron junction outside the first doped structure 2:

[0089] S21 performs laser ablation on the first doped structure 2 to remove the BSG outside the first doped structure 2. The laser power is 50W to 120W, preferably an ultraviolet picosecond or green picosecond laser, which has low damage and low cost; a femtosecond laser can also be used.

[0090] S22 removes the boron junction outside the first doped structure 2:

[0091] First, the BSG on the front and sides of the silicon substrate 1 is removed using an HF solution with a concentration of 5% to 20% (volume concentration). In an optional embodiment, this step is performed in a chain machine.

[0092] The material is then polished to remove the boron junction outside the first doped structure 2, as well as the boron junction wrapped around the front side. The boron junction of the first doped structure 2 and the BSG are retained. In an optional embodiment, this step is performed in a tank mill.

[0093] This step removes the boron junction outside the first doped structure 2, as well as the BSG on the front and sides and the boron junction expanded on the front. The process is simple and lays a good foundation for subsequent processes.

[0094] S3 Backside Tunneling Passivation Contact Structure and Mask Layer: A tunneling layer 31 and a phosphorus-doped amorphous silicon layer are grown on the entire backside using PECVD in-situ doping, with a mask layer grown on the outermost side. Here, multiple alternating layers of tunneling layers 31 and phosphorus-doped amorphous silicon layers are deposited to form a tunneling passivation contact structure including multiple tunneling layers 31 and doped polycrystalline silicon layers 32.

[0095] In one embodiment, the tunneling layer 31 is SiOx, and its thickness is preferably 1.4 nm to 2.3 nm.

[0096] In another embodiment, the tunneling layer 31 is SiC, which is more dense and preferably has a thickness of 1 nm to 1.8 nm.

[0097] The thickness of the N-poly layer is preferably 80 nm to 120 nm.

[0098] The mask layer is preferably a silicon oxide layer, with a thickness controlled in the range of 10nm to 50nm.

[0099] S4 uses a high-temperature annealing furnace, and the annealing temperature can be matched according to the tunneling conditions. The tunneling layer 31 has a large thickness, requiring a high annealing temperature. In an optional embodiment, the annealing temperature is 850℃~950℃, which can be optimally matched with conventional tunneling layers 31, ensuring a doping concentration of 1E19cm⁻¹ in the n-poly region electrochemical doping concentration test (ECV test). -3 ~1E21cm -3 .

[0100] During this process, a BSG layer is retained in the tunneling layer 31 of the first doped structure 2 to prevent the inward diffusion of phosphorus; while outside the first doped structure 2, phosphorus diffuses through the tunneling layer 31 into the silicon substrate 1 to form a phosphorus doped region.

[0101] The annealing temperature is related to the density and thickness of the tunneling layer 31. In one optional embodiment, when the tunneling layer 31 is silicon oxide, the thickness is 1.4 nm to 2.3 nm and the annealing temperature is 880 °C to 950 °C; when the tunneling layer 31 is silicon carbide, the thickness is 1 nm to 1.8 nm and the annealing temperature is 850 °C to 900 °C, so as to ensure that the phosphorus outside the first doped structure 2 diffuses inward to the silicon substrate 1.

[0102] S5 removes the mask layer, doped polysilicon layer 32, and tunneling layer 31 outside the second doped structure 3 that is spaced apart from the first doped structure 2:

[0103] S51 uses a laser process to remove the mask layer outside the second doped structure 3, exposing the underlying doped polycrystalline silicon layer 32. Laser parameters: laser power 50W~120W, preferably ultraviolet picosecond or green picosecond laser, the less damaging the laser, the more beneficial it is for film opening.

[0104] The S52 uses a chain machine and HF solution to remove the mask layer that has been wrapped around the front side.

[0105] S53 then uses a tank etching machine and alkaline solution to remove the doped polysilicon layer 32 and tunneling layer 31 outside the second doped structure 3 on the back side; at the same time, alkaline etching is performed on the front side of the silicon substrate 1 to form a pyramid structure on the exposed silicon substrate 1, and finally it is cleaned.

[0106] In step S5, the film layers at the location of the second doped structure 3 and the location of the spacer region 4 can be removed in a patterned manner, so that the depression depth H2 at the location of the second doped structure 3 and the depression depth H3 at the location of the spacer region 4 are different.

[0107] Compared to related technologies that "first form a textured structure on the surface of silicon substrate 1 and then prepare other films", this invention forms a pyramid structure on the front side after the important structures and films of the first doped structure 2 and the second doped structure 3 are prepared. On the one hand, there is no need to polish the back side before boron diffusion; on the other hand, step S53 forms a pyramid structure on the front side while removing the doped polysilicon layer 32 and tunneling layer 31 on the back side, achieving multiple benefits; furthermore, when the front side is flat, it is more conducive to the deposition and cleaning of films in the above steps.

[0108] In addition, the boron junction, tunneling layer 31, and doped polysilicon layer 32 between the first doped structure 2 and the second doped structure 3 have all been removed to form a spacer region 4, thereby preventing leakage between the first doped structure 2 and the second doped structure 3.

[0109] In this invention, the width W3 and depth of the interval 4 are as described above, and will not be repeated here.

[0110] S6 Double-sided passivation. Using the ALD process, aluminum oxide is deposited on both the front and back sides, with a preferred thickness of 3nm to 6nm. Al2O3 provides excellent field passivation for the first doped structure 2 and excellent interface passivation for the second doped structure 3. In this invention, the double-sided passivation layer is not a mandatory process step.

[0111] S7 Double-sided antireflective layer: can be a stacked film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60nm to 130nm. In this invention, the double-sided antireflective layer is not a necessary process step.

[0112] S8 electrode fabrication: The electrode is fabricated by screen printing and sintering, including the fabrication of the back main gate electrode and the fabrication of the back sub-gate electrodes of the first doped structure 2 and the second doped structure 3.

[0113] The S9 uses laser-assisted contact optimization (LECO) technology to laser sinter the first electrode 91 and the second electrode 92, which can improve the contact between silver and silicon in the electrodes, thereby increasing the battery efficiency by more than 0.2% to 0.3%. It can also change the electrode paste, such as using silver-coated copper paste with low silver content, to save costs.

[0114] The laser wavelength is 1064nm or 532nm, and the laser width is 100 micrometers or 1mm to 2mm.

[0115] In summary, the solar cell 100 of the present invention improves cell efficiency by placing both the first electrode 91 and the second electrode 92 on the back side, eliminating metal electrode obstruction on the front side, resulting in a large light-receiving area and high light conversion efficiency. Furthermore, by incorporating an SE structure in the first doped structure 2, the open-circuit voltage and short-circuit current of the cell are improved; and by incorporating a passivated contact structure in the second doped structure 3 to passivate its surface, the short-circuit current is increased, thus enhancing overall cell efficiency.

[0116] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0117] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A solar cell, characterized in that, include: A plurality of first doped structures are spaced apart, wherein the first doped structure is a diffusion region formed by the diffusion of dopant from the back side of the silicon substrate inward; A second doped structure is alternately disposed with the first doped structure. The second doped structure is located in a region recessed from the back side to the front side of the silicon substrate. The second doped structure is a tunneling passivation contact structure, and the doping type of the tunneling passivation contact structure is opposite to that of the diffusion region. The spacer region is located between the first doped structure and the second doped structure; The first electrode is located on the back side of the first doped structure; The second electrode is located on the back side of the tunneling passivation contact structure; The tunneling passivation contact structure includes n tunneling layers and a doped polysilicon layer located on the side of each tunneling layer facing away from the silicon substrate; wherein, n≥2, and in the direction from the silicon substrate to the back side, the second electrode is in contact with at least one of the 2nd to nth doped polysilicon layers, and the doping type of the different doped polysilicon layers is the same.

2. The solar cell according to claim 1, characterized in that: The first doped structure is a diffusion region formed by boron diffusing inward from the back side of the silicon substrate, and the diffusion depth of boron is 0.5 μm to 1.0 μm.

3. The solar cell according to claim 1, characterized in that: One of the first doped structure and the second doped structure forms a PN junction with the silicon substrate, and the other forms a high-low junction with the silicon substrate. The area of ​​the PN junction region is larger than the area of ​​the high-low junction region.

4. The solar cell according to claim 1, characterized in that: The spacer region is recessed from the back side to the front side of the silicon substrate, and the recess depth of the spacer region at the location of the second doped structure is not less than the diffusion depth of the diffusion region.

5. The solar cell according to claim 4, characterized in that: The depth of the depression at the location of the second doped structure is less than the depth of the depression in the spacer region.

6. The solar cell according to claim 1, characterized in that: The width of the interval is 10μm to 150μm.

7. The solar cell according to claim 1, characterized in that: The spacer region is recessed from the back side of the silicon substrate to the front side, and the distance from the back surface of the spacer region to the back surface of the first doped structure is 1 μm to 20 μm.

8. The solar cell according to claim 1, characterized in that: The distance from the back surface of the second doped structure to the front surface of the silicon substrate is not greater than the distance from the back surface of the first doped structure to the front surface of the silicon substrate; or The dimension of the second doped structure in the thickness direction of the silicon substrate is not greater than the recess depth of the spacer region; or The distance between the back surface of the first doped structure and the back surface of the second doped structure in the thickness direction of the silicon substrate is 1 μm to 10 μm.

9. The solar cell according to claim 1, characterized in that: The diffusion region includes a gate line region and a non-gate line region, wherein the doping concentration of the gate line region is greater than that of the non-gate line region, and the first electrode is in contact with the gate line region.

10. The solar cell according to claim 9, characterized in that: The sheet resistance of the gate line region is 80 ohm / sq to 130 ohm / sq, and the sheet resistance of the non-gate line region is 200 ohm / sq to 400 ohm / sq.

11. The solar cell according to any one of claims 1 to 10, characterized in that: The first doped structure is a P-type diffusion region, and the doped polysilicon layer is an N-type doped polysilicon layer; or The first doped structure is an N-type diffusion region, and the doped polysilicon layer is a P-type doped polysilicon layer.

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