Solar cell and manufacturing method thereof

Abstract

The invention provides a solar cell and a manufacturing method thereof. The solar cell comprises a substrate; the epitaxial structure is arranged on the surface of one side of the substrate; the ohmic contact layer is arranged on the surface, deviating from the substrate, of the epitaxial structure; the grid line electrode is in contact with the ohmic contact layer; the back electrode is arranged on the surface of one side, deviating from the epitaxial structure, of the substrate; wherein the ohmic contact layer comprises a composite stacked structure formed by a phosphide layer and an arsenide layer. Through the arrangement, the conduction band bottom of the phosphide layer is higher than the arsenide layer, and an electron barrier (delta Ec) is formed at the interface of the phosphide layer and the arsenide layer; heavy doping is carried out on the ohmic contact layer, so that a Schottky barrier between the grid line electrode and the phosphide layer and a heterojunction barrier (delta Ec) between the phosphide layer and the arsenide layer become thin barriers capable of being tunneled by electrons due to narrowing of a depletion region, and overall low-resistance ohmic contact is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, and more particularly to a solar cell and a manufacturing method thereof. BACKGROUND

[0002] Gallium arsenide solar cells are superior to silicon cells in matching the energy gap with the solar spectrum, and their conversion efficiency is about twice that of crystalline silicon, and they are more sensitive to light. Because of their high photoelectric conversion efficiency, excellent radiation resistance and high temperature resistance, arsenide solar cells (such as GaAs cells) have an irreplaceable position in space, aerospace, concentrated photovoltaic (CPV) and some special ground applications. In recent years, with the development trend of higher conversion efficiency, the highest efficiency of III-V multijunction solar cells has reached 47%. Under the epitaxial technology of high photoelectric conversion efficiency, ordinary chip technology has been difficult to match, especially in combination with the grid line electrode technology. In order to reduce the resistance, it is necessary to increase the width or thickness of the grid line electrode, but this will block more incident light and reduce the effective light absorption area of the cell, thereby causing the short-circuit current (Jsc) to decrease, which is a typical "resistance-shading" trade-off contradiction.

[0003] In view of this, the present application has been specially designed, and the present application has been produced. SUMMARY

[0004] The purpose of the present application is to provide a solar cell and a manufacturing method thereof, which can reduce the contact resistance and light blocking of the grid line electrode to adapt to the application of high photoelectric conversion efficiency solar cells.

[0005] In order to achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows:

[0006] A solar cell, comprising:

[0007] a substrate;

[0008] an epitaxial structure provided on one side surface of the substrate;

[0009] an ohmic contact layer provided on the surface of the epitaxial structure away from the substrate;

[0010] a grid line electrode in contact with the ohmic contact layer;

[0011] a back electrode provided on the surface of the substrate away from the epitaxial structure;

[0012] wherein the ohmic contact layer comprises a composite stack structure composed of a phosphide layer and an arsenide layer.

[0013] Preferably, the ohmic contact layer comprises alternating stacked phosphide layers and arsenide layers; and the top layer of the ohmic contact layer is an arsenide layer, and the bottom layer of the ohmic contact layer is a phosphide layer.

[0014] Preferably, the composite stacked structure includes at least two units composed of the phosphide layer and the arsenide layer; and in at least one unit, the thickness of the arsenide layer is L1 and the thickness of the phosphide layer is L2, then L1≥2*L2.

[0015] Preferably, at least two repeating units in the composite stacked structure have different thicknesses.

[0016] Preferably, the composite stacking structure is a periodic structure.

[0017] Preferably, the ohmic contact layer has n-type doping, and the n-type doping concentration of the ohmic contact layer is not less than the n-type doping concentration of the epitaxial structure; further, the n-type doping concentration of the ohmic contact layer is between 1E18cm⁻¹. -3 Up to 1E21 cm -3 Between these values, including endpoint values. Furthermore, the n-type doping concentration of the ohmic contact layer is not less than 5E18cm⁻¹. -3 Preferably, the n-type doping concentration of the ohmic contact layer is between 1E19cm⁻¹. -3 Up to 1E20cm -3 Between, including endpoint values.

[0018] Preferably, at least two repeating units in the composite stack structure have different n-type doping concentrations.

[0019] Preferably, the ohmic contact layer comprises at least one of the following: Al GaInP / Al GaInAs composite stacked structure, Al GaInP / GaAs composite stacked structure, Al GaInP / GaInAs composite stacked structure, GaInP / Al GaInAs composite stacked structure, GaInP / GaAs composite stacked structure, and GaInP / GaInAs composite stacked structure.

[0020] Preferably, the gate electrode is stacked on the side surface of the ohmic contact layer opposite to the epitaxial structure.

[0021] Preferably, the ohmic contact layer has a channel, and at least a portion of the gate electrode is filled in the channel; wherein the channel penetrates the ohmic contact layer to expose a portion of the surface of the epitaxial structure, or the channel does not penetrate the ohmic contact layer.

[0022] Preferably, the filling height of the gate electrode is flush with the surface of the ohmic contact layer on the side facing away from the structure;

[0023] Alternatively, the filling height of the gate electrode may be higher than the side surface of the ohmic contact layer that faces away from the structure.

[0024] Alternatively, the filling height of the gate electrode may be lower than the side surface of the ohmic contact layer that faces away from the structure.

[0025] Preferably, within the channel, the contact surface between the gate electrode and the ohmic contact layer includes the channel sidewall.

[0026] Preferably, the bottom surface of the channel is provided with an ohmic contact layer with an uneven surface, and the gate electrode contacts the ohmic contact layer through the uneven surface.

[0027] Preferably, the channel has sloping sidewalls.

[0028] Preferably, it further includes a transparent conductive layer disposed on the surface of the epitaxial structure near the ohmic contact layer.

[0029] The present invention also provides a method for manufacturing a solar cell, comprising:

[0030] Provide a substrate;

[0031] An epitaxial structure is fabricated on one side surface of the substrate;

[0032] An ohmic contact layer is grown on an epitaxial structure; wherein the ohmic contact layer comprises a composite stacked structure consisting of an arsenide layer and a phosphide layer, and the ohmic contact layer is obtained through steps 1 to 4:

[0033] Step 1: The epitaxial structure is obtained by growing it in a reaction chamber at a growth temperature of TO.

[0034] Step 2: Lower the growth temperature to T1 to grow the phosphide layer, and TO-T1≥30℃;

[0035] Step 3: Increase the growth temperature to T2 to grow the arsenide layer, and T2-T1≥10℃;

[0036] Step 4: Repeat steps 2 to 3 above to form alternating layers of phosphide and arsenide.

[0037] A gate electrode is fabricated, wherein the gate electrode is disposed on the surface of the ohmic contact layer; or the ohmic contact layer has a channel that exposes a portion of the surface of the epitaxial structure, and at least a portion of the gate electrode is filled in the channel;

[0038] A back electrode is fabricated, wherein the back electrode is disposed on the surface of the substrate opposite to the epitaxial structure;

[0039] The annealing process is carried out in a nitrogen atmosphere; furthermore, the annealing is performed at 250–400°C for 20–30 minutes in a nitrogen atmosphere.

[0040] As can be seen from the above technical solution, the solar cell provided by the present invention includes a substrate; an epitaxial structure disposed on one side surface of the substrate; an ohmic contact layer disposed on the surface of the epitaxial structure opposite to the substrate; a gate electrode forming contact with the ohmic contact layer; and a back electrode disposed on the surface of the substrate opposite to the epitaxial structure. The ohmic contact layer comprises a composite stacked structure composed of a phosphide layer and an arsenide layer. Through this configuration, the conduction band bottom of the phosphide layer is higher than that of the arsenide layer, forming an electron barrier (ΔEc) at their interface. By heavily doping the ohmic contact layer, the Schottky barrier between the gate electrode and the phosphide layer, and the heterojunction barrier (ΔEc) between the phosphide layer and the arsenide layer, become thin barriers through which electrons can tunnel due to the narrowing of the depletion region, thereby achieving an overall low-resistance ohmic contact.

[0041] Meanwhile, during the annealing process of electrode alloy formation, the electrode metal (such as AuGeNi) undergoes an alloying reaction with the semiconductor. If the metal reacts directly with GaAs, irregular and deep-extending metal-semiconductor compound peaks are easily formed due to interfacial energy and component segregation, introducing high-resistivity phases and point defects (such as arsenic vacancies). These defects and inhomogeneous interfaces lead to uneven contact characteristics, poor stability, and excessive leakage current. In this solution, by inserting a phosphide layer on the arsenide layer, a chemically more stable and diffusion-controlled interface is provided for metal incorporation. This effectively suppresses rapid metal diffusion and confines the intense alloying reaction interface within the phosphide layer itself, acting as a diffusion barrier layer. This effectively prevents excessive metal penetration and damage to the epitaxial structure, thereby improving device reliability and ensuring core electrical performance.

[0042] Secondly, by setting the ohmic contact layer to include alternating stacked phosphide and arsenide layers; with the top layer of the ohmic contact layer being an arsenide layer and the bottom layer being a phosphide layer; furthermore, the composite stacked structure includes at least two units composed of the phosphide and arsenide layers; and in at least one unit, the thickness of the arsenide layer is L1, and the thickness of the phosphide layer is L2, then L1≥2*L2. Thus, while ensuring the protection of the bottom phosphide layer, using a highly conductive arsenide as the main metal contact layer on the top layer can effectively achieve low contact resistance between the electrode and the ohmic contact layer.

[0043] Then, the ohmic contact layer is configured to have n-type doping, and the n-type doping concentration of the ohmic contact layer is not less than the n-type doping concentration of the epitaxial structure; furthermore, the n-type doping concentration of the ohmic contact layer is between 1E18cm⁻¹. -3 Up to 1E21cm -3 Between these values, including endpoint values. Furthermore, the n-type doping concentration of the ohmic contact layer is not less than 5E18cm⁻¹. -3 Preferably, the n-type doping concentration of the ohmic contact layer is between 1E19cm⁻¹. -3 Up to 1E20cm -3 Between these values, including endpoint values, effective tunneling of the ohmic contact layer can be achieved, resulting in low contact resistance.

[0044] Furthermore, the ohmic contact layer has channels, and at least a portion of the gate electrode fills the channels; wherein, the channels penetrate the ohmic contact layer to expose a portion of the surface of the epitaxial structure, or the channels do not penetrate the ohmic contact layer. Thus, the gate electrode forms an embedded three-dimensional contact structure with the ohmic contact layer through channel embedding, increasing the physical contact area between the metal electrode (gate electrode) and the ohmic contact layer, breaking through the area limitation of traditional planar contacts, and achieving a synergistic improvement in the electrical performance and reliability of the ohmic contact by enhancing the mechanical interlocking effect.

[0045] This invention also provides a method for fabricating a solar cell, which possesses the beneficial effects of the aforementioned solar cells while being simple, convenient, and conducive to mass production. Further, the ohmic contact layer is obtained through steps 1 to 4: Step 1, growing the epitaxial structure in a reaction chamber at a growth temperature of T0; Step 2, lowering the growth temperature to T1 to grow the phosphide layer, where T0-T1≥30℃; Step 3, increasing the growth temperature to T2 to grow the arsenide layer, where T2-T1≥10℃; Step 4, repeating steps 2 to 3 to form alternating stacked phosphide and arsenide layers. By using a temperature-controlled epitaxial growth process, the crystal quality of each component material in the ohmic contact layer and the integrity of its interfaces are improved, providing a crucial fabrication guarantee for achieving a high-performance, high-stability composite ohmic contact structure. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0047] Figure 1This is a schematic diagram of the structure of the solar cell provided in Embodiment 1 of the present invention;

[0048] Figure 2 This is a schematic diagram of the ohmic contact layer of the solar cell provided in Embodiment 1 of the present invention;

[0049] Figure 3 This is a schematic diagram of the epitaxial structure of the solar cell provided in Embodiment 1 of the present invention;

[0050] Figure 4 This is another structural schematic diagram of the solar cell provided in Embodiment 1 of the present invention;

[0051] Figure 5 This is a schematic diagram of the structure of the solar cell provided in Embodiment 2 of the present invention;

[0052] Figure 6 This is a schematic diagram of the structure of the solar cell provided in Embodiment 3 of the present invention;

[0053] Figure 7 This is another structural schematic diagram of the solar cell provided in Embodiment 3 of the present invention;

[0054] Figure 8 This is another structural schematic diagram of the solar cell provided in Embodiment 3 of the present invention;

[0055] Figure 9 This is another structural schematic diagram of the solar cell provided in Embodiment 3 of the present invention;

[0056] Figure 10 This is another structural schematic diagram of the solar cell provided in Embodiment 3 of the present invention;

[0057] Figure 11 This is another structural schematic diagram of the solar cell provided in Embodiment 3 of the present invention;

[0058] Figure 12 This is a schematic diagram of the structure of the solar cell provided in Embodiment 4 of the present invention;

[0059] Figure 13 This is another structural schematic diagram of the solar cell provided in Embodiment 4 of the present invention;

[0060] Figure 14 This is another structural schematic diagram of the solar cell provided in Embodiment 4 of the present invention;

[0061] Figure 15 This is another structural schematic diagram of the solar cell provided in Embodiment 4 of the present invention;

[0062] Figure 16 This is another structural schematic diagram of the solar cell provided in Embodiment 4 of the present invention;

[0063] Figure 17 This is a schematic diagram of the structure of the solar cell provided in Embodiment 5 of the present invention;

[0064] Figure 18 This is another structural schematic diagram of the solar cell provided in Embodiment 5 of the present invention;

[0065] Figure 19 This is another structural schematic diagram of the solar cell provided in Embodiment 5 of the present invention;

[0066] Figure 20 This is another structural schematic diagram of the solar cell provided in Embodiment 5 of the present invention;

[0067] Figure 21 This is another structural schematic diagram of the solar cell provided in Embodiment 5 of the present invention;

[0068] Figure 22 This is a schematic diagram of the structure of the solar cell provided in Embodiment 6 of the present invention;

[0069] Figure 23 This is another structural schematic diagram of the solar cell provided in Embodiment 6 of the present invention;

[0070] Figure 24 This is another structural schematic diagram of the solar cell provided in Embodiment 6 of the present invention;

[0071] Figure 25 This is another structural schematic diagram of the solar cell provided in Embodiment 6 of the present invention;

[0072] Figure 26 This is another structural schematic diagram of the solar cell provided in Embodiment 6 of the present invention;

[0073] Explanation of symbols in the diagram:

[0074] 1. Substrate;

[0075] 2. Back electrode;

[0076] 3. Ohmic contact layer; 3.1. Phosphate layer; 3.2. Arsenide layer;

[0077] 4. Grid line electrode;

[0078] 5. Transparent conductive layer;

[0079] 10. First sub-cell;

[0080] 20. Second sub-cell;

[0081] 30. Third sub-cell;

[0082] 40. Tunneling knot;

[0083] 100. Extensional structure. Detailed Implementation

[0084] To make the content of this invention clearer, the following description, in conjunction with the accompanying drawings, further illustrates the invention. This invention is not limited to this specific embodiment. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0085] Example 1

[0086] like Figure 1 As shown, a solar cell includes:

[0087] Substrate 1;

[0088] An epitaxial structure 100 is disposed on one side surface of the substrate 1;

[0089] Ohmic contact layer 3, wherein the ohmic contact layer 3 is disposed on the surface of the epitaxial structure 100 opposite to the substrate 1;

[0090] The gate electrode 4 is in contact with the ohmic contact layer 3. Specifically, in this embodiment, the ohmic contact layer 3 is laid flat on the surface of the epitaxial structure 100, and the gate electrode 4 is arranged in a grid structure on the side surface of the ohmic contact layer 3 away from the epitaxial structure 100.

[0091] Back electrode 2, the back electrode 2 is disposed on the surface of the substrate 1 on the side opposite to the epitaxial structure 100;

[0092] Among them, such as Figure 2 As shown, the ohmic contact layer 3 comprises a composite stacked structure consisting of a phosphide layer 3.1 and an arsenide layer 3.2.

[0093] It should be noted that the specific number of junctions in the solar cell is not limited in the embodiments of the present invention. The solar cell can be a triple-junction solar cell or a quadruple-junction solar cell. Moreover, the triple-junction solar cell and the quadruple-junction solar cell can be lattice-matched multi-junction solar cells or lattice-mismatched multi-junction solar cells. The present invention does not impose any limitations on this. Specifically, when the solar cell is a triple-junction solar cell, as follows... Figure 3As shown, the epitaxial structure 100 includes: a Ge first sub-cell 10, an InGaAs second sub-cell 20, and a GaInP third sub-cell 30 arranged sequentially along the growth direction, with a tunnel junction 40 between adjacent sub-cells. When the solar cell is a four-junction solar cell, the epitaxial structure 100 may include: a Ge first sub-cell, an InGaAs second sub-cell, an AlInGaAs third sub-cell, and a GaInP fourth sub-cell arranged sequentially along the growth direction, with a tunnel junction between adjacent sub-cells.

[0094] The gate electrode 4 and the back electrode 2 include metal electrodes, such as a metal alloy of AuGeNi.

[0095] Optionally, the ohmic contact layer 3 includes alternating stacked phosphide layers 3.1 and arsenide layers 3.2; and the top layer of the ohmic contact layer 3 is the arsenide layer 3.2, and the bottom layer of the ohmic contact layer 3 is the phosphide layer 3.1.

[0096] Optionally, the composite stacked structure includes at least two units composed of the phosphide layer 3.1 and the arsenide layer 3.2; and in at least one unit, the thickness of the arsenide layer 3.2 is L1 and the thickness of the phosphide layer 3.1 is L2, then L1≥2*L2.

[0097] Optionally, at least two repeating units in the composite stacked structure have different thicknesses.

[0098] Optionally, the composite stacked structure is a periodic structure.

[0099] Optionally, the ohmic contact layer 3 has n-type doping (e.g., Si doping), and the n-type doping concentration of the ohmic contact layer 3 is not less than the n-type doping concentration of the epitaxial structure 100; further, the n-type doping concentration of the ohmic contact layer 3 is between 1E18cm⁻¹. -3 Up to 1E21 cm -3 Between these values, including endpoint values. Furthermore, the n-type doping concentration of the ohmic contact layer 3 is not less than 5E18cm⁻¹. -3 Preferably, the n-type doping concentration of the ohmic contact layer 3 is between 1E19cm⁻¹. -3 Up to 1E20cm -3 Between, including endpoint values.

[0100] Optionally, at least two repeating units in the composite stacked structure have different n-type doping concentrations.

[0101] Optionally, the ohmic contact layer 3 includes at least one of the following: AlGaInP / AlGaInAs composite stacked structure, AlGaInP / GaAs composite stacked structure, AlGaInP / GaInAs composite stacked structure, GaInP / AlGaInAs composite stacked structure, GaInP / GaAs composite stacked structure, and GaInP / GaInAs composite stacked structure.

[0102] Optionally, such as Figure 4 As shown, it also includes a transparent conductive layer 5, which is disposed on the surface of the epitaxial structure 100 near the ohmic contact layer 3. Further, the transparent conductive layer 5 includes one or more of ITO, FTO, IZO, AZO, GZO, and TCO layers, and this application does not impose any limitations on this.

[0103] This invention also provides a method for manufacturing a solar cell, comprising:

[0104] Provide a substrate 1;

[0105] An epitaxial structure 100 is formed on one side surface of the substrate 1;

[0106] An ohmic contact layer 3 is grown on the epitaxial structure 100; wherein the ohmic contact layer 3 comprises a composite stacked structure consisting of an arsenide layer 3.2 and a phosphide layer 3.1, and the ohmic contact layer 3 is obtained through steps 1 to 4:

[0107] Step 1: The epitaxial structure 100 is obtained by growing in a reaction chamber at a growth temperature of TO. Optionally, the temperature of TO is 630℃~680℃, including the endpoint values.

[0108] Step 2: Lower the growth temperature to T1 to grow the phosphide layer 3.1, and TO-T1≥30℃; optionally, the temperature of T1 is 580℃~620℃, including the endpoint value.

[0109] Step 3: Increase the growth temperature to T2 to grow the arsenide layer 3.2, and T2-T1≥10℃; optionally, the temperature of T2 is 600℃~640℃, including the endpoint value.

[0110] Step 4: Repeat steps 2 to 3 above to form alternating stacked phosphide layers 3.1 and arsenide layers 3.2;

[0111] A grid line electrode 4 is fabricated, and the grid line electrode 4 is disposed on the surface of the ohmic contact layer 3;

[0112] A back electrode 2 is fabricated, which is disposed on the surface of the substrate 1 on the side opposite to the epitaxial structure 100;

[0113] The annealing process is carried out in a nitrogen atmosphere; furthermore, the annealing is performed at 250–400°C for 20–30 minutes in a nitrogen atmosphere.

[0114] As can be seen from the above technical solution, the solar cell provided by the present invention includes a substrate 1; an epitaxial structure 100 disposed on one side surface of the substrate 1; an ohmic contact layer 3 disposed on the surface of the epitaxial structure 100 opposite to the substrate 1; a grid electrode 4 forming contact with the ohmic contact layer 3; and a back electrode 2 disposed on the surface of the substrate 1 opposite to the epitaxial structure 100; wherein the ohmic contact layer 3 includes a composite stacked structure composed of a phosphide layer 3.1 and an arsenide layer 3.2. With the above configuration, the conduction band bottom of the phosphide layer 3.1 is higher than that of the arsenide layer 3.2, forming an electronic barrier (ΔEc) at the interface between the two. By heavily doping the ohmic contact layer 3, the Schottky barrier between the gate electrode 4 and the phosphide layer 3.1, as well as the heterojunction barrier (ΔEc) between the phosphide layer 3.1 and the arsenide layer 3.2, become thin barriers through which electrons can tunnel due to the narrowing of the depletion region, thereby achieving an overall low-resistance ohmic contact.

[0115] Meanwhile, during the annealing process of the electrode alloy, the electrode metal (such as AuGeNi) undergoes an alloying reaction with the semiconductor. If the metal reacts directly with GaAs, irregular and deep-extending metal-semiconductor compound peaks are easily formed due to interfacial energy and component segregation, introducing high-resistivity phases and point defects (such as arsenic vacancies). These defects and inhomogeneous interfaces lead to uneven contact characteristics, poor stability, and excessive leakage current. In this solution, by inserting a phosphide layer 3.1 on the arsenide layer 3.2, a chemically more stable interface with more controllable diffusion behavior is provided for metal incorporation. This effectively suppresses rapid metal diffusion and confines the intense alloying reaction interface within the phosphide layer 3.1 itself, acting as a diffusion barrier layer. This effectively prevents excessive penetration and damage of the metal into the epitaxial structure 100, thereby improving device reliability and ensuring core electrical performance.

[0116] Secondly, by setting the ohmic contact layer 3 to include alternating stacked phosphide layers 3.1 and arsenide layers 3.2; with the top layer of the ohmic contact layer 3 being the arsenide layer 3.2 and the bottom layer being the phosphide layer 3.1; furthermore, the composite stacked structure includes at least two units composed of the phosphide layer 3.1 and the arsenide layer 3.2; and in at least one unit, the thickness of the arsenide layer 3.2 is L1, and the thickness of the phosphide layer 3.1 is L2, then L1≥2*L2. Thus, while ensuring the protection of the bottom phosphide layer 3.1, using a highly conductive arsenide as the main metal contact layer on the top layer can effectively achieve low contact resistance between the electrode and the ohmic contact layer 3.

[0117] Then, the ohmic contact layer 3 is configured to have n-type doping, and the n-type doping concentration of the ohmic contact layer 3 is not less than the n-type doping concentration of the epitaxial structure 100; furthermore, the n-type doping concentration of the ohmic contact layer is between 1E18cm⁻¹. -3 Up to 1E21cm -3 Between these values, including endpoint values. Furthermore, the n-type doping concentration of the ohmic contact layer is not less than 5E18cm⁻¹. -3 Preferably, the n-type doping concentration of the ohmic contact layer is between 1E19cm⁻¹. -3 Up to 1E20cm -3 Between these values, including endpoint values, effective tunneling of the ohmic contact layer 3 can be achieved, resulting in low contact resistance.

[0118] This invention also provides a method for fabricating a solar cell, which possesses the beneficial effects of the aforementioned solar cells while being simple, convenient, and conducive to mass production. Further, the ohmic contact layer 3 is obtained through steps 1 to 4: Step 1, growing the epitaxial structure 100 in a reaction chamber at a growth temperature of T0; Step 2, lowering the growth temperature to T1 to grow the phosphide layer 3.1, where T0-T1≥30℃; Step 3, increasing the growth temperature to T2 to grow the arsenide layer 3.2, where T2-T1≥10℃; Step 4, repeating steps 2 to 3 to form alternately stacked phosphide layers 3.1 and arsenide layers 3.2. By using a temperature-controlled epitaxial growth process, the crystal quality of each component material in the ohmic contact layer 3 and the integrity of its interfaces are improved, providing a crucial fabrication guarantee for achieving a high-performance, high-stability composite ohmic contact structure.

[0119] Example 2

[0120] The difference between this embodiment and Embodiment 1 is that in this embodiment, as shown in Embodiment 1... Figure 5 As shown, the ohmic contact layer 3 is only disposed on the side surface of the gate electrode 4 facing the epitaxial structure 100.

[0121] Example 3

[0122] The difference between this embodiment and Embodiment 1 is that in this embodiment, the ohmic contact layer 3 has channels, and the gate electrode 4 fills the channels; wherein, the channels penetrate the ohmic contact layer 3 to expose a portion of the surface of the epitaxial structure 100. Thus, the gate electrode 4 forms an embedded three-dimensional contact structure with the ohmic contact layer 3 through channel embedding, increasing the physical contact area between the metal electrode (gate electrode 4) and the ohmic contact layer 3, breaking through the area limitation of traditional planar contacts, and achieving a synergistic improvement in the electrical performance and reliability of the ohmic contact by enhancing the mechanical interlocking effect.

[0123] Furthermore, the filling height of the gate electrode 4 is flush with the side surface of the ohmic contact layer 3 facing away from the structure.

[0124] Optionally, such as Figure 6 As shown, the channel runs straight through the ohmic contact layer 3, and the gate electrode 4 completely fills the channel.

[0125] Optionally, such as Figure 7 As shown, the channel runs straight through the ohmic contact layer 3; and the gate electrode 4 only makes contact with part of the sidewall of the channel, without completely filling the channel.

[0126] Optionally, such as Figure 8 As shown, the bottom surface of the channel is provided with an ohmic contact layer 3 with an uneven surface, and the gate electrode 4 completely fills the channel.

[0127] Optionally, such as Figure 9 As shown, the bottom surface of the channel is provided with an ohmic contact layer 3 with an uneven surface, and the contact surface between the gate electrode 4 and the ohmic contact layer 3 is limited to the uneven portion.

[0128] Optionally, such as Figure 10 As shown, the bottom surface of the channel is provided with an ohmic contact layer 3 with an uneven surface, and the contact surface between the gate electrode 4 and the ohmic contact layer 3 is limited to the uneven portion and part of the sidewall of the channel.

[0129] Optionally, such as Figure 11 As shown, the channel has sloping sidewalls.

[0130] Example 4

[0131] The difference between this embodiment and Embodiment 3 is that in this embodiment, the channel does not penetrate the ohmic contact layer 3. Furthermore, the filling height of the gate electrode 4 is higher than the side surface of the ohmic contact layer 3 facing away from the structure.

[0132] Optionally, such as Figure 12As shown, the channel extends straight through a portion of the ohmic contact layer 3, and the gate electrode 4 completely fills the channel.

[0133] Optionally, such as Figure 13 As shown, the channel extends straight through a portion of the ohmic contact layer 3; and the gate electrode 4 only contacts a portion of the sidewall of the channel, without completely filling the channel.

[0134] Optionally, such as Figure 14 As shown, the bottom surface of the channel is provided with an ohmic contact layer 3 with an uneven surface, and the gate electrode 4 completely fills the channel.

[0135] Optionally, such as Figure 15 As shown, the bottom surface of the channel is provided with an ohmic contact layer 3 with an uneven surface, and the contact surface between the gate electrode 4 and the ohmic contact layer 3 is limited to the uneven portion.

[0136] Optionally, such as Figure 16 As shown, the bottom surface of the channel is provided with an ohmic contact layer 3 with an uneven surface, and the contact surface between the gate electrode 4 and the ohmic contact layer 3 is limited to the uneven portion and part of the sidewall of the channel.

[0137] Example 5

[0138] The difference between this embodiment and embodiment 3 is that in this embodiment, the channel penetrates the ohmic contact layer 3 to expose part of the surface of the epitaxial structure 100, and the filling height of the gate electrode 4 is higher than the side surface of the ohmic contact layer 3 that is away from the structure.

[0139] Optionally, such as Figure 17 As shown, the channel runs straight through the ohmic contact layer 3, and the gate electrode 4 completely fills the channel.

[0140] Optionally, such as Figure 18 As shown, the channel runs straight through the ohmic contact layer 3; and the gate electrode 4 only makes contact with part of the sidewall of the channel, without completely filling the channel.

[0141] Optionally, such as Figure 19 As shown, the bottom surface of the channel is provided with an ohmic contact layer 3 with an uneven surface, and the gate electrode 4 completely fills the channel.

[0142] Optionally, such as Figure 20 As shown, the bottom surface of the channel is provided with an ohmic contact layer 3 with an uneven surface, and the contact surface between the gate electrode 4 and the ohmic contact layer 3 is limited to the uneven portion.

[0143] Optionally, such as Figure 21As shown, the bottom surface of the channel is provided with an ohmic contact layer 3 with an uneven surface, and the contact surface between the gate electrode 4 and the ohmic contact layer 3 is limited to the uneven portion and part of the sidewall of the channel.

[0144] Example 6

[0145] The difference between this embodiment and embodiment 3 is that in this embodiment, the channel penetrates the ohmic contact layer 3 to expose part of the surface of the epitaxial structure 100, and the filling height of the gate electrode 4 is lower than the side surface of the ohmic contact layer 3 that is away from the structure.

[0146] Optionally, such as Figure 22 As shown, the channel runs straight through the ohmic contact layer 3, and the gate electrode 4 is completely filled in the channel.

[0147] Optionally, such as Figure 23 As shown, the channel runs straight through the ohmic contact layer 3; the gate electrode 4 is completely filled in the channel and only makes contact with a portion of the sidewall of the channel.

[0148] Optionally, such as Figure 24 As shown, the bottom surface of the channel is provided with an ohmic contact layer 3 with an uneven surface, and the gate electrode 4 is completely filled in the channel.

[0149] Optionally, such as Figure 25 As shown, the bottom surface of the channel is provided with an ohmic contact layer 3 with an uneven surface, and the contact surface between the gate electrode 4 and the ohmic contact layer 3 is limited to the uneven portion.

[0150] Optionally, such as Figure 26 As shown, the bottom surface of the channel is provided with an ohmic contact layer 3 with an uneven surface, and the contact surface between the gate electrode 4 and the ohmic contact layer 3 is limited to the uneven portion and part of the sidewall of the channel.

[0151] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0152] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0153] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A solar cell, characterized in that, include: Substrate; An epitaxial structure, wherein the epitaxial structure is disposed on one side surface of the substrate; An ohmic contact layer is disposed on the surface of the epitaxial structure opposite to the substrate; A gate line electrode, wherein the gate line electrode forms contact with the ohmic contact layer; A back electrode is disposed on the surface of the substrate opposite to the epitaxial structure. The ohmic contact layer comprises a composite stacked structure consisting of a phosphide layer and an arsenide layer.

2. A solar cell according to claim 1, characterized in that, The ohmic contact layer comprises alternating stacked phosphide and arsenide layers; and the top layer of the ohmic contact layer is an arsenide layer, while the bottom layer of the ohmic contact layer is a phosphide layer.

3. A solar cell according to claim 1, characterized in that, The composite stacked structure includes at least two units composed of the phosphide layer and the arsenide layer; and in at least one unit, the thickness of the arsenide layer is L1 and the thickness of the phosphide layer is L2, then L1≥2*L2.

4. A solar cell according to claim 1, characterized in that, The composite stacked structure is a periodic structure.

5. A solar cell according to claim 1, characterized in that, The ohmic contact layer has n-type doping, and the n-type doping concentration of the ohmic contact layer is between 1E18cm⁻¹. -3 Up to 1E21cm -3 Between, including endpoint values.

6. A solar cell according to claim 5, characterized in that, In the composite stacked structure, at least two repeating units have different n-type doping concentrations.

7. A solar cell according to claim 1, characterized in that, The ohmic contact layer includes at least one of the following: Al GaInP / Al GaInAs composite stacked structure, Al GaInP / GaAs composite stacked structure, Al GaInP / GaInAs composite stacked structure, GaInP / Al GaInAs composite stacked structure, GaInP / GaAs composite stacked structure, and GaInP / GaInAs composite stacked structure.

8. A solar cell according to any one of claims 1 to 7, characterized in that, The gate electrode is stacked on the side surface of the ohmic contact layer opposite to the epitaxial structure.

9. A solar cell according to any one of claims 1 to 7, characterized in that, The ohmic contact layer has channels, and at least a portion of the gate electrode is filled in the channels; wherein the channels penetrate the ohmic contact layer to expose a portion of the surface of the epitaxial structure, or the channels do not penetrate the ohmic contact layer.

10. A solar cell according to claim 9, characterized in that, The fill height of the gate electrode is flush with the surface of the ohmic contact layer on the side facing away from the structure; Alternatively, the filling height of the gate electrode may be higher than the side surface of the ohmic contact layer that faces away from the structure. Alternatively, the filling height of the gate electrode may be lower than the side surface of the ohmic contact layer that faces away from the structure.

11. A solar cell according to claim 10, characterized in that, Within the channel, the contact surface between the gate electrode and the ohmic contact layer includes the channel sidewall.

12. A solar cell according to claim 10, characterized in that, The bottom surface of the channel is provided with an ohmic contact layer with an uneven surface, and the gate electrode contacts the ohmic contact layer through the uneven surface.

13. A solar cell according to claim 10, characterized in that, The channel has sloping sidewalls.

14. A method for manufacturing a solar cell, characterized in that, include: Provide a substrate; An epitaxial structure is fabricated on one side surface of the substrate; An ohmic contact layer is grown on an epitaxial structure; wherein the ohmic contact layer comprises a composite stacked structure consisting of an arsenide layer and a phosphide layer, and the ohmic contact layer is obtained through steps 1 to 4: Step 1: The epitaxial structure is obtained by growing it in a reaction chamber at a growth temperature of TO. Step 2: Lower the growth temperature to T1 to grow the phosphide layer, and TO-T1≥30℃; Step 3: Increase the growth temperature to T2 to grow the arsenide layer, and T2-T1≥10℃; Step 4: Repeat steps 2 to 3 above to form alternating layers of phosphide and arsenide. A gate electrode is fabricated, wherein the gate electrode is disposed on the surface of the ohmic contact layer; or the ohmic contact layer has a channel that exposes a portion of the surface of the epitaxial structure, and at least a portion of the gate electrode is filled in the channel; A back electrode is fabricated, wherein the back electrode is disposed on the surface of the substrate opposite to the epitaxial structure; The annealing process is carried out in a nitrogen atmosphere; furthermore, the annealing is performed at 250–400°C for 20–30 minutes in a nitrogen atmosphere.

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