Semiconductor device and manufacturing method thereof
By setting an intermetallic compound protective layer and a dielectric layer of appropriate thickness on the resistor layer, the problem of damage to the resistor layer caused by through-hole etching is solved, and the stability of the resistor layer and the process efficiency are improved.
Patent Information
- Application Number
- CN202511417772.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-29
- Publication Date
- 2026-02-17
AI Technical Summary
During the fabrication of logic devices, when metal replacement gate technology is used to form resistors, vias penetrating the resistor layer are prone to damage, leading to problems such as resistor layer oxidation and low resistor stability.
An intermetallic compound protective layer is used to cover the resistor layer, combined with a dielectric layer of appropriate thickness, to protect the resistor layer from through-hole etching damage, and a metal oxide layer is used to prevent resistance drift.
It effectively reduces the damage to the resistive layer caused by through-hole etching, improves the stability of the resistive layer, simplifies the process flow, reduces the difficulty of planarization, and improves manufacturing efficiency.
Smart Images
Figure CN121548296A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to semiconductor devices and methods of manufacturing the same. Background Technology
[0002] In the fabrication of logic devices, as node sizes decrease, metal-substituted gate (MSG) technology has gradually become the mainstream in logic technology. When forming resistors using MSG, a through-hole (via) process is typically required for resistor connections. However, the via can easily damage the resistive layer during the through-hole process, and may even penetrate the resistive layer entirely. Therefore, semiconductor devices in related technologies often add a thicker barrier layer, such as silicon nitride, on top for buffering. However, the barrier layer deposition process can also easily damage the resistive layer, leading to resistance shift after oxidation and low resistance stability. Summary of the Invention
[0003] To address the aforementioned technical problems, this application provides a semiconductor device and a method for manufacturing the same.
[0004] To solve the above-mentioned technical problems, the present application adopts the following technical solution: providing a semiconductor device, including a substrate, a dielectric layer, a resistive layer, and an intermetallic compound protective layer; the substrate includes a device region and a resistive region; the dielectric layer covers the substrate; the resistive layer is disposed in the dielectric layer, and the resistive layer is located at least in the region corresponding to the resistive region; the intermetallic compound protective layer is disposed in the dielectric layer and covers the resistive layer.
[0005] In one embodiment of this application, the intermetallic compound protective layer includes an aluminum-containing intermetallic compound protective layer.
[0006] In one embodiment of this application, the resistive layer includes a titanium nitride and / or tantalum nitride high-resistivity material layer; the intermetallic compound protective layer includes a titanium-aluminum intermetallic compound protective layer.
[0007] In one embodiment of this application, the dielectric layer includes: a first dielectric layer covering the substrate and further covering the resistive region and the device region, wherein the resistive layer and the intermetallic compound protective layer cover the first dielectric layer and are located in the region corresponding to the resistive region; a second dielectric layer covering the first dielectric layer and further covering the resistive layer and the intermetallic compound protective layer; wherein the first dielectric layer and the second dielectric layer are made of the same material.
[0008] In one embodiment of this application, the thickness of the second dielectric layer is greater than 1200 Å.
[0009] In one embodiment of this application, the length of the intermetallic compound protective layer is less than the length of the resistive layer, so as to expose the resistive layer; the semiconductor device further includes: a resistor guide plug formed in the dielectric layer and connected to the exposed portion of the resistive layer.
[0010] In one embodiment of this application, an NMOS device and / or a PMOS device are formed in the device region, and the device region includes the gate structure of the NMOS device and / or the gate structure of the PMOS device. The gate structure includes a high-k metal gate structure. A dummy gate structure is provided in the resistance region and is formed in the same process as the gate structure in the device region.
[0011] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate including a device region and a resistive region; forming a dielectric layer covering the substrate; forming a resistive layer and an intermetallic compound protective layer covering the resistive layer in the dielectric layer, wherein the resistive layer is at least located in the region corresponding to the resistive region.
[0012] In one embodiment of this application, the dielectric layer includes a first dielectric layer and a second dielectric layer made of the same material; forming the dielectric layer to cover the substrate includes: forming the first dielectric layer to cover the substrate; forming a resistive layer and an intermetallic compound protective layer covering the resistive layer in the dielectric layer, wherein the resistive layer is at least located in the region corresponding to the resistive region, including: forming the resistive layer to cover the first dielectric layer, wherein the resistive layer is at least located in the region corresponding to the resistive region; forming the intermetallic compound protective layer to cover the resistive layer; and forming the second dielectric layer to cover the first dielectric layer, thereby further covering the resistive layer and the intermetallic compound protective layer.
[0013] In one embodiment of this application, after the step of forming the second dielectric layer to cover the first dielectric layer to further cover the resistive layer and the intermetallic compound protective layer, the manufacturing method further includes: removing a portion of the intermetallic compound protective layer and exposing the resistive layer.
[0014] This application provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a dielectric layer, a resistive layer, and an intermetallic compound protective layer. The substrate includes a device region and a resistive region. The dielectric layer covers the substrate. The resistive layer is disposed in the dielectric layer and is located at least in the region corresponding to the resistive region. The intermetallic compound protective layer is disposed in the dielectric layer and covers the resistive layer, serving to protect the resistive layer. Therefore, the intermetallic compound protective layer, as a protective layer, can exhibit lower etching loss during via etching, preventing penetration of the resistive layer during via etching and reducing damage to the resistive layer. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of the structure of one embodiment of the semiconductor device in this application; Figure 2 This is a schematic diagram of a structure of an embodiment of the patterned semiconductor device in this application; Figure 3 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method in this application; Figure 4 This is a flowchart illustrating an embodiment of step S13 in this application; Figure 5 This is a schematic diagram of the structure of the first embodiment of forming a resistive layer and an intermetallic compound protective layer in this application; Figure 6 This is a schematic diagram of the structure of the second embodiment of forming a resistive layer and an intermetallic compound protective layer in this application.
[0016] Among them, 10 is the substrate; 11 is the device region; 112 is the NMOS device; 113 is the PMOS device; 13 is the first well region; 14 is the second well region; 20 is the dielectric layer; 21 is the first dielectric layer; 22 is the second dielectric layer; 30 is the resistive layer; 40 is the intermetallic compound protective layer; 50 is the mask layer; 51 is the first mask layer; 52 is the second mask layer; 60 is the anti-reflection layer; 61 is the bottom anti-reflection layer; 62 is the third dielectric layer; and 70 is the photoresist layer. Detailed Implementation
[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0018] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.
[0019] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.
[0020] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of one embodiment of the semiconductor device in this application. Figure 1 As shown, this application embodiment first provides a semiconductor device, which includes a substrate 10, a dielectric layer 20, a resistive layer 30, and an intermetallic compound protective layer 40.
[0021] The substrate 10 includes a device region 11 and a resistive region (not shown in the figure); a dielectric layer 20 covers the substrate 10; a resistive layer 30 is disposed in the dielectric layer 20, and the resistive layer 30 is located at least in the region corresponding to the resistive region. An intermetallic compound protective layer 40 is disposed in the dielectric layer 20 and covers the resistive layer 30. The intermetallic compound protective layer 40 is used to protect the resistive layer 30.
[0022] Specifically, the substrate 10 of the semiconductor device includes a device region 11 and a resistor region, wherein the device region 11 is the area where the semiconductor device is disposed. In a possible embodiment, the device region 11 is provided with a gate structure to define the source / drain regions of the semiconductor device. The gate structure of the device region 11 is used to directly control the channel on / off via the gate voltage to achieve control of at least one of the following: signal, charge, power supply, etc.
[0023] A dielectric layer 20 covers the substrate 10, and a resistive layer 30 and an intermetallic compound protective layer 40 are embedded in the dielectric layer 20. The intermetallic compound protective layer 40 covers the resistive layer 30 and is a compound protective layer composed of two or more metals. The intermetallic compound protective layer 40 is used to cover the resistive layer 30 with a metal oxide layer generated by the reaction of metal and oxygen, so as to prevent the resistance value drift caused by oxidation of the resistive layer 30.
[0024] In this embodiment, the semiconductor device substrate 10 includes a device region 11 and a resistive region; a dielectric layer 20 covers the substrate 10; a resistive layer 30 is disposed in the dielectric layer 20, and the resistive layer 30 is located at least in the region corresponding to the resistive region; an intermetallic compound protective layer 40 is disposed in the dielectric layer 20 and covers the resistive layer 30, and the intermetallic compound protective layer 40 is used to protect the resistive layer 30. Therefore, the intermetallic compound protective layer 40, as a protective layer, can exhibit lower etching loss during via etching, thereby preventing the via etching process from penetrating the resistive layer 30 and reducing damage to the resistive layer 30. Furthermore, the intermetallic compound protective layer 40 protects the resistive layer 30 by reacting with oxygen to generate a metal oxide layer, thereby preventing the resistive layer 30 from being oxidized and causing resistance value drift, thus improving the stability of the resistive layer 30.
[0025] In some embodiments, the intermetallic compound protective layer 40 includes an aluminum-containing intermetallic compound protective layer.
[0026] Specifically, aluminum-containing intermetallic compounds are compounds formed by aluminum and one or more other metallic elements in a specific stoichiometric ratio. In possible embodiments, aluminum-containing intermetallic compounds include, but are not limited to, compounds formed by aluminum and at least one metal such as titanium, scandium, tantalum, or gold.
[0027] In this embodiment, the intermetallic compound protective layer 40 includes an aluminum-containing intermetallic compound protective layer. This aluminum-containing intermetallic compound protective layer can rapidly form a dense metal oxide layer upon contact with oxygen. The metal oxide layer includes at least a dense aluminum oxide layer. The aluminum oxide layer has high stability and can effectively prevent resistance drift caused by oxidation of the resistive layer 30. By introducing metals other than aluminum into the aluminum-containing intermetallic compound protective layer, the etching loss of the intermetallic compound protective layer 40 can be effectively reduced. This allows the intermetallic compound protective layer 40 to protect the resistive layer 30 and reduce damage to it during etching, further improving the stability of the resistive layer 30.
[0028] In some embodiments, the resistive layer 30 includes a high-resistivity material layer containing metal.
[0029] Specifically, the resistive layer 30 includes a high-resistivity material layer containing metal. The resistive layer 30 may be, but is not limited to, metal compounds such as titanium nitride or tantalum nitride. The high-resistivity material layer can be used to impede the flow of current, so that the resistive layer 30 has high resistance characteristics.
[0030] In some embodiments, the resistive layer 30 comprises a high-resistivity material layer of titanium nitride and / or tantalum nitride. The intermetallic compound protective layer 40 comprises a titanium-aluminum intermetallic compound protective layer 40.
[0031] Specifically, titanium nitride (TiN) and / or tantalum nitride (TaN) are used as the resistive layer 30 material. Titanium nitride and / or tantalum nitride have high resistivity to ensure the resistive characteristics of the resistive layer 30. When titanium nitride and / or tantalum nitride react with external oxygen atoms to undergo oxidation, the resistivity of the oxidized resistive layer 30 becomes too high, and the resistance value drifts. Therefore, in this embodiment, a titanium-aluminum intermetallic compound protective layer 40 is disposed on the resistive layer 30, allowing the titanium-aluminum intermetallic compound protective layer 40 to absorb external oxygen atoms and generate substances such as titanium oxide and aluminum oxide, thereby preventing external oxygen atoms from penetrating into the inner resistive layer 30 and reducing or avoiding problems such as excessively high resistivity and resistance value drift after the resistive layer 30 is oxidized. The resistive layer 30 can be formed using titanium nitride or tantalum nitride alone, or the two can be combined to form a multilayer structure; the titanium-aluminum intermetallic compound protective layer 40 can be a TiAl alloy, or an intermetallic compound composed of titanium, aluminum, and other metals, without specific limitations.
[0032] In some embodiments, see Figure 2 , Figure 2 This is a schematic diagram of the structure of one embodiment of the patterned semiconductor device in this application. Figure 2 As shown, the dielectric layer 20 includes a first dielectric layer 21 and a second dielectric layer 22. The first dielectric layer 21 covers the substrate 10 and further covers the resistive region and the device region 11. The resistive layer 30 and the intermetallic compound protective layer 40 cover the first dielectric layer 21 and are located in the region corresponding to the resistive region. The second dielectric layer 22 covers the first dielectric layer 21 and further covers the resistive layer 30 and the intermetallic compound protective layer 40.
[0033] Specifically, Figure 2 This is a schematic diagram of the structure during the patterning of a semiconductor device. A first dielectric layer 21 covers the substrate 10, a resistive layer 30 and an intermetallic compound protective layer 40 cover the first dielectric layer 21, and a second dielectric layer 22 covers the resistive layer 30 and the intermetallic compound protective layer 40. During patterning, a mask layer 50, an anti-reflective layer 60, and a photoresist layer 70 need to be formed on the second dielectric layer 22 to pattern the semiconductor device and form via connections on the resistive layer 30.
[0034] The first dielectric layer 21 can be used as an isolation layer for the substrate 10 to protect the gate structure on the substrate 10 from the outside environment. The first dielectric layer 21 can also be used to adjust the effective work function of the gate structure at the interface of the substrate 10 through the interface dipole effect to ensure the stability of the threshold voltage. The resistive layer 30 and the intermetallic compound protective layer 40 cover the first dielectric layer 21 and are located in the region corresponding to the resistive region. The second dielectric layer 22 covers the first dielectric layer 21 and further covers the resistive layer 30 and the intermetallic compound protective layer 40. The thickness of the second dielectric layer 22 covering the device region 11 is greater than the thickness of the second dielectric layer 22 covering the intermetallic compound protective layer 40. The second dielectric layer 22 is used to cover the resistive layer 30 and the intermetallic compound protective layer 40 to meet the planarization requirements and facilitate subsequent layer processing.
[0035] The first dielectric layer 21 and the second dielectric layer 22 are made of the same material. The material of the first dielectric layer 21 and the second dielectric layer 22 may be, but is not limited to, silicon oxide, silicon nitride, low-k dielectrics, high-k dielectrics, silicon oxynitride, etc.
[0036] In some embodiments, the thickness of the second dielectric layer 22 is greater than 1200 Å.
[0037] Specifically, in related technologies, the barrier layer is usually made of inorganic materials such as silicon nitride. Since silicon nitride has high loss as a barrier layer, it needs to be set with a large thickness to ensure barrier performance. This results in a large height difference between the barrier layer and the device region 11 in related technologies. Consequently, when forming the second dielectric layer 22 on the barrier layer and the device region 11, planarization is required after the deposition of the second dielectric layer 22. This increases the difficulty of planarization and the complexity of the manufacturing process.
[0038] In the semiconductor device of this embodiment, since the through-hole etching causes very low metal loss, the intermetallic compound protective layer 40 can ensure that the through-hole etching process does not penetrate the resistive layer 30 with a very thin thickness, thereby reducing the height difference between the resistive region and the device region 11 after the subsequent deposition of the second dielectric layer 20, and reducing the difficulty of subsequent planarization.
[0039] The semiconductor device of this embodiment controls the thickness of the second dielectric layer 22 to be greater than 1200 Å, or in other words, the thickness of the second dielectric layer 22 is greater than 1200 angstroms. In this case, the semiconductor device of this embodiment does not require planarization treatments such as chemical mechanical polishing after depositing the second dielectric layer 22, thus meeting the flatness requirements of the semiconductor device. Therefore, the process flow can be simplified, and the manufacturing efficiency of the semiconductor device can be improved.
[0040] In some embodiments, the length of the intermetallic compound protective layer 40 is less than the length of the resistive layer 30 to expose the resistive layer 30. The semiconductor device also includes a resistor lead plug (not shown) formed in the dielectric layer 20 and connected to the exposed portion of the resistive layer 30.
[0041] Specifically, the intermetallic compound protective layer 40 covers the resistive layer 30, and its length covering the resistive layer 30 is less than the overall length of the resistive layer 30. Before connecting the resistor lead plugs, vias can be formed in the dielectric layer 20 by methods such as etching. Part of the vias penetrate the intermetallic compound protective layer 40 to expose the resistive layer 30. For example, at least both ends of the resistive layer 30 can be exposed. The semiconductor device includes at least two resistor lead plugs, which are respectively connected to both ends of the resistive layer 30 for electrical connection. The resistor lead plugs are used to accurately introduce external voltage / current signals into the resistive layer 30, enabling them to participate in circuit functions.
[0042] In one possible configuration, at least two resistor leads of the semiconductor device can be divided into two groups, with one group of resistor leads disposed at the beginning of the resistor layer 30 and the other group of resistor leads disposed at the end of the resistor layer 30. The number of resistor leads in the two groups can be the same or different, and the number of resistor leads in the two groups can be, but is not limited to, one or more. Further, the arrangement direction of the device region 11 and the resistor region is defined as a first direction, and the direction perpendicular to the first direction is defined as a second direction. Both the first and second directions are located on a horizontal plane; for example, the first direction is the length direction of the resistor layer 30, and the second direction is the width direction of the resistor layer 30. In this case, the beginning and end of the resistor layer 30 can be the two ends of the resistor layer 30 in the first direction, or, as... Figure 1 As shown, the beginning and end points of the resistive layer 30 can be the two ends of the resistive layer 30 in the second direction, so that only one via location is shown in this view. The beginning and end points of the resistive layer 30 can be defined according to the lead requirements, and are not limited here.
[0043] In some embodiments, an NMOS device 112 and / or a PMOS device 113 are formed in the device region 11. The device region 11 includes the gate structure of the NMOS device 112 and / or the gate structure of the PMOS device 113, and the gate structure includes a high-k metal gate structure. A dummy gate structure (not shown) is provided in the resistor region, and the dummy gate structure in the resistor region is formed synchronously with the gate structure in the device region 11.
[0044] Specifically, in one embodiment, device region 11 forms an NMOS device 112, and the gate structure of NMOS device 112 is a high-k metal gate structure. In this case, a first well region 13 corresponding to NMOS device 112 is provided on substrate 10. The first well region 13 includes a first source / drain region, a second source / drain region, and a first channel region, with the first and second source / drain regions located on opposite sides of the first channel region. In another embodiment, device region 11 forms a PMOS device 113, and the gate structure of PMOS device 113 is a high-k metal gate structure. In this case, a second well region 14 corresponding to PMOS device 113 is provided on substrate 10. The second well region 14 includes a third source / drain region, a fourth source / drain region, and a second channel region, with the third and fourth source / drain regions located on opposite sides of the second channel region. In yet another embodiment, device region 11 forms both NMOS device 112 and PMOS device 113, with the gate structures of NMOS device 112 and PMOS device 113 arranged side-by-side on substrate 10. In one possible manner, a shallow trench or other isolation structure may be provided between the first well region 13 of the NMOS device 112 and the second well region 14 of the PMOS device 113 on the substrate 10, or the first well region 13 and the second well region 14 may be provided as a single unit, without any specific limitation here.
[0045] Among them, the High-K Metal Gate (HKMG) structure is a gate structure that uses a high-dielectric-constant (High-K) material as the gate dielectric layer and uses a metal material instead of polysilicon as the gate electrode.
[0046] In this context, the pseudo-gate structure in the resistor region exists only as a process aid or isolation structure and has no current path function. The pseudo-gate structure in the resistor region is formed in the same process as the gate structure in the device region 11. It can fill the passive area of the resistor region with the pseudo-gate structure without adding process steps, so that the formed substrate 10 has a uniform and flat substrate, reducing or avoiding processing difficulties caused by layout differences and uneven thickness.
[0047] Please see Figure 3 , Figure 3 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method in this application. Figure 3 and Figure 1 As shown in the embodiments of this application, a method for manufacturing a semiconductor device is also provided, the method comprising the following steps: Step S11: Provide a substrate 10, which includes a device region 11 and a resistor region.
[0048] Specifically, the substrate 10 is divided into a device region 11 and a resistor region. The device region 11 is used to set semiconductor devices, and the resistor region is used to set the resistor layer 30.
[0049] Step S12: Form a dielectric layer 20 to cover the substrate 10.
[0050] A dielectric layer 20 is formed on the substrate 10 so that the dielectric layer 20 covers the gate structure of the resistive region and the device region 11.
[0051] Step S13: A resistive layer 30 and an intermetallic compound protective layer 40 covering the resistive layer 30 are formed in the dielectric layer 20, wherein the resistive layer 30 is located at least in the region corresponding to the resistive region.
[0052] A resistive layer 30 and an intermetallic compound protective layer 40 are formed in the dielectric layer 20, with the intermetallic compound protective layer 40 covering the resistive layer 30. The intermetallic compound protective layer 40 protects the resistive layer 30. Vias may be formed in the dielectric layer 20 to facilitate electrical connection between the resistive layer 30 and external components. Vias may be, but are not limited to, located in the regions of the dielectric layer 20 corresponding to the PMOS device 112, the NMOS device 113, and / or the resistive layer 30.
[0053] Therefore, the semiconductor device manufacturing method of this embodiment can be achieved by providing a substrate 10, which is divided into a device region 11 and a resistor region; forming a dielectric layer 20 to cover the substrate 10; forming a resistor layer 30 in the dielectric layer 20 and an intermetallic compound protective layer 40 covering the resistor layer 30, wherein the resistor layer 30 is located at least in the region corresponding to the resistor region. The intermetallic compound protective layer 40, as a protective layer, can exhibit lower etching loss during via etching, thereby preventing penetration of the resistor layer 30 during via etching and reducing damage to the resistor layer 30.
[0054] In some embodiments, see Figures 4-6 , Figure 4 This is a flowchart illustrating an embodiment of step S13 in this application. Figure 5 This is a schematic diagram of the structure of the first embodiment of forming a resistive layer and an intermetallic compound protective layer in this application. Figure 6 This is a schematic diagram of the structure of the second embodiment of forming a resistive layer and an intermetallic compound protective layer in this application. In this embodiment, as... Figure 2 As shown, the dielectric layer 20 includes a first dielectric layer 21 and a second dielectric layer 22 made of the same material. Step S13 includes forming the first dielectric layer 21 to cover the substrate 10.
[0055] like Figure 4 As shown, in this manufacturing method, step S13 further includes the following steps: Step 131: Form a resistive layer 30 covering the first dielectric layer 21, wherein the resistive layer 30 is located at least in the region corresponding to the resistive region.
[0056] Specifically, a first dielectric layer 21 is formed on the substrate 10, and the first dielectric layer 21 is used to cover the resistive region and the device region 11. For example... Figure 5 As shown, a resistive layer 30 is further formed to cover the first dielectric layer 21. At this time, the resistive layer 30 is located at least in the region corresponding to the resistive region.
[0057] Step S132: Form an intermetallic compound protective layer 40 covering the resistive layer 30.
[0058] An intermetallic compound protective layer 40 is further formed on the resistive layer 30, the intermetallic compound protective layer 40 being used to cover the resistive layer 30.
[0059] Step S133: Form a second dielectric layer 22 to cover the first dielectric layer 21, so as to further cover the resistive layer 30 and the intermetallic compound protective layer 40.
[0060] A second dielectric layer 22 is formed to cover the first dielectric layer 21, and the second dielectric layer 22 can cover the resistive layer 30 and the intermetallic compound protective layer 40, such that the resistive layer 30 and the intermetallic compound protective layer 40 are located between the first dielectric layer 21 and the second dielectric layer 22 to ensure planarization requirements. The resistive layer 30 can be formed using atomic layer deposition (ALD), and the material of the resistive layer 30 can be, but is not limited to, materials such as TaN and TiN.
[0061] In possible ways, such as Figure 6 As shown, after step S132, the manufacturing method of this embodiment further includes: removing a portion of the resistive layer 30 and the intermetallic compound protective layer 40, so that the resistive layer 30 and the intermetallic compound protective layer 40 are located in the region corresponding to the resistive region.
[0062] In the manufacturing method of this embodiment, since the through-hole etching causes extremely low metal loss, the intermetallic compound protective layer 40 can ensure that it does not penetrate the resistive layer 30 during the through-hole etching process even with a very thin thickness. Therefore, the height difference between the intermetallic compound protective layer 40 and the device region 11 is small, effectively reducing the planarization difficulty caused by excessive height difference. The second dielectric layer 22 can be an interlayer dielectric layer. When the thickness of the second dielectric layer 22 is greater than 1200 Å, planarization treatments such as chemical mechanical polishing can be omitted after depositing the second dielectric layer 22 to meet the planarization requirements of the semiconductor device, simplifying the process flow and improving the manufacturing efficiency of the semiconductor device.
[0063] In some embodiments, such as Figure 2As shown, after step S133 above, the manufacturing method of this embodiment further includes the following steps: a mask layer 50, an anti-reflection layer 60 and a photoresist layer 70 are sequentially formed on the second dielectric layer 22, and the photoresist layer 70 is provided with at least one pattern window; the layer material exposed by the pattern window is etched to form a through hole.
[0064] Specifically, a mask layer 50, an anti-reflection layer 60, and a photoresist layer 70 are sequentially deposited on the second dielectric layer 22. The mask layer 50 is disposed on the second dielectric layer 22, the anti-reflection layer 60 is disposed on the mask layer 50, and the photoresist layer 70 is disposed on the anti-reflection layer 60. The mask layer 50 serves as a hard mask during the via etching process, reducing uneven etching and improving the accuracy of via formation. The anti-reflection layer 60 is used to suppress light reflection interference, eliminate the standing wave effect of the photoresist layer 70, and improve the exposure morphology of the photoresist layer 70, thereby improving the pattern transfer accuracy. The photoresist layer 70 has at least one pattern window to define the etching location of the underlying material.
[0065] The photoresist layer 70 serves as the top mask, allowing for layer-by-layer etching of the material layers exposed in the pattern window. Specifically, when etching the vias in the resistor layer 30, the etching penetrates the anti-reflective layer 60, the mask layer 50, and the second dielectric layer 22, and partially etches the intermetallic compound protective layer 40 covering both ends of the resistor layer 30 to form the vias. Similarly, when etching the vias in the gate structure of the device region 11, the etching penetrates the anti-reflective layer 60, the mask layer 50, and the second dielectric layer 22, and partially etches the gate structure material to facilitate the subsequent formation of the vertical electrical path of the gate structure in the device region 11 through the vias. Furthermore, the etching processes for different layers can be performed using the same or different process parameters; no specific limitations are imposed here.
[0066] In one possible embodiment, mask layer 50 may include a first mask layer 51 and a second mask layer 52, with the second mask layer 52 located between the first mask layer 51 and the second dielectric layer 22, and the first mask layer 51 located above the second mask layer 52. During via etching, vias in the resistive layer 30 and the gate structure of the device region 11 need to be formed. The first mask layer 51 serves as a hard mask for etching the gate structure of the device region 11 and also optimizes the standing wave effect. The second mask layer 52 serves as a hard mask for etching the second dielectric layer 22. And / or, anti-reflective layer 60 may include a bottom anti-reflective layer 61 and a third dielectric layer 62, with the third dielectric layer 62 located between the first mask layer 51 and the bottom anti-reflective layer 61, and the bottom anti-reflective layer 61 located above the third dielectric layer 62. The bottom anti-reflection layer 61 is used to eliminate the standing wave effect of the photoresist layer 70 and improve the exposure morphology of the photoresist layer 70. The third dielectric layer 62 is used to block the nitrogen atoms of the bottom anti-reflection layer 61 from migrating to the substrate 10, so as to improve the stability of the substrate 10.
[0067] In some embodiments, after step S13, the manufacturing method of this embodiment further includes: removing part of the intermetallic compound protective layer 40 and exposing the resistive layer 30.
[0068] Specifically, such as Figure 1 As shown, by removing part of the intermetallic compound protective layer 40, the resistor layer 30 beneath the intermetallic compound protective layer 40 can be partially exposed. This facilitates the installation of resistor guide plugs on the resistor layer 30 and its connection to external devices, thereby achieving the resistor function. The exposed position of the resistor layer 30 can be selected and adjusted according to lead requirements, and no specific limitation is made here.
[0069] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate comprising a device region and a resistor region; a dielectric layer covering the substrate; a resistor layer disposed in the dielectric layer and located at least in a region corresponding to the resistor region; an intermetallic compound protective layer disposed in the dielectric layer and covering the resistor layer.
2. The semiconductor device of claim 1, wherein: the intermetallic compound protective layer comprises an intermetallic compound protective layer containing aluminum.
3. The semiconductor device of claim 2, wherein: the resistor layer comprises a high-resistance material layer of titanium nitride and / or tantalum nitride; the intermetallic compound protective layer comprises a titanium-aluminum intermetallic compound protective layer.
4. The semiconductor device of claim 1, wherein The dielectric layer comprises: a first dielectric layer covering the substrate and further covering the resistor region and the device region, wherein the resistor layer and the intermetallic compound protective layer cover the first dielectric layer and are located in a region corresponding to the resistor region; a second dielectric layer covering the first dielectric layer and further covering the resistor layer and the intermetallic compound protective layer; wherein the first dielectric layer and the second dielectric layer are made of the same material.
5. The semiconductor device of claim 4, wherein: the thickness of the second dielectric layer is greater than 1200A.
6. The semiconductor device of claim 1, wherein: the length of the intermetallic compound protective layer is less than the length of the resistor layer, so as to expose the resistor layer; and the semiconductor device further comprises: a resistor guide plug formed in the dielectric layer and connected to the exposed part of the resistor layer.
7. The semiconductor device of claim 1, wherein: the device region comprises an NMOS device and / or a PMOS device, and the device region comprises a gate structure of the NMOS device and / or a gate structure of the PMOS device, and the gate structure comprises a high-K metal gate structure; the resistor region is provided with a dummy gate structure formed synchronously with the gate structure in the device region.
8. A method of manufacturing a semiconductor device, characterized by The semiconductor device comprises: providing a substrate comprising a device region and a resistor region; forming a dielectric layer covering the substrate; forming a resistor layer in the dielectric layer and an intermetallic compound protective layer covering the resistor layer, the resistor layer being located at least in a region corresponding to the resistor region.
9. The production method according to claim 8, wherein The dielectric layer comprises a first dielectric layer and a second dielectric layer; and the forming a dielectric layer covering the substrate comprises: forming the first dielectric layer covering the substrate; the forming a resistor layer in the dielectric layer and an intermetallic compound protective layer covering the resistor layer, the resistor layer being located at least in a region corresponding to the resistor region, comprises: forming the resistor layer covering the first dielectric layer, the resistor layer being located at least in a region corresponding to the resistor region; forming the intermetallic compound protective layer covering the resistor layer; forming the second dielectric layer covering the first dielectric layer, so as to further cover the resistor layer and the intermetallic compound protective layer.
10. The manufacturing method according to claim 9, wherein After the step of forming the second dielectric layer to cover the first dielectric layer to further cover the resistive layer and the intermetallic compound protective layer, the manufacturing method further comprises: removing a portion of the intermetallic compound protective layer and exposing the resistive layer.