Embedded re-wiring package structure and method of manufacturing the same

Abstract

The embodiment of the present application provides a kind of inner buried rewiring packaging structure and preparation method thereof, it is related to chip packaging technical field, the inner buried rewiring packaging structure includes first chip, first plastic encapsulation layer, stacked wiring combination layer, second chip and substrate wiring combination layer, the side edge of the first plastic encapsulation layer is provided with accommodating groove, the accommodating groove extends to the back surface edge of first chip, and substrate wiring layer can be filled to accommodating groove, improve the bonding force between substrate wiring layer and first chip, can slow down the delamination phenomenon between chip and substrate wiring layer.In addition, through the edge step structure of first chip, the thermal stress between plastic encapsulation material and first chip can be reduced, and the chip edge cracking phenomenon can be slowed down.The conductive column is arranged in accommodating groove area, the length of conductive column can be shortened, and then the signal transmission distance is reduced, and the electrical transmission efficiency is improved.And it can reduce the preparation difficulty of conductive column.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to an embedded redistribution packaging structure and its fabrication method. Background Technology

[0002] With the rapid development of the semiconductor industry, chiplet (chiplet packaging) technology has emerged in chip packaging, which packages small chips with different functions together. However, inconsistencies in the thermal expansion coefficients and Young's modulus of various materials within the package structure can easily lead to delamination between the chip and the dielectric layer, affecting the structural stability of the package structure. At the same time, thermal stress exists between chips, which can easily cause microcracks at the chip edges, affecting chip performance.

[0003] Furthermore, conventional chiplet technology typically involves multiple wiring layers, located on either side of the molding layer. In the transmission path of ultra-high frequency signals in the 100GHz-300GHz range, the longer the transmission distance between wiring layers, the greater the transmission loss. Consequently, the signal transmission characteristics are unstable, resulting in low transmission efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide an embedded redistribution packaging structure and its fabrication method, which can alleviate the delamination phenomenon between the chip and the dielectric layer and the chip edge microcrack phenomenon, while shortening the transmission path and improving the electrical transmission efficiency.

[0005] In a first aspect, the present invention provides an embedded redistribution package structure, comprising:

[0006] The first chip with multiple intervals set;

[0007] A first molding compound covers the sidewall and front side of the first chip, and the back side of the first chip is exposed on one side surface of the first molding compound. A receiving groove is also provided on one side surface of the first molding compound between adjacent first chips. The receiving groove extends to the back edge of the adjacent first chip so that the back edge of the first chip forms a stepped structure.

[0008] A stacked wiring assembly layer is disposed on the other side surface of the first molding layer and is electrically connected to the first chip;

[0009] The second chip is disposed on the side of the stacked wiring assembly layer away from the first chip and is electrically connected to the stacked wiring assembly layer;

[0010] A substrate wiring assembly layer is disposed on one side surface of the first molding layer and fills the receiving groove;

[0011] The first molding layer also has a conductive post through it. One end of the conductive post is connected to the stacked wiring assembly layer, and the other end extends to the receiving groove and is electrically connected to the substrate wiring assembly layer. The stacked wiring assembly layer and the substrate wiring assembly layer are electrically connected through the conductive post.

[0012] In an optional embodiment, the embedded redistribution package structure further includes a second molding layer disposed on the side of the stacked wiring assembly layer away from the first chip and covering the second chip.

[0013] In an optional embodiment, the conductive post is located at the center of the receiving groove.

[0014] In an optional embodiment, the substrate wiring assembly layer includes a substrate dielectric layer, a substrate wiring layer, a first dielectric layer, a first wiring layer, a first conductive layer, and a first protective layer. The substrate dielectric layer is disposed on one side surface of the first molding compound and fills the receiving groove. The substrate wiring layer is disposed in the substrate dielectric layer and is electrically connected to the conductive post. The first dielectric layer is disposed on the side surface of the substrate wiring layer away from the first molding compound. The first wiring layer is disposed in the first dielectric layer and is electrically connected to the substrate wiring layer. The first protective layer is disposed on the side surface of the first dielectric layer away from the first molding compound. The first conductive layer is disposed in the first protective layer and exposed outside the first protective layer.

[0015] In an optional embodiment, a solder ball is further provided on the side of the substrate wiring assembly layer away from the first molding layer, and the solder ball is electrically connected to the substrate wiring assembly layer.

[0016] In an optional embodiment, the first molding layer is further provided with heat dissipation pillars, which are spaced apart from the conductive pillars and extend to the receiving groove.

[0017] In an optional embodiment, there are multiple heat dissipation columns, which surround the conductive column.

[0018] In an optional embodiment, a metal layer is further provided in the receiving groove, one side surface of the metal layer is in contact with the conductive pillar and the heat dissipation pillar, and the substrate wiring assembly layer is in contact with the other side surface of the metal layer.

[0019] In an optional embodiment, the thickness of the metal layer is less than the depth of the receiving groove and partially fills the receiving groove so that the edge of the metal layer contacts the adjacent first chip.

[0020] In an optional embodiment, a discharge wiring layer is further provided in the receiving groove. The discharge wiring layer is electrically connected to both the conductive pillar and the heat dissipation pillar, and is spaced apart from the first chip. The discharge wiring layer is also electrically connected to the substrate wiring combination layer.

[0021] In an optional embodiment, an inductive wiring layer is further provided on the side of the discharge wiring layer away from the first molding layer, and the inductive wiring layer is in electrical contact with the discharge wiring layer.

[0022] In an optional embodiment, the stacked wiring combination layer includes a stacked dielectric layer, a stacked wiring layer, a second dielectric layer, a second wiring layer, a second conductive layer, and a second protective layer. The stacked dielectric layer is disposed on the first molding layer, the stacked wiring layer is disposed within the stacked dielectric layer, the second dielectric layer is disposed on the stacked dielectric layer, the second wiring layer is disposed within the second dielectric layer, the second protective layer is disposed on the second dielectric layer, the second conductive layer is disposed within the second protective layer and exposed outside the second protective layer, and the second chip is connected to the second conductive layer.

[0023] Secondly, the present invention provides a method for fabricating an embedded redistribution package structure, used to fabricate the embedded redistribution package structure as described in the foregoing embodiments, the method comprising:

[0024] Provide a vehicle;

[0025] Multiple first chips are spaced and mounted on the carrier;

[0026] A first molding compound is formed on the carrier, wherein the first molding compound covers the sidewalls and front side of the first chip;

[0027] A stacked wiring assembly layer is formed on the first molding layer, wherein the stacked wiring assembly layer is electrically connected to the first chip;

[0028] A second chip is mounted on the stacked wiring assembly layer, wherein the second chip is electrically connected to the stacked wiring assembly layer.

[0029] A second molding compound is formed on the stacked wiring assembly layer, wherein the second molding compound covers the second chip;

[0030] Remove the carrier to expose the back side of the first chip to the first molding compound;

[0031] A receiving groove is formed on the surface of the first molding compound and the back edge of the first chip, wherein the receiving groove is located on one side surface of the first molding compound between adjacent first chips and extends to the back edge of the adjacent first chip, so that the back edge of the first chip forms a stepped structure.

[0032] A through-type conductive post is formed in the first molding layer, wherein one end of the conductive post is connected to the stacked wiring assembly layer and the other end extends to the receiving groove;

[0033] A substrate wiring assembly layer is formed on the first molding layer, wherein the substrate wiring assembly layer fills the receiving groove and is electrically connected to the conductive post, and the stacked wiring assembly layer and the substrate wiring assembly layer are electrically connected through the conductive post.

[0034] The beneficial effects of the embodiments of the present invention include:

[0035] The embedded redistribution packaging structure and its fabrication method provided in this invention include a first molding compound layer covering the sidewalls and front side of a first chip. A receiving groove is formed on one side surface of the first molding compound layer between adjacent first chips, extending to the back edge of the adjacent first chip, thus creating a stepped structure on the back edge of the first chip. A stacked wiring assembly layer and a second chip are sequentially disposed on the other side surface of the first molding compound layer, completing chip stacking. A substrate wiring assembly layer is disposed on one side surface of the first molding compound layer and fills the receiving groove. A conductive post is also disposed through the first molding compound layer, with one end connected to the stacked wiring assembly layer and the other end extending to the receiving groove and connecting to the substrate wiring assembly layer. The stacked wiring assembly layer and the substrate wiring assembly layer are electrically connected through the conductive post.

[0036] Compared to existing technologies, this invention provides a receiving groove on one edge of the first molding compound, extending to the back edge of the first chip. The substrate wiring layer can fill the receiving groove, improving the adhesion between the substrate wiring layer and the first chip and mitigating delamination between the chip and the substrate wiring layer. Furthermore, the edge step structure of the first chip reduces the contact area between the first molding compound and the first chip, thereby reducing thermal stress between the molding compound and the first chip and mitigating microcracks at the chip edge. The conductive pillars located in the receiving groove area shorten the length of the conductive pillars, thereby reducing the signal transmission distance and improving electrical transmission efficiency. It also reduces the difficulty of fabricating the conductive pillars. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1This is a schematic diagram of an embedded redistribution package provided in the first embodiment of the present invention;

[0039] Figure 2 This is a partial top view of the embedded redistribution package provided in the first embodiment of the present invention;

[0040] Figures 3 to 12 This is a process flow diagram of the fabrication method of the embedded redistribution package provided in the first embodiment of the present invention;

[0041] Figure 13 This is a schematic diagram of an embedded rewiring package provided in the second embodiment of the present invention;

[0042] Figure 14 This is a partial top view of the embedded redistribution package provided in the second embodiment of the present invention;

[0043] Figure 15 This is a schematic diagram of an embedded redistribution package provided in the third embodiment of the present invention;

[0044] Figure 16 This is a partial top view of the embedded redistribution package provided in the third embodiment of the present invention.

[0045] Icons: 100 - Embedded redistribution package structure; 110 - First chip; 120 - First molding compound layer; 121 - Receiving recess; 122 - Metal layer; 123 - Discharge wiring layer; 124 - Inductor wiring layer; 125 - Discharge dielectric layer; 130 - Stacked wiring combination layer; 131 - Stacked dielectric layer; 132 - Stacked wiring layer; 133 - Second dielectric layer; 134 - Second wiring layer; 135 - Second conductive layer; 136 - Second protective layer; 140 - Second chip; 150 - Substrate wiring combination layer; 151 - Substrate dielectric layer; 152 - Substrate wiring layer; 153 - First dielectric layer; 154 - First wiring layer; 155 - First conductive layer; 156 - First protective layer; 160 - Conductive pillar; 161 - Heat sink pillar; 170 - Second molding compound layer; 180 - Solder ball; 200 - Carrier. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0047] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0048] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0049] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed during use, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0050] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0051] As disclosed in the background section, conventional chiplet (chiplet packaging) technology typically integrates multiple chips together, connected by different redistribution layers. These redistribution layers are electrically connected via conductive pillars formed by electroplating after opening. Because the redistribution layers and chips are usually planarly bonded, inconsistencies in the thermal expansion coefficients and Young's modulus of various materials within the package structure can easily lead to delamination between the chip and the dielectric layer, affecting the structural stability of the package. Simultaneously, thermal stress exists between chips, and in conventional technologies, the contact area between the chip's side and the molding compound is relatively large, resulting in significant thermal stress and a higher risk of microcracks at the chip edges, impacting chip performance.

[0052] Furthermore, in the transmission path of ultra-high frequency signals in the 100GHz-300GHz range, the longer the transmission distance between wiring layers, the greater the transmission loss, resulting in unstable signal transmission characteristics and low transmission efficiency.

[0053] Furthermore, existing chiplet packaging technology integrates multiple small chips into a single package, which increases the number of wiring layers and wiring density. Its fine-pitch wiring layers (e.g., 2µm linewidth) are susceptible to lightning surges. These surges occur in very short time, typically on the order of microseconds. When a surge occurs, the voltage and current amplitudes exceed twice the normal values. Because the input filter capacitor charges rapidly, the peak current is much greater than the steady-state input current, easily causing wiring layer breakdown and damaging the chip.

[0054] To address the aforementioned problems, embodiments of the present invention provide a novel embedded redistribution package structure and a method for fabricating such a structure. It should be noted that, unless otherwise specified, features in the embodiments of the present invention can be combined with each other.

[0055] First Embodiment

[0056] See Figure 1 and Figure 2 This invention provides an embedded redistribution packaging structure 100, which can mitigate the delamination phenomenon between the chip and the dielectric layer and the chip edge microcrack phenomenon, while shortening the transmission path and improving the electrical transmission efficiency.

[0057] The embedded redistribution package structure 100 provided in this embodiment of the invention includes a first chip 110, a first molding compound 120, a stacked wiring assembly layer 130, a second chip 140, and a substrate wiring assembly layer 150. Multiple first chips 110 are spaced apart. The first molding compound 120 covers the sidewalls and front side of the first chip 110, with the back side of the first chip 110 exposed on one side surface of the first molding compound 120. A receiving groove 121 is also provided on one side surface of the first molding compound 120 between adjacent first chips 110, extending to the back edge of the adjacent first chip 110 to form a stepped structure on the back edge of the first chip 110. The stacked wiring assembly layer 130 is disposed on the other side surface of the first molding compound 120 and is electrically connected to the first chip 110. The second chip 140 is disposed on the side of the stacked wiring assembly layer 130 away from the first chip 110 and is electrically connected to the stacked wiring assembly layer 130. A substrate wiring assembly layer 150 is disposed on one side surface of the first molding compound 120 and fills the receiving groove 121. A conductive post 160 is also disposed through the first molding compound 120. One end of the conductive post 160 is connected to the stacked wiring assembly layer 130, and the other end extends into the receiving groove 121 and is electrically connected to the substrate wiring assembly layer 150. The stacked wiring assembly layer 130 and the substrate wiring assembly layer 150 are electrically connected through the conductive post 160.

[0058] It should be noted that the receiving groove 121 can extend to the back edge of the adjacent first chip 110. This means that the groove area during the fabrication of the receiving groove 121 extends to the back edge region of the first chip 110, thereby enabling a stepped structure to be formed on the back edge of the first chip 110. It is worth noting that since the groove of the receiving groove 121 is located at the back edge of the first chip 110, damage to the surface transistors of the first chip 110 can be avoided. By providing a receiving groove 121 on one side edge of the first molding compound 120, extending to the back edge of the first chip 110, and allowing the substrate wiring layer 152 to fill the receiving groove 121, the bonding force between the substrate wiring layer 152 and the first chip 110 is improved, mitigating delamination between the chip and the substrate wiring layer 152. Furthermore, the stepped edge structure of the first chip 110 reduces the contact area between the first molding compound 120 and the first chip 110, thereby reducing thermal stress between the molding compound and the first chip 110 and mitigating microcracks at the chip edge. The conductive post 160 is positioned in the receiving groove 121 region, which can shorten the length of the conductive post 160, thereby reducing the signal transmission distance and improving the electrical transmission efficiency. It can also reduce the difficulty of fabricating the conductive post 160.

[0059] In this embodiment, the embedded redistribution package structure 100 further includes a second molding compound 170. The second molding compound 170 is disposed on the side of the stacked wiring assembly layer 130 away from the first chip 110 and covers the second chip 140. Specifically, there can be multiple second chips 140, which are spaced apart on the side of the stacked wiring assembly layer 130 away from the first chip 110. The second molding compound 170 can cover multiple second chips 140 simultaneously, providing protection. The second molding compound 170 and the first molding compound 120 are made of the same material, such as epoxy resin, silicon dioxide, or other polymer composite materials.

[0060] It is worth noting that in this embodiment, the first chip 110 has a first connection pad on its front side, which is electrically connected to the stacked wiring layer 132 through the first connection pad. Meanwhile, the second chip 140 can be a flip chip, which also has a second connection pad on its front side. The second connection pad can be electrically connected to the stacked wiring layer 132 after solder balls are formed on the second connection pad.

[0061] In this embodiment, the conductive post 160 is located at the center of the receiving groove 121. Specifically, the depth of the receiving groove 121 can be 1 / 10 to 1 / 2 of the thickness of the first chip 110, which can effectively shorten the length of the conductive post 160 and improve the transmission efficiency. The distance from the center of the receiving groove 121 to the multiple first chips 110 is the same, and the conductive post 160 is located at the center of the receiving groove 121. In actual fabrication, the receiving groove 121 can be formed first, then the center of the receiving groove 121 can be positioned, and the conductive post 160 can be formed by electroplating after slotting. It should be noted that the conductive post 160 is spaced apart from the multiple first chips 110, thereby avoiding interference between the conductive post 160 and the first chips 110. Of course, in other preferred embodiments of the present invention, the conductive post 160 can also be located at the edge of the receiving groove 121 or other areas, as long as the conductive post 160 is spaced apart from the sidewall of the first chip 110.

[0062] In this embodiment, the substrate wiring assembly layer 150 includes a substrate dielectric layer 151, a substrate wiring layer 152, a first dielectric layer 153, a first wiring layer 154, a first conductive layer 155, and a first protective layer 156. The substrate dielectric layer 151 is disposed on one side surface of the first molding layer 120 and fills the receiving groove 121. The substrate wiring layer 152 is disposed in the substrate dielectric layer 151 and is electrically connected to the conductive post 160. The first dielectric layer 153 is disposed on the side surface of the substrate wiring layer 152 away from the first molding layer 120. The first wiring layer 154 is disposed in the first dielectric layer 153 and is electrically connected to the substrate wiring layer 152. The first protective layer 156 is disposed on the side surface of the first dielectric layer 153 away from the first molding layer 120. The first conductive layer 155 is disposed in the first protective layer 156 and exposed outside the first protective layer 156.

[0063] Furthermore, the substrate dielectric layer 151, the first dielectric layer 153, and the first protective layer 156 are all dielectric materials, such as silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. Meanwhile, the substrate wiring layer 152, the first wiring layer 154, and the first conductive layer 155 are all conductive metal materials, such as copper. Since the substrate dielectric layer 151 fills the receiving groove 121 and contacts the stepped structure of the first chip 110, the contact area between the substrate dielectric layer 151 and the first chip 110 is increased, thereby improving the bonding force between them. In addition, since the stepped structure is covered by the substrate dielectric layer 151, the contact area between the first chip 110 and the first molding compound 120 is reduced, thereby reducing the thermal stress transfer between the molding compound and the first chip 110 and mitigating microcracks at the chip edges.

[0064] It should be noted that both the first dielectric layer 153 and the first wiring layer 154 can be multiple layers, thus forming a multi-layer wiring structure. In this embodiment, the example is that both the first dielectric layer 153 and the first wiring layer 154 are single layers.

[0065] In this embodiment, a solder ball 180 is also provided on the side of the substrate wiring assembly layer 150 away from the first molding compound layer 120, and the solder ball 180 is electrically connected to the substrate wiring assembly layer 150. Specifically, the solder ball 180 can be formed by attaching balls, and the solder ball 180 is electrically connected to the first conductive layer 155 of the substrate wiring layer 152.

[0066] In this embodiment, the stacked wiring combination layer 130 includes a stacked dielectric layer 131, a stacked wiring layer 132, a second dielectric layer 133, a second wiring layer 134, a second conductive layer 135, and a second protective layer 136. The stacked dielectric layer 131 is disposed on the first molding compound 120, the stacked wiring layer 132 is disposed in the stacked dielectric layer 131, the second dielectric layer 133 is disposed on the stacked dielectric layer 131, the second wiring layer 134 is disposed in the second dielectric layer 133, the second protective layer 136 is disposed on the second dielectric layer 133, the second conductive layer 135 is disposed in the second protective layer 136 and exposed on the second protective layer 136, and the second chip 140 is connected to the second conductive layer 135.

[0067] Furthermore, the stacked dielectric layer 131, the second dielectric layer 133, and the second protective layer 136 are all dielectric materials, such as silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. Meanwhile, the stacked wiring layer 132, the second wiring layer 134, and the second conductive layer 135 are all conductive metal materials, such as copper. The second conductive layer 135 can form a pad structure on the surface of the second protective layer 136, thereby facilitating the direct soldering and fixing of the second chip 140.

[0068] It should be noted that the second dielectric layer 133 and the second wiring layer 134 can both be multiple layers, thus forming a multi-layer wiring structure. In this embodiment, the second dielectric layer 133 and the second wiring layer 134 are both single layers for illustration.

[0069] This invention also provides a method for fabricating an embedded redistribution package structure 100, used to fabricate the embedded redistribution package structure 100 as described above. The method includes the following steps:

[0070] S1: Provide one vehicle (200).

[0071] See also Figure 3Specifically, the carrier 200 can be made of materials such as glass, silicon dioxide, or metal. A liquid adhesive layer can be applied to the surface of the carrier 200 using a spin coater, and then soft-set into a film using a hot plate. The adhesive layer here is a thermoplastic adhesive layer and can be separated by irradiation with UV light (ultraviolet light), including high molecular composite materials such as epoxy resin, polyimide, and benzocyclobutene.

[0072] S2: Multiple first chips 110 are mounted at intervals on the carrier 200.

[0073] See also Figure 4 Specifically, multiple first chips 110 are mounted on the back side of the carrier 200 with the chip pads facing upwards, and gaps are left between the multiple first chips 110.

[0074] S3: Form a first plastic sealant layer 120 on the vehicle 200.

[0075] See also Figure 5 The first molding compound 120 covers the sidewalls and front side of the first chip 110. Specifically, the first molding compound 120 is formed by printing a liquid molding compound on the carrier 200 using a molding process and then baking it. The molding compound material can be composed of polymer composite materials such as micro-epoxy resin and silicon dioxide. After molding, the first molding compound 120 can be polished using diamond to polish the surface of the molding compound, thereby exposing the pads on the front side of the first chip 110.

[0076] S4: A stacked wiring assembly layer 130 is formed on the first molding layer 120.

[0077] See also Figure 6The stacked wiring layer 130 is electrically connected to the first chip 110. Specifically, a dielectric material can be first coated onto the first molding compound 120 using a spin coating process to form a stacked dielectric layer 131. This dielectric material can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. Then, a photomask is placed over the stacked dielectric layer 131, and an exposure and development process is used to form patterned layer openings. Next, a metal material is electroplated onto the patterned layer openings using an electroplating process to form a stacked wiring layer 132. This stacked wiring layer 132 can be a copper layer, and it can connect to the pads on the first chip 110, thereby achieving an electrical connection between the stacked wiring layer 130 and the first chip 110. Then, another dielectric material is coated onto the stacked dielectric layer 131 using a spin coating process to form a second dielectric layer 133. Finally, a metal material is electroplated after the openings are developed using photolithography to form a second wiring layer 134. Finally, a layer of dielectric material is coated onto the second dielectric layer 133 again using a spin coating process to form the second protective layer 136. Then, after opening, electroplating is performed to form the second conductive layer 135, wherein the second conductive layer 135 can form a pad structure.

[0078] S5: Attach the second chip 140 on the stacked wiring combination layer 130.

[0079] See also Figure 7 The second chip 140 is electrically connected to the stacked wiring assembly layer 130. Specifically, multiple second chips 140 are mounted on the stacked wiring assembly layer 130 using a flip-chip process and then fixed by reflow soldering. The bottom of the second chip 140 can be soldered to the second conductive layer 135, thereby achieving the electrical connection between the second chip 140 and the stacked wiring assembly layer 130.

[0080] S6: A second molding layer 170 is formed on the stacked wiring combination layer 130.

[0081] See also Figure 8 The second molding compound 170 covers the second chip 140. Specifically, the second molding compound 170 is formed on the second protective layer 136 by molding again using a molding process. The material of the second molding compound 170 can be the same as that of the first molding compound 120, thus achieving the protection of the second chip 140.

[0082] S7: Remove the carrier 200 so that the back side of the first chip 110 is exposed to the first molding compound 120.

[0083] See also Figure 9Specifically, UV light is irradiated on the back of the carrier 200, causing the adhesive to debond from the carrier 200, thereby removing the carrier 200. After removing the carrier 200, the packaging structure is flipped so that the back of the first chip 110 can be exposed to the first molding layer 120.

[0084] S8: A receiving groove 121 is formed on the surface of the first molding layer 120 and the back edge of the first chip 110.

[0085] See also Figure 10 The receiving groove 121 is located on one side surface of the first molding compound 120 between adjacent first chips 110 and extends to the back edge of the adjacent first chips 110, so that the back edge of the first chip 110 forms a stepped structure. Specifically, the receiving groove 121 can be formed by slotting the back edge sidewall of the first chip 110 and the first molding compound 120 using a cutting process. The cutting can be achieved by mechanical cutting with a grinding wheel mesh of 2000-4000, a cutting speed of 250um / min, and a linear velocity parameter of 5m / s-20m / s. The formed receiving groove 121 can precisely form a stepped structure at the edge of each first chip 110.

[0086] S9: A conductive post 160 is formed through the first molding layer 120.

[0087] See also Figure 11 One end of the conductive post 160 is connected to the stacked wiring assembly layer 130, and the other end extends to the receiving groove 121. Specifically, the laser drilling process can be used to create an opening by slotting the first molding layer 120 at the center of the receiving groove 121. Since the receiving groove 121 is first formed by a cutting process, the precision of the laser drilling is improved, and the depth of the laser drilling is reduced, thereby reducing the aspect ratio of the laser drilling and simplifying the slotting process. After the opening is formed, the conductive post 160 can be formed inside the opening by an electroplating process. One end of the conductive post 160 is connected to the stacked wiring layer 132 of the stacked wiring assembly layer 130, and the other end is exposed on the bottom wall of the receiving groove 121. There can be multiple conductive posts 160, which are evenly distributed.

[0088] S10: A substrate wiring assembly layer 150 is formed on the first molding layer 120.

[0089] See also Figure 12 The substrate wiring assembly layer 150 fills the receiving groove 121 and is electrically connected to the conductive post 160, and the stacked wiring assembly layer 130 and the substrate wiring assembly layer 150 are electrically connected through the conductive post 160.

[0090] Specifically, a dielectric material can first be coated onto the surface of the first molding layer 120 and the back side of the first chip 110 using a spin coating process to form a substrate dielectric layer 151. This substrate dielectric layer 151 fills the receiving groove 121 and remains planarized. The dielectric material can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. Then, a photomask is placed on the substrate dielectric layer 151, and an exposure and development process is used to form patterned layer openings. Then, a metal material is electroplated onto the patterned layer openings to form a substrate wiring layer 152. This substrate wiring layer 152 can be a copper layer, and the substrate wiring layer 152 can be connected to the conductive pillars 160, thereby realizing direct electrical connection between the substrate wiring assembly layer 150 and the conductive pillars 160. Then, a dielectric material is coated onto the stacked dielectric layer 131 again using a spin coating process to form a first dielectric layer 153. Then, a metal material is electroplated again after photolithography and development to form a first wiring layer 154. Finally, a layer of dielectric material is coated on the first dielectric layer 153 again using a spin coating process to form the first protective layer 156. Then, after opening, electroplating is performed to form the first conductive layer 155, wherein the first conductive layer 155 can form a pad structure.

[0091] Finally, solder balls 180 can be formed on the first conductive layer 155 by stencil printing or electroplating. The solder balls 180 can be SnAg or SnAgCu, etc., and then a cutting process is performed to form the final product.

[0092] The embedded redistribution packaging structure 100 provided in this embodiment of the invention includes a first molding compound 120 covering the sidewalls and front side of a first chip 110. A receiving groove 121 is formed on one side surface of the first molding compound 120 between adjacent first chips 110, extending to the back edge of the adjacent first chip 110, thereby forming a stepped structure on the back edge of the first chip 110. A stacked wiring assembly layer 130 and a second chip 140 are sequentially disposed on the other side surface of the first molding compound 120, completing chip stacking. A substrate wiring assembly layer 150 is disposed on one side surface of the first molding compound 120 and fills the receiving groove 121. A conductive post 160 is also disposed through the first molding compound 120, with one end connected to the stacked wiring assembly layer 130 and the other end extending to the receiving groove 121 and connecting to the substrate wiring assembly layer 150. The stacked wiring assembly layer 130 and the substrate wiring assembly layer 150 are electrically connected through the conductive post 160. Compared to existing technologies, this embodiment of the invention provides a receiving groove 121 on one side edge of the first molding compound 120. This receiving groove 121 extends to the back edge of the first chip 110, and the substrate wiring layer 152 can fill the receiving groove 121, improving the bonding force between the substrate wiring layer 152 and the first chip 110 and mitigating delamination between the chip and the substrate wiring layer 152. Furthermore, the edge step structure of the first chip 110 reduces the contact area between the first molding compound 120 and the first chip 110, thereby reducing thermal stress between the molding compound and the first chip 110 and mitigating microcracks at the chip edge. The conductive post 160 is disposed in the receiving groove 121 region, which shortens the length of the conductive post 160, thereby reducing the signal transmission distance and improving electrical transmission efficiency. It also reduces the fabrication difficulty of the conductive post 160.

[0093] Second Embodiment

[0094] See Figure 13 and Figure 14 This invention provides an embedded redistribution packaging structure 100, whose basic structure, principle, and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0095] In this embodiment, the first molding layer 120 is further provided with heat dissipation pillars 161, which are spaced apart from the conductive pillars 160 and extend into the receiving groove 121. Specifically, there are multiple heat dissipation pillars 161, which surround the conductive pillars 160. The heat dissipation pillars 161 can also be metal pillars, with the same material and diameter as the conductive pillars 160. For example, both the heat dissipation pillars 161 and the conductive pillars 160 can be copper pillars. There is no electrical connection between the heat dissipation pillars 161 and the stacked wiring assembly layer 130, and the heat dissipation pillars 161 are lower in height, resulting in a smaller gap. This improves the bonding force between the first molding layer 120 and the heat dissipation pillars 161, enhancing the stability of the packaging structure. Furthermore, the heat dissipation pillars 161 better facilitate heat dissipation and prevent short circuits between the heat dissipation pillars 161 and the stacked wiring assembly layer 130. By setting up heat dissipation pillars 161, the heat dissipation effect can be improved. At the same time, the heat dissipation pillars 161 surround the conductive pillars 160 and can serve as a support structure to improve the stability of the overall packaging structure.

[0096] It should be noted that the heat dissipation pillars 161 are also spaced apart from the first chip 110 to prevent interference. The multiple heat dissipation pillars 161 can be arranged in a rectangular pattern, with the conductive pillar 160 located at the center of the rectangle. The arrangement of multiple heat dissipation pillars 161 can further improve the heat dissipation and support effects.

[0097] Furthermore, a metal layer 122 is also disposed in the receiving groove 121. One side surface of the metal layer 122 contacts the conductive pillar 160 and the heat dissipation pillar 161, and the substrate wiring assembly layer 150 contacts the other side surface of the metal layer 122. Specifically, the metal layer 122 can be a copper layer, which can further improve the heat dissipation effect. In addition, the metal layer 122 is in electrical contact with the substrate wiring layer 152, so that the metal layer 122 can also realize the electrical connection between the conductive pillar 160 and the substrate wiring layer 152. Moreover, the metal layer 122 can also play a discharge role, enabling rapid discharge, thereby effectively mitigating lightning surge phenomena and ensuring chip performance.

[0098] In this embodiment, the thickness of the metal layer 122 is less than the depth of the receiving groove 121, and it partially fills the receiving groove 121 so that the edge of the metal layer 122 contacts the adjacent first chip 110. Specifically, the metal layer 122 does not completely fill the receiving groove 121, allowing the substrate dielectric layer 151 to fill the remaining space of the receiving groove 121. Furthermore, the metal layer 122 can cover the bottom wall of the receiving groove 121 and contact the stepped structure of the first chip 110 to achieve heat conduction, quickly transferring the heat generated by the first chip 110 to the heat dissipation pillar 161, thereby improving the heat dissipation effect.

[0099] The embedded redistribution packaging structure 100 provided in this embodiment of the invention can improve structural stability by additionally designing heat dissipation pillars 161, and the design of heat dissipation pillars 161 and metal layer 122 can improve heat dissipation performance.

[0100] Third Embodiment

[0101] See Figure 15 and Figure 16 This invention provides an embedded redistribution packaging structure 100, whose basic structure, principle, and technical effects are the same as those of the first or second embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first or second embodiment.

[0102] In this embodiment, a heat sink 161 is further provided in the first molding layer 120. The heat sink 161 is spaced apart from the conductive pillar 160 and penetrates the first molding layer 120 so that the heat sink 161 extends to the receiving groove 121. A discharge wiring layer 123 is further provided in the receiving groove 121. The discharge wiring layer 123 is electrically connected to both the conductive pillar 160 and the heat sink 161, and is spaced apart from the first chip 110. The discharge wiring layer 123 is also electrically connected to the substrate wiring combination layer 150.

[0103] Specifically, the discharge wiring layer 123 can be a copper layer, and it is disposed within a discharge dielectric layer 125, the material of which is the same as that of the substrate dielectric layer 151. The discharge wiring layer 123 can form a discharge coil through wiring, which is used in filter circuits with common-mode inductors designed on the substrate wiring combination layer 150. In traditional filter circuits, the wiring layer is susceptible to lightning surges, which occur in very short time, approximately on the microsecond scale. When a surge occurs, the voltage and current amplitudes exceed twice the normal values. Because the input filter capacitor charges rapidly, the peak current is much greater than the steady-state input current, easily leading to chip damage. Here, the discharge wiring layer 123 can be used as a discharge coil for rapid discharge, effectively mitigating lightning surges and ensuring chip performance.

[0104] In this embodiment, the heat sink 161 can also be electrically connected to the stacked wiring assembly layer 130 to conduct electricity.

[0105] In this embodiment of the invention, the discharge wiring layer 123 serves as a discharge coil, which can also solve the problem of electrostatic discharge within the dielectric layer or the first molding layer 120 in the package structure. This prevents the first chip 110 from being damaged by electrostatic discharge, leading to failure. Furthermore, it prevents current from forming an inductive effect between multiple wiring layers, thus avoiding parasitic inductance that could cause leakage, short circuits, overheating, and other problems between wiring layers.

[0106] In this embodiment, an inductor wiring layer 124 is also provided on the side of the discharge wiring layer 123 away from the first molding layer 120, and the inductor wiring layer 124 is in electrical contact with the discharge wiring layer 123. Specifically, the inductor wiring layer 124 can be located within the substrate dielectric layer 151 and fabricated together with the substrate wiring layer 152, and can serve as an inductor coil to perform inductance and achieve filtering.

[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An embedded redistribution packaging structure, characterized in that, include: The first chip with multiple intervals set; A first molding compound covers the sidewall and front side of the first chip, and the back side of the first chip is exposed on one side surface of the first molding compound. A receiving groove is also provided on one side surface of the first molding compound between adjacent first chips. The receiving groove extends to the back edge of the adjacent first chip so that the back edge of the first chip forms a stepped structure. A stacked wiring assembly layer is disposed on the other side surface of the first molding layer and is electrically connected to the first chip; The second chip is disposed on the side of the stacked wiring assembly layer away from the first chip and is electrically connected to the stacked wiring assembly layer; A substrate wiring assembly layer is disposed on one side surface of the first molding layer and fills the receiving groove; The first molding layer also has a conductive post through it. One end of the conductive post is connected to the stacked wiring assembly layer, and the other end extends to the receiving groove and is electrically connected to the substrate wiring assembly layer. The stacked wiring assembly layer and the substrate wiring assembly layer are electrically connected through the conductive post. The conductive post is located at the center of the receiving groove and is spaced apart from the plurality of first chips. The embedded redistribution packaging structure is fabricated using the following method: Provide a vehicle; Multiple first chips are spaced and mounted on the carrier; A first plastic sealant layer is formed on the vehicle; A stacked wiring assembly layer is formed on the first molding layer; A second chip is mounted on the stacked wiring assembly layer; A second molding layer is formed on the stacked wiring assembly layer; Remove the carrier to expose the back side of the first chip to the first molding compound; A receiving groove is formed on the surface of the first molding layer and at the back edge of the first chip; Position the center of the receiving groove, and after slotting in the first molding layer, electroplating is performed to form a through conductive pillar; A substrate wiring assembly layer is formed on the first molding layer.

2. The embedded redistribution packaging structure according to claim 1, characterized in that, The embedded rewiring package structure further includes a second molding layer, which is disposed on the side of the stacked wiring assembly layer away from the first chip and covers the second chip.

3. The embedded redistribution packaging structure according to claim 1, characterized in that, The substrate wiring assembly layer includes a substrate dielectric layer, a substrate wiring layer, a first dielectric layer, a first wiring layer, a first conductive layer, and a first protective layer. The substrate dielectric layer is disposed on one side surface of the first molding layer and fills the receiving groove. The substrate wiring layer is disposed in the substrate dielectric layer and is electrically connected to the conductive pillar. The first dielectric layer is disposed on the side surface of the substrate wiring layer away from the first molding layer. The first wiring layer is disposed in the first dielectric layer and is electrically connected to the substrate wiring layer. The first protective layer is disposed on the side surface of the first dielectric layer away from the first molding layer. The first conductive layer is disposed in the first protective layer and exposed outside the first protective layer.

4. The embedded redistribution packaging structure according to claim 1 or 3, characterized in that, The substrate wiring assembly layer is further provided with solder balls on the side away from the first molding layer, and the solder balls are electrically connected to the substrate wiring assembly layer.

5. The embedded redistribution packaging structure according to claim 1, characterized in that, The first molding layer is also provided with heat dissipation pillars, which are spaced apart from the conductive pillars and extend to the receiving groove.

6. The embedded redistribution packaging structure according to claim 5, characterized in that, There are multiple heat dissipation columns, which are arranged around the conductive column.

7. The embedded redistribution packaging structure according to claim 5, characterized in that, A metal layer is also provided in the receiving groove. One side surface of the metal layer is in contact with the conductive pillar and the heat dissipation pillar, and the substrate wiring assembly layer is in contact with the other side surface of the metal layer.

8. The embedded redistribution packaging structure according to claim 7, characterized in that, The thickness of the metal layer is less than the depth of the receiving groove, and it partially fills the receiving groove so that the edge of the metal layer contacts the adjacent first chip.

9. The embedded redistribution packaging structure according to claim 5, characterized in that, The receiving groove is further provided with a discharge wiring layer, which is electrically connected to both the conductive pillar and the heat dissipation pillar, and is spaced apart from the first chip. The discharge wiring layer is also electrically connected to the substrate wiring combination layer.

10. The embedded redistribution packaging structure according to claim 9, characterized in that, An inductive wiring layer is also provided on the side of the discharge wiring layer away from the first molding layer, and the inductive wiring layer is in electrical contact with the discharge wiring layer.

11. The embedded redistribution packaging structure according to claim 1, characterized in that, The stacked wiring combination layer includes a stacked dielectric layer, a stacked wiring layer, a second dielectric layer, a second wiring layer, a second conductive layer, and a second protective layer. The stacked dielectric layer is disposed on the first molding layer, the stacked wiring layer is disposed within the stacked dielectric layer, the second dielectric layer is disposed on the stacked dielectric layer, the second wiring layer is disposed within the second dielectric layer, the second protective layer is disposed on the second dielectric layer, the second conductive layer is disposed within the second protective layer and exposed outside the second protective layer, and the second chip is connected to the second conductive layer.

12. A method for fabricating an embedded redistribution package structure, used to fabricate the embedded redistribution package structure as described in claim 1, characterized in that, The method includes: Provide a vehicle; Multiple first chips are spaced and mounted on the carrier; A first molding compound is formed on the carrier, wherein the first molding compound covers the sidewalls and front side of the first chip; A stacked wiring assembly layer is formed on the first molding layer, wherein the stacked wiring assembly layer is electrically connected to the first chip; A second chip is mounted on the stacked wiring assembly layer, wherein the second chip is electrically connected to the stacked wiring assembly layer. A second molding compound is formed on the stacked wiring assembly layer, wherein the second molding compound covers the second chip; Remove the carrier to expose the back side of the first chip to the first molding compound; A receiving groove is formed on the surface of the first molding compound and the back edge of the first chip, wherein the receiving groove is located on one side surface of the first molding compound between adjacent first chips and extends to the back edge of the adjacent first chip, so that the back edge of the first chip forms a stepped structure. A through-type conductive post is formed in the first molding layer, wherein one end of the conductive post is connected to the stacked wiring assembly layer and the other end extends to the receiving groove; A substrate wiring assembly layer is formed on the first molding layer, wherein the substrate wiring assembly layer fills the receiving groove and is electrically connected to the conductive post, and the stacked wiring assembly layer and the substrate wiring assembly layer are electrically connected through the conductive post.

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