In-situ delay measurement on integrated circuits using real-time data and pulse width modulation

Abstract

The integrated circuit includes a delay monitor that monitors a delay of the data signal from the digital circuitry by generating a pulse having a width determined by the delay. In some embodiments, a delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal for clocking the data signal. The pulse generator generates a pulse according to the received data signal and the clock signal, wherein a width of the pulse is determined by a delay of the data signal relative to the clock signal. The event generator generates events that are temporally distributed with respect to the clock signal. As a result, the delay may be estimated based on an overlap between the event and the pulse.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to delay measurement for electronic circuits. In particular, the present disclosure relates to in-situ monitoring of delays in electronic circuits. BACKGROUND

[0002] As technology nodes shrink and the complexity and gate count of devices increase, it becomes increasingly important to monitor the performance of integrated circuits over their lifetime. An increasing number of critical applications, such as automotive electronics and health monitoring devices, also make failure avoidance and prediction an increasingly important requirement for these devices. SUMMARY

[0003] In some aspects, an integrated circuit includes digital circuitry. The integrated circuit also includes a delay monitor that monitors a delay of a data signal from the digital circuitry by generating a pulse having a width determined by the delay.

[0004] For example, the delay monitor can be implemented as digital circuitry that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal for clocking the data signal. The pulse generator generates a pulse from the received data signal and clock signal, where the width of the pulse is determined by a delay of the data signal relative to the clock signal. The event generator generates events that are distributed in time relative to the clock signal. As a result, the delay can be estimated based on an overlap between the events and the pulse.

[0005] In alternative embodiments, the monitor can monitor other properties of the digital circuitry by generating a pulse having a width that is a function of the property being monitored.

[0006] Other aspects include components, devices, systems, improvements, methods, processes, applications, computer readable media, and other technologies related to any of the above. BRIEF DESCRIPTION OF DRAWINGS

[0007] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which like reference numerals refer to like elements throughout. The drawings provided are for purposes of illustration and description only. Further, the drawings are not necessarily to scale, emboiy, with the scope of the disclosure.

[0008] Figure 1 is a block diagram of an integrated circuit with a built-in delay monitoring system according to some embodiments of the present disclosure.

[0009] Figure 2Ais a block diagram of a clock-data delay monitor (CDM) that monitors data access latency for reading data from a memory, in accordance with some embodiments of the present disclosure.

[0010] Figure 2B is a timing diagram illustrating operation of the CDM of Figure 2A

[0011] Figure 3A is a block diagram of a CDM that monitors propagation delay of a signal propagating along a logic path, in accordance with some embodiments of the present disclosure.

[0012] Figure 3B is a timing diagram illustrating operation of the CDM of Figure 3A

[0013] Figure 4 is a timing diagram illustrating statistical sampling of pulse width, in accordance with some embodiments of the present disclosure.

[0014] Figure 5A is a block diagram of a CDM, in accordance with some embodiments of the present disclosure.

[0015] Figure 5B is a timing diagram illustrating operation of the CDM of Figure 5A

[0016] Figure 6 is a flow diagram for monitoring delay in an integrated circuit, in accordance with some embodiments of the present disclosure.

[0017] Figure 7 depicts a flow diagram of various processes used during design and fabrication of an integrated circuit, in accordance with some embodiments of the present disclosure.

[0018] Figure 8 depicts a diagram of an example computer system that can operate embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] Aspects of the present disclosure relate to in-situ delay measurement on an integrated circuit using real-time data and pulse width modulation. Monitoring integrated circuits over their life cycle is becoming increasingly important. Delay of signals is an important parameter that needs to be monitored. One type of delay is memory access delay, i.e., delay in reading data from embedded memories in an integrated circuit. Another type of delay is propagation delay, i.e., delay in propagation of a signal through a logic path in an integrated circuit.

[0020] ​​​These delays and other delays can change over time and due to changes in conditions. Changing temperature and voltage can affect the delay times. Transistor aging can also affect the delay times. Longer delays can cause device errors. Monitoring the delays across different conditions and over time can be used to predict future failures before they occur as part of overall lifecycle management of the device.

[0021] However, monitoring the delays presents challenges. As devices operate at higher speeds using faster clocks, the delays will decrease, meaning that the delay monitors must be more sensitive. For current devices, it is useful for the delay monitors to be able to estimate the delays with accuracy on the order of picoseconds (ps). Another challenge is that as devices become larger and more complex, more delay monitors can be added. As a result, the delay monitors themselves should not take up too much area. It is also beneficial to be able to estimate the delays for real-time data produced by the circuit during its expected operation. This is sometimes referred to as task mode, as opposed to test mode or calibration mode. Delay monitoring during task mode is efficient because the device is still operating for its intended purpose while being monitored. It can also be more accurate because the conditions during the monitoring are the actual task mode conditions, as opposed to conditions for other modes, which can be different.

[0022] In some aspects, a delay monitor can monitor a signal delay using pulse width modulation. The delay monitor receives a data signal and a clock signal used to clock the data signal. It generates a pulse based on the two signals, where the width of the pulse is determined by the delay of the data signal relative to the clock signal. The data signal can be real-time data produced during task mode of an integrated circuit. The pulse is generated as long as the real-time data changes value. The width of the pulse can be measured by asynchronously sampling the pulse. Events distributed in time relative to the clock signal are generated. These events are used to sample the pulse. The proportion of events that overlap with the pulse can be used to estimate the width of the pulse, and then the delay.

[0023] Technical advantages of the present disclosure include, but are not limited to, the following technical advantages. Statistical sampling of the pulse width can produce more accurate estimates compared to, for example, methods using delay lines. The above-described delay monitors can also be implemented using digital circuits built from standard cells. As a result, they can be included in integrated circuit designs at the register transfer level (RTL) level without the need for simulation or custom design. The ability to use task mode data is also beneficial because it presents a more accurate picture of the device operation and does not interrupt the operation of the device.

[0024] Figure 1is a block diagram of an integrated circuit with a built-in delay monitoring system according to some embodiments of the present disclosure. In this particular example, the integrated circuit 100 is divided into four sectors, each with four processor cores 110 and associated logic and embedded memory 112. The integrated circuit also includes a central processing unit (CPU) 114, on-chip memory 116, and input / output (I / O) functions 118 such as serializer / deserializer (Serdes), Peripheral Component Interconnect Express (PCIe), High-Definition Multimedia Interface (HDMI), and Double Data Rate (DDR).

[0025] The delay monitoring system includes instances of clock-data delay monitor (CDM) circuits (shown as black squares, some of which are labeled 130) and a CDM controller 150. The CDMs 130 are distributed throughout the integrated circuit to monitor delays across different points of the integrated circuit and for different signals. In Figure 1 In some embodiments, for convenience, the CDMs 130 are not shown in every block.

[0026] The CDMs 130 are integrated with the signal paths being monitored. As a result, the integrated circuit can be monitored in real-time during normal operation. Normal operation is sometimes referred to as task mode. That is, the CDMs do not require a special monitor mode, and the task mode does not need to be interrupted for delay measurements.

[0027] The CDM controller 150 is also integrated on-chip. In Figure 1 it is shown as one block, but it can be implemented in a distributed manner. The CDM controller 150 communicates with the CDMs 130. The controller 150 can send control signals 140 to the CDMs 130. Examples of control signals include signals for the CDMs to initiate and terminate measurements. Another example is a mode selection signal to place the CDMs in different modes.

[0028] The CDM controller 150 also receives data from the CDMs. This includes CDM signals 160, which are the outputs produced by the CDMs from their delay measurements. The CDM signals 160 can include estimates of the delays, or they can include preambles (such as counts cl and c2 below) that are then processed to estimate the delays. The controller 150 analyzes the CDM signals 160, thus providing a delay monitoring capability across the integrated circuit. For example, it can combine data from individual CDMs to provide a chip-level delay model.

[0029] Because both the CDM 130 and the CDM controller 150 are on-chip, the delay monitoring system can provide real-time in-situ monitoring of delays across an integrated circuit. Data produced by the monitoring system can be consumed on-chip. For example, the estimated delay can be used as feedback to change the operation of other circuitry on the chip.

[0030] The CDM data produced by the delay monitoring system can also be used to monitor changes in delay over the life of a chip. Current delay data can be compared to historical data to identify trends and predict future problems. Delay data can also be analyzed off-chip. More complex analysis can require computational resources that are not available on-chip, and storing delay data captured over long periods of time can require more space than is available on-chip. Analysis can also combine delay data with other data that is not available on-chip, such as external measurements of temperature or power consumption. As another example, delay data from multiple chips can be analyzed together to provide a view of a circuit board, rack-mounted device, or other environment that is larger than just a single chip.

[0031] Figure 2A is a block diagram of a CDM that monitors a data access delay for reading data from a memory according to some embodiments of the present disclosure. Figure 2B is a timing diagram illustrating the operation of the CDM of Figure 2A . Figure 2A An embedded memory 210 is shown that stores data. A circuitry 208 controls the memory 210 to read data from the memory. The data, represented as Q, is read from the memory port into a timing circuit 213, such as a flip-flop. The read operation is clocked by a clock signal 215.

[0032] A CDM 230 monitors the delay of reading the data Q from the memory 210. This delay is the data access delay T CQ , where the subscripts C and Q represent the clock CLK and the data Q. Figure 2B A clock signal CLK is shown that has a period T CLK . The data read is triggered by a leading edge 216 of the clock, but the data Q is not available until some later time 226. The delay between the trigger edge 216 and the availability 226 of the data Q is the data access delay T CQ .

[0033] The CDM 230 operates to generate a pulse 235 that has a period T CQwidth of the function of the data access delay T PW is the data access delay T CQ is a measure of the width of the function of the data access delay T T CQ = T CLK - T PW (1A)

[0034] The signals 260 output from the CDM indicate the pulse width. They can be estimates of the pulse width. Alternatively, they can be data from which the pulse width or the data access delay can be calculated. Figure 4 In the example of FIG. 3, the pulse width is proportional to the ratio of two counts (c1 / c2). The CDM 330 can output two integers c1 and c2, and a CDM controller or other processor can estimate the delay from these counts.

[0035] Figure 3A is a block diagram of a CDM that monitors the propagation delay of a signal as it propagates along a logic path, according to some embodiments of the present disclosure. Figure 3B is a timing diagram illustrating the operation of the CDM of Figure 3A In this example, the logic path 310 begins at a sequential circuit 311, propagates through a combinational circuit device 312, and terminates at a sequential circuit 313. Here, the sequential circuits 311, 313 are flip-flops, and the start flip-flop 311 and the end flip-flop 313 are clocked by a clock signal 315.

[0036] The CDM 330 monitors the propagation delay T ab . Figure 3B A clock signal CLK is shown with a period T CLK . The signal propagation is triggered by a leading edge 316 of the clock, but the DATA is not available until some later time 326. The delay between the triggering edge 316 and the availability 326 of the DATA is the propagation delay T ab .

[0037] The operation of the CDM 330 is similar to the CDM 230 in FIG. 2. The CDM 330 generates a pulse 335, which has a leading edge 336 and a trailing edge 337. The leading edge 336 of the pulse 335 is triggered by the leading edge 316 of the clock, and the trailing edge 337 of the pulse 335 is triggered by the availability 326 of the DATA. The pulse width T abof the function. In this example, the pulse 335 is generated at the time of the DATA transition. The CDM 330 receives both the clock signal CLK and the data signal DATA. The leading edge 336 of the pulse 335 is triggered by the transition of DATA, which occurs at time 326. The trailing edge 337 of the pulse 335 is triggered by the next leading edge 317 of the clock CLK, assuming the propagation delay is less than one clock cycle. The pulse width T PW is then a measure of the propagation delay T ab , where T ab = T CLK - T PW (1B) This is the same as equation 1A, except that the data access delay T ab is replaced by the propagation delay T CQ . If the signal propagation takes more than one clock cycle, T CLK in equation 1B can be increased by the appropriate number of clock cycles. The signal 360 output from the CDM indicates the pulse width, and can take any of the forms described above for the CDM signal 260.

[0038] Figure 4 is a timing diagram illustrating statistical sampling of pulse widths in accordance with some embodiments of the present disclosure. Figure 4 Four columns are shown, labeled Toggle 1-4. Each column is a different instance when DATA transitions its value. The leading edge of the clock cycle shown triggers the change in the DATA value. Because DATA is transitioning its value, a corresponding pulse 435 is also generated. As described previously, the leading edge of the pulse 435 is triggered by the change in the DATA value, and the trailing edge of the pulse is triggered by the leading edge of the next clock cycle. Figure 4 Other clock cycles that are not data triggered (e.g., no data is retrieved from memory during that clock cycle) or that do not result in a change in the DATA value (e.g., the retrieved data value is the same as the previously retrieved value) are not shown in FIG. 4.

[0039] The pulse 435 has a width T PW , where the width T PW is some fraction of the clock period T CLK . This width is a measure of the delay, and for the time scales considered here, both the delay and the pulse width T PW can be considered constant. For illustrative purposes, the delay for a transition of DATA from a logic 0 to a logic 1 is shown as being the same as for a transition from a logic 1 to a logic 0. If this is not the case, the techniques described herein can be used to separately estimate the delay for both transitions. The pulse width T PWOne way to measure the pulse width T directly is, for example, by using a digital delay line. However, this requires a large amount of high-performance circuitry to achieve good accuracy for high-speed circuits.

[0040] In contrast, in Figure 4 the pulse width T PW is measured by statistically sampling. Figure 4 An event 445 distributed in time with respect to a clock signal CLK is shown. In this example, the event 445 is a rising edge of an event signal 447, which can be an asynchronous clock with respect to CLK 415. Assume that the events 445 are uniformly distributed across the clock period. Some events 445 overlap with the pulse 435, while some events do not overlap with the pulse. The percentage of events that overlap with the pulse is a direct measure of the pulse width T PW If cl is the count of events that overlap with the pulse and c2 is the total count of events that fall within the clock cycle 415 of the DATA transition, the pulse width can be estimated by the following equation: T PW = (cl / c2) T CLK (1) In the example of Figure 4 , the count cl includes events 445B, 445D, 445E. The count c2 also includes events 445A, 445C. Neither count includes 445X because it does not fall within the clock period of the DATA transition.

[0041] The events do not have to be uniformly distributed across the clock cycle. They can take some other distribution, or they can span less than the entire clock cycle. If it is known that the delay falls within some range, the events can be distributed across that range instead of across the entire clock period.

[0042] Figure 5A is a block diagram of a CDM according to some embodiments of the disclosure. Figure 5B is a timing diagram illustrating the operation of the CDM of Figure 5A The CDM receives a clock signal CLK and a data signal DATA. It produces two counts cl and c2. The ratio (cl / c2) indicates the delay between CLK and DATA. The pulse generator 530 receives CLK and DATA and generates the pulse 535 as described previously. It also produces an enable pulse 537, which is high for the clock period of the DATA transition. The event generator 540 generates events that are used to sample the stream of pulses. The events are distributed in time with respect to the clock signal such that the sampling provides a measure of the pulse width of the pulses.

[0043] For example, event generator 540 could be a random event generator, meaning that events are generated with a degree of randomness in their timing. If the delay falls within a known range, the events can be distributed across that range. The same distribution can also be achieved using a non-random event generator. For example, the event generator could be a clock with a different frequency than the clock signal CLK, where the periods of the two clocks are not multiples of each other. Then the timing difference between the event and the edge of CLK will vary over time, and the events can be uniformly distributed across the delay range. In this example, event generator 540 is a clock with a different frequency than CLK, and the events are... Figure 5B The rising edge of the event clock shown.

[0044] Figure 5B The top two lines show the incoming clock signal CLK and the incoming data signal DATA. (Example) Figure 5B As shown in the third line, pulse generator 530 receives these signals and generates pulse stream 535. Event generator 540 generates... Figure 5B The fourth line shows the event clock 547, and the event is the rising edge of that clock signal.

[0045] Figure 5A The top row generates a count c1, which is the count of events overlapping with the pulse. Edge detector 560 receives pulse 535 and event 547. Edge detector 560 and counter 562 then generate count c1. Figure 5B In the code, the tick_c1 signal toggles whenever the condition for counter c1 is met. The next line, c1, shows the actual value of c1, which increments on each rising edge of tick_c1.

[0046] Figure 5A The bottom row generates a count c2, which is the total count of events within the clock cycle during which a pulse is generated (i.e., data toggles). Note that events occurring within clock cycles that do not generate pulses are not counted. Enable counters 570 and 572 to generate count c2. Figure 5B In the code, the signal tick_c2 is the counting pulse (ticks) for c2, and the next line c2 is the actual value of c2.

[0047] The statistical method can provide higher accuracy. For integrated circuits manufactured using sub-micron technology nodes, embedded memories can have data access delays on the order of hundreds of picoseconds. The method can be used to estimate the delay with 100 ps, or even 10 ps or higher accuracy. Furthermore, since the method is statistical in nature, it can be more tolerant to varying conditions. Changes in temperature, voltage, or aging can affect other methods, leading to the use of calibration or other compensation techniques, while using the method can avoid the use of calibration or other compensation techniques. The CDM circuit of Figure 5 is also a fairly simple digital circuit. The circuit can be built from standard cells. This is not a very demanding circuit and does not take up much area.

[0048] Figure 6 is a flowchart for monitoring delays in an integrated circuit according to some embodiments of the present disclosure. At 620, a data signal 625 and a corresponding clock signal 615 are received. At 630, pulses are generated from the received data signal and the received clock signal. The width of the pulses is determined by the delay of the data signal with respect to the clock signal. At 640, events 645 are received. The events are distributed in time with respect to the clock signal. At 650, the delay of the data signal is estimated based on the overlap between the events and the pulses.

[0049] The delay estimates can be used for various purposes. At 662, they are used for life cycle management. Predictive failure analysis can be performed based on the estimated delays over time. By observing the changes in the delays over time, trends and rates of change of the delays can be estimated and used to predict future actual delays. This can be used to predict when the actual delays are approaching a critical value. Appropriate warnings and alarms can be provided to avoid fatal errors of the system. In this way, problem areas on the device can be identified and appropriate measures taken before the problem areas on the device fail. For example, the clock frequency can be reduced or the voltage level dynamically changed in response to the delay estimates.

[0050] At 664, the technique can be used to measure and monitor signal quality, such as eye opening in data transmission. For data transmission, the CDM can be incorporated into the PHY circuit to measure the data-to-clock signal distance for DDR, UCIe, HBM, PCIe, USB, MIPI, HDMI, and other PHYs, thereby measuring or evaluating the data transmission eye opening. One advantage of this method compared to delay lines is that the method is applicable to different clock frequencies, while delay lines are specific to clock frequencies.

[0051] Statistical sampling methods can also be used to measure quantities other than delay, where the measured quantity is converted to pulse width modulation. Examples include temperature and voltage. Higher temperatures can be converted to wider pulses, or higher voltages can result in wider pulses. The pulse width can be measured as described above. It can also be used to measure the duty cycle of a periodic signal.

[0052] Figure 7 An example set of processes 700 used to transform and verify design data and instructions representing an integrated circuit during the design, verification, and fabrication of the manufactured item, such as an integrated circuit, is illustrated. Each of these processes can be structured and enabled as a number of modules or operations. The term "EDA" means the term "electronic design automation." These processes begin with creating a product concept 710 with information provided by a designer, which is transformed into creating artifacts using a set of EDA processes 712. When the design is finalized, the design is tape-out 734, that is, the art (e.g., geometric patterns) for the integrated circuit is sent to a fabrication plant to manufacture a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor dies 736 are manufactured and packaging and assembly processes 738 are performed to produce the finished integrated circuit 740.

[0053] The specification for a circuit or electronic structure can range from a low-level transistor material layout to a high-level description language. High-level representations can be used to design circuits and systems using a hardware description language ('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be transformed into a logic-level register transfer level ('RTL') description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of representation that is a more detailed description adds more useful detail to the design description, for example, including more detail of the modules described. Lower level representations that are more detailed descriptions can be generated by a computer, derived from a design library, or created by another design automation process. One example of a specification language under which a lower level representation language is used to specify more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each level of representation is enabled for use by a corresponding system at that layer, for example, a formal verification system. The design process can use Figure 7 The processes described are enabled by EDA products (or EDA systems).

[0054] During system design 714, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction, among others. Partitioning the design into different types of modules or components can occur at this stage.

[0055] During logic design and functional verification 716, the modules or components in the circuit are specified in one or more description languages, and the specification is checked for functional accuracy. For example, components of the circuit can be verified to generate outputs that match the specification requirements of the circuit or system being designed. Functional verification can use simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, a particular component system, referred to as a "simulator" or "prototype system," is used to speed up functional verification.

[0056] During synthesis and design for testing 718, the HDL code is transformed into a netlist. In some embodiments, the netlist can be a graph structure where the edges of the graph structure represent components of the circuit and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are layered artifacts that can be used by EDA products to verify that the integrated circuit, when manufactured, performs according to the specified design. The netlist can be optimized for the target semiconductor manufacturing technology. Furthermore, the completed integrated circuit can be tested to verify that the integrated circuit meets the specification requirements.

[0057] During netlist verification 720, the netlist is checked for compliance with timing constraints and correspondence with the HDL code. During design planning 722, the overall layout plan for the integrated circuit is constructed and analyzed for timing and top-level routing.

[0058] During layout or physical implementation 724, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of circuit components through multiple conductors) occur, and selection of cells from a library to enable particular logic functions can be performed. As used herein, the term "cell" can specify a collection of transistors, other components, and interconnections that provide a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function such as a flip-flop or latch. As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and as two physical structures and enabled in simulation. Parameters such as size are specified for selected cells (based on "standard cells") and are accessible in a database for use by EDA products.

[0059] During analysis and extraction 726, the circuit functionality is verified at the layout level, which allows refinement of the layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints, such as DRC constraints, electrical constraints, photolithographic constraints, are correct and that the circuit device functionality matches the HDL design specification. During resolution enhancement 730, the geometry of the layout is transformed to improve how the circuit design is manufactured.

[0060] During tape-out, data is created to be used to produce photolithographic masks (after photolithographic enhancements are applied as needed). During mask data preparation 732, the "tape-out" data is used to produce photolithographic masks, which are used to produce the finished integrated circuit.

[0061] The storage subsystem of a computer system, such as the computer system 800 of Figure 8 The storage subsystem of a computer system, such as the computer system 800 of

[0062] Figure 8 FIG. 1 1 illustrates an example machine of a computer system 800, upon which an instance of the machine can be executed, to cause the machine to perform any one or more of the methods discussed herein. In alternative implementations, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0063] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a

[0064] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM); flash memory; volatile RAM (e.g., synchronous DRAM (SDRAM)); a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 818, which communicate with each other via a bus 830.

[0065] The processing device 802 represents one or more processors such as a microprocessor, a central processing unit, or both. More particularly, the processing device can be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 802 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 802 can be configured to execute instructions 826 for performing the operations and steps described herein.

[0066] The computer system 800 can further include a network interface device 808 to communicate over the network 820. The computer system 800 also can include a video display unit 810 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), a graphics processing unit 822, a signal generation device 816 (e.g., a speaker), a graphics processing unit 822, a video processing unit 828, and an audio processing unit 832.

[0067] The data storage device 818 can include a machine-readable storage medium 824 (also known as a computer-readable medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methodologies or functions described herein. The instructions 826 can also reside, completely or at least partially, within the main memory 804 and / or within the processing device 802 during execution thereof by the computer system 800, the main memory 804 and the processing device 802 also constituting machine-readable storage media.

[0068] In some implementations, the instructions 826 include instructions to implement functionality corresponding to the disclosure. While the machine-readable storage medium 824 is shown in an example implementation to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and the processing device 802 to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0069] Some portions of the foregoing detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is a sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Such quantities can take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0070] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the prior discussion, it is appreciated that throughout the description, certain terms refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

[0071] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0072] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure described herein.

[0073] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), a random access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, flash memory devices, etc.

[0074] In the foregoing disclosure, implementations of the present disclosure have been described with reference to particular examples implementations. It is readily apparent to a person having ordinary skill in the art that various modifications can be made to the implementations without departing from the broader spirit and scope of implementations of the present disclosure as set forth in the appended claims. Where, in the foregoing disclosure, reference has been made to specific elements implementing the present disclosure, plural elements can be depicted in the drawings and like elements are labeled with like reference numerals. The present disclosure and drawings are, therefore, to be regarded as illustrative rather than restrictive.

Claims

1. An integrated circuit comprising: a digital circuit device; and a plurality of attribute monitors that monitor attributes of the digital circuit device; wherein the plurality of attribute monitors generate pulses having widths that are a function of the attributes.

2. The integrated circuit of claim 1, wherein the attribute monitors are delay monitors that monitor a delay of a data signal from the digital circuit device, and the delay monitors generate pulses having widths determined by the delay.

3. The integrated circuit of claim 2, wherein the delay monitors each comprise: a first counter that counts a number of events cl that overlap with the pulses, wherein the events are distributed in time with respect to a clock signal that clocks the data signal; and a second counter that counts a total number of events c2, wherein the delay is estimable as a function of (cl / c2).

4. The integrated circuit of claim 2, wherein the digital circuit device comprises an embedded memory, and, for at least one of the delay monitors, the data signal is a data value read from the embedded memory, and the delay is a data access delay for reading the data value from the embedded memory.

5. The integrated circuit of claim 2, wherein the digital circuit device comprises a logic path, and, for at least one of the delay monitors, the data signal propagates through the logic path, and the delay is a propagation delay for the data signal propagating through the logic path.

6. The integrated circuit of claim 2, wherein the data signal is a real-time data signal from a task mode of the integrated circuit.

7. The integrated circuit of claim 1, wherein the integrated circuit is fabricated using a sub-micron technology node.

8. The integrated circuit of claim 1, wherein the attribute monitors are not calibrated for temperature, supply voltage, or aging.

9. The integrated circuit of claim 1, wherein the attributes monitored include at least one of temperature, voltage, and current.

10. A delay monitor digital circuit comprising: a first input that receives a data signal; a second input that receives a clock signal, the clock signal used to clock the data signal; a pulse generator coupled to the first and second inputs, wherein the pulse generator generates a plurality of pulses from the received data signal and the received clock signal, and a width of the pulses is determined by a delay of the data signal with respect to the clock signal; an event generator that generates a plurality of events that are distributed in time with respect to the clock signal, wherein the delay is estimable based on an overlap between the events and the pulses.

11. The delay monitor digital circuit of claim 10, wherein the pulse generator is configured to start a pulse when the data signal flips and to end the pulse at a next rising edge of the clock signal.

12. The delay monitor digital circuit of claim 10, wherein the event generator is a random event generator that generates events with random timing with respect to the clock signal.

13. The delay monitor digital circuit of claim 10, wherein the event generator does not generate the events with random timing, but is asynchronous with respect to the clock signal and generates the events distributed over a range of possible values for the delay.

14. The delay monitor digital circuit of claim 10, further comprising: a first counter that counts a number of events cl that overlap with the pulses; and a second counter that counts a total number of events c2, wherein the delay is estimable as a function of (cl / c2).

15. The delay monitor digital circuit of claim 10, wherein the delay monitor digital circuit is synthesized from an RTL description and the delay monitor digital circuit is constructed from standard cells.

16. A method comprising: receiving a data signal and a clock signal, the clock signal used to clock the data signal; generating a plurality of pulses from the received data signal and the received clock signal, wherein a width of the pulses is determined by a delay of the data signal with respect to the clock signal; receiving a plurality of events distributed in time with respect to the clock signal; and estimating the delay based on an overlap between the events and the pulses.

17. The method of claim 16, wherein generating the plurality of pulses comprises: starting a pulse when the data signal flips, wherein the flip of the data signal is clocked by a first cycle of the clock signal; and ending the pulse based on a next cycle of the clock signal.

18. The method of claim 16, wherein estimating the delay comprises: counting a number of events cl that overlap with the pulses; counting a total number of events c2; and estimating the delay based on a period of the clock signal multiplied by (cl / c2).

19. The method of claim 16, further comprising: performing a predictive fault analysis of a circuit based on monitoring the estimated delay over time.

20. The method of claim 16, further comprising: using the data signal to evaluate an eye opening of a data transmission based on the estimated delay. ​ ​ ​ ​

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