Fabrication of solar cell emitter regions with differentiated p-type and n-type layouts with punctiform diffusion

Abstract

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type layouts and employing punctiform diffusion, and solar cells fabricated thereby, are described herein. In an example, a solar cell includes a substrate having a light receiving surface and a back surface. A first polysilicon emitter region of a first conductivity type is on a first thin dielectric layer on the back surface of the substrate. A second polysilicon emitter region of a different second conductivity type is on a second thin dielectric layer on the back surface of the substrate. The vertical thickness of the second polysilicon emitter region is smaller than the vertical thickness of the first polysilicon emitter region.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of renewable energy, particularly a method for manufacturing solar cell emitter regions with differentiated P-type and N-type layouts and employing dotted diffusion, and the solar cells thereby manufactured. Background Technology

[0002] A photovoltaic (PV) cell (commonly known as a solar cell) is a common device that directly converts solar radiation into electrical energy. Typically, a solar cell is made by forming a pn junction near the surface of a semiconductor wafer or substrate using semiconductor processing techniques. Solar radiation strikes the substrate surface and penetrates the substrate, generating electron-hole pairs within the substrate. These electron-hole pairs migrate to p-type and n-type doped regions in the substrate, creating a voltage difference between the doped regions. The doped regions connect to conductive regions on the solar cell, thus guiding current from the cell to an externally coupled circuit.

[0003] Efficiency is a crucial characteristic of solar cells because it directly affects their power generation capacity. Similarly, the manufacturing efficiency of solar cells directly impacts their cost-effectiveness. Therefore, technologies that improve solar cell efficiency or manufacturing efficiency are generally desirable. Some embodiments of this disclosure achieve improved manufacturing efficiency by providing novel processes for manufacturing solar cell structures. Other embodiments of this disclosure achieve improved solar cell efficiency by providing novel solar cell structures. Attached Figure Description

[0004] Figures 1A-1C Cross-sectional and planar views of each stage in the solar cell manufacturing process are shown.

[0005] Figure 2A A cross-section of a portion of a solar cell is shown.

[0006] Figure 2B It shows Figure 2A An exemplary layout of multiple circular trenches surrounding multiple polycrystalline silicon structures in a solar cell.

[0007] Figures 3A-3D Cross-sectional views illustrating various operations of a solar cell manufacturing method according to embodiments of the present disclosure are shown.

[0008] Figure 4A A cross-section of a portion of a solar cell according to an embodiment of the present disclosure is shown, for example, according to Figures 3A-3D Solar cells made using this method.

[0009] Figure 4B An embodiment according to this disclosure is shown. Figure 4A An exemplary layout of multiple circular trenches surrounding multiple polycrystalline silicon structures in a solar cell.

[0010] Figure 5 The embodiments of this disclosure are listed below. Figures 3A-3D A flowchart of the corresponding operations in the solar cell manufacturing method. Detailed Implementation

[0011] The following detailed description is illustrative in nature only and is not intended to limit the embodiments or the application and use of such embodiments. As used herein, the word "exemplary" means "as an example, instance, or illustration." Any embodiment described herein as exemplary is not necessarily preferred or advantageous over other embodiments. Furthermore, one should not be bound by any explicit or implicit theory presented in prior art, background art, summary of the invention, or the following detailed description.

[0012] The terms "one embodiment" or "an embodiment" do not necessarily refer to the same embodiment. Specific features, structures, or characteristics can be combined in any suitable manner according to this disclosure.

[0013] Terminology Explanation. The following paragraphs provide definitions and / or background for the terms appearing in this disclosure (including the appended claims): "Comprising" is an open-ended term that does not exclude additional structures or steps.

[0014] "Configured to" indicates a structure in which a device (e.g., a unit or component) is configured to perform one or more tasks during operation, even if the device is not currently in operation (e.g., not powered on / not activated). The explicit purpose of "configured to" a device to perform one or more tasks is to avoid invoking the interpretation of the device or procedure plus function as specified in 35 USC §112(f) or paragraph 6.

[0015] The terms “first,” “second,” etc., used as labels for the nouns that follow them do not imply any kind of order (e.g., spatial, temporal, logical, etc.). For example, mentioning a “first” solar cell does not necessarily mean that this solar cell is the first in a sequence; rather, the term “first” is used to distinguish this solar cell from another solar cell (e.g., a “second” solar cell).

[0016] "Coupled" means that an element, feature, structure, or node can be directly or indirectly engaged or communicated with another element / node / feature, without necessarily being directly and mechanically joined together, unless otherwise expressly specified.

[0017] "Inhibit" means to reduce, mitigate, minimize, or effectively or practically eliminate something, such as completely preventing a certain result, outcome, or future state.

[0018] "Doped regions," "semiconductor regions," and similar terms refer to areas in a semiconductor located within, on, above, or on a substrate. These regions can exhibit N-type or P-type conductivity, and the doping concentration can vary. Multiple regions can be referred to, such as a first doped region, a second doped region, a first semiconductor region, a second semiconductor region, etc. These regions can be formed from polysilicon on the substrate or as part of the substrate itself.

[0019] A “thin dielectric layer,” “tunneling dielectric layer,” “dielectric layer,” “thin dielectric material,” or intermediate layer / material refers to a material located on a semiconductor region, between a substrate and another semiconductor layer, or on or within a substrate between doped or semiconductor regions. In embodiments, the thin dielectric layer may be a tunneling oxide or nitride layer with a thickness of approximately 2 nanometers or less. The thin dielectric layer, also referred to as an ultrathin dielectric layer, can be used to achieve conductivity. Conductivity may be due to quantum tunneling effects and / or the presence of tiny, directly physically connected regions within the thin dot-like structure of the dielectric layer. Exemplary materials include silicon oxide, silicon dioxide, silicon nitride, and other dielectric materials.

[0020] An "intervening layer" or "insulating layer" refers to a layer provided to achieve electrical insulation, passivation, and light reflection suppression. Intervening layers can be multiple layers, such as stacked layers. In some contexts, the insulating layer may be interchangeable with a tunneling dielectric layer, while in others, it is a masking layer or an "antireflective coating layer" (ARC layer). Exemplary materials include silicon nitride, silicon oxynitride, silicon dioxide, aluminum oxide, amorphous silicon, polycrystalline silicon, molybdenum oxide, tungsten oxide, indium tin oxide, tin oxide, vanadium oxide, titanium oxide, silicon carbide, and other materials. In examples, the intervening layer may contain materials that can act as a moisture barrier. Furthermore, for example, the insulating layer may be a passivation layer for a solar cell.

[0021] The term "substrate" can refer to, but is not limited to, semiconductor substrates, such as silicon, specifically monocrystalline silicon substrates, polycrystalline silicon substrates, wafers, silicon wafers, and other semiconductor substrates used in solar cells. In the examples, such substrates can be used in microelectronic devices, photovoltaic cells or solar cells, diodes, photodiodes, printed circuit boards, and other devices. These terms are used interchangeably herein.

[0022] “About” or “approximately”. As used herein, when referring to cited numerical values ​​(including, for example, integers, fractions, and / or percentages), the use of “about” or “approximately” generally indicates that the cited value covers a range of values ​​(e.g., differing from the cited value by + / - 5% to 10%) that a person skilled in the art would consider equivalent to the cited value (e.g., performing substantially the same function, working in substantially the same manner, and / or producing substantially the same results).

[0023] Additionally, in the following description, certain terms may be used for illustrative purposes only and are therefore not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” and “below” refer to orientation in the referenced figures. Terms such as “front,” “back,” “rear,” “side,” “outboard,” and “inboard” describe the orientation and / or position of a part within a consistent but arbitrary frame of reference, which is clearly discernible from the text describing the part under discussion and the associated figures. Such terms may include the words specifically mentioned above, their derivatives, and words with similar meanings.

[0024] This document describes a method for manufacturing solar cell emitter regions with differentiated P-type and N-type layouts and employing dot-matrix diffusion, and the solar cells thereby manufactured. In the following description, numerous specific details, such as specific process operations, are set forth in order to provide a thorough understanding of the embodiments of this disclosure. It will be apparent to those skilled in the art that the embodiments of this disclosure can be practiced without these specific details. In other instances, well-known manufacturing techniques, such as photolithography and patterning techniques, have not been described in detail to avoid unnecessarily obscuring the embodiments of this disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0025] This document discloses a solar cell. In one embodiment, the solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitting region of a first conductivity type is provided on a first thin dielectric layer on the back surface of the substrate. A second polycrystalline silicon emitting region of a different second conductivity type is provided on a second thin dielectric layer on the back surface of the substrate. The vertical thickness of the second polycrystalline silicon emitting region is less than the vertical thickness of the first polycrystalline silicon emitting region.

[0026] This document also discloses a method for manufacturing a solar cell. In an embodiment, the method for manufacturing a solar cell involves: forming an N+ polycrystalline silicon layer on a thin dielectric layer on the back surface of a substrate; forming a boron-doped silica glass (BSG) layer on the N+ polycrystalline silicon layer; forming an amorphous silicon (aSi) layer on the BSG layer; performing laser ablation to form openings in the aSi layer and the BSG layer, doping regions of the N+ polycrystalline silicon layer, and exposing unmodified external regions of the N+ polycrystalline silicon layer; performing etching to remove the exposed unmodified external regions in the N+ polycrystalline silicon layer, thereby forming an N+ polycrystalline silicon emitter region and a residual polycrystalline silicon region beneath the boron-doped silicon cap; performing etching to remove the boron-doped silicon cap, leaving the residual polycrystalline silicon region; and doping the residual polycrystalline silicon region to form a P+ polycrystalline silicon emitter region.

[0027] In another embodiment, a method of manufacturing a solar cell involves providing a substrate having a light-receiving surface and a back surface. The method includes forming a first polycrystalline silicon emitting region of a first conductivity type on a first thin dielectric layer on the back surface of the substrate. The method also includes forming a second polycrystalline silicon emitting region of a different conductivity type on a second thin dielectric layer on the back surface of the substrate. The vertical thickness of the second polycrystalline silicon emitting region is less than the vertical thickness of the first polycrystalline silicon emitting region.

[0028] One or more embodiments described herein relate to the fabrication of solar cells with dot-matrix diffusion. In these embodiments, implementing a dot-matrix diffusion design with differentiated P-type and N-type layouts can produce laser-patterned emitters with greater stability and lower reverse bias breakdown. Dot-matrix diffusion can be achieved using laser ablation, as described in more detail below. However, in another embodiment, non-laser methods can also be used to form island-like diffusion, such as by printing an etchant or by masking and etching methods.

[0029] Solar cell efficiency is a crucial operating characteristic of solar cells, as it directly affects their power generation capacity. Carrier recombination is a significant factor determining solar cell efficiency, as recombined carriers may not contribute a net to the current generated by the solar cell. Diffusion trenches (e.g., trenches in portions of the substrate volume where dopants diffuse into) are likely to have the worst recombination properties on the solar cell surface. Additionally, the carrier recombination properties may also be poor at the locations where metal components on the solar cell surface contact the semiconductor substrate.

[0030] As background, patterning emitters in conventional solar cell structures using lasers can be challenging because linear emitters require the removal of a considerable area of ​​material. This removal can be difficult and, when using diode-pumped solid-state (DPSS) lasers, may pose a challenge in achieving single-number-per-hour (UPH) values. Some designs also rely on edge-vertical sidewall junctions as reverse-biased breakdown paths, thus requiring high uniformity. Forming such edge-vertical sidewall junctions using "clean" laser processes can be difficult because they involve overlapping dotted structures, which is the conventional approach when pulsed lasers form continuous emitters. The reverse breakdown voltage is also proportional to the length of the butting junction, which acts as the breakdown region.

[0031] To address one or more of the aforementioned issues, a dotted design is employed in the embodiments. This allows for easy control of the spot size and the achievement of a high-density dot matrix layout, potentially improving the device's breakdown performance. In specific embodiments, forming a dot matrix structure as the emitter enables faster laser processing, more uniform ablation (e.g., non-overlapping dot structures) to obtain better sidewalls, the use of lower energy (e.g., extending the UV laser option, which also benefits sidewall uniformity), and can improve the breakdown voltage. Other benefits of using point emitter designs with differentiated P-type and N-type architectures may include one or more of the following: (1) increasing junction area to reduce breakdown voltage; (2) eliminating the overlapping structure required for continuous emitters; (3) improving UPH problems; (4) improving edge overlap and control problems; (5) reducing island contact problems by using monolithic N-type amorphous silicon (na-Si) deposition; (6) enabling the formation of discrete regions (“islands”) such as single rows, double rows, and triple rows on the substrate; (7) enabling the adjustment of island size; and / or (8) enabling the clean removal of oxides and the formation of clean sidewalls using UV or CO2 laser sources without causing significant damage to the emitter.

[0032] As further context, earlier approaches involved implementing point diffusion designs with differentiated P-type and N-type structures. For process flow comparison, Figures 1A-1C Cross-sectional views of various stages in the solar cell manufacturing process are shown.

[0033] refer to Figure 1A A method for manufacturing alternating N-type and P-type emitter regions in a solar cell involves forming a first silicon layer 106 of a first conductivity type on a first thin dielectric layer 104 formed on the back surface of a substrate 102.

[0034] In this example, substrate 102 is a single-crystal silicon substrate, such as a bulk single-crystalline N-type doped silicon substrate. However, it should be understood that substrate 102 can be a layer on an overall solar cell substrate, such as a polycrystalline silicon layer. In this example, the first thin dielectric layer 104 is a thin oxide layer, such as a tunnel dielectric silicon oxide layer with a thickness of approximately 2 nanometers or less.

[0035] In the example, the first silicon layer 106 is a polycrystalline silicon layer, doped to have a first conductivity type by in-situ doping, post-deposition implantation, or a combination thereof. In another example, the first silicon layer 106 is an amorphous silicon layer, such as a silicon hydride layer (e.g., a silicon hydride layer represented by a-Si:H), which is implanted with dopants of the first conductivity type after the amorphous silicon layer is deposited. In one such example, the first silicon layer 106 is subsequently annealed (at least at a later stage of the process flow) to ultimately form a polycrystalline silicon layer. In the example, for either the polycrystalline or amorphous silicon layer, if post-deposition implantation is performed, then implantation is performed using ion beam implantation or plasma immersion implantation. In one such example, implantation is performed using a shadow mask. In a specific example, the first conductivity type is P-type (e.g., formed using boron impurity atoms).

[0036] Refer again Figure 1A An insulating layer 108 is formed on the first silicon layer 106. In this example, the insulating layer 108 comprises silicon dioxide.

[0037] refer to Figure 1B The insulating layer 108 and the first silicon layer 106 are patterned to form a first silicon region 110 of a first conductivity type, on which an insulating cap 112 is provided. In this example, the insulating layer 108 and the first silicon layer 106 are patterned using a laser ablation process (e.g., direct writing). Where applicable, in one example, a first thin dielectric layer 104 is also patterned in this process, such as... Figure 1B As depicted in [the text]. It should be understood that, Figure 1B The cross-sectional view is along Figure 1B It is intercepted by the a-a' axis of the plan view.

[0038] In the example, Figure 1B The laser ablation process exposes multiple regions 109 of the N-type monocrystalline silicon substrate 102. Each of the multiple regions 109 of the N-type monocrystalline silicon substrate 102 can be regarded as multiple discontinuous trenches 111 (see cross-sectional view) formed in the N-type monocrystalline silicon substrate 102, with a spacing 112 between the trenches (see plan view for the spacing). Figure 1B The cross-sectional view depicts an option for the depth or thickness 111 of the trench 109 in the substrate. In one such example, each of a plurality of discontinuous trenches 109 formed by a laser ablation process has a non-zero depth 111 of less than approximately 10 micrometers in the substrate 102.

[0039] As mentioned above, the plurality of openings and corresponding plurality of discontinuous trenches 109 can be formed by applying a laser ablation process. In the example, the laser ablation process is used such that each of the plurality of discontinuous trenches has a width (e.g., maximum diameter) in the range of approximately 30 to 60 micrometers. In one such example, the continuous trenches in the plurality of discontinuous trenches 109 are formed to be spaced apart at a distance in the range of approximately 50 to 300 micrometers. If the distance is much less than 50 micrometers, it may result in trench overlap (which, as mentioned earlier, is likely undesirable). On the other hand, if the distance is much greater than 300 micrometers, it may result in increased contact resistance at the contacts of the subsequently formed and linked trenches 109. In the example, the laser ablation process involves using a laser beam with an approximately Gaussian profile or an approximately flat-top profile.

[0040] Next, the surface of trench 109 can be texturized to form a textured recess or trench with a textured surface within substrate 102. The light-receiving surface of the substrate can also be texturized using the same or similar process. In the example, at least a portion of the recess is formed using a hydroxide-based wet etchant, and / or the exposed portion of substrate 102 is texturized. The textured surface can be a surface with a regular or irregular shape to scatter incident light and reduce the amount of light reflected from the light-receiving surface and / or exposed surface of the solar cell. However, it should be understood that the texturization of the back surface, or even the formation of the recess, can be omitted in the process flow. It should also be understood that if texturization is performed, the texturization process may increase the depth of trench 109 compared to the initially formed depth.

[0041] Next, a second thin dielectric layer is formed on the exposed side of the first silicon region. In one example, the second thin dielectric layer is formed by an oxidation process and is a thin oxide layer, such as a tunnel dielectric silicon oxide layer with a thickness of approximately 2 nanometers or less. In another example, the second thin dielectric layer is formed by a deposition process and is a thin silicon nitride layer or a silicon oxynitride layer.

[0042] Next, a second silicon layer of a different second conductivity type is formed on the exposed portion formed on the back surface of the substrate 102 (e.g., in each of the plurality of discontinuous trenches 109 formed in each of the plurality of regions of the N-type monocrystalline silicon substrate 102) and on the third thin dielectric layer on the second thin dielectric layer of the first silicon region and the insulating cap. The second silicon layer covers (from a top view) the trench region 109.

[0043] Next, a corresponding thin dielectric layer and a second silicon layer of the second conductivity type can be formed on the light-receiving surface of the substrate 102 using the same or similar process operations. Additionally, an ARC layer can be formed on the corresponding second silicon layer.

[0044] In the example, the third thin dielectric layer 122 is formed by an oxidation process and is a thin oxide layer, such as a tunnel dielectric silicon oxide layer with a thickness of approximately 2 nanometers or less. In the example, the second silicon layer is a polycrystalline silicon layer, doped to have a second conductivity type by in-situ doping, post-deposition implantation, or a combination thereof. In another example, the second silicon layer is an amorphous silicon layer, such as a silicon hydride layer (e.g., a silicon hydride layer represented by a-Si:H), after which a dopant of the second conductivity type is implanted. In one such example, the second silicon layer is subsequently annealed (at least at a later stage of the process flow) to ultimately form a polycrystalline silicon layer. In the example, for either the polycrystalline or amorphous silicon layer, if post-deposition implantation is performed, implantation is performed using ion beam implantation or plasma immersion implantation. In one such example, implantation is performed using a shadow mask. In a specific example, the second conductivity type is N-type (e.g., formed using phosphorus or arsenic impurity atoms).

[0045] Next, the second silicon layer is patterned to form isolated second silicon regions of a second conductivity type, and contact openings are formed in the region of the second silicon layer above the insulating cap of the first silicon region. In the example, each isolated N-type silicon region is electrically coupled to one (or more) corresponding regions of a plurality of regions 109 of the N-type monocrystalline silicon substrate. In the example, discrete silicon regions may be retained as a product of the patterning process. In the example, the second silicon layer is patterned using a laser ablation process.

[0046] Next, the insulating cap is patterned through the contact openings to expose portions of the first silicon region. In this example, the insulating cap is patterned using a laser ablation process. For example, in one example, a first laser pass is used to pattern the second silicon layer, including forming the contact openings. A second laser pass is then performed at the same locations as the contact openings to pattern the insulating cap. In this example, from a top view perspective, a single discrete region (e.g., a single discrete N-type silicon region) covers a strip consisting of multiple openings 109.

[0047] refer to Figure 1CMultiple conductive contacts are formed, each electrically connected to one of the P-type silicon regions or isolating one of the N-type silicon regions. In an exemplary example, a metal seed layer 128 is formed on the exposed portion of the first silicon region 110 and on the isolated second silicon region 124. Next, a metal layer 130 is plated on the metal seed layer to form conductive contacts 132 and 134 for the first silicon region 110 and the isolated second silicon region 124, respectively. In this example, the metal seed layer 128 is an aluminum-based metal seed layer, and the metal layer 130 is a copper layer. In this example, a mask is first formed to expose only the exposed portion of the first silicon region 110 and the isolated second silicon region 124, thereby forming the metal seed layer 128 in a defined location.

[0048] Refer again Figure 1C In this example, the final solar cell comprises a substrate 102 having a light-receiving surface 101 and a corresponding back surface. A first polycrystalline silicon emitting region 110 of a first conductivity type is provided on a first thin dielectric layer 104 on the back surface of the substrate 102. Multiple discontinuous trenches (in...) are present on the back surface of the substrate 102. Figure 1C The second thin dielectric layer 122 (shown as a recess in the cross-sectional view) has second polycrystalline silicon emitter regions 124 of different second conductivity types. In the example, the substrate 102 is an N-type monocrystalline silicon substrate, the first conductivity type is P-type, and the second conductivity type is N-type. In the example, the solar cell is a back-contact solar cell, such as... Figure 1C As depicted in the text.

[0049] In the example, each of the multiple discontinuous trenches has a width in the range of approximately 30 to 60 micrometers, as per [reference to...]. Figure 1B As described above. In the example, adjacent trenches in a plurality of discontinuous trenches are spaced apart by a distance in the range of approximately 50 to 300 micrometers, as also as per the description of... Figure 1B As described above. In the example, each of the plurality of discontinuous trenches has a depth approximately in the range of 0.5 to 10 micrometers, extending from the back surface into the interior of the substrate 102. The final trench depth can be formed by laser ablation, texturing processes, or both. In the example, each discontinuous trench has a generally circular shape in a planar view. Figure 1C As depicted, each discontinuous trench has a textured surface.

[0050] Refer again Figure 1CIn this example, the solar cell further includes a third thin dielectric layer 118 laterally positioned directly between the first polysilicon emitter region 110 and the second polysilicon emitter region 124. In this example, the solar cell also includes a first conductive contact structure 130 electrically connected to the first polysilicon emitter region 110 and a second conductive contact structure 134 electrically connected to the second polysilicon emitter region 124. In this example, the solar cell also includes an insulating layer 112 on the first polysilicon emitter region 110. The first conductive contact structure 130 extends through the insulating layer 112. In one such example, a portion of the second polysilicon emitter region 124 overlaps with the insulating layer 112 but is separated from the first conductive contact structure 130, as shown below. Figure 1C As depicted in the illustration. In another example, the polysilicon region 125 of the second conductivity type is on the insulating layer 112, and the first conductive contact structure 130 passes through the polysilicon region 125 of the second conductivity type and through the insulating layer 112, as shown in the illustration. Figure 1C As depicted in the text.

[0051] On the other hand, to provide more background information, earlier approaches included implementing point diffusion designs with differentiated P-type and N-type layouts.

[0052] In one example, a narrow diffusion trench can be formed using a self-aligned process. By limiting the width of the trench (which is the part of the solar cell surface with the worst carrier recombination characteristics), carrier recombination characteristics can be effectively improved. Additionally, in one example, because the metal layer in the solar cell contacts polycrystalline silicon rather than a semiconductor substrate, another common source of unfavorable carrier recombination is avoided. As a result, this solar cell architecture limits the opportunities for carrier recombination that may exist in solar cells of different designs. In one example, limiting the opportunities for carrier recombination aims to reduce carrier recombination, thereby having a beneficial effect on the voltage generated by the solar cell, the net contribution of carriers to the current, and the efficiency of the solar cell.

[0053] Figure 2A A cross-section of a portion of an example solar cell 200 (hereinafter referred to as "solar cell 200") is shown. It should be understood that solar cell 200 can be used with respect to... Figures 1A-1C Manufactured using one or more of the aforementioned process operations or material schemes.

[0054] In one example, solar cell 200 includes substrate 201, tunnel oxide 203, n-type doped polycrystalline silicon 205, and p-type doped polycrystalline silicon 207. 1、 Trench 208a, trench 208b, doped region 209a, doped region 209b, insulating layer 211, insulating layer 213, wiring layer 215, and wiring layer 217.

[0055] refer toFigure 2A The substrate 201 constitutes a substrate on which a semiconductor layer, an insulating layer, and a wiring layer of a solar cell 200 are formed. In one example, a tunnel oxide 203 is formed on the surface of the substrate 201 and includes a space through which doped regions 209a and 209b are formed, and an insulating layer 213 is formed in the space. In one example, a p-type doped polysilicon layer 2071 is formed on a portion of the tunnel oxide 203, which exists between portions of the tunnel oxide 203 below the laterally positioned portions of the n-type doped polysilicon layer 205. In one example, the p-type doped polysilicon layer 2071 includes a side surface covered by the insulating layer 213 and a top surface partially covered by the insulating layer 213. Additionally, in one example, the p-type doped polysilicon layer 2071 contacts the wiring layer 215 on its top surface through a space in the insulating layer 213. In one example, an n-type doped polysilicon layer 205 is formed on the surface of tunnel oxide 203 and is laterally separated from p-type doped polysilicon layer 2071 by a portion of insulating layer 213 extending into the space within tunnel oxide 203 (on both sides of p-type doped polysilicon layer 2071). In one example, a doped region 209a is formed in the surface of substrate 201, below a portion of insulating layer 213 extending into the first space within tunnel oxide 203. In one example, doped region 209a extends laterally below the portions of tunnel oxide 203 formed below p-type doped polysilicon layer 2071 and below n-type doped polysilicon layer 205. In one example, a doped region 209b is formed in the surface of substrate 201, below a portion of insulating layer 213 extending into the second space within tunnel oxide 203. In one example, the doped region 209b extends laterally beneath the portions of tunnel oxide 203 formed below the p-type doped polysilicon layer 2071 and below the n-type doped polysilicon layer 205. In one example, an insulating layer 213 is formed above the insulating layer 211, along the bottom and sidewalls of trenches 208a and 208b (which are located above doped regions 209a and 209b), and on the top surface of the p-type doped polysilicon layer 2071. In one example, the insulating layer 213 includes openings above the p-type doped polysilicon layer 2071 and the n-type doped polysilicon layer 205, allowing the p-type doped polysilicon layer 2071 and the n-type doped polysilicon layer 205 to contact wiring layers 215 and 217, respectively. In one example, an insulating layer 211 is formed over an n-type doped polysilicon layer 205 and includes an opening over the n-type doped polysilicon layer 205 that allows the n-type doped polysilicon layer to contact the wiring layer 217. In one example, trenches 208a and 208b are trenches surrounding a p-type doped polysilicon layer 2071 (e.g., see reference 208a). Figure 2BThe groove 2081 described is the cross-sectional portion on both sides.

[0056] refer to Figure 2A In one example, wiring layer 215 may occupy a larger area than p-type doped polysilicon layer 2071. However, in other examples, wiring layer 215 may be confined to the area occupied by p-type doped polysilicon layer 2071, or to the area occupied by p-type doped polysilicon layer 2071 and the areas occupied by p-type doped regions 209a and 209b. In one example, confining wiring layer 215 to a p-type conductive semiconductor region may involve using a larger p-type semiconductor region. In other examples, confining wiring layer 215 to a p-type conductive semiconductor region may not involve using a larger p-type semiconductor region. In one example, wiring layer 215 may be limited to a p-type semiconductor region that does not have a continuous or contiguous configuration but may have a cell architecture with module interconnects, which may include, but are not limited to, conductive circuit boards, such as conductive circuit boards for metallization wrapthrough (MWT) solar cells and interdigitated back contact (IBC) solar cells.

[0057] refer to Figure 2B In one example, Figure 2A The trenches 208a and 208b shown are cross-sectional portions of opposite sides of trench 2081 formed around the p-type doped polycrystalline silicon layer 2071 and above the doped region 2091. Furthermore, in one example, trench 2081 is formed on multiple polycrystalline silicon islands 2071-207 in the solar cell 200. n Multiple surrounding trenches 2081-208 n One of them (in) Figure 2B In the middle, the arrow indicates trench 2081-208. n Compared to the doped region 2091-209 n (Location). In one example, the trench can have shapes including, but not limited to, circular, rectangular, elongated, elliptical, polygonal, and irregular shapes. In one example, polycrystalline silicon islands 2071-207 n Used as an emitter, its surface region is part of the surface region of the n-type doped polysilicon layer 205 (emitter). In one example, trench 2081-208 nIt is self-aligned. In one example, the trenches formed by self-alignment can be narrower than those achievable through some other processes. In one example, because the diffusion trenches can form part of a surface region that may undergo a higher level of recombination, narrow trenches can have a beneficial effect on recombination and performance.

[0058] In one example, polycrystalline silicon islands 2071-207 n These are multiple non-adjacent doped polysilicon regions with p-type conductivity formed in the lasered region of a semiconductor structure. In one example, the semiconductor regions with p-type polarity (e.g., 2071-207) n The associated wiring layer 215 ( Figure 2A (However, in some other examples, the overlap between a semiconductor region of one polarity and the metallization structure associated with a semiconductor region of another polarity is avoided.)

[0059] In one example, substrate 201 can be formed of silicon. In other examples, substrate 201 can be formed of other materials. In one example, tunnel oxide 203 can be formed of silicon oxide. In other examples, tunnel oxide 203 can be formed of other materials. In one example, doped polysilicon layer 205 can be doped with phosphorus. In other examples, doped polysilicon layer 205 can be doped with other impurities. In one example, doped polysilicon layer 2071 can be doped with boron. In other examples, doped polysilicon layer 2071 can be doped with other impurities. In one example, doped regions 209a and 209b can be doped with boron. In other examples, doped regions 209a and 209b can be doped with other materials. In one example, insulating layer 211 can comprise borosilicate glass and undoped silicate glass (hereinafter referred to as "BPSG(+USG)"). In other examples, insulating layer 211 can comprise other materials. In one example, insulating layer 213 may comprise boron-doped silicate glass, undoped silicate glass, and silicon nitride (hereinafter referred to as "BSG(+USG)+SiN"). In other examples, insulating layer 213 may comprise other materials. In one example, wiring layer 215 may comprise aluminum, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, tin, platinum, and tantalum. In other examples, wiring layer 215 may comprise other materials. In one example, wiring layer 217 may comprise aluminum, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, tin, platinum, and tantalum. In other examples, wiring layer 217 may comprise other materials.

[0060] In operation, when exposed to light, solar cell 200 converts light energy into electrical energy based on the photovoltaic effect. Some charge carriers reach the pn junction, contributing to the current generated by solar cell 200. However, other charge carriers recombine without making a net contribution to the current generated by solar cell 200. Charge carrier recombination is a crucial factor determining the efficiency of solar cells. The diffusion trenches are likely the worst part of the surface of solar cell 200 for recombination. However, in one example, the narrowness of the diffusion trenches 208a and 208b, achieved through a self-aligned process, is beneficial for charge carrier recombination in this part of the surface of solar cell 200. The metal-contacted doped region is another important source of charge carrier recombination. In one example, solar cell 200 does not employ a metal structure that directly contacts any part of the substrate 201. Therefore, the design of this solar cell 200 limits the opportunities for charge carrier recombination that may exist in solar cells of different designs. In one example, limiting the opportunities for charge carrier recombination can have a favorable impact on both charge carrier recombination and solar cell efficiency.

[0061] On the other hand, according to one or more examples of this disclosure, point diffusion designs with differentiated P-type and N-type layouts and differentiated P-type and N-type architectures have been implemented. It should be understood that the processes and solar cells described below can be used with reference to... Figures 1A-1C and Figures 2A-2B Manufactured using one or more of the aforementioned process operations or material schemes.

[0062] As background, existing technologies achieve 25.5% efficiency through high N-type polysilicon (Npoly) device side coverage. This results in good bulk lifetime and low device current density (Jo). The remaining half of the total device current density comes from the P-type regions. These currently occupy 6% of the device side area, generating a total current density of 3.5 fA / cm². The embodiments described herein can reduce this P-type Jo value by introducing P-type polysilicon into the P-type regions without adding additional process operations.

[0063] To provide further background, N-type polysilicon has a deposited mask film containing oxides and amorphous silicon. A first improvement in the process was the use of a boron-phosphorus-doped oxide stack instead of undoped oxides. The idea is to laser-process the boron-doped portion, introducing the dopant into the undoped polysilicon region within the boron-doped p-type region. Boron-selective silicon etching is then employed, and this region resists etching, thus preserving the polysilicon region. Subsequently, in furnace operation, phosphorus and boron are mixed in the oxide, with phosphorus dominating diffusion into the polysilicon, forming N-type polysilicon outside the p-type region. According to one or more embodiments of this disclosure, to address this issue, the phosphorus-doped oxide component in the mask is removed, and predoped N-type polysilicon is used. In one embodiment, the phosphorus dopant is placed on the outermost layer of the N-type polysilicon and is as thin as possible. After an initial boron-selective polyetch to form a dotted structure, a second non-boron-selective etch is performed, etching back the top of the dotted structure and removing the phosphorus dopant on top of the stack. No space charge recombination was observed in this process.

[0064] As an example process solution Figures 3A-3D Cross-sectional views illustrating various operations in a solar cell manufacturing method according to embodiments of the present disclosure are shown. Figure 5 The embodiments of this disclosure are listed below. Figures 3A-3D A flowchart 500 shows the corresponding operations in the solar cell manufacturing method. It should be understood that the processes and solar cells described below can be used with reference to... Figures 1A-1C and Figures 2A-2B The manufacturing process is carried out using one or more of the aforementioned process operations, material schemes, or operating schemes.

[0065] refer to Figure 3A Referring to the corresponding operation 502 of flowchart 500, forming the initial structure 300 includes: forming an N+ polysilicon layer 306 on a thin dielectric layer 304 on the back surface of a substrate 302 (e.g., a silicon substrate); forming a boron-doped silicate glass (BSG) layer 308 on the N+ polysilicon layer 306; and forming an amorphous silicon (aSi) layer 310 on the BSG layer 308. In one embodiment, the N+ polysilicon layer 306 has a thickness in the range of 200 to 300 nanometers, for example, about 220 nanometers.

[0066] refer to Figure 3B Referring to the corresponding operation 504 in flowchart 500, this method includes: laser ablation. Figure 3AThe structure involves forming an opening 314 in the aSi layer 310, followed by etching the BSG layer 308 to form a patterned aSi layer 310A and a patterned BSG layer 308A. In an embodiment, during laser ablation, the BSG layer 308 is doped with boron in a region of the underlying N+ polysilicon layer 306 to form a modified N+ polysilicon layer 306A with a P+ region 312. In one such embodiment, the doped region is at the center of the opening 314 but does not completely cover the opening 314, thus exposing the outer unmodified region. In a particular embodiment, laser ablation is performed using a green laser with a flat-top profile. In an embodiment, the opening is a discrete circle or other discrete shape (e.g., a square or rectangle). In another embodiment, the opening is linear. In an embodiment, the laser pulse ablates the oxide and dops boron in a smaller central region, thereby forming a self-aligned boron-doped polysilicon structure within a dotted structure.

[0067] refer to Figure 3C Referring to the corresponding operation 506 in flowchart 500, this method includes etching. Figure 3B The structure is designed to remove the exposed external unmodified regions in the modified N+ polysilicon layer 306A, thereby forming the N+ polysilicon emitter region 306B and the residual polysilicon region 306C beneath the boron-doped silicon cap 312A, with a gap 316 between the two regions. In one such embodiment, the etching process is a wet etching process that is hindered by boron-doped silicon but beneficial for etching N+ silicon, such as hydroxide-based wet etching.

[0068] refer to Figure 3D And referring to the corresponding operation 508 in flowchart 500, this method includes etching. Figure 3B The structure is designed to remove the boron-doped silicon cap 312A and leave the residual polysilicon region 306D. In one embodiment, the dopant of the N+ polysilicon layer 306 is concentrated at the top of the layer, such that the residual polysilicon region 306D is substantially undoped. In one embodiment, the residual polysilicon region 306D is laterally spaced from the N+ polysilicon emitter region 306B, for example, at a spacing of about 20 micrometers at location 316A. In one embodiment, the residual polysilicon region 306D is a discrete island surrounded by the N+ polysilicon emitter region 306B. In one such embodiment, the discrete island is substantially circular in plan view, or has another discrete shape, such as a square or rectangle. In another embodiment, the residual polysilicon region 306D is linear. In one embodiment, the total area of ​​the N+ polysilicon emitter region 306B on the entire back surface of the solar cell accounts for more than 90% of the surface area of ​​the back surface of the solar cell substrate (i.e., the total area of ​​the residual polysilicon region 306D accounts for less than 10% of the surface area of ​​the back surface of the solar cell substrate).

[0069] In an embodiment, Figure 3CThe etching is a boron-selective polysilicon etching, while Figure 3D The etching process thins the central point-like structure, which is non-selective for boron. In the embodiment, in Figure 3C and Figure 3D After etching, the thin dielectric layer 304 remains continuous, as depicted. In another embodiment, in Figure 3C and Figure 3D After etching, the exposed portion of the thin dielectric layer 304 is removed, thereby exposing a portion of the substrate 302, for example... Figure 4A As illustrated in the example. In the embodiment, in Figure 3C and Figure 3D After etching, the vertical thickness of the residual polysilicon region 306D is 10% to 50% smaller than the vertical thickness of the N+ polysilicon emitter region 306B. In an embodiment, in Figure 3C and Figure 3D After etching, the vertical thickness of the residual polysilicon region 306D is approximately 160 nanometers, and the vertical thickness of the N+ polysilicon emitter region 306B is approximately 220 nanometers.

[0070] In an embodiment, referring to operation 510 of flowchart 500, the method further includes doping the residual polysilicon region 306D to form a P+ polysilicon emitter region. In one embodiment, the boron-doped silicate glass (BSG) layer is... Figure 3D The structure is formed on top of the annealing process, allowing boron dopant to penetrate the residual polysilicon region 306D. This BSG layer can be retained in the final structure, for example, as described below. Figure 4A Layer 411. In a specific embodiment, this second BSG layer may dope the exposed surface of the substrate, for example, to form the layer described below. Figure 4A Regions 409A and 409B. Subsequent processing may include forming conductive contacts to contact the formed P+ polysilicon emitter regions.

[0071] As an example of a solar cell Figure 4A Solar cells according to embodiments of the present disclosure are shown (e.g., according to...) Figures 3A-3D A cross section of a solar cell made using the method described above. Figure 4B An embodiment according to this disclosure is shown. Figure 4A An exemplary layout of multiple circular trenches surrounding multiple polycrystalline silicon structures in a solar cell. It should be understood that the processes and solar cells described below can be used with reference to... Figures 1A-1C , Figures 2A-2B , Figures 3A-3D and Figure 5 The manufacturing process is carried out using one or more of the aforementioned process operations, material schemes, or operating schemes.

[0072] In one embodiment, the solar cell 400 includes a substrate 401, a tunnel oxide 403, an n-type doped polycrystalline silicon 405, a p-type doped polycrystalline silicon 4071, trenches 408a and 408b, doped regions 409a and 409b, an insulating layer 411, an insulating layer 413, a wiring layer 415, and a wiring layer 417.

[0073] refer to Figure 4AA substrate 401 is formed thereon on which a semiconductor layer, an insulating layer, and a wiring layer of a solar cell 400 are formed. In one embodiment, a tunnel oxide 403 is formed on the surface of the substrate 401 and includes a space through which doped regions 409a and 409b are formed, and an insulating layer 413 is formed in the space. In one example, a p-type doped polysilicon layer 4071 is formed on a portion of the tunnel oxide 403, which exists between portions of the tunnel oxide 403 below the laterally positioned portions of the n-type doped polysilicon layer 405. In one example, the p-type doped polysilicon layer 4071 includes a side surface covered by the insulating layer 413 and a top surface partially covered by the insulating layer 413. Additionally, in one embodiment, the p-type doped polysilicon layer 4071 contacts the wiring layer 415 on its top surface through a space in the insulating layer 413. In one example, an n-type doped polysilicon layer 405 is formed on the surface of tunnel oxide 403 and is laterally separated from p-type doped polysilicon layer 4071 by a portion of insulating layer 413 extending into the space of tunnel oxide 403 (on both sides of p-type doped polysilicon layer 4071). In one embodiment, a doped region 409a is formed in the surface of substrate 401, below a portion of insulating layer 413 extending into the first space of tunnel oxide 403. In one embodiment, doped region 409a extends laterally below the portions of tunnel oxide 403 formed below p-type doped polysilicon layer 4071 and the portions of tunnel oxide 403 formed below n-type doped polysilicon layer 405. In one embodiment, a doped region 409b is formed in the surface of substrate 401, below a portion of insulating layer 413 extending into the second space of tunnel oxide 403. In one embodiment, the doped region 409b extends laterally beneath the portions of tunnel oxide 403 formed below the p-type doped polysilicon layer 4071 and the portions of tunnel oxide 403 formed below the n-type doped polysilicon layer 405. In one embodiment, an insulating layer 413 is formed above the insulating layer 411, along the bottom and sidewalls of trenches 408a and 408b (which are located above the doped regions 409a and 409b), and on the top surface of the p-type doped polysilicon layer 4071. In one embodiment, the insulating layer 413 includes openings above the p-type doped polysilicon layer 4071 and the n-type doped polysilicon layer 405, which allow the p-type doped polysilicon layer 4071 and the n-type doped polysilicon layer 405 to contact wiring layers 415 and 417, respectively, wherein various overlaps of such layers may exist in the final structure. In one embodiment, an insulating layer 411 is formed over an n-type doped polysilicon layer 405 and includes an opening over the n-type doped polysilicon layer 405 that allows the n-type doped polysilicon layer to contact the wiring layer 417.In one embodiment, trenches 408a and 408b are trenches surrounding a p-type doped polysilicon layer 4071 (e.g., reference). Figure 4B The groove 4081 described is the cross-sectional portion on both sides.

[0074] refer to Figure 4A In one embodiment, wiring layer 415 may occupy a larger area than p-type doped polysilicon layer 4071. However, in other embodiments, wiring layer 415 may be limited to the area occupied by p-type doped polysilicon layer 4071, or to the area occupied by p-type doped polysilicon layer 4071 and the area occupied by p-type doped regions 409a and 409b. In one embodiment, limiting wiring layer 415 to a p-type conductive semiconductor region may involve using a larger p-type semiconductor region. In other embodiments, limiting wiring layer 415 to a p-type conductive semiconductor region may not involve using a larger p-type semiconductor region. In one embodiment, wiring layer 415 may be limited to a p-type semiconductor region that does not have a continuous or adjacent configuration but may have a cell architecture with module interconnects, which may include, but are not limited to, conductive circuit boards, such as conductive circuit boards for metallized wrapped (MWT) solar cells and interdigitated back contact (IBC) solar cells.

[0075] refer to Figure 4B In one embodiment, Figure 4A The trenches 408a and 408b shown are cross-sectional portions of opposite sides of trench 4081 formed around the p-type doped polycrystalline silicon layer 4071 and above the doped region 4091. Furthermore, in one embodiment, trench 4081 is formed on one of the plurality of polycrystalline silicon islands 4071-407 in the solar cell 400. n Multiple surrounding trenches 4081-408 n One of them (in) Figure 4B In the middle, the arrow indicates trench 4081-408. n Compared to the doped region 4091-409 n (Location). In one embodiment, the trench may have a shape including, but not limited to, circular, rectangular, elongated, elliptical, polygonal, and irregular shapes. In one embodiment, polycrystalline silicon islands 4071-407 n Used as an emitter, its surface region is part of the surface region of the n-type doped polysilicon layer 405 (emitter). In one embodiment, trenches 4081-408 n It is self-aligned. In one embodiment, the trenches formed by self-alignment can be narrower than those achievable through some other processes. In one embodiment, because the diffusion trenches can form part of a surface region that may undergo a high level of composite, narrow trenches can have a beneficial effect on composite and performance.

[0076] In one embodiment, polycrystalline silicon islands 4071-407 n These are multiple p-type conductive, non-adjacent doped polysilicon regions formed within the laser processing region of a semiconductor structure. In one embodiment, the semiconductor regions with p-type polarity (e.g., 4071-407...) n The associated wiring layer 415 ( Figure 4A (However, in some other embodiments, overlap between a semiconductor region of one polarity and a metallization structure associated with a semiconductor region of another polarity is avoided.)

[0077] In one embodiment, substrate 401 may be formed of silicon. In other embodiments, substrate 401 may be formed of other materials. In one embodiment, tunnel oxide 403 may be formed of silicon oxide. In other embodiments, tunnel oxide 403 may be formed of other materials. In one embodiment, doped polysilicon layer 405 may be doped with phosphorus. In other embodiments, doped polysilicon layer 405 may be doped with other impurities. In one embodiment, doped polysilicon layer 4071 may be doped with boron. In other embodiments, doped polysilicon layer 4071 may be doped with other impurities. In one embodiment, doped regions 409a and 409b may be doped with boron. In other embodiments, doped regions 409a and 409b may be doped with other materials. In one embodiment, insulating layer 411 may comprise boron-doped silicate glass (hereinafter referred to as "BSG"). In other embodiments, insulating layer 411 may comprise other materials. In one embodiment, insulating layer 413 may comprise silicon nitride (hereinafter referred to as "SiN"). In other embodiments, insulating layer 413 may comprise other materials. In one embodiment, wiring layer 415 may comprise aluminum, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, tin, platinum, and tantalum. In other embodiments, wiring layer 415 may comprise other materials. In one embodiment, wiring layer 417 may comprise aluminum, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, tin, platinum, and tantalum. In other embodiments, wiring layer 417 may comprise other materials.

[0078] Refer again Figure 4A and Figure 4B According to an embodiment of this disclosure, a solar cell 400 includes a substrate 401 having a light-receiving surface and a back surface. A first polycrystalline silicon emitting region 405 of a first conductivity type is provided on a first thin dielectric layer 403 on the back surface of the substrate 401. A second polycrystalline silicon emitting region 4071 of a different second conductivity type is provided on a second thin dielectric layer on the back surface of the substrate 401. The vertical thickness of the second polycrystalline silicon emitting region 4071 is less than the vertical thickness of the first polycrystalline silicon emitting region.

[0079] In one embodiment, the second polysilicon emitter region 4071 includes a plurality of discrete islands 407 surrounded by the first polysilicon emitter region 405. n As depicted. In one such embodiment, each of the plurality of discrete islands is substantially circular in shape when viewed in a plan view, as depicted. In another embodiment, the second polysilicon emitter region 4071 comprises a plurality of lines alternating with the lines (not depicted) of the first polysilicon emitter region 405.

[0080] In one embodiment, the first polysilicon emitter region 405 occupies more than 90% of the surface area of ​​the back surface of the substrate 401.

[0081] In one embodiment, the first polysilicon emitter region 405 is n-type and the second polysilicon emitter region 4071 is p-type. In another embodiment, the first polysilicon emitter region 405 is p-type and the second polysilicon emitter region 4071 is n-type.

[0082] In one embodiment, the first thin dielectric layer 403 is discontinuous with the second thin dielectric layer, as depicted. In another embodiment, the first thin dielectric layer 403 is continuous with the second thin dielectric layer (in... Figure 4A Not depicted in the text, but examples of it are already available. Figure 3D (Depicted in Chinese).

[0083] In one embodiment, the vertical thickness of the second polysilicon emitter region 4071 is 10% to 50% smaller than the vertical thickness of the first polysilicon emitter region 405. In one embodiment, the vertical thickness of the second polysilicon emitter region 4071 is approximately 160 nanometers, and the vertical thickness of the first polysilicon emitter region 405 is approximately 200 nanometers.

[0084] In one embodiment, the second polysilicon emitter region 4071 is laterally spaced from the first polysilicon emitter region 405 by approximately 20 micrometers.

[0085] In one embodiment, the solar cell further includes a first conductive contact structure 417 electrically connected to a first polycrystalline silicon emitter region 405 and a second conductive contact structure 415 electrically connected to a second polycrystalline silicon emitter region 4071.

[0086] In operation, when exposed to light, solar cell 400 converts light energy into electrical energy based on the photovoltaic effect. Some charge carriers reach the pn junction and contribute to the current generated by solar cell 400. However, other charge carriers recombine and do not contribute net to the current generated by solar cell 400. Charge carrier recombination is a crucial factor determining the efficiency of solar cells. The diffusion trenches are likely the worst part of the surface of solar cell 400 for recombination. However, in one embodiment, the narrowness of the diffusion trenches 408a and 408b, achieved through a self-aligned process, is beneficial for charge carrier recombination in this part of the surface of solar cell 400. Metal contact doped regions are another important source of charge carrier recombination. In one embodiment, solar cell 400 does not employ a metal structure that directly contacts any part of the substrate 401. Therefore, the design of this solar cell 400 limits the opportunities for charge carrier recombination that may exist in solar cells of different designs. In one embodiment, limiting the opportunities for charge carrier recombination can have a beneficial effect on both charge carrier recombination and solar cell efficiency.

[0087] According to one or more embodiments of this disclosure, SEM cross-sections can be used to detect polycrystalline silicon regions within a P-type region having a small ring without polycrystalline silicon, and a thickness difference between the P-type polycrystalline silicon and the surrounding area. In one embodiment, the method is applicable to IBC solar cells. In one embodiment, the method is applicable to front-contact solar cells.

[0088] According to one or more embodiments of this disclosure, the process described herein enables the formation of polycrystalline silicon in a P-type region. An etch-back version of this process uses pre-doped N-type polycrystalline silicon. Pre-doping requires etch-back of the dotted structure using a non-boron-selective chemical method. Pre-doped N-type polycrystalline silicon can mitigate space charge recombination problems. This method could be used in front-contact cells to form polycrystalline silicon aligned with grid lines.

[0089] Therefore, one or more embodiments described herein relate to forming P+ and N+ polycrystalline silicon emitter regions in a solar cell, wherein the respective arrangements of the P+ and N+ polycrystalline silicon emitter regions differ from each other. This approach can be used to simplify the manufacturing process of solar cells. Furthermore, the resulting structure may have lower breakdown voltage and lower power loss compared to other solar cell architectures.

[0090] While specific materials have been described in detail in the above embodiments, some materials can be easily replaced by other materials, and such embodiments remain within the spirit and scope of this disclosure. For example, in the embodiments, substrates of different materials, such as group III-V material substrates, can be used instead of silicon substrates. Furthermore, although this document primarily refers to back-contact solar cell arrangements, it should be understood that the methods described herein can also be applied to front-contact solar cells. In other embodiments, the above methods can be applied to the manufacture of products other than solar cells. For example, the manufacture of light-emitting diodes (LEDs) can benefit from the methods described herein. Moreover, it should be understood that although N+ and P+ type doping has been specifically described herein, other embodiments covering opposite conductivity types, such as P+ and N+ type doping respectively, are also conceivable.

[0091] Furthermore, in embodiments, clustered plasma-enhanced chemical vapor deposition (PECVD) tools can be used to combine the aforementioned numerous process operations into a single run of the tool. For example, in one such embodiment, up to four different PECVD operations and one RTP operation can be performed in a single run of the cluster tool. PECVD operations can include layer deposition (e.g., the aforementioned back N+ polysilicon layer).

[0092] Therefore, this paper discloses a method for manufacturing solar cell emitter regions with differentiated P-type and N-type layouts and employing point diffusion, as well as the solar cells manufactured thereby.

[0093] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of this disclosure, even where only a single embodiment is described with respect to a particular feature. Unless otherwise stated, the examples of features provided in this disclosure are intended to be illustrative rather than restrictive. The above description is intended to cover such alternatives, modifications, and equivalents that will be apparent to those skilled in the art as to benefit from this disclosure.

[0094] The scope of this disclosure includes any feature or combination of features disclosed herein (expressly or implicitly), or any generalization thereof, whether or not it improves any or all of the problems described herein. Therefore, new claims may be formulated during the examination of any such combination of features of this application (or an application claiming priority thereto). In particular, referring to the appended claims, features of dependent claims may be combined with features of independent claims, and features of corresponding independent claims may be combined in any suitable manner, not limited to the specific combinations listed in the appended claims.

[0095] The following examples relate to other embodiments. Various features of different embodiments can be combined in various ways, including including some features while excluding others, to suit a variety of different applications.

[0096] Example Embodiment 1: A solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitting region of a first conductivity type is provided on a first thin dielectric layer on the back surface of the substrate. A second polycrystalline silicon emitting region of a different second conductivity type is provided on a second thin dielectric layer on the back surface of the substrate. The vertical thickness of the second polycrystalline silicon emitting region is less than the vertical thickness of the first polycrystalline silicon emitting region.

[0097] Example 2: A solar cell according to Example 1, wherein the second polycrystalline silicon emitter region comprises a plurality of discrete islands surrounded by the first polycrystalline silicon emitter region.

[0098] Example 3: A solar cell according to Example 2, wherein, viewed from a plan view, each of the plurality of discrete islands has a substantially circular shape.

[0099] Example 4: A solar cell according to Example 1, wherein the second polycrystalline silicon emitter region includes multiple lines that alternate with the lines of the first polycrystalline silicon emitter region.

[0100] Example 5: A solar cell according to Example 1, 2, 3 or 4, wherein the first polycrystalline silicon emitting region occupies more than 90% of the surface area of ​​the back surface of the substrate.

[0101] Example 6: A solar cell according to Example 1, 2, 3, 4 or 5, wherein the first polycrystalline silicon emitter is n-type and the second polycrystalline silicon emitter is p-type.

[0102] Example 7: A solar cell according to Example 1, 2, 3, 4 or 5, wherein the first polycrystalline silicon emitter is p-type and the second polycrystalline silicon emitter is n-type.

[0103] Example 8: A solar cell according to Example 1, 2, 3, 4, 5, 6 or 7, wherein the first thin dielectric layer and the second thin dielectric layer are discontinuous.

[0104] Example 9: A solar cell according to Example 1, 2, 3, 4, 5, 6 or 7, wherein the first thin dielectric layer is continuous with the second thin dielectric layer.

[0105] Example 10: A solar cell according to Example 1, 2, 3, 4, 5, 6, 7, 8 or 9, wherein the vertical thickness of the second polycrystalline silicon emitter is 10% to 50% smaller than the vertical thickness of the first polycrystalline silicon emitter.

[0106] Example 11: A solar cell according to Example 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10, wherein the vertical thickness of the second polycrystalline silicon emitter is approximately 160 nanometers and the vertical thickness of the first polycrystalline silicon emitter is approximately 200 nanometers.

[0107] Example 12: A solar cell according to Example 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, wherein the second polycrystalline silicon emitter region is laterally spaced from the first polycrystalline silicon emitter region by about 20 micrometers.

[0108] Example 13: A solar cell according to Example 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12 further includes a first conductive contact structure electrically connected to a first polycrystalline silicon emitter region and a second conductive contact structure electrically connected to a second polycrystalline silicon emitter region.

[0109] Example 14: A method of manufacturing a solar cell includes: forming an N+ polycrystalline silicon layer on a thin dielectric layer on the back surface of a substrate; forming a boron-doped silicate glass (BSG) layer on the N+ polycrystalline silicon layer; forming an amorphous silicon (aSi) layer on the BSG layer; performing laser ablation to form openings in the aSi layer and the BSG layer, doping regions of the N+ polycrystalline silicon layer, and exposing unmodified external regions of the N+ polycrystalline silicon layer; performing etching to remove the exposed unmodified external regions in the N+ polycrystalline silicon layer, thereby forming an N+ polycrystalline silicon emitter region and a residual polycrystalline silicon region below a boron-doped silicon cap; performing etching to remove the boron-doped silicon cap, leaving the residual polycrystalline silicon region; and doping the residual polycrystalline silicon region to form a P+ polycrystalline silicon emitter region.

[0110] Example 15: The method according to Example 14, wherein laser ablation is performed using a green laser with a flat-top profile.

[0111] Example 16: The method according to Example 14 or 15, wherein forming the opening includes forming a discrete circle.

[0112] Example 17: The method according to Example 14 or 15, wherein forming an opening includes forming a linear shape.

[0113] Example 18: A method of manufacturing a solar cell includes: providing a substrate having a light-receiving surface and a back surface; forming a first polycrystalline silicon emitting region of a first conductivity type on a first thin dielectric layer on the back surface of the substrate; and forming a second polycrystalline silicon emitting region of a different second conductivity type on a second thin dielectric layer on the back surface of the substrate, wherein the vertical thickness of the second polycrystalline silicon emitting region is less than the vertical thickness of the first polycrystalline silicon emitting region.

[0114] Example 19: According to the method of Example 18, forming the second polysilicon emitter region includes forming a plurality of discrete islands surrounded by the first polysilicon emitter region.

[0115] Example 20: According to the method of Example 18, forming the second polysilicon emitter region includes forming a plurality of lines that alternate with the lines of the first polysilicon emitter region.

Claims

1. A solar cell, comprising: A substrate having a light-receiving surface and a back surface; A first polysilicon emitter of a first conductivity type is located on a first thin dielectric layer on the back surface of the substrate. as well as A second polysilicon emitter region of a different second conductivity type, the second polysilicon emitter region being on a second thin dielectric layer on the back surface of the substrate, the vertical thickness of the second polysilicon emitter region being less than the vertical thickness of the first polysilicon emitter region.

2. The solar cell according to claim 1, wherein, The second polysilicon emitter region includes a plurality of discrete islands surrounded by the first polysilicon emitter region.

3. The solar cell according to claim 2, wherein, From the plan view, each of the plurality of discrete islands has a substantially circular shape.

4. The solar cell according to claim 1, wherein, The second polysilicon emitter region includes multiple lines that alternate with the lines of the first polysilicon emitter region.

5. The solar cell according to claim 1, wherein, The first polysilicon emitter region occupies more than 90% of the surface area of ​​the back surface of the substrate.

6. The solar cell according to claim 1, wherein, The first polysilicon emitter region is n-type, and the second polysilicon emitter region is p-type.

7. The solar cell according to claim 1, wherein, The first polysilicon emitter region is p-type, and the second polysilicon emitter region is n-type.

8. The solar cell according to claim 1, wherein, The first thin dielectric layer and the second thin dielectric layer are discontinuous.

9. The solar cell according to claim 1, wherein, The first thin dielectric layer is continuous with the second thin dielectric layer.

10. The solar cell according to claim 1, wherein, The vertical thickness of the second polysilicon emitter region is 10% to 50% smaller than that of the first polysilicon emitter region.

11. The solar cell according to claim 1, wherein, The vertical thickness of the second polysilicon emitter region is approximately 160 nanometers, and the vertical thickness of the first polysilicon emitter region is approximately 200 nanometers.

12. The solar cell according to claim 1, wherein, The second polysilicon emitter region is laterally spaced from the first polysilicon emitter region by approximately 20 micrometers.

13. The solar cell according to claim 1, further comprising: A first conductive contact structure is electrically connected to the first polysilicon emitter region; as well as The second conductive contact structure is electrically connected to the second polysilicon emitter region.

14. A method for manufacturing a solar cell, the method comprising: An N+ polysilicon layer is formed on a thin dielectric layer on the back surface of the substrate; A boron-doped silicate glass (BSG) layer is formed on the N+ polycrystalline silicon layer; An amorphous silicon (aSi) layer is formed on the BSG layer; Laser ablation is performed to form openings in the aSi layer, doping regions of the N+ polysilicon layer and exposing unmodified external regions of the N+ polysilicon layer. Etching is performed to remove the exposed external unmodified regions in the N+ polysilicon layer, thereby forming the N+ polysilicon emitter region and the residual polysilicon region under the boron-doped silicon cap. Etching is performed to remove the boron-doped silicon cap and leave the residual polysilicon region. as well as The residual polysilicon region is doped to form a P+ polysilicon emitter region.

15. The method according to claim 14, wherein, The laser ablation is performed using a green laser with a flat-top profile.

16. The method of claim 14, wherein, Forming the opening includes forming discrete circles.

17. The method of claim 14, wherein, Forming the opening includes forming a linear shape.

18. A method for manufacturing a solar cell, the method comprising: Provide a substrate having a light-receiving surface and a back surface; A first polysilicon emitter region of a first conductivity type is formed on a first thin dielectric layer on the back surface of the substrate; as well as A second polysilicon emitter region of a different second conductivity type is formed on a second thin dielectric layer on the back surface of the substrate, and the vertical thickness of the second polysilicon emitter region is less than the vertical thickness of the first polysilicon emitter region.

19. The method according to claim 18, wherein, Forming the second polysilicon emitter region includes forming a plurality of discrete islands surrounded by the first polysilicon emitter region.

20. The method according to claim 18, wherein, Forming the second polysilicon emitter region includes forming multiple lines that alternate with the lines of the first polysilicon emitter region.

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