A circuit and method for sampling and transmitting telemetry data from a cochlear implant.

Abstract

This invention provides a circuit and method for sampling and transmitting telemetry data from a cochlear implant, belonging to the field of telemetry technology for cochlear implants. The method amplifies the analog signal under test using a programmable gain amplifier, converts the signal into a pulse width signal using a voltage ramp generator and comparator, and then generates a short-duration step signal on the coil via an output driver to form a ringing pattern. An external device detects the interval between the step signals to reconstruct the signal magnitude. This invention eliminates the need for an analog-to-digital converter, significantly reducing power consumption and chip area, and improving data transmission efficiency. It is suitable for telemetry systems in various implantable medical devices such as cochlear implants. This invention significantly reduces the power consumption and layout area of ​​the implanted chip and shortens the single data transmission time to 48μs, improving efficiency by approximately 10 times, making it suitable for low-power implantable devices such as cochlear implants.

Description

Technical Field

[0001] This invention belongs to the field of cochlear implant telemetry technology, and particularly relates to a cochlear implant telemetry data sampling and transmission circuit and method. Background Technology

[0002] A cochlear implant is an implantable electronic device used to restore hearing. It typically requires the acquisition of neural response signals from the cochlea, such as telemetry recording of the evoked compound action potential (ECAP) signal induced by the electrodes implanted in the cochlea. ECAP signals have relatively small amplitudes (tens of μV to a few mV). Traditional methods use a programmable gain amplifier (PGA) to amplify the signal, then convert it into a digital signal via an analog-to-digital converter (ADC). This digital signal is then encoded into a specific sequence and transmitted to an external device via load modulation or other methods using a coupling coil. The external device then decodes the signal to reconstruct the information. For example, US Patent Publication No. US11998741B2, entitled "Charge Compensation Circuit for Nerve Stimulation," discloses the use of an ADC to convert analog signals into digital control signals. In addition to the ECAP signal, it is usually necessary to telemetry other parameters within the implanted chip, such as power supply voltage, electrode voltage, and internal current.

[0003] However, ADC modules consume a lot of power and occupy a large chip area. Furthermore, when acquiring ECAP signals, the carrier energy supply must be stopped, relying solely on the energy storage capacitor for operation, resulting in limited sampling time and low transmission efficiency. Therefore, there is an urgent need for a low-power, small-area, and high-efficiency telemetry data sampling and transmission solution. Summary of the Invention

[0004] This invention provides a circuit and method for sampling and transmitting telemetry data from a cochlear implant, which avoids the use of an ADC and instead converts the analog signal into a pulse width signal, which is transmitted to the external device via a coil. The external device detects the width of the pulse width signal to reconstruct the corresponding voltage or current magnitude.

[0005] To achieve the above objectives, the technical solution of the present invention is: a method for sampling and transmitting telemetry data from a cochlear implant, comprising the following steps:

[0006] The analog signal to be tested is amplified in the implanted body using a programmable gain amplifier (PGA).

[0007] The amplified signal is input to the positive input terminal of the comparator (CMP);

[0008] A ramp voltage is generated using a voltage ramp generator and input to the negative input terminal of the comparator.

[0009] The amplified signal is compared with the ramp voltage by the comparator, and a pulse width signal is output.

[0010] The pulse width signal is converted into a step signal by the output driver and then coupled to the external unit coil. The external unit detects the interval time of the step signal and reconstructs the magnitude of the simulated signal under test based on the interval time.

[0011] Furthermore, the analog signal to be tested includes at least one of the following: ECAP signal, power supply voltage, electrode voltage, or internal current.

[0012] Furthermore, the voltage ramp generator includes a current source and a capacitor, the current source charging the capacitor to generate the ramp voltage.

[0013] Furthermore, the above method also includes a step of calibrating the current source:

[0014] Disconnect the PGA from the comparator and connect the reference voltage to the positive input terminal of the comparator;

[0015] Adjust the current value of the current source so that the ramp voltage reaches the reference voltage within a predetermined time.

[0016] Furthermore, the width of the pulse width signal is proportional to the magnitude of the analog signal under test.

[0017] Furthermore, the pulse width signal is transmitted to the implant coil via a DC blocking capacitor to form the step signal, which is then coupled to the external machine coil. The external machine detects the time interval between the two step signals and subtracts the initialization time to obtain the ramp voltage rise time, and then calculates the magnitude of the simulated signal to be measured.

[0018] The present invention also provides a circuit structure for sampling and transmitting telemetry data from a cochlear implant, comprising:

[0019] PGA is used to receive and amplify the analog signal under test;

[0020] A voltage ramp generator is used to generate a ramp voltage.

[0021] The comparator has its positive input connected to the output of the PGA and its negative input connected to the output of the voltage ramp generator.

[0022] An output driver, connected to the output of the comparator, is used to convert the pulse width signal output by the comparator into a step signal. The step signal generates ringing on the coil, and the external machine restores the analog signal under test by detecting the step signal interval.

[0023] Furthermore, the voltage ramp generator includes a current source and a capacitor, wherein the current source charges the capacitor to generate a ramp voltage, the current source having a current range of 0.1μA to 1μA, and the capacitor having a size range of 1pF to 10pF.

[0024] Furthermore, the circuit also includes a switching network for connecting a reference voltage to the positive input of the comparator in calibration mode.

[0025] Furthermore, the output driver is a low-impedance driver with an output resistance of less than 100Ω, preferably less than 50Ω, and the output terminal of the output driver is connected to the implant receiving coil through a DC blocking capacitor.

[0026] The beneficial effects of this invention are:

[0027] This invention amplifies the analog signal under test using a PGA; converts the amplified signal into a pulse width signal using a voltage ramp generator and a comparator; generates a short-duration step signal on the coil through an output driver to form a ringing signal; and detects the interval of the step signal in an external device to reconstruct the signal. The circuit structure of this invention eliminates the need for an ADC module, significantly reducing power consumption and chip area while improving data transmission efficiency. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the circuit structure of the present invention;

[0029] Figure 2 This is a timing diagram of the operation of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0031] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0032] This invention provides a method for sampling and transmitting telemetry data from a cochlear implant, comprising the following steps: amplifying the simulated signal to be measured within the implant using a PGA; inputting the amplified signal to the positive input of a comparator; generating a ramp voltage using a voltage ramp generator and inputting it to the negative input of the comparator; comparing the amplified signal with the ramp voltage using the comparator and outputting a pulse width signal; transmitting the pulse width signal to the implant coil via a DC blocking capacitor using an output driver to form the step signal, which is then coupled to the external device coil; and calculating the magnitude of the simulated signal to be measured by detecting the time interval between two step signals and subtracting the initialization time from it.

[0033] The analog signal to be tested in this embodiment includes at least one of the following: ECAP signal, power supply voltage, electrode voltage, or internal current.

[0034] The voltage ramp generator described in this embodiment includes a current source and a capacitor, wherein the current source charges the capacitor to generate the ramp voltage.

[0035] The method described in this embodiment further includes a step of calibrating the current source: disconnecting the PGA from the comparator and connecting the reference voltage to the positive input terminal of the comparator; adjusting the current value of the current source so that the ramp voltage reaches the reference voltage within a predetermined time.

[0036] In this embodiment, the width of the pulse width signal is proportional to the magnitude of the analog signal under test.

[0037] In this embodiment, the external machine detects the time interval between two step signals and subtracts the initialization time to obtain the ramp voltage rise time, and then calculates the magnitude of the simulated signal to be measured.

[0038] Embodiment 2 of the present invention provides a circuit structure for sampling and transmitting telemetry data of a cochlear implant, comprising: a PGA for receiving and amplifying the analog signal to be measured; a voltage ramp generator for generating a ramp voltage; a comparator, the positive input of which is connected to the output of the PGA and the negative input of which is connected to the output of the voltage ramp generator; an output driver connected to the output of the comparator for converting the pulse width signal output by the comparator into a step signal; and a DC blocking capacitor connected to the output of the output driver and the implant receiving coil. The external device detects the time interval between two step signals and subtracts the initialization time to obtain the ramp voltage rise time, and then calculates the magnitude of the analog signal to be measured.

[0039] The voltage ramp generator described in this embodiment includes a current source and a capacitor, wherein the current source charges the capacitor to generate a ramp voltage.

[0040] The circuit described in this embodiment further includes a switching network for connecting a reference voltage to the positive input terminal of the comparator in calibration mode. The output driver in this embodiment is a low-impedance driver, with an output resistance of less than 100Ω. Figure 1 and Figure 2 As shown, the circuit structure in this embodiment includes a PGA, a comparator CMP, a voltage ramp generator, an output driver, and a DC blocking capacitor C2. The input of the PGA can be connected to the ECAP signal, power supply voltage, electrode voltage, or internal current. The output of the PGA is connected to the positive input terminal V of the comparator via switch S1. P The voltage ramp generator consists of a current source and capacitor C1, and its output is connected to the negative input terminal V of the comparator. N The comparator output V1 is driven by logic gates and an inverting driver, and then coupled to the coil through the DC blocking capacitor C2.

[0041] Working principle: The connection point between the current source and capacitor C1 in the voltage ramp generator is connected to the negative input terminal V of the comparator. N The input to the PGA can be an ECAP signal, power supply voltage, electrode voltage, or internal current, etc. After the signal is amplified by the PGA, it is connected to the positive input terminal V of the comparator through switch S1. P The comparator output is V1. CLK is the clock signal; when CLK is high, the entire system operates normally; when CLK is low, the system is in a shutdown state. The timing diagram is attached. Figure 2 As shown, firstly, CLK rises from low to high, while the comparator output V1 remains high initially. This causes V2 to generate a falling edge, which, after passing through the inverting driver composed of N1 and P1, generates a rising edge on the inverting driver output V3. Then, V3 is connected to the positive terminal of the implant's receiving coil via the DC blocking capacitor C2, i.e., the system output V... OUT When the receiving coil of the implant is connected, a short-duration step signal in the positive direction will be generated on both the receiving coil of the implant and the transmitting coil of the external device, exhibiting exponentially decaying ringing at the resonant frequency. After the initialization time t1, the current source in the voltage ramp generator begins to charge capacitor C1, when V N Voltage exceeding V P At this time, a falling edge is generated on V3, resulting in a negative step signal on the coil, forming the second ringing. The external machine detects the time interval between the two step signals on the coil. Subtracting time t1 from this time interval yields the ramp voltage rise time t2. This is calculated using the following formula:

[0042]

[0043] The PGA output signal V can then be obtained. P Size. V PDividing by the PGA amplification factor gives the magnitude of the detected signal. Here, t1 is the initialization time used for PGA signal amplification, t3 is the full-scale voltage ramp time, and t4 is the duration of the entire cycle.

[0044] At work, such as Figure 1 , Figure 2 As shown, the system starts when the CLK signal is high. During the initialization time t1, V1 is high, and the output driver generates a rising edge step, forming the first ringing on the coil. Subsequently, the current source charges C1, and V... N Rise, when V N More than V P When V1 decreases, a falling edge step signal is generated, forming the second ringing. The external instrument detects the time interval t2 between the two step signals and calculates V using the formula. P The magnitude is then divided by the PGA gain to restore the original signal. The PGA input is connected to the ECAP signal, power supply voltage, electrode voltage, or internal current, etc. The PGA output is connected to one end of switch S1, and the other end of switch S1 is connected to the positive input terminal V of the comparator. P Meanwhile, V P It is also connected to one end of switch S2, and the other end of switch S2 is connected to the reference voltage V. REF The comparator's negative input terminal VN is connected to the common terminal of the current source and capacitor C1. The other end of the current source is connected to the power supply, and the other end of capacitor C1 is grounded. The comparator's output terminal V1 is connected to one input terminal of a NAND gate, and the other end of the NAND gate is connected to the clock signal CLK. The NAND gate's output V2 is connected to the input terminal of an inverting driver composed of NMOS transistor N1 and PMOS transistor P1. The source terminal of N1 is grounded, and the source terminal of P1 is connected to the power supply. V3 is connected to one end of DC blocking capacitor C2, and the other end of C2 is connected to V... OUT Connect the positive terminal of the receiving coil of the implant to the positive terminal, and connect one end of the tuning capacitor C3 to VOUT and the other end to ground.

[0045] Assuming the carrier frequency for wireless transmission between the implant and the external unit is 5MHz, the initialization time t1 = 4.8μs, the full-scale voltage ramp time t3 = 38.4μs, and the sampling and transmission period t4 = 48μs, then the minimum inter-pulse detection interval is 4.8µs, and the actual ramp duration is less than or equal to time t3. REF=2V, meaning the maximum full-scale ramp voltage is 2V. Since the carrier frequency is 5MHz, the carrier clock period is 200ns, and t3 is 192 carrier clock periods. Therefore, the ramp time resolution is 200ns / t3 = 200ns / 38.4μs = 0.52%. Under ECAP telemetry conditions, the PGA gain can be selected as 40dB, 60dB, and 70dB; under voltage telemetry conditions, the PGA gain can be selected as 1 / 5, 2 / 5, 1, and 2. The resolution and maximum input signal swing under ECAP telemetry and voltage telemetry conditions are shown in Table 1 below.

[0046] Table 1

[0047]

[0048] Furthermore, assuming the total noise is greater than the typical resolution, if the telemetry performs 100 samplings, then averaging these 100 values ​​can improve the effective resolution by a factor of 10. Under typical conditions, this accuracy is equivalent to an 11-bit ADC.

[0049] The formula for charging a capacitor with a fixed current is as follows:

[0050]

[0051] A current source with a current I of 0.2μA and a capacitor C1 of 3.84pF can be designed. This can ensure current accuracy and also make the layout area occupied by capacitor C1 very small.

[0052] The calibration process for the current source: Due to semiconductor process variations, the values ​​of the current source and capacitor C1 will deviate significantly from the design values. To ensure that the full-scale voltage ramp is V... REF =2V, the full-scale ramp time is t3=38.4μs, meaning the voltage ramp slope is accurate, but the current source magnitude needs adjustment. Switch S1 is open, switch S2 is closed, meaning the comparator's positive input terminal V... P Connect to reference voltage V REF For the first calibration, the current source current was set to its minimum value, and V was recorded. N Rise to V REF The charging time is set such that when the charging time is less than the set time t3, the current value of the current source is continuously increased until it is exactly within time t3, V N Reaching V REF The current of the current source at this time is denoted as I.

[0053] Telemetry output driver parameters: Output driver output V OUT By default, it is in a low-level state, and V OUTConnect to ground. Note that at this point, the DC blocking capacitor C2 is connected in parallel with the implant tuning capacitor C3 and acts as part of the tuning capacitor. Typically, C2 accounts for about 20% of the total tuning capacitor. Therefore, under typical conditions, at VDD=5V, the output resistance of N1 needs to be less than 100Ω, as it will participate in resonance and draw some RF (radio frequency) current.

[0054] In this invention, sampling and data transmission do not require analog-to-digital conversion via an ADC, eliminating a major module and significantly reducing chip area and power consumption. Specifically:

[0055] 1) In terms of power consumption, the power consumption of a PGA is usually around 100uA, while the power consumption of an ADC with 11 effective bits and a sampling rate of 20kS / s is usually tens to hundreds of uA. The current of the voltage ramp generator and the comparator CMP does not exceed 10uA. In this way, eliminating the ADC greatly saves power consumption.

[0056] 2) Regarding the layout area, under the typical parameter conditions mentioned above, the capacitor C1 is 3.84pF, which occupies a relatively small layout area. In addition, the layout area of ​​the current source and comparator CMP is much smaller than that of the ADC.

[0057] Secondly, in the embodiments of this invention, the signals transmitted between the implanted chip and the external device are analog signals rather than digital signals. The implanted chip converts the telemetry signal into a pulse width signal and transmits it to the external device through a coil. The sampling accuracy can reach more than 11 bits, and the return transmission efficiency is high, specifically reflected in:

[0058] 1) In terms of accuracy, as mentioned earlier, under typical conditions, with a PGA gain of 2, a maximum input voltage swing of 1V, and averaging after 100 samplings, the resolution can reach 0.5mV, i.e., 0.5mV / 1V=0.05%, which is equivalent to 11 significant bits.

[0059] 2) Regarding transmission efficiency, traditional load modulation return methods typically require transmitting a 12-bit data bit (the output of a 12-bit ADC; to achieve 11 significant bits, a 12-bit ADC is usually needed). This typically involves transmitting the start bit (4 bits), data bit (12 bits), parity bit (1 bit), and stop bit (2 bits) sequentially, totaling 19 bits. To ensure load modulation stability, transmitting 1 bit of data generally requires 128 carrier cycles, with one carrier cycle being 200 ns, resulting in a total transmission time of 486.4 μs. Using the method proposed in this invention, the transmission time for one data bit is t4 = 48 μs, significantly less than the time required by traditional load modulation return methods.

[0060] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for sampling and transmitting telemetry data from a cochlear implant, characterized in that, Includes the following steps: The analog signal to be tested implanted in the body is amplified by a programmable gain amplifier; The amplified signal voltage is input to the positive input terminal of the comparator; A ramp voltage is generated using a voltage ramp generator and input to the negative input terminal of the comparator. The amplified signal voltage is compared with the ramp voltage by the comparator, and a pulse width signal is output. The output of the comparator is connected to one input of a NAND gate, and the other end of the NAND gate is connected to the clock signal CLK. The output of the NAND gate is connected to the input of an inverting driver composed of an NMOS transistor and a PMOS transistor. The source of the NMOS transistor is grounded, and the source of the PMOS transistor is connected to the power supply. The NAND gate and the inverting driver constitute an output driver. The output of the output driver is connected to one end of a DC blocking capacitor. The other end of the DC blocking capacitor is connected to the positive terminal of the receiving coil of the implant and one end of a tuning capacitor. The other end of the tuning capacitor is grounded. The pulse width signal is converted into a step signal by the output driver and then coupled to the external unit coil. The external unit detects the step signal interval to reconstruct the magnitude of the analog signal under test. Specifically, the external unit detects the time interval between two step signals, subtracts the initialization time to obtain the ramp voltage rise time, and records the initialization time as t1. The amplified signal voltage is calculated according to the formula, and the magnitude of the analog signal under test is obtained by dividing the amplified signal voltage by the amplification factor of the programmable gain amplifier. The formula is: ， Among them, V P t2 is the amplified signal voltage, t3 is the ramp voltage rise time, and t4 is the full-scale voltage ramp time. REF This is the reference voltage.

2. The method for sampling and transmitting telemetry data from an artificial cochlea according to claim 1, characterized in that, The simulated signal to be tested includes at least one of the following: ECAP signal, power supply voltage, electrode voltage, or internal current.

3. The method for sampling and transmitting telemetry data from an artificial cochlea according to claim 1, characterized in that, The voltage ramp generator includes a current source and a capacitor, wherein the current source charges the capacitor to generate the ramp voltage.

4. The method for sampling and transmitting telemetry data from an artificial cochlea according to claim 3, characterized in that, It also includes the step of calibrating the current source: Disconnect the programmable gain amplifier from the comparator and connect the reference voltage to the positive input terminal of the comparator; Adjust the current value of the current source so that the ramp voltage reaches the reference voltage within a predetermined time.

5. The method for sampling and transmitting telemetry data from an artificial cochlea according to claim 1, characterized in that, The width of the pulse width signal is proportional to the magnitude of the analog signal under test.

6. A cochlear implant telemetry data sampling and transmission circuit, used to implement the cochlear implant telemetry data sampling and transmission method according to any one of claims 1-5, characterized in that, include: A programmable gain amplifier is used to receive and amplify the analog signal under test. A voltage ramp generator is used to generate a ramp voltage. The comparator has its positive input connected to the output of the programmable gain amplifier and its negative input connected to the output of the voltage ramp generator. The output of the comparator is connected to one input of a NAND gate, the other end of which is connected to a clock signal CLK. The output of the NAND gate is connected to the input of an inverting driver composed of an NMOS transistor and a PMOS transistor. The source of the NMOS transistor is grounded, and the source of the PMOS transistor is connected to the power supply. The NAND gate and the inverting driver together form an output driver. The output of the output driver is connected to one end of a DC blocking capacitor. The other end of the DC blocking capacitor is connected to the positive terminal of the receiving coil of the implant and one end of a tuning capacitor. The other end of the tuning capacitor is grounded. The output driver is used to convert the pulse width signal output by the comparator into a step signal, and the in vitro machine restores the simulated signal under test by detecting the step signal interval.

7. The cochlear implant telemetry data sampling and transmission circuit according to claim 6, characterized in that, The voltage ramp generator includes a current source and a capacitor. The current source charges the capacitor to generate a ramp voltage. The current source has a current range of 0.1μA to 1μA, and the capacitor has a size range of 1pF to 10pF.

8. The cochlear implant telemetry data sampling and transmission circuit according to claim 6, characterized in that, It also includes a switching network for connecting a reference voltage to the positive input of the comparator in calibration mode.

9. The cochlear implant telemetry data sampling and transmission circuit according to claim 8, characterized in that, The output driver is a low-impedance driver with an output resistance of less than 100Ω. The output terminal of the output driver and the implant receiving coil are connected through a DC blocking capacitor.

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