Method for testing saturation current of IO port

Abstract

The invention provides a method for testing the saturation current of an IO port, and the method comprises the steps: a, measuring a first average current flowing through a source input end corresponding to an MOS tube when the MOS tube in the IO port is in a cut-off state; b, an MOS tube in the IO port is controlled to be switched between a conduction stage and a cut-off stage, and the MOS tube is always in a saturated state in the conduction stage; c, measuring a second average current flowing through the source input end corresponding to the MOS tube in the process of the step b; and d, obtaining the IO port saturation current according to the difference value of the first average current and the second average current and the proportion of the conduction time T1 and the cut-off time T2 of the MOS tube.

Description

Technical Field

[0001] This invention relates to circuit design, and more particularly to a method for testing the saturation current of an I / O port. Background Technology

[0002] As market competition intensifies, MCU manufacturers are integrating commonly used driver chip functions (such as LED driver and IGBT driver functions) into MCUs to highlight their product capabilities. This eliminates the need for related peripheral components and greatly enhances product competitiveness.

[0003] Integrated MCUs involve large I / O drive capabilities, requiring testing during the chip manufacturing process to ensure these capabilities meet design specifications and eliminate defective chips. However, testing the saturation current capability of I / O output drives is challenging due to limitations of conventional testing equipment, which cannot test larger currents (e.g., above 100mA). Even when some equipment can test larger currents, the testing time is lengthy, and prolonged high current can cause the chip to heat up rapidly, further affecting the saturation current test results of the I / O output drives.

[0004] The common practice is to limit the load voltage and convert it to a measurable current by the testing equipment. In this method, the internal MOSFET of the I / O is in the linear region, and the impedance introduced by the equipment cabling and contact impedance will affect the accuracy of the converted current test. Using methods that test current and voltage separately, such as the Kelvin test, can eliminate the impedance introduced by the testing equipment, but the cost is high, and the measured current is the current in the linear region, which cannot reflect the actual saturation current.

[0005] Therefore, there is an urgent need for a method that can test the saturation current of I / O ports with high accuracy and low cost. Summary of the Invention

[0006] In view of the current inability to test saturation current, the present invention provides a method for testing the saturation current of an I / O port.

[0007] The method for testing the saturation current of an I / O port according to the present invention includes, but is not limited to, the following steps:

[0008] a. Measure the first average current flowing through the source input terminal corresponding to the MOSFET when the MOSFET inside the IO port is in the off state;

[0009] b. Control the MOS transistor inside the IO port to switch between the on-phase and off-phase, wherein the MOS transistor is always in a saturated state during the on-phase;

[0010] c. Measure the second average current flowing through the source input terminal corresponding to the MOS transistor during step b;

[0011] d. The saturation current of the I / O port is obtained based on the difference between the first average current and the second average current and the ratio of the on-time T1 to the off-time T2 of the MOSFET.

[0012] In one embodiment, when the MOS transistor is a PMOS transistor, the source input terminal is the VIN terminal, and the IO port saturation current obtained in step d is the IO output saturation current.

[0013] In one embodiment, the IO output saturation current I P Saturation is:

[0014]

[0015] Among them, I H1 Let I be the first average current. H2 This is the second average current.

[0016] In one embodiment, when the MOS transistor is an NMOS transistor, the source input terminal is grounded, and the IO port saturation current obtained in step d is the IO input saturation current.

[0017] In one embodiment, the IO input saturation current I N Saturation is:

[0018]

[0019] Among them, I L1 Let I be the first average current. L2 This is the second average current.

[0020] In one embodiment, the method for controlling the switching of the MOSFET inside the I / O port between the on and off phases includes:

[0021] The MOSFET is switched between the on and off phases by using pulse width modulation and an appropriate duty cycle is set so that it is in the saturation state during the on phase of the MOSFET.

[0022] In one embodiment, during the cutoff phase, the final load voltage of the MOSFET remains consistent.

[0023] In one embodiment, the I / O port is the I / O port of the MCU.

[0024] This invention controls the on / off state of the internal MOSFET of the I / O port using a PWM signal. By setting an appropriate duty cycle, the MOSFET is kept in saturation during the on-state. Repeating this process and measuring the overall average current of the MCU allows the determination of the MOSFET's saturation current. This I / O port saturation current measurement method has low equipment requirements, significantly reducing mass production testing costs and improving measurement accuracy. Attached Figure Description

[0025] The above-described invention and the following detailed description will be better understood when read in conjunction with the accompanying drawings. It should be noted that the drawings are merely examples of the claimed invention. In the drawings, the same reference numerals represent the same or similar elements.

[0026] Figure 1 This diagram illustrates a common IO saturation current testing method for MCUs in the mass production stage in the prior art.

[0027] Figure 2 A schematic diagram illustrating a method for mass-producing and testing the IO saturation current of an MCU according to an embodiment of the present invention is shown.

[0028] Figure 3 The voltage waveform at the C terminal of the load capacitor is shown when the saturation current of the test IO output (PMOS) is reached according to an embodiment of the present invention.

[0029] Figure 4 The voltage waveform at the load capacitor C is shown when the saturation current of the test IO input (NMOS) is reached according to an embodiment of the present invention. Detailed Implementation

[0030] The following detailed description of the features and advantages of the present invention provides sufficient information for any person skilled in the art to understand and implement the invention. Furthermore, based on the specification, claims, and drawings disclosed herein, those skilled in the art can easily understand the related objectives and advantages of the invention. Although the description of the invention is presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may arise based on the claims of the invention. To provide a thorough understanding of the invention, numerous specific details will be included in the following description. The invention may also be implemented without using these details. Moreover, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description.

[0031] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0032] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood as the orientations shown in the relevant paragraphs and accompanying drawings. These relative terms are for illustrative purposes only and do not imply that the described apparatus must be manufactured or operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0033] It is understood that while terms such as "first," "second," and "third" may be used herein to describe various components, channels, assemblies, regions, layers, and / or parts, these components, channels, assemblies, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, channels, assemblies, regions, layers, and / or parts. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0034] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0035] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0036] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0037] More and more MCUs are supporting high driving capabilities (such as infrared code transmission, LED driving, IGBT driving, etc.) in their I / O, and these driving capabilities are becoming increasingly powerful. During the factory testing phase, due to the large current to be tested and the limitations of conventional testing equipment in measuring current, it is not possible to test large currents (such as above 100mA).

[0038] Even if some test equipment can measure high current, the test time is long. Prolonged high current will cause the chip to heat up quickly, which will further affect the saturation current of the IO output drive.

[0039] The common practice is to limit the load voltage and convert it to the current that the test instrument can measure. At this time, the MOSFET of the I / O is in the linear region, and the impedance introduced by the instrument's cabling and contact impedance will affect the accuracy of the converted current test. Using methods that test current and voltage separately, such as the Kelvin test method, can eliminate the impedance introduced by the test instrument's cabling, etc., but the cost is high, and the current tested is the current in the linear region, which cannot reflect the actual current in the saturation region.

[0040] To address the shortcomings of existing technologies, this invention provides a method for testing the saturation current of an I / O port. This method uses a PWM signal to control the on / off state of the internal MOSFET of the I / O port. By setting an appropriate duty cycle, the MOSFET is kept in a saturated state during the on-state. Repeating this process and measuring the overall average current of the MCU allows the determination of the MOSFET's saturation current. This I / O port saturation current testing method requires minimal equipment, significantly reducing mass production testing costs and improving measurement accuracy.

[0041] Figure 1 This diagram illustrates a common method for testing the saturation current of MCU I / O during mass production in the prior art. Wherein, resistor R represents the contact / cable impedance between the testing equipment and the tested I / O, It represents the current supplied or measured by the testing equipment, and V... IO1 This method provides or measures the port voltage for the instrument. It works by operating the MOSFET in the linear region, thus reducing the current to be measured, and inversely inferring the saturation current.

[0042] The testing method is as follows:

[0043] When testing the saturation current output of the I / O port, the internal PMOS transistor of the I / O port is turned on (operating in the linear region). At this time, the I / O port outputs V. IN Voltage; the test equipment pulls the I / O port voltage down to V. IO1 Test the current It output by the IO port at this time (or the test machine pulls a constant current It to the IO port and tests the voltage that is pulled down when the IO port outputs the It current).

[0044] Conversely, when testing the saturation current of the IO port, the internal NMOS transistor of the IO is turned on (operating in the linear region), and the IO port outputs GND voltage. The test instrument raises the IO port voltage to VIO1 and tests the current It flowing into the IO port at this time (or the test instrument injects a constant current It into the IO and tests the voltage rise of the IO port when It current is injected into the IO port).

[0045] The above testing method has the following limitations:

[0046] Firstly, when the output saturation current or input saturation current of the I / O port exceeds the test range of the instrument, it is impossible to test the current. Generally, the saturation current performance is inferred by reducing the current to be measured by making the MOSFET work in the linear region. However, since the current characteristics in the saturation region are different from those in the linear region, this method has uncertainties.

[0047] Secondly, higher-cost equipment can measure a wider current range. When directly testing the saturation current of its I / O port, the internal MOSFET temperature rises due to the long test time (generally on the order of milliseconds) and large current. The saturation current of the MOSFET is different at different temperatures, which affects the current test results at the actual temperature.

[0048] Figure 2 This diagram illustrates a method for mass-producing and testing the saturation current of an I / O circuit in an MCU according to an embodiment of the present invention. The resistor R represents the contact / cable impedance between the testing equipment and the I / O circuit, C represents the load capacitance, and VC represents the voltage across the C terminal of the load capacitor.

[0049] The method for testing the IO saturation current of the present invention includes, but is not limited to, the following steps:

[0050] Test the saturation current I of the IO output (PMOS) P When saturated:

[0051] 1) Measure the average current I at the source input terminal VIN when the PMOS transistor inside the IO is in the off state. H1 .

[0052] 2) Control the PMOS transistor inside the IO to turn on and off (period T1+T2), and ensure that the PMOS transistor is always in the saturation region during time T1 and always in the off state during time T2.

[0053] In one embodiment, PWM or other methods can be used to control the on and off states of the PMOS transistor inside the IO.

[0054] 3) Measure the average current I at the source input terminal VIN during process 2). H2 The current I at this time H2 Satisfy the following formula:

[0055]

[0056] 4) From the known facts in step 3), it can be deduced that the current change through VIN (I H2 - I H1 The internal PMOS output saturation current I is introduced. P saturation:

[0057]

[0058] Figure 3 The diagram shows the voltage waveform at the load capacitor C when the test IO output (PMOS) saturation current is reached, according to an embodiment of the present invention, wherein the load capacitor C discharges to GND during the PMOS off phase.

[0059] Test I / O input (NMOS) saturation current I N When saturated:

[0060] 1) Measure the average current I flowing through GND from the source input terminal when the NMOS transistor inside the IO is off. L1 .

[0061] 2) Control the NMOS transistor inside the IO to turn on and off (period T1+T2), and ensure that the NMOS transistor is always in the saturation region during time T1 and always in the off state during time T2.

[0062] In one embodiment, PWM or other methods can be used to control the on and off states of the PMOS transistor inside the IO.

[0063] 3) Measure the average current I flowing through GND from the source input terminal during process 2). L2 The current I at this time L2 Satisfy the following formula:

[0064]

[0065] 4) From the known facts in step 3), it can be deduced that the change in current flowing through GND at the input terminal (I) L2 -I L1 ) Introducing the internal NMOS input saturation current I N saturation:

[0066]

[0067] Figure 4 The diagram shows the voltage waveform at the load capacitor C when the test IO input (NMOS) saturation current is reached, according to an embodiment of the present invention, wherein the load capacitor C is charged to VIN when the NMOS is off.

[0068] This invention controls the on / off state of the internal MOSFET of the I / O port using a PWM signal. By setting an appropriate duty cycle, the MOSFET is kept in saturation during the on-state. Repeating this process and measuring the overall average current of the MCU allows the determination of the MOSFET's saturation current. This I / O port saturation current testing method requires minimal equipment, significantly reducing mass production testing costs and improving measurement accuracy.

[0069] Compared with traditional IO output / input saturation current testing methods, this invention has the following highly beneficial technical effects:

[0070] 1. It does not have high requirements for testing equipment, which can reduce investment costs;

[0071] 2. The current under test is in the required MOS operating state, and the test current result is more in line with the requirements;

[0072] 3. The conduction time is short throughout the test, there is no MOSFET heating, and the test current results are more accurate.

[0073] Those skilled in the art will understand that the various illustrative components, modules, blocks, units, circuits, systems, and steps described in conjunction with the embodiments disclosed herein can be implemented in hardware, software (including firmware, resident software, microcode, etc.), or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, modules, blocks, units, circuits, systems, and steps described above are generalized in their functional form. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the invention.

[0074] The operations or steps described in this invention are not necessarily performed in a precise sequential order. Instead, various operations or steps can be processed in reverse order or simultaneously. Additionally, other operations or steps may be added to these processes, or one or more operations or steps may be removed from these processes.

[0075] Unless expressly stated in the claims, the order of processing elements and sequences, the use of numbers and letters, or the use of other names described in this application are not intended to limit the order of the processes and methods of this application.

[0076] Furthermore, aspects of this application may be manifested as a computer product located on one or more computer-readable media, the product including computer-readable program code.

[0077] A computer-readable signal medium may contain a propagated data signal containing computer program encoding, for example, on baseband or as part of a carrier wave. This propagated signal may take various forms, including electromagnetic, optical, and so on, or suitable combinations thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can be connected to an instruction execution system, apparatus, or device to enable communication, propagation, or transmission of a program for use. The program encoding located on the computer-readable signal medium can be propagated through any suitable medium, including radio, cable, fiber optic cable, RF, or similar media, or any combination of the above media.

[0078] The computer program code required for the operation of each part of this application can be written in any one or more programming languages, including object-oriented programming languages ​​such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C++, C#, VB.NET, Python, etc., conventional procedural programming languages ​​such as C, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, dynamic programming languages ​​such as Python, Ruby, and Groovy, or other programming languages. This program code can run entirely on the user's computer, or as a standalone software package on the user's computer, or partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any network, such as a local area network (LAN) or wide area network (WAN), or connected to an external computer (e.g., via the Internet), or in a cloud computing environment, or used as a service such as Software as a Service (SaaS).

[0079] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read and write information to / from the storage medium. In an alternative, the storage medium may be integrated into the processor. In an alternative, the processor and storage medium may reside as discrete components in the user terminal.

[0080] In one or more exemplary embodiments, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software as a computer program product, the functionality may be stored or transmitted as one or more instructions or code on or through a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, encompassing any medium that facilitates the transfer of a computer program from one location to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. Any connection is also legitimately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of a medium. As used in this article, disk and disc include compact discs (CDs), laser discs, optical discs, digital multi-purpose discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0081] The terminology and expressions used above are for descriptive purposes only, and the invention should not be limited to these terms and expressions. The use of these terms and expressions does not mean excluding any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

[0082] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the present application requires more features than those mentioned in the claims.

[0083] Similarly, it should be noted that although the present invention has been described with reference to the specific embodiments described above, those skilled in the art should recognize that the above embodiments are only used to illustrate the present invention, and various equivalent changes or substitutions can be made without departing from the spirit of the present invention. Therefore, any changes or modifications to the above embodiments within the scope of the essential spirit of the present invention will fall within the scope of the claims of this application.

Claims

1. A method for testing the saturation current of an I / O port, characterized in that, The method includes: a. Measure the first average current flowing through the source input terminal corresponding to the MOSFET when the MOSFET inside the IO port is in the off state; b. Control the MOS transistor inside the IO port to switch between the on-phase and off-phase, wherein the MOS transistor is always in a saturated state during the on-phase; c. Measure the second average current flowing through the source input terminal corresponding to the MOS transistor during step b; d. The saturation current of the I / O port is obtained based on the difference between the first average current and the second average current and the ratio of the on-time T1 to the off-time T2 of the MOSFET.

2. The method for testing the saturation current of an I / O port as described in claim 1, characterized in that, When the MOS transistor is a PMOS transistor, the source input terminal is the VIN terminal, and the IO port saturation current obtained in step d is the IO output saturation current.

3. The method for testing the saturation current of an I / O port as described in claim 2, characterized in that, The IO output saturation current I P Saturation is: Among them, I H1 Let I be the first average current. H2 This is the second average current.

4. The method for testing the saturation current of an I / O port as described in claim 1, characterized in that, When the MOS transistor is an NMOS transistor, the source input terminal is grounded, and the IO port saturation current obtained in step d is the IO input saturation current.

5. The method for testing the saturation current of an I / O port as described in claim 4, characterized in that, The IO input saturation current I N Saturation is: Among them, I L1 Let I be the first average current. L2 This is the second average current.

6. The method for testing the saturation current of an I / O port as described in claim 1, characterized in that, The method for controlling the switching of the MOSFET inside the I / O port between the on and off phases includes: The MOSFET is switched between the on and off phases by using pulse width modulation and an appropriate duty cycle is set so that it is in the saturation state during the on phase of the MOSFET.

7. The method for testing the saturation current of an I / O port as described in claim 1, characterized in that, During the cutoff phase, the final load voltage of the MOSFET remains consistent.

8. The method for testing the saturation current of an I / O port as described in claim 1, characterized in that, The I / O port is the I / O port of the MCU.

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