Data transmission DMA controller

Abstract

The invention relates to a data transmission DMA controller, and belongs to the field of network data communication. Data of a switching module supporting Ethernet two-layer forwarding and gateway data processing is mounted on a bus bridge of an SoC system, so that the data of the switching module is directly moved to a storage space of the SoC system, the system comprises a Crossbar module, a DMA module and an AXI Master interface module, and the AXI Master interface module is connected with the bus bridge of the SoC system through an AXI bus; the Crossbar module is used for realizing cross matrix path selection between the DMA module and a port of the switching module and conversion between local parallel data and an AXI-Stream data format; and the DMA module carries out full-duplex carrying of data between the port of the switching module and the main memory of the SoC system. According to the invention, efficient data interaction between the network switching module and the processor in the network processor can be realized.

Description

Technical Field

[0001] This invention relates to the field of network data communication, and in particular to a DMA (Direct Memory Access) controller that combines network switching processing and full-duplex operation, suitable for efficient data interaction between the network hard forwarding unit and the processor in a network processor. Background Technology

[0002] In modern high-performance network equipment, hard forwarding units are responsible for rapidly forwarding data frames, while some network data frames requiring software processing need to be processed by the processor. To improve system performance, DMA modules are typically used to achieve high-speed data transfer between the processor and main memory, which can effectively reduce the processor's workload, accelerate protocol processing speed, and reduce network communication latency.

[0003] Traditional DMA solutions suffer from low efficiency and poor compatibility in handling the conversion between other protocol data and Ethernet frames, flexible protocol frame data capture, and descriptor management, making it difficult to meet the high-performance data transmission requirements of complex application scenarios. Therefore, there is an urgent need for a high-efficiency, flexible, scalable DMA module that supports multi-channel and multi-priority scheduling.

[0004] Chinese patent application number 201611049706.2 discloses a method and apparatus for flexibly configuring a multi-channel DMA controller, and Chinese patent application number 201210433375.8 discloses a multi-channel direct memory access (DMA) controller. Both patents involve multi-channel data processing, but fail to flexibly configure the capture port, data port, and DMA channel, and cannot logically isolate data transmission. Chinese patent application number CN202410174202.1 discloses a flow table processing method, apparatus, smart network interface card, switch, and storage medium, involving the combination of flow table data processing and DMA functionality, but it cannot bind forwarded data to ports, making it difficult to handle complex network applications. Summary of the Invention

[0005] The purpose of this invention is to provide a data transfer DMA controller to enable efficient data interaction between the network switching module and the processor in a network processor.

[0006] The technical solution adopted in this invention is as follows:

[0007] A data transfer DMA controller, applied in a SoC system, is used to mount data from a switching module supporting Ethernet Layer 2 forwarding and gateway data processing onto the SoC system's bus bridge, thereby directly moving the data from the switching module to the SoC system's storage space. The controller includes a Crossbar module, a DMA module, and an AXI Master interface module, wherein:

[0008] The AXI Master interface module connects to the bus bridge of the SoC system via the AXI bus.

[0009] The Crossbar module implements the selection of cross-matrix paths between the DMA module and the switching module ports, as well as the conversion between local parallel data and AXI-Stream data formats;

[0010] The DMA module performs full-duplex data transfer between the switching module port and the main memory of the SoC system.

[0011] Furthermore, the AXI Master module is responsible for processing the AXI read and write transaction commands generated by the AXI Master external control logic in the DMA, generating the AXI bus timing according to the commands, and performing read and write operations on the main memory on the AXI bus.

[0012] The AXI Master module includes a 4K address boundary detection module and a data non-alignment processing module. It completes zero-copy reassembly through pre-reading and shift registers, enabling data splicing from a non-8-byte aligned AXI bus to any address offset.

[0013] The 4K address boundary detection module is located at the entry point of AXI receiving DMA read and write transfer commands. It has one read channel and one write channel, responsible for aligning AXI read and write addresses and splitting read and write transactions. The 4K address boundary detection module first aligns the address of the input read and write command to 8H, then adds the first address of the 8H-aligned command to the read / write length to obtain the AXI transmission tail address. If the tail address and the first address are not within the same 4K address segment, it indicates that the transmission has crossed the 4K address boundary. The transmission transaction is then split at the address boundary into two or more sub-transactions and output to the AXI command queue FIFO. If the tail address and the first address are within the same 4K address segment, no splitting is performed, and the transaction is directly output to the command queue FIFO.

[0014] The AXI Master interface module has two levels of priority arbitration on the write channel side. When multiple channels simultaneously request the AXI Master interface module to write to the channel, fixed priority arbitration is performed, first judging the transaction priority and then the channel priority, with the transaction priority being greater than the channel priority. When the current channel's transaction is selected, the write address, write byte count, write descriptor enable, receive parsing completion enable, and descriptor channel number information are sent to the AXI Master interface module. In the next cycle after sending this transaction, the current transaction enable for the current channel is cleared.

[0015] The AXI Master interface module has two levels of priority arbitration on the read channel side. When multiple channels simultaneously request the AXI Master interface module to read the channel, fixed priority arbitration is performed, first determining the transaction priority and then the channel priority, with the transaction priority being greater than the channel priority. When the current channel's transaction is selected, the read address, number of bytes to read, read descriptor enable, send parsing end enable, and descriptor channel number information to the AXI Master interface module. In the next cycle after sending this transaction, the current transaction enable for the current channel is cleared.

[0016] Furthermore, the DMA module includes a DMA control module, an AXI read channel arbitration module, an AXI write channel arbitration module, a transmit descriptor parsing module, a transmit descriptor arbitration module, a receive descriptor parsing module, a receive descriptor arbitration module, an N-channel transmit descriptor FIFO module, an N-channel transmit data FIFO module, an N-channel receive descriptor FIFO module, and an N-channel receive data FIFO module, wherein:

[0017] The DMA control module controls the behavior of DMA, indicating the status of receiving / transmitting, data storage address, interrupt status, requesting AXI read / write channel information, reading / writing back descriptor address, reading / writing back descriptor bytes, and enabling receiving / transmitting. It arbitrates the parsing results of the descriptor resolution module with the control signals of multiple DMA channels, and performs high-speed data exchange between the real-time data of the switching module and the specified storage space.

[0018] The AXI read channel arbitration module is used to perform priority arbitration when multiple channels are read simultaneously;

[0019] The AXI write channel arbitration module is used to perform priority arbitration when multiple channels are written simultaneously;

[0020] The arbitration of the AXI read channel arbitration module and the AXI write channel arbitration module uses a two-level priority arbitration, first judging the transaction priority and then the channel priority. The fixed transaction priority is greater than the adjustable channel priority. In terms of transaction priority, the write channel receive descriptor read / write > send descriptor read / write > data read / write, and the read channel receive descriptor read > send descriptor read > send data read. The priority of each write channel is executed according to the settings.

[0021] The receive descriptor parsing module completes the transmission of received data by parsing and constructing descriptors. In the receive descriptor parsing process, the receiving process obtains the buffer storage address based on the parsed descriptor, writes the buffer length back to the constructed descriptor, and pulls the OWN bit low. The descriptor is written back to the write-back descriptor, and then written back to the storage space and informs the processor of the data address and length.

[0022] The send descriptor parsing module completes the transmission of data by parsing and constructing descriptors. In the send descriptor parsing process, the send process obtains the buffer storage address and buffer length based on the parsed descriptor. After the parsing is completed, the OWN bit is pulled low, the descriptor is constructed and written back to the write-back descriptor, and then written back to the memory space to inform the processor that this descriptor is owned by the application.

[0023] The beneficial effects of this invention are as follows:

[0024] 1. This invention combines the functions of the network switching module to allow for flexible configuration of the capture port, data port, and DMA channel, and can logically isolate data transmission.

[0025] 2. This invention uses flow table algorithms to obtain network data and further binds forwarded data to ports. Through DMA data transmission, it realizes a network-connected network switching module with high efficiency, flexibility, scalability, and support for multi-channel and multi-priority scheduling, which is suitable for complex network applications. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the DMA controller.

[0027] Figure 2 This is a schematic diagram of the two-level priority arbitration on the write channel side of the AXI Master interface module.

[0028] Figure 3 This is a schematic diagram of the two-level priority arbitration on the read channel side of the AXI Master interface module. Detailed Implementation

[0029] The present invention will now be described in detail with reference to the accompanying drawings and specific examples.

[0030] A data transfer DMA controller is disclosed, in which data from the switching port is mounted to the SoC system via a Crossbar module and a DMA controller module. The DMA controller is primarily responsible for arbitrating the parsing results from the descriptor parsing module with control signals from multiple DMA channels, and sending all DMA control information to the AXI Master interface module for overall DMA control. The DMA controller includes a Crossbar module, a DMA module, and an AXI Master interface module, used to mount Ethernet switching module port data to the SoC system. The AXI Master interface module connects to the SoC system's bus bridge via an AXI bus; the Crossbar module implements the cross-matrix path selection between the DMA module and the switching module ports, as well as the conversion between local parallel data and AXI-Stream data formats; the DMA module is primarily responsible for arbitrating the parsing results from the descriptor parsing module with control signals from multiple DMA channels, enabling high-speed data exchange between the switching module's large amounts of real-time data and designated storage space. The DMA module includes an AXI write channel arbitration module, an AXI read channel arbitration module, a receive descriptor parsing module, a receive descriptor arbitration module, a transmit descriptor parsing module, a transmit descriptor arbitration module, an N-channel transmit descriptor FIFO module, an N-channel transmit data FIFO module, an N-channel receive descriptor FIFO module, an N-channel receive data FIFO module, and an N-channel receive data FIFO module, as well as a DMA control module with an expandable number of channels. The AXI write channel arbitration module performs priority arbitration when multiple channels simultaneously write to the channel; the AXI read channel arbitration module performs priority arbitration when multiple channels simultaneously request to read the channel; the receive descriptor parsing module completes the transmission of received data by parsing and constructing descriptors; the transmit descriptor parsing module completes the transmission of transmitted data by parsing and constructing descriptors; the channel DMA control module controls the behavior of DMA, indicating the status of receive / transmit, data storage address, interrupt status, requesting AXI read / write channel information, reading / writing back descriptor address, reading / writing back descriptor byte count, and enabling / distributing receive / transmit; the transmit descriptor arbitration module, the N-channel transmit descriptor FIFO module, and the N-channel transmit data FIFO module complete the design of the transmit descriptor FIFO and its channel confirmation; the receive descriptor arbitration module, the N-channel receive descriptor FIFO module, and the N-channel receive data FIFO module complete the design functions of the receive descriptor FIFO and its channel confirmation.

[0031] The receive descriptor contains four 32-bit receive descriptor register settings. When reading descriptor shifted data, descriptor register setting 0 contains the 32-bit address bits corresponding to the received data, register settings 1 and 2 are reserved, and bit 31 of register setting 3 is the QWN control bit set high and the interrupt control bit, while the remaining bits are reserved. When writing back descriptor shifted data, register settings 1, 2, and 3 are reserved, and bit 31 of register setting 3 is the QWN control bit pulled low, writing the buffer length back to the lower 14 bits.

[0032] The transmit descriptor also contains four 32-bit receive descriptor register settings. When reading the descriptor, descriptor register setting 0 contains the 32-bit address bits corresponding to the received data. Register settings 1 and 2 are reserved. In register setting 3, bit 31 is the QWN control bit set high, bit 31 is the interrupt control bit, the lower 14 bits are the buffer length, and the remaining bits are reserved. When writing back the descriptor to move data, register settings 1, 2, and 3 are reserved, and bit 31 of register setting 3 is the QWN control bit pulled low.

[0033] The AXI Master module is responsible for processing AXI read and write transaction commands generated by the AXI Master external control logic in the DMA, generating AXI bus timing according to the commands, and performing read and write operations on the Slave devices (main memory) on the AXI bus. For example... Figure 1 As shown in the AXI module connection design diagram, the AXI interface connects multiple descriptor FIFOs and frame data FIFOs according to the type of DMA read / write data. Depending on the read / write command, it can write data in a specified FIFO to the slave device (main memory). The control command selects whether the data to be written by the AXI Master interface module comes from the receive data FIFO or the read / write descriptor to be written back, or whether the data read by the AXI interface comes from an external data storage FIFO or a descriptor storage FIFO, and stores the data read from the main memory into the specified data FIFO or descriptor FIFO.

[0034] The 4K address boundary detection module is located at the entry point of the AXI DMA read / write transfer command acceptance, with one module for each read and write channels. It is responsible for aligning AXI read / write addresses and splitting read / write transactions. This module first aligns the addresses of the input read / write commands. It then adds the aligned start address to the read / write length (in bytes) to obtain the AXI transfer tail address. If the tail address and start address are not within the same 4K address segment, it indicates that the transfer has crossed the 4K address boundary. In this case, the module splits the transfer transaction at the address boundary into two or more sub-transactions and outputs them to the AXI command queue FIFO. If the tail address and start address are within the same 4K address segment, no splitting is performed, and the transaction is directly output to the command queue FIFO.

[0035] The unaligned data transmission module supports non-8-byte address-aligned transmission when reading DMA transmission data. Since the bus width is eight bytes, the AXI Master interface module only supports eight-byte address-aligned transmission. To accommodate address offsets in different protocol frames, a module is needed on the data transmission buffer side to perform byte concatenation based on the offset address. The AXI bus width is 8 bytes, and all read data is 8-byte aligned. For data frames with a storage base address offset of N (N=1-7), the lower N bits are invalid data. Therefore, the lower bits of the next valid data signal need to be continuously concatenated to the higher bits of the current data frame. For example, for a data frame with a storage base address offset of 3 bytes, the lower 3 bytes of the first frame need to be removed, the higher 5 bytes moved to the lower 5 bytes, and the lower 3 bytes of the next frame concatenated to the higher 3 bytes of the current frame.

[0036] The AXI Master interface module has a two-level priority arbitration on the write channel side. The arbitration module operates on independent channels. When multiple channels simultaneously request the AXI Master interface module to write, a fixed-priority arbitration is required, first determining the transaction priority and then the channel priority. Figure 2 The transaction priority shown (receive descriptor write-back > send descriptor write-back > receive data write) is greater than the channel priority (channel 0 > channel 1 > ... > channel n). When selecting a transaction for the current channel, the write address, write byte count, write descriptor enable, receive parsing completion enable, and descriptor channel number information need to be sent to the AXI Master interface module. In the next cycle after sending this transaction, the enable for this transaction on the current channel needs to be cleared.

[0037] The AXI Master interface module's read channel side also has two levels of priority arbitration. When multiple channels simultaneously request read channels from the AXI Master interface module, fixed priority arbitration is required, first determining the transaction priority and then the channel priority. Figure 3 The transaction priority shown (receive descriptor read > send descriptor read > send data read) is greater than the channel priority (channel 0 > channel 1 > ... > channel n). When selecting a transaction for the current channel, the read address, number of bytes to read, read descriptor enable, send parsing end enable, and descriptor channel number information need to be sent to the AXI Master interface module. In the next cycle after sending this transaction, the enable for this transaction on the current channel needs to be cleared.

[0038] The core of DMA technology lies in controlling data transfer between hardware and memory through a descriptor mechanism. Reading and writing back descriptors are crucial steps in DMA operations, directly impacting data transfer efficiency, reliability, and system coordination. Each channel description has its own independent descriptor and data FIFO storage space; descriptor storage and parsing require channel identification. The DMA controller module uses rate adjustment parameters to control the DMA data transfer speed, dynamically adjusting the transmit port burst rate to adapt to the receiving data rate of the switching module.

[0039] The channel DMA control module is used to control the behavior of DMA, indicating the status of receiving / transmitting, data storage address, interrupt status, requesting AXI read / write channel information, reading / writing back descriptor address, reading / writing back descriptor bytes, and enabling / distributing.

[0040] In the DMA receive descriptor parsing design, the receive process is based on the current write transaction action. It obtains the buffer storage address by parsing the descriptor, writes the buffer length back to the descriptor construction, and pulls the OWN bit low. The descriptor is then written back to the write-back descriptor, subsequently written back to the memory space, and the processor is informed of the data address and length. This module completes the transmission of received data by parsing and constructing descriptors.

[0041] In the DMA send descriptor resolution design, the sending process is based on the current read transaction. The buffer storage address and buffer length are obtained by resolving the descriptor. After resolution, the OWN bit is pulled low, the descriptor is constructed, and it is written back to the write-back descriptor. Subsequent write-backs to memory inform the processor that this descriptor is owned by the application. This module completes the transmission of data by resolving and constructing descriptors.

[0042] The design of the sending descriptor FIFO and its channel confirmation in this module includes channel confirmation for reading descriptor information from the AXI Master interface module, channel confirmation for writing back descriptor information from the AXI Master interface module, channel confirmation for reading descriptor information from the parsing module, channel confirmation for writing back descriptor information from the parsing module, and a sending polling module. Figure 1The diagram showing the transmit descriptor channel and FIFO read / write operations illustrates the AXI Master interface module's read descriptor information channel confirmation. This primarily involves the AXI Master interface module confirming the write enable, write data, and full signal of the transmit descriptor FIFO. The arbitration signal originates from the transmit read descriptor channel number, which is sent along with the read address and byte count from the DMA controller to the AXI Master interface module. Similarly, the AXI Master interface module's write-back descriptor information channel confirmation primarily confirms the read enable, read data, and empty signal of the transmit write-back descriptor FIFO to the AXI Master interface module. The arbitration signal also originates from the transmit write-back descriptor channel number, which is sent along with the write address and byte count from the DMA controller to the AXI Master interface module. Finally, the parsing module's read descriptor information channel confirmation primarily arbitrates the read enable and read data transmissions from each channel's transmit read descriptor FIFO to the DMA control module's transmit descriptor parsing module. The arbitration signal originates from the port number of the currently selected descriptor FIFO in the transmit poll. The parsing module's write-back descriptor information channel confirmation mainly involves the DMA send descriptor parsing module sending write enable and read data confirmation to each channel's write-back descriptor FIFO. The arbitration signal comes from the data port number selected in the current send polling. If the send polling module's polling signal is that the descriptor is not empty and the send FIFO is not full, then it considers the descriptor not empty and can be polled.

[0043] The receive descriptor FIFO and its channel acknowledgment design in this module include channel acknowledgment for reading descriptor information from the AXI Master interface module side, channel acknowledgment for writing back descriptor information from the AXI Master interface module side, channel acknowledgment for reading descriptor information from the parsing module side, and channel acknowledgment for writing back descriptor information from the parsing module side. For example... Figure 1The AXI Master interface module's read descriptor information channel confirmation, as shown in the FIFO read / write diagram, primarily confirms the read descriptor information channel from the AXI Master interface module for enabling, writing data, and full signals in the receive read descriptor FIFO. The arbitration signal comes from the receive read descriptor channel number sent along with the read address and byte count from the DMA controller to the AXI Master interface module. The AXI Master interface module's write-back descriptor information channel confirmation primarily confirms the read enable, read data, and empty signals from the receive write-back descriptor FIFO to the AXI Master interface module. The arbitration signal comes from the receive write-back descriptor channel number sent along with the write address and byte count from the DMA controller to the AXI Master interface module. The parsing module's read descriptor information channel confirmation primarily confirms the read enable and read data signals from each channel's receive read descriptor FIFO to the DMA receive descriptor parsing module. The arbitration signal comes from the currently selected descriptor FIFO port number in the receive poll. The parsing module's write-back descriptor information channel confirmation mainly completes the write enable and read data selection for the DMA receive descriptor parsing module to receive write-back descriptor FIFOs for each channel. The arbitration signal comes from the currently selected data port number in the receive poll.

[0044] In the descriptor arbitration module design, the arbitration signal is based on the descriptor channel number, the data FIFO port number, and the descriptor FIFO port number. On the AXI Master interface module side, the arbitration signal for reading and writing descriptor channels originates from the descriptor channel number; on the parsing module side, the arbitration signal for writing descriptor channels originates from the data port number; and on the parsing module side, the arbitration signal for reading descriptor channels originates from the FIFO port number.

[0045] In the transmit port flow control design, the maximum read channel rate of the DMA master is usually quite high. When the processor sends multiple descriptors at once, the AXI Master interface module will move the data from the storage space to the DMA's buffer FIFO at the maximum rate. The DMA then transmits the data to the switching module interface via the Crossbar interface. The switching module's processing speed is relatively low, and a batch of descriptors can easily flow into one port, causing overspeeding. To avoid a large number of dropped frames, the transmit port needs to be rate-limited. Data transmission of length X bytes requires taking the entire cycle up to X / 32. If the flow control number is set to n for the hard forwarding unit, the time until the next transmission can proceed is... The data transfer speed of DMA can be controlled by setting the flow control parameter n in one clock cycle.

[0046] The Crossbar module implements the cross-matrix path selection between DMA channels and switching module ports, as well as the format conversion between parallel port data and AXI-Stream data. The Crossbar module converts parallel port data from the switching module into AXI-Stream port data, which is equivalent to port data, enabling port-based switching functionality. Through configuration, each DMA module receive channel can independently specify to receive data from the Crossbar module's receive stream port 0, receive stream port 1, or capture data port, or choose to close the current receive channel. The 4-bit selection type signal of the channel module is set to 0 for receive stream port 0; 1 for receive stream port 1; 2 for capture data port; and F for currently closed receive channel. Each DMA transmit channel can also be configured to independently specify a corresponding switching module transmit stream port 0, transmit stream port 1, or choose to close the current transmit channel. The 4-bit selection type signal of the channel module is set to 0 for transmit stream port 0; 1 for transmit stream port 1; and F for currently closed transmit channel. For random transmission, data from multiple logical channels transmitted by the DMA can be sent arbitrarily to the switching module ports. To isolate data from different switching ports, it is recommended to specify the switching port for each data type when sending data.

[0047] The data at each port of the switching module is parallel data containing start and end markers. The Cossbar module converts this parallel port data into AXI-Stream port data. AXI-Stream data is equivalent to parallel port data, enabling port-based switching functionality. Furthermore, the configuration determines the corresponding DMA module channel for data transfer within the switching module. Data attributes are stored in descriptors. The DMA module internally parses the descriptors and saves the data properties to them, completing descriptor write-back. This allows data from the switching module to be transferred to storage via the DMA channel and AXI4. Similarly, Ethernet-compliant data from the processor is transferred by the DMA module, converted via the crossbar interface, and provided to the switching module in Ethernet frame format. DMA data transfer primarily occurs in two directions: during reception, Ethernet data from the switching module is transferred to main memory; during transmission, data from main memory is transferred to the switching module port via DMA, enabling Ethernet data transmission. DMA can perform full-duplex data transfer.

Claims

1. A data transfer DMA controller, applied in a SoC system, for mounting data from a switching module supporting Ethernet Layer 2 forwarding and gateway data processing onto the SoC system's bus bridge, thereby directly moving the data from the switching module to the SoC system's storage space, characterized in that... This includes the Crossbar module, DMA module, and AXI Master interface module, among which: The AXI Master interface module connects to the bus bridge of the SoC system via the AXI bus. The Crossbar module implements the selection of cross-matrix paths between the DMA module and the switching module ports, as well as the conversion between local parallel data and AXI-Stream data formats; The DMA module performs full-duplex data transfer between the switching module port and the main memory of the SoC system.

2. A data transfer DMA controller according to claim 1, characterized in that, The AXI Master module is responsible for processing the AXI read and write transaction commands generated by the AXI Master external control logic in the DMA, generating the AXI bus timing according to the commands, and performing read and write operations on the main memory on the AXI bus. The AXI Master module includes a 4K address boundary detection module and a data non-alignment processing module. It completes zero-copy reassembly through pre-reading and shift registers, enabling data splicing from a non-8-byte aligned AXI bus to any address offset. The 4K address boundary detection module is located at the entry point of AXI receiving DMA read and write transfer commands. It has one read channel and one write channel, responsible for aligning AXI read and write addresses and splitting read and write transactions. The 4K address boundary detection module first aligns the address of the input read and write command to 8H, then adds the first address of the 8H-aligned command to the read / write length to obtain the AXI transmission tail address. If the tail address and the first address are not within the same 4K address segment, it indicates that the transmission has crossed the 4K address boundary. The transmission transaction is then split at the address boundary into two or more sub-transactions and output to the AXI command queue FIFO. If the tail address and the first address are within the same 4K address segment, no splitting is performed, and the transaction is directly output to the command queue FIFO. The AXI Master interface module has two levels of priority arbitration on the write channel side. When multiple channels simultaneously request the AXI Master interface module to write to the channel, fixed priority arbitration is performed, first judging the transaction priority and then the channel priority, with the transaction priority being greater than the channel priority. When the current channel's transaction is selected, the write address, write byte count, write descriptor enable, receive parsing completion enable, and descriptor channel number information are sent to the AXI Master interface module. In the next cycle after sending this transaction, the current transaction enable for the current channel is cleared. The AXI Master interface module has two levels of priority arbitration on the read channel side. When multiple channels simultaneously request the AXI Master interface module to read the channel, fixed priority arbitration is performed, first determining the transaction priority and then the channel priority, with the transaction priority being greater than the channel priority. When the current channel's transaction is selected, the read address, number of bytes to read, read descriptor enable, send parsing end enable, and descriptor channel number information to the AXI Master interface module. In the next cycle after sending this transaction, the current transaction enable for the current channel is cleared.

3. A data transfer DMA controller according to claim 1, characterized in that, The DMA module includes a DMA control module, an AXI read channel arbitration module, an AXI write channel arbitration module, a transmit descriptor parsing module, a transmit descriptor arbitration module, a receive descriptor parsing module, a receive descriptor arbitration module, an N-channel transmit descriptor FIFO module, an N-channel transmit data FIFO module, an N-channel receive descriptor FIFO module, and an N-channel receive data FIFO module, wherein: The DMA control module controls the behavior of DMA, indicating the status of receiving / transmitting, data storage address, interrupt status, requesting AXI read / write channel information, reading / writing back descriptor address, reading / writing back descriptor bytes, and enabling receiving / transmitting. It arbitrates the parsing results of the descriptor resolution module with the control signals of multiple DMA channels, and performs high-speed data exchange between the real-time data of the switching module and the specified storage space. The AXI read channel arbitration module is used to perform priority arbitration when multiple channels are read simultaneously; The AXI write channel arbitration module is used to perform priority arbitration when multiple channels are written simultaneously; The arbitration of the AXI read channel arbitration module and the AXI write channel arbitration module uses a two-level priority arbitration, first judging the transaction priority and then the channel priority. The fixed transaction priority is greater than the adjustable channel priority. In terms of transaction priority, the write channel receive descriptor read / write > send descriptor read / write > data read / write, and the read channel receive descriptor read > send descriptor read > send data read. The priority of each write channel is executed according to the settings. The receive descriptor parsing module completes the transmission of received data by parsing and constructing descriptors. In the receive descriptor parsing process, the receiving process obtains the buffer storage address based on the parsed descriptor, writes the buffer length back to the constructed descriptor, and pulls the OWN bit low. The descriptor is written back to the write-back descriptor, and then written back to the storage space and informs the processor of the data address and length. The send descriptor parsing module completes the transmission of data by parsing and constructing descriptors. In the send descriptor parsing process, the send process obtains the buffer storage address and buffer length based on the parsed descriptor. After the parsing is completed, the OWN bit is pulled low, the descriptor is constructed and written back to the write-back descriptor, and then written back to the memory space to inform the processor that this descriptor is owned by the application.

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