Display device and image brightness modulation method thereof

Abstract

The invention provides a display device and an image brightness modulation method thereof. In the display device, a clock signal generator is used for generating a plurality of original clock signals in a display frame. The display frame has a valid frame and a plurality of skip frames. Each of the original clock pulse signals has a first pulse duration in a valid frame and a plurality of skip frames, respectively. The pulse width modulator is used for receiving a plurality of original clock pulse signals and setting a plurality of pulse width compensation values respectively corresponding to each original clock pulse signal in a plurality of skip frames. The pulse width modulator modulates each original clock signal from a first pulse duration to a second pulse duration in a plurality of pulse durations in a plurality of skip frames according to a plurality of pulse width compensation values.

Description

Technical Field

[0001] This invention relates to an image brightness modulation technology, and more particularly to a display device and its image brightness modulation method. Background Technology

[0002] In existing display technologies, when a display device operates at a low refresh rate, the current flowing through the light-emitting elements of the pixel circuit is easily affected by the leakage current of the transistors, causing changes that result in noticeable flickering of the displayed image over time. In this situation, users are easily affected by this flickering, thus impacting the viewing experience.

[0003] Therefore, how to effectively improve the flickering phenomenon when the display device operates at a low screen refresh rate, thereby improving the display quality of the display device, will be an important issue for those skilled in the art. Summary of the Invention

[0004] The present invention provides a display device and an image brightness modulation method thereof, which can effectively improve the flickering phenomenon when the display device operates at a low screen update frequency.

[0005] The display device of the present invention includes a clock signal generator and a pulse width modulator. The clock signal generator generates multiple raw clock signals for a display frame, wherein the display frame has a valid frame and multiple skipped frames, and each raw clock signal has a first pulse duration in the valid frame and the multiple skipped frames. The pulse width modulator is coupled to the clock signal generator to receive the multiple raw clock signals and set multiple pulse width compensation values ​​corresponding to each raw clock signal in the multiple skipped frames, wherein the pulse width modulator modulates the pulse duration of each raw clock signal in the multiple skipped frames from the first pulse duration to a second pulse duration according to the multiple pulse width compensation values.

[0006] The image brightness modulation method of the display device of the present invention includes: generating a plurality of original clock signals in a display frame by a clock signal generator, wherein the display frame has a valid frame and a plurality of skipped frames, and each original clock signal has a first pulse duration in the valid frame and the plurality of skipped frames; receiving the plurality of original clock signals by a pulse width modulator and setting a plurality of pulse width compensation values ​​corresponding to each original clock signal in the plurality of skipped frames; and modulating the plurality of pulse durations of each original clock signal in the plurality of skipped frames from the first pulse duration to a second pulse duration according to the plurality of pulse width compensation values.

[0007] Based on the above, the display device and its image brightness modulation method described in the embodiments of the invention can, when the display device is operating in low-frequency mode, modulate (shorten or lengthen) the duration of multiple pulses in multiple skipped frames of the original clock signal by using multiple pulse width compensation values ​​recorded in a lookup table, thereby compensating for each skipped frame in the display frame. In this way, even at low frame update frequencies, the display brightness of the display device can remain consistent across multiple skipped frames, improving flicker in low-frequency mode and enhancing the user's viewing experience. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present invention.

[0009] Figure 2A as well as Figure 2B According to the present invention Figure 1 The timing diagrams of multiple raw clock signals in the valid frames of the display frame and multiple skipped frames.

[0010] Figure 3 According to the present invention Figure 1 A schematic diagram of the lookup table for a pulse width modulator.

[0011] Figure 4 According to the present invention Figure 1 The compensated clock signal is used in the timing diagram of the valid frames and multiple skipped frames of the display frame.

[0012] Figure 5 This is a schematic diagram of a display device according to another embodiment of the present invention.

[0013] Figure 6 According to the present invention Figure 5 A schematic diagram of multiple lookup tables for a pulse width modulator.

[0014] Figure 7 According to the present invention Figure 5 The operation flowchart of the processor of the pulse width modulator.

[0015] Figure 8 This is a flowchart of an image brightness modulation method for a display device according to an embodiment of the present invention.

[0016] In the attached figures, the following labels are used:

[0017] 100, 500: Display device

[0018] 110, 510: Clock signal generator

[0019] 120, 520: Pulse Width Modulator

[0020] 121, 521: Processor

[0021] 122. APL_LUT1~APL_LUTM: Lookup Tables

[0022] 130, 530: Light emission control signal generator

[0023] 522: Adder

[0024] 523: Selector

[0025] ACTIVE: Valid Frame

[0026] CKA~CKC: Raw clock signal

[0027] CKA'~CKC': Compensated clock signal

[0028] CLKSEL: Clock Selection Signal

[0029] DF: Display Frame

[0030] D1~D8, D11~DNM, DOFFSET: Pulse width compensation value

[0031] EMST: Light emission start signal

[0032] EM[N]: Light emission control signal

[0033] F1: Pulse duration

[0034] IM: Image Data

[0035] PABV1~PABVM: Preset average brightness value

[0036] SFS: Skip Frame Selection Signal

[0037] SKIP1~SKIPN: Skip frames

[0038] S710~S760, S810~S830: Steps Detailed Implementation

[0039] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device via other devices or some means of connection. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terminology in different embodiments may be referred to cross-referenced in the relevant descriptions.

[0040] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present invention. Please refer to... Figure 1 The display device 100 includes a clock signal generator 110, a pulse width modulator 120, and a light emission control signal generator 130. The pulse width modulator 120 is coupled to the clock signal generator 110 and the light emission control signal generator 130.

[0041] In this embodiment, the pulse width modulator 120 includes a processor 121 and a lookup table 122. The pulse width modulator 120 can receive a light emission start signal EMST and multiple raw clock signals CKA to CKC from the clock signal generator 110. The processor 121 can be, for example, a central processing unit (CPU), a graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), or other similar components or combinations thereof, but is not limited thereto.

[0042] Please refer to the following at the same time: Figures 1 to 2B , Figure 2A as well as Figure 2B According to the present invention Figure 1 The timing diagram of multiple raw clock signals in the effective frames and multiple skipped frames of the display frame is shown. In this embodiment, the clock signal generator 110 can generate a light emission start signal EMST and multiple raw clock signals CKA to CKC in the display frame DF of the display device 100 according to the requirements of the indication signal. Those skilled in the art can set the number of these raw clock signals CKA to CKC according to the design requirements of the display device 100; this embodiment is not limited to the aforementioned number.

[0043] like Figure 2A As shown, when the display device 100 operates in low-frequency mode, a display frame DF of the display device 100 can be divided into a valid frame ACTIVE and multiple skipped frames SKIP1 to SKIPN, where N is a positive integer. The display device 100 can operate on the valid frame ACTIVE and the multiple skipped frames SKIP1 to SKIPN sequentially, and the valid frame ACTIVE and the multiple skipped frames SKIP1 to SKIPN do not overlap with each other.

[0044] In the active frame of the display frame DF, the display device 100 can perform data writing, resetting, compensation, and light emission operations based on the light emission start signal EMST and multiple raw clock signals CKA to CKC. However, in the multiple skipped frames SKIP1 to SKIPN of the display frame DF, the display device 100 can only perform light emission procedures based on the light emission start signal EMST and multiple raw clock signals CKA to CKC, and cannot perform data writing, resetting, or compensation procedures.

[0045] It is worth mentioning that since these original clock signals CKA to CKC differ only in phase, while their pulse duration (or pulse width) is identical, for ease of explanation, the modulation methods for these original clock signals CKA to CKC will be illustrated using the original clock signal CKA as an example. The modulation methods for the other original clock signals CKB and CKC can be deduced by analogy from the relevant explanations mentioned for the original clock signal CKA.

[0046] Regarding the waveform state of the original clock signal CKA in the display frame DF of the display device 100, for example, the following: Figures 1 to 4 The embodiment assumes that the display frame DF of the display device 100 includes eight skip frames SKIP1 to SKIP8. In this regard, Figure 2B The clock signal waveform CKAA shown can be represented as the waveform state of the original clock signal CKA in the active frame ACTIVE, while the clock signal waveforms CKA1 to CKA8 can be represented as the waveform states of the original clock signal CKA in the skip frames SKIP1 to SKIP8, respectively.

[0047] like Figure 2A as well as Figure 2B As shown, in this embodiment, the original clock signal CKA may have a first pulse duration F1 in the effective frame ACTIVE of the display frame DF and in the multiple skipped frames SKIP1 to SKIPN. That is, the pulse duration values ​​(or pulse width values) of the effective frame ACTIVE and the multiple skipped frames SKIP1 to SKIPN in the display frame DF of the display device 100 are all the same. In this embodiment, the first pulse duration F1 can be the time during which the original clock signal is in a low-voltage state.

[0048] For implementation details of the display device 100, please also refer to... Figures 1 to 4 , Figure 3 According to the present invention Figure 1 A schematic diagram of the lookup table for a pulse width modulator, and Figure 4 According to the present invention Figure 1The compensated clock signal is used in the timing diagram of the valid frames and multiple skipped frames of the display frame.

[0049] In this embodiment, Figure 3 The lookup table 122 shown can be used to record the relationship between multiple skip frames (e.g., skip frames SKIP1 to SKIP8) of the display device 100 and multiple pulse width compensation values ​​(e.g., pulse width compensation values ​​D1 to D8). The processor 121 can obtain multiple pulse width compensation values ​​D1 to D8 corresponding to these skip frames SKIP1 to SKIP8 respectively through the lookup table 122 based on the skip frame selection signal SFS.

[0050] It is worth noting that the aforementioned pulse width compensation values ​​D1 to D8 can be related to the amount of brightness change of the image data at a grayscale value and the number of these skipped frames D1 to D8. Furthermore, the lookup table 122 of this embodiment can record or store multiple pulse width compensation values ​​D1 to D8 with positive or negative polarities. Those skilled in the art can set the polarity of these pulse width compensation values ​​D1 to D8 according to the design requirements of the display device 100. The following description will use multiple pulse width compensation values ​​D1 to D8 with positive polarities as examples.

[0051] In detail, in this embodiment, when the processor 121 receives the original clock signal CKA, the processor 121 can select one skip frame from these skip frames SKIP1 to SKIP8 as the selected skip frame (for example, skip frame SKIP1) according to the skip frame selection signal SFS. Then, the processor 121 can look up the pulse width compensation value D1 corresponding to the selected skip frame SKIP1 through lookup table 122.

[0052] Next, as Figure 2B as well as Figure 4 As shown, in some embodiments, the processor 121 may extend the duration value (or pulse width value) of the original clock signal CKA in the first pulse duration F1 of the skipped frame SKIP1 by a pulse width compensation value D1 (e.g., a pulse width compensation value D1 with positive polarity) according to the pulse width compensation value D1 corresponding to the skipped frame SKIP1. Figure 4 The clock signal waveform CKA'1 is shown in the figure. In this way, the processor 121 of the pulse width modulator 120 can modulate the pulse duration of the original clock signal CKA in the skip frame SKIP1 from the original first pulse duration F1 to the second pulse duration F2 (that is, the time length value (or pulse width value) of the pulse duration of the original clock signal CKA in the skip frame SKIP1 is modulated to F1+D1).

[0053] In addition, in some other embodiments, the processor 121 may reduce the duration (or pulse width) of the first pulse duration F1 of the original clock signal CKA in the skip frame SKIP1 by a pulse width compensation value D1, based on the pulse width compensation value D1 corresponding to the skip frame SKIP1 (e.g., a pulse width compensation value D1 with negative polarity). In this way, the processor 121 of the pulse width modulator 120 can modulate the pulse duration of the original clock signal CKA in the skip frame SKIP1 from the original first pulse duration F1 to the second pulse duration F2 (that is, the duration (or pulse width) of the original clock signal CKA in the skip frame SKIP1 is modulated to F1-D1).

[0054] Similarly, when the processor 121 selects skip frame SKIP2 from these skip frames SKIP1 to SKIP8 as the selected skip frame based on the skip frame selection signal SFS, the processor 121 can look up the pulse width compensation value D2 corresponding to the skip frame SKIP2 through the lookup table 122 based on the selected skip frame SKIP2.

[0055] Next, in some embodiments, the processor 121 may extend the duration value (or pulse width value) of the first pulse duration F1 of the original clock signal CKA in the skipped frame SKIP2 by a pulse width compensation value D2 (e.g., a pulse width compensation value D2 with positive polarity) based on the pulse width compensation value D2 corresponding to the skipped frame SKIP2. Figure 4 The clock signal waveform CKA'2 is shown in the figure. In this way, the processor 121 of the pulse width modulator 120 can modulate the pulse duration of the original clock signal CKA in the skip frame SKIP2 from the original first pulse duration F1 to the second pulse duration F2 (that is, the time length value (or pulse width value) of the pulse duration of the original clock signal CKA in the skip frame SKIP2 is modulated to F1+D2).

[0056] In addition, in some other embodiments, the processor 121 may reduce the duration (or pulse width) of the first pulse duration F1 of the original clock signal CKA in the skip frame SKIP2 by a pulse width compensation value D2, based on the pulse width compensation value D2 corresponding to the skip frame SKIP2 (e.g., a pulse width compensation value D2 with negative polarity). In this way, the processor 121 of the pulse width modulator 120 can modulate the pulse duration of the original clock signal CKA in the skip frame SKIP2 from the original first pulse duration F1 to the second pulse duration F2 (that is, the duration (or pulse width) of the pulse duration of the original clock signal CKA in the skip frame SKIP2 is modulated to F1-D2).

[0057] It is worth mentioning that the modulation method of the pulse width modulator 120 on the original clock signal CKA in the remaining skip frames SKIP3 to SKIP8 can be deduced by analogy with the relevant explanations mentioned above regarding the pulse width modulator 120 on the original clock signal CKA in skip frames SKIP1 to SKIP2. Furthermore, Figure 4 To illustrate an embodiment where the pulse width modulator 120 extends the duration F1 of the first pulse wave in the skipped frame of the original clock signal by a pulse width compensation value, the embodiment where the pulse width modulator 120 reduces the duration F1 of the first pulse wave in the skipped frame by a pulse width compensation value can be described according to... Figure 4 The description of the embodiments follows the same pattern.

[0058] In this way, the pulse width modulator 120 of this embodiment can set the polarity of these pulse width compensation values ​​D1 to D8 according to the design requirements of the display device 100, and modulate the original clock signal CKA (and the original clock signals CKB, CKC) in multiple first pulse durations F1 in multiple skip frames SKIP1 to SKIP8 (e.g., modulated to F1±D1, F1±D2, ... or / and F1±D8) to serve as the compensated clock signal CKA' (and the compensated clock signals CKB', CKC'). Furthermore, the pulse width modulator 120 can provide the compensated clock signal CKA' (and the compensated clock signals CKB', CKC') to the back-end light emission control signal generator 130, so that the light emission control signal generator 130 can generate the light emission control signal EM[N] based on the light emission start signal EMST and the compensated clock signal CKA' (and the compensated clock signals CKB', CKC').

[0059] according to Figures 1 to 4 As can be seen from the description of the embodiments, in the embodiment where the display device 100 displays a single display screen, when the display device 100 operates in low frequency mode, the pulse width modulator 120 of this embodiment can modify (shorten or lengthen) the duration of multiple pulse waves in multiple skipped frames SKIP1 to SKIP8 of the original clock signal CKA in the display frame DF by looking up multiple pulse width compensation values ​​D1 to D8 in the table 122, so as to compensate for each skipped frame in the display frame DF.

[0060] In this way, even at low frame refresh rates, the display brightness of the display device 100 can remain consistent across multiple skipped frames SKIP1 to SKIP8 of the display frame DF, thereby improving the flickering phenomenon of the display device 100 in low-frequency mode and enhancing the viewing quality for the user.

[0061] Figure 5This is a schematic diagram of a display device according to another embodiment of the present invention. Please refer to... Figure 5 The display device 500 includes a clock signal generator 510, a pulse width modulator 520, and a light emission control signal generator 530. Unlike... Figure 1 The display device 100 shown in this embodiment includes a pulse width modulator 520 comprising a processor 521, an adder 522, a selector 523, and multiple lookup tables APL_LUT1 to APL_LUTM, where M is a positive integer.

[0062] In this embodiment, the pulse width modulator 520 can receive the raw clock signals CKA to CKC. The processor 521 is coupled to the adder 522 and multiple lookup tables APL_LUT1 to APL_LUTM. The adder 522 is coupled to the processor 521 and the selector 523. The selector 523 is coupled to the adder 522 and the light emission control signal generator 530.

[0063] It should be noted that, Figure 5 The clock signal generator 510 and the light emission control signal generator 530 shown can be referenced. Figure 1 The descriptions of the clock signal generator 110 and the light emission control signal generator 130 mentioned above can be deduced by analogy, so they will not be repeated here.

[0064] Figure 6 According to the present invention Figure 5 A schematic diagram of multiple lookup tables for a pulse width modulator, and Figure 7 According to the present invention Figure 5 The flowchart below shows the operation of the pulse width modulator's processor. For ease of explanation, the modulation methods for the multiple raw clock signals CKA to CKC will also be illustrated using the raw clock signal CKA as an example. The modulation methods for the other raw clock signals CKB and CKC can be deduced by analogy from the relevant explanations mentioned for the raw clock signal CKA.

[0065] For implementation details of the display device 500, please also refer to... Figures 5 to 7 In this embodiment, in step S710, the pulse width modulator 520 can receive image data IM, skip frame selection signal SFS, and original clock signal CKA. Next, in step S720, the processor 521 can calculate the average brightness value ABV of the image data IM based on the image data IM and using an algorithm.

[0066] In this embodiment, the algorithm can be, for example, the Average Pixel Level (APL) algorithm. Furthermore, the average brightness value (ABV) of the aforementioned image data IM can be used to represent the overall average brightness of the display screen of the current display device 500, and the aforementioned average brightness value (ABV) can be a value less than 255.

[0067] After the processor 521 calculates the current average brightness value ABV of the image data IM, in step S730, the processor 521 can start reading multiple lookup tables APL_LUT1 to APL_LUTM based on the average brightness value ABV of the image data IM and the skip frame selection signal SFS.

[0068] Furthermore, in this embodiment, Figure 6 The multiple lookup tables APL_LUT1 to APL_LUTM shown can be used to record the relationships between multiple preset average luminance values ​​PABV1 to PABVM, multiple skip frames SKIP1 to SKIPN, and multiple pulse width compensation values ​​D11 to DNM. Furthermore, the processor 521 can obtain the multiple pulse width compensation values ​​D11 to DNM corresponding to these skip frames SKIP1 to SKIPN through these lookup tables APL_LUT1 to APL_LUTM based on the average luminance value ABV of the image data IM and the skip frame selection signal SFS.

[0069] Next, in step S740, the processor 521 can pre-determine whether the current average brightness value ABV of the image data IM matches one of the multiple preset average brightness values ​​PABV1 to PABVM in these lookup tables APL_LUT1 to APL_LUTM. In other words, the processor 521 can determine whether these lookup tables APL_LUT1 to APL_LUTM record multiple pulse width compensation values ​​corresponding to the current average brightness value ABV of the image data IM.

[0070] Specifically, when processor 521 determines that the average brightness value ABV of the image data IM matches one of the multiple preset average brightness values ​​PABV1 to PABVM in the lookup tables APL_LUT1 to APL_LUTM, the processor may continue to execute the operation in step S750. Conversely, when processor 521 determines that the average brightness value ABV of the image data IM does not match one of the multiple preset average brightness values ​​PABV1 to PABVM in the lookup tables APL_LUT1 to APL_LUTM, the processor may continue to execute the operation in step S760.

[0071] In detail, in step S750, assuming that the processor 521 determines that the average brightness value ABV of the image data IM matches the preset average brightness value PABV1 in the lookup table APL_LUT1, the processor 521 can select a skip frame from these skip frames SKIP1 to SKIPN as the selected skip frame (for example, skip frame SKIP1) according to the skip frame selection signal SFS.

[0072] Next, the processor 521 can look up the pulse width compensation value D11 corresponding to the skipped frame SKIP1 through the lookup table APL_LUT1 based on the average brightness value ABV of the image data IM and the selected skipped frame SKIP1. Furthermore, the processor 521 can provide the pulse width compensation value D11 as the pulse width compensation value DOFFSET to the back-end adder 522.

[0073] On the other hand, in step S760, when the processor 521 determines that the average brightness value ABV of the image data IM does not match one of the multiple preset average brightness values ​​PABV1 to PABVM in these lookup tables APL_LUT1 to APL_LUTM, the processor 521 can search for two preset average brightness values ​​adjacent to the average brightness value ABV of the image data IM from the multiple preset average brightness values ​​PABV1 to PABVM in these lookup tables APL_LUT1 to APL_LUTM. Furthermore, the processor 521 can perform interpolation based on the average brightness value ABV, the two preset average brightness values, and the pulse width compensation value corresponding to the two preset average brightness values ​​to obtain the pulse width compensation value DOFFSET corresponding to the average brightness value ABV of the image data IM.

[0074] For example, suppose processor 521 calculates the current average brightness value ABV of image data IM to be 253, and the preset average brightness values ​​PABV1 and PABV2 recorded in lookup tables APL_LUT1 and APL_LUT2 are 255 and 240, respectively. In this case, processor 521 can perform interpolation based on the average brightness value ABV, the preset average brightness values ​​PABV1 and PABV2, and the pulse width compensation values ​​corresponding to the preset average brightness values ​​PABV1 and PABV2, to obtain the pulse width compensation value DOFFSET corresponding to the average brightness value ABV.

[0075] It is worth mentioning that, in this embodiment, the processor 521 obtains the pulse width compensation value DOFFSET through interpolation, which can effectively save the hardware design space required for lookup table construction.

[0076] After the processor 521 obtains the pulse width compensation value DOFFSET through the operation of step S750 or step S760, the adder 522 of the pulse width modulator 520 can receive the pulse width compensation value DOFFSET and the original clock signal CKA.

[0077] Next, adder 522 can perform addition on the time length value (or pulse width value) of the first pulse duration F1 in the skip frame indicated by the skip frame selection signal SFS and the pulse width compensation value DOFFSET of the original clock signal CKA, thereby providing the compensated clock signal CKA'.

[0078] For example, similar to Figure 4 As shown in the embodiments, in some embodiments, it is assumed that the processor 521 selects skip frame SKIP1 as the selected skip frame based on the skip frame selection signal SFS, and the pulse width compensation value corresponding to the selected skip frame SKIP1 is a pulse width compensation value DOFFSET with positive polarity. In this case, the pulse width modulator 520 can use adder 522 to extend the time length value (or pulse width value) of the first pulse duration F1 of the original clock signal CKA in the skip frame SKIP1 by a pulse width compensation value DOFFSET (similar to...). Figure 4 The clock signal waveform CKA'1 is shown in the diagram. Herein, the pulse width modulator 520 can modulate the pulse duration of the original clock signal CKA in the skip frame SKIP1 from the original first pulse duration F1 to the second pulse duration F2 (that is, the duration value (or pulse width value) of the original clock signal CKA in the skip frame SKIP1 is modulated to F1+DOFFSET). Furthermore, the adder 522 can provide the compensated clock signal CKA' to the selector 523 at the back end.

[0079] In addition, in some embodiments, it is assumed that the processor 521 selects skip frame SKIP1 as the selected skip frame based on the skip frame selection signal SFS, and the pulse width compensation value corresponding to the selected skip frame SKIP1 is a pulse width compensation value DOFFSET with negative polarity. In this case, the pulse width modulator 520 can reduce the duration (or pulse width) of the first pulse duration F1 of the original clock signal CKA in the skip frame SKIP1 by a pulse width compensation value DOFFSET using the adder 522. Thus, the pulse width modulator 520 can modulate the pulse duration of the original clock signal CKA in the skip frame SKIP1 from the original first pulse duration F1 to the second pulse duration F2 (that is, the duration (or pulse width) of the pulse duration of the original clock signal CKA in the skip frame SKIP1 is modulated to F1-DOFFSET). Furthermore, the adder 522 can provide the compensated clock signal CKA' to the selector 523 at the back end.

[0080] Next, the selector 523 of the pulse width modulator 520 can receive the original clock signal CKA, the compensated clock signal CKA', and the clock selection signal CLKSEL. Specifically, in this embodiment, the selector 523 can select to provide the original clock signal CKA or the compensated clock signal CKA' to the back-end light emission control signal generator 530 according to the clock selection signal CLKSEL, so that the light emission control signal generator 530 can generate the light emission control signal EM[N] according to the light emission start signal EMST and the compensated clock signal CKA' (or the original clock signal CKA) according to the design requirements of the display device 500.

[0081] according to Figures 5 to 7 As can be seen from the description of the embodiments, the display device 500 of this embodiment can look up the corresponding pulse width compensation value DOFFSET from multiple lookup tables APL_LUT1 to APL_LUTM based on the current average brightness value of the display data IM. In addition, the pulse width modulator 520 of this embodiment can also use the calculated pulse width compensation value DOFFSET to modulate (shorten or lengthen) the duration of multiple pulses in multiple skipped frames SKIP1 to SKIPN of the original clock signal CKA in the display frame DF, so as to compensate for each skipped frame in the display frame DF.

[0082] In this way, the display device 500 can compensate for the display brightness under different display screens. Furthermore, at low screen refresh rates, the display brightness of the display device 500 can remain consistent across multiple skipped frames SKIP1 to SKIPN of display frame DF, thereby improving the flickering phenomenon of the display device 500 in low-frequency mode and enhancing the viewing quality for the user.

[0083] Figure 8 This is a flowchart of an image brightness modulation method for a display device according to an embodiment of the present invention. Please also refer to... Figure 1 as well as Figure 8 In step S810, the display device can generate multiple original clock signals in the display frame by a clock signal generator, wherein the display frame has a valid frame and multiple skip frames, and each original clock signal has a first pulse duration in the valid frame and multiple skip frames respectively.

[0084] In step S820, the display device can receive multiple raw clock signals via a pulse width modulator and set multiple pulse width compensation values ​​corresponding to each raw clock signal in multiple skipped frames. In step S830, the display device can use the pulse width modulator to adjust the duration of each raw clock signal in multiple skipped frames from a first pulse duration to a second pulse duration based on the multiple pulse width compensation values.

[0085] The implementation details of each step are explained in detail in the foregoing embodiments and implementation methods, and will not be repeated here.

[0086] In summary, the display device and its image brightness modulation method described in this embodiment of the invention can, when the display device is operating in low-frequency mode, modulate (shorten or lengthen) the duration of multiple pulses in multiple skipped frames of the original clock signal by using multiple pulse width compensation values ​​recorded in a lookup table, thereby compensating for each skipped frame in the display frame. In this way, even at low frame update frequencies, the display brightness of the display device can remain consistent across multiple skipped frames, improving flicker in low-frequency mode and enhancing the user's viewing experience.

[0087] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A display device, characterized in that, include: A clock signal generator is used to generate multiple raw clock signals for a display frame, wherein the display frame has a valid frame and multiple skip frames, and each of the raw clock signals has a first pulse duration in the valid frame and the skip frames. as well as A pulse width modulator is coupled to the clock signal generator to receive the original clock signals and set multiple pulse width compensation values ​​corresponding to each of the original clock signals in the skipped frames. The pulse width modulator modulates the duration of multiple pulse waves of each of the original clock signals in the skipped frames from the first pulse duration to a second pulse duration according to the pulse width compensation values.

2. The display device as claimed in claim 1, characterized in that, The pulse width modulator includes: A lookup table is used to record the relationship between these skipped frames and these pulse width compensation values; and A processor is configured to receive each of the original clock signals and a skip frame selection signal, the processor obtaining each of the pulse width compensation values ​​through a lookup table based on the skip frame selection signal, and adjusting the pulse duration of each of the original clock signals in the skip frames from the first pulse duration to the second pulse duration based on the pulse width compensation values, so as to provide a compensated clock signal.

3. The display device as claimed in claim 1, characterized in that, Each of these pulse width compensation values ​​is related to a brightness change of an image data at a grayscale value and the number of skipped frames.

4. The display device as claimed in claim 1, characterized in that, The pulse width modulator includes: A processor is configured to receive image data and a skip frame selection signal, and to calculate an average brightness value of the image data using an algorithm based on the image data; and Multiple lookup tables, coupled to the processor, are used to record the relationships between multiple preset average brightness values ​​and the skipped frames and pulse width compensation values. The processor obtains the pulse width compensation value by means of the average brightness value of the image data and the skip frame selection signal through the lookup tables.

5. The display device as claimed in claim 4, characterized in that, The algorithm in question is the average pixel level algorithm.

6. The display device as claimed in claim 4, characterized in that, The processor further determines whether the average brightness value of the image data matches one of the preset average brightness values ​​in the lookup tables. When the processor determines that the average brightness value of the image data matches one of the preset average brightness values ​​in the lookup tables, the processor obtains the pulse width compensation values ​​by using the lookup tables based on the average brightness value of the image data and the skip frame selection signal. When the processor determines that the average brightness value of the image data does not match one of the preset average brightness values ​​in the lookup tables, the processor searches for two preset average brightness values ​​adjacent to the average brightness value in the lookup tables, and the processor performs an interpolation operation based on the average brightness value and the two preset average brightness values ​​to obtain each pulse width compensation value.

7. The display device as claimed in claim 4, characterized in that, The pulse width modulator further includes: An adder, coupled to the processor and the clock signal generator, is configured to receive each of the pulse width compensation values ​​and each of the original clock signals, and perform an addition operation on the duration value of the first pulse wave of each of the original clock signals and each of the pulse width compensation values ​​to provide a compensated clock signal; and A selector, coupled to the adder and the clock signal generator, is used to provide either the original clock signal or the compensated clock signal based on a clock selection signal.

8. A method for image brightness modulation in a display device, characterized in that, include: A clock signal generator generates multiple raw clock signals in a display frame, wherein the display frame has a valid frame and multiple skip frames, and each of the raw clock signals has a first pulse duration in the valid frame and the skip frames respectively. The original clock signals are received by a pulse width modulator, and multiple pulse width compensation values ​​corresponding to each of the original clock signals in the skipped frames are set; and The pulse width modulator modulates the duration of each pulse wave in the skipped frames of the original clock signal from the first pulse wave duration to a second pulse wave duration based on the pulse width compensation values.

9. The image brightness modulation method as described in claim 8, characterized in that, Including: A lookup table records the relationship between these skipped frames and these pulse width compensation values; A processor receives each of the original clock signals and a skip frame selection signal, and obtains each of the pulse width compensation values ​​by using the lookup table based on the skip frame selection signal; and The processor adjusts the pulse duration of each original clock signal in the skipped frames according to the pulse width compensation values, changing it from the first pulse duration to the second pulse duration, to provide a compensated clock signal.

10. The image brightness modulation method as described in claim 8, characterized in that, Each of these pulse width compensation values ​​is related to a brightness change of an image data at a grayscale value and the number of skipped frames.

11. The image brightness modulation method as described in claim 8, characterized in that, Including: A processor receives image data and a skip frame selection signal, and uses an algorithm to calculate an average brightness value of the image data based on the image data. Multiple lookup tables record the relationship between multiple preset average brightness values ​​and these skipped frames and these pulse width compensation values; and The processor obtains each pulse width compensation value by means of the average brightness value of the image data and the skip frame selection signal through the lookup tables.

12. The image brightness modulation method as described in claim 11, characterized in that, The algorithm in question is the average pixel level algorithm.

13. The image brightness modulation method as described in claim 11, characterized in that, Including: The processor determines whether the average brightness value of the image data matches one of the preset average brightness values ​​in the lookup tables; When it is determined that the average brightness value of the image data matches one of the preset average brightness values ​​in the lookup tables, the processor obtains each pulse width compensation value by using the lookup tables based on the average brightness value of the image data and the skip frame selection signal; and When it is determined that the average brightness value of the image data does not match one of the preset average brightness values ​​in the lookup tables, the processor searches for two preset average brightness values ​​adjacent to the average brightness value in the lookup tables, and performs an interpolation operation based on the average brightness value and the two preset average brightness values ​​to obtain each pulse width compensation value.

14. The image brightness modulation method as described in claim 11, characterized in that, Including: An adder receives each pulse width compensation value and each original clock signal, and performs an addition operation on the duration value of the first pulse wave of each original clock signal and each pulse width compensation value to provide a compensated clock signal; and A selector provides either the original clock signal or the compensated clock signal based on a clock selection signal.

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