Voltage fast switching enhancement circuit, method, dc-dc power supply, chip and device

Abstract

The application provides a voltage fast switching enhancement circuit, method, DCDC power supply, chip and device. The voltage fast switching enhancement circuit comprises a DVS enhancement trigger module, a boost enhancement sub-circuit, a buck enhancement sub-circuit and a DVS enhancement closing sub-circuit which are electrically connected; the DVS enhancement trigger module receives a DVS signal; the output end of the boost enhancement sub-circuit, the output end of the buck enhancement sub-circuit and the input end of the DVS enhancement closing sub-circuit are coupled with the voltage output end of the DCDC circuit at a first node; the boost enhancement sub-circuit charges the first node when the DCDC circuit switches from low voltage to high voltage, and the buck enhancement sub-circuit discharges the first node when the switching mode is from high voltage to low voltage; the charging / discharging operation is stopped when the enhancement closing preset condition is met. The application can greatly shorten the DVS switching time of the DCDC circuit, meet the timing requirements of the communication system and guarantee the quality of communication.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a voltage fast switching enhancement circuit, method, DC-DC power supply, chip, and device. Background Technology

[0002] With the development of DC-DC switching power supply technology, its application in integrated circuit equipment is becoming increasingly widespread. As integrated circuits are increasingly used in various fields, the requirements for switching power supplies are also becoming more stringent. Especially in 5G RF front-end applications, to improve system efficiency, existing technologies typically employ APT (Average Power Tracking) control to dynamically adjust the DC-DC output voltage to match the transmit power of the power amplifier (PA). Typically, APT control requires the DC-DC output to switch from one voltage to another (e.g., from 0.5V to 3.4V) within a very short time (e.g., within 5µs). If the switching time exceeds 5µs, the power amplifier has already turned on, but the power supply has not yet been established, preventing the power amplifier from outputting the target power. This not only causes power attenuation but also degrades the linearity of the power amplifier. Therefore, the switching speed of the DC-DC output voltage is crucial to the performance of the power amplifier; in other words, it places stringent requirements on the switching speed of DC-DCs using APT control.

[0003] In existing technologies, the output voltage switching time (DVS) of a typical switching power supply DC-DC circuit is usually above 5µs, or even above 10µs. As mentioned earlier, in some special application scenarios, this time cannot meet the timing requirements of system communication. Furthermore, if the output voltage needs to be adjusted, for a typical switching power supply DC-DC circuit, it is unavoidable to use a power inductor to charge or discharge the output node. However, inductors have a choking effect; the inductor current cannot change abruptly. Therefore, the output node cannot be charged or discharged quickly, and the output voltage is difficult to switch and adjust rapidly.

[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a voltage fast switching enhancement circuit, method, DC-DC power supply, chip, and device. This invention can significantly shorten the DVS switching time of the DC-DC circuit, thereby meeting the timing requirements of the communication system and ensuring the quality of communication.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a voltage fast switching enhancement circuit for a DC-DC circuit, the voltage fast switching enhancement circuit comprising a DVS enhancement trigger module, a boost enhancement sub-circuit, a buck enhancement sub-circuit, and a DVS enhancement shutdown sub-circuit; the DVS enhancement trigger module receives a DVS signal, and its first and second output terminals are respectively coupled to the control terminals of the boost enhancement sub-circuit and the buck enhancement sub-circuit; the output terminals of the boost enhancement sub-circuit, the buck enhancement sub-circuit, and the input terminal of the DVS enhancement shutdown sub-circuit are connected to the voltage output terminal of the DC-DC circuit. Coupled to the first node; the DVS enhancement triggering module is configured to obtain the switching mode of the output voltage of the DC-DC circuit according to the DVS signal, and trigger the boost enhancement sub-circuit to work to charge the first node when the switching mode is switching from low voltage to high voltage; and trigger the buck enhancement sub-circuit to work to discharge the first node when the switching mode is switching from high voltage to low voltage; the DVS enhancement shutdown sub-circuit is configured to determine whether the charging / discharging of the first node meets the enhancement shutdown preset condition, and if so, reset the boost enhancement sub-circuit / the buck enhancement sub-circuit to stop the charging / discharging operation of the first node.

[0007] Optionally, the first input terminal of the DVS enhancement trigger module receives the DVS signal, and the second and third input terminals of the DVS enhancement trigger module receive a preset reference high voltage and a preset reference low voltage, respectively, wherein the preset reference high voltage is greater than the preset reference low voltage; the DVS enhancement trigger module is configured to determine that the switching mode is switching from low voltage to high voltage and trigger the boost enhancement sub-circuit to work when the DVS signal is greater than the preset reference high voltage; and to determine that the switching mode is switching from high voltage to low voltage and trigger the buck enhancement sub-circuit to work when the DVS signal is less than the preset reference low voltage.

[0008] Optionally, the DVS enhancement trigger module includes a first comparator, a second comparator, an AND gate, and a first NOR gate; the negative input terminal of the first comparator receives the preset reference high voltage, the positive input terminals of the first comparator and the second comparator are coupled to the output terminal or reference voltage input terminal of the error amplifier of the DCDC circuit, the negative input terminal of the second comparator receives the preset reference low voltage, the output terminal of the first comparator, the first input terminal of the AND gate, and the first input terminal of the first NOR gate are coupled, the output terminal of the second comparator, the second input terminal of the AND gate, and the second input terminal of the first NOR gate are coupled, the output terminal of the AND gate is coupled to the first input terminal of the boost enhancement sub-circuit, and the output terminal of the first NOR gate is coupled to the first input terminal of the buck enhancement sub-circuit.

[0009] Optionally, the boost enhancement sub-circuit includes a boost control module, a boost signal generation module, and a boost drive module connected in sequence; the buck enhancement sub-circuit includes a buck control module, a buck signal generation module, and a buck drive module connected in sequence; and the DVS enhancement shutdown sub-circuit includes a boost enhancement shutdown module and a buck enhancement shutdown module. The first and second input terminals of the boost control module are respectively coupled to the first output terminal of the DVS enhancement trigger module and the output terminal of the boost enhancement shutdown module. The first and second input terminals of the buck control module are respectively coupled to the second output terminal of the DVS enhancement trigger module and the second output terminal of the DVS enhancement shutdown sub-circuit. The output terminals of the boost drive module and the buck drive module are coupled to the first node. The input terminal of the boost enhancement shutdown module is coupled to the boost signal generation module at a second node or to the first node, and the input terminal of the buck enhancement shutdown module is coupled to the buck signal generation module at a third node or to the first node.

[0010] Optionally, the boost control module includes a first sampling module, a first RS flip-flop, and a first inverter; the input terminal of the first sampling module is coupled to the first output terminal of the DVS enhancement trigger module, the output terminal of the first sampling module is coupled to the set terminal of the first RS flip-flop, the reset terminal of the first RS flip-flop is coupled to the output terminal of the boost enhancement shutdown module, the output terminal of the first RS flip-flop and the input terminal of the first inverter are coupled to the first control terminal of the boost signal generation module at a fourth node, and the output terminal of the first inverter is coupled to the second control terminal of the boost signal generation module at a fifth node; the boost enhancement shutdown module is configured to reset the boost control module to stop the charging operation of the first node when it is determined that the voltage of the first node is greater than or equal to a boost enhancement preset value; the boost enhancement preset value is less than the target high voltage value for voltage switching of the DCDC circuit; And / or, the buck control module includes a second sampling module, a second RS flip-flop, and a second inverter. The input of the second sampling module is coupled to the second output of the DVS enhancement trigger module. The output of the second sampling module is coupled to the set input of the second RS flip-flop. The reset input of the second RS flip-flop is coupled to the output of the buck enhancement shutdown module. The output of the second RS flip-flop and the input of the second inverter are coupled to the first control input of the buck signal generation module at a sixth node. The output of the second inverter is coupled to the second control input of the buck signal generation module at a seventh node. The buck enhancement shutdown module is configured to reset the buck control module to stop the discharge operation on the first node when it is determined that the voltage of the first node is less than or equal to the buck enhancement preset value. The buck enhancement preset value is greater than the target low voltage value for voltage switching of the DCDC circuit.

[0011] Optionally, the first sampling module and / or the second sampling module are sampling units. The sampling unit includes a delay, a third inverter, and a second NOR gate. The input terminal of the delay and the input terminal of the third inverter share a common connection point to form the input terminal of the sampling unit. The output terminal of the delay and the output terminal of the third inverter are respectively coupled to the first input terminal and the second input terminal of the second NOR gate. The output terminal of the second NOR gate forms the output terminal of the sampling unit.

[0012] Optionally, the boost signal generation module includes a first switch to a fourth switch, a first MOSFET, a first capacitor, a first current source, and a second current source; the control terminals of the first switch and the fourth switch are coupled to the fifth node, the control terminals of the second switch and the third switch are coupled to the fourth node, the first terminal of the first switch, the first terminal of the second switch, the gate of the first MOSFET, and the first terminal of the first capacitor are coupled, the second terminal of the first switch, the second terminal of the first capacitor, and the source / drain of the first MOSFET are coupled to reference ground, the second terminal of the second switch is coupled to the output terminal of the first current source, the output terminal of the second current source, the drain / source of the first MOSFET, and the first terminal of the third switch are coupled to the second node, the input terminals of the first current source, the input terminals of the second current source, and the first terminal of the fourth switch are coupled to a first power supply, and the second terminals of the third switch and the second terminals of the fourth switch are coupled to the control terminal of the boost drive module; And / or, the buck signal generation module includes a fifth to an eighth switch, a second MOSFET, a second capacitor, a third current source, and a fourth current source; the control terminals of the fifth and eighth switches are coupled to the seventh node, the control terminals of the sixth and seventh switches are coupled to the sixth node, the first terminal of the fifth switch, the first terminal of the sixth switch, the gate of the second MOSFET, and the first terminal of the second capacitor are coupled, the second terminal of the fifth switch, the second terminal of the second capacitor, and the source / drain of the second MOSFET are coupled to a second power supply, the second terminal of the sixth switch is coupled to the input terminal of the third current source, the input terminal of the fourth current source, the drain / source of the second MOSFET, and the first terminal of the seventh switch are coupled to the third node, the output terminals of the third and fourth current sources, and the first terminal of the eighth switch are coupled to a reference ground, and the second terminals of the seventh and eighth switches are coupled to the control terminal of the buck drive module.

[0013] Optionally, the boost signal generation module includes a ninth to twelfth switch, a third capacitor, and a fifth current source; the control terminals of the ninth and twelfth switches are coupled to the fifth node, the control terminals of the tenth and eleventh switches are coupled to the fourth node, the first terminals of the ninth, tenth, and eleventh switches and the first terminal of the third capacitor are coupled to the second node, the second terminal of the ninth switch and the second terminal of the third capacitor are coupled to reference ground, the second terminal of the tenth switch is coupled to the output terminal of the fifth current source, the input terminal of the fifth current source and the first terminal of the twelfth switch are coupled to a first power supply, and the second terminals of the eleventh and twelfth switches are coupled to the control terminal of the boost drive module; and / or The step-down signal generation module includes switches 13 to 16, a fourth capacitor, and a sixth current source. The control terminals of the 13th and 16th switches are coupled to the seventh node, the control terminals of the 14th and 15th switches are coupled to the sixth node, the first terminals of the 13th, 14th, and 15th switches and the first terminal of the fourth capacitor are coupled to the third node, the second terminal of the 13th switch and the second terminal of the fourth capacitor are coupled to a second power supply, the second terminal of the 14th switch is coupled to the input terminal of the sixth current source, the output terminal of the sixth current source and the first terminal of the 16th switch are coupled to a reference ground, and the second terminals of the 15th and 16th switches are coupled to the control terminal of the step-down drive module.

[0014] Optionally, the boost signal generation module includes a seventeenth switch, an eighteenth switch, a seventh current source, and a third MOSFET. The control terminal of the seventeenth switch is coupled to the fourth node. The first terminal of the seventeenth switch, the input terminal of the seventh current source, and the gate and drain of the third MOSFET are coupled. The second terminal of the seventeenth switch and the first terminal of the eighteenth switch are coupled to the control terminal of the boost drive module. The control terminal of the eighteenth switch is coupled to the fifth node. The second terminal of the eighteenth switch and the source of the third MOSFET are coupled to a first power supply. The output terminal of the seventh current source is coupled to a reference ground. And / or, the buck signal generation module includes a nineteenth switch, a twentieth switch, an eighth current source, and a fourth MOSFET. The control terminal of the nineteenth switch is coupled to the sixth node. The first terminal of the nineteenth switch, the output terminal of the eighth current source, and the gate and drain of the fourth MOSFET are coupled. The second terminal of the nineteenth switch and the first terminal of the twentieth switch are coupled to the control terminal of the buck drive module. The control terminal of the twentieth switch is coupled to the seventh node. The second terminal of the twentieth switch and the source of the fourth MOSFET are coupled to a reference ground. The input terminal of the eighth current source is coupled to a second power supply.

[0015] Optionally, the boost enhancement shutdown module includes a third sampling module and a third comparator. The output of the third sampling module is coupled to the second input of the boost control module, the input of the third sampling module is coupled to the output of the third comparator, the positive input of the third comparator is coupled to the first node or the second node, and the negative input of the third comparator receives a first reference voltage; and / or, the buck enhancement shutdown module includes a fourth sampling module and a fourth comparator. The output of the fourth sampling module is coupled to the second input of the buck control module, the input of the fourth sampling module is coupled to the output of the fourth comparator, the positive input of the fourth comparator receives a second reference voltage, and the negative input of the fourth comparator is coupled to the first node or the fourth node.

[0016] Optionally, the boost control module includes a fifth sampling module and a third RS flip-flop; the input of the fifth sampling module is coupled to the first output of the DVS enhancement trigger module, the output of the fifth sampling module is coupled to the set terminal of the third RS flip-flop, the reset terminal of the third RS flip-flop is coupled to the output of the boost enhancement shutdown module, and the output of the third RS flip-flop, the control terminal of the boost signal generation module, and the input of the boost enhancement shutdown module are coupled to the eighth node; the boost enhancement shutdown module is configured to reset the boost control module when it is determined that the working time of the boost control module has reached a preset boost time, so as to stop the charging operation of the first node; And / or, the buck control module includes a sixth sampling module and a fourth RS flip-flop; the input terminal of the sixth sampling module is coupled to the second output terminal of the DVS enhancement trigger module, the output terminal of the sixth sampling module is coupled to the set terminal of the fourth RS flip-flop, the reset terminal of the fourth RS flip-flop is coupled to the output terminal of the buck enhancement shutdown module, and the output terminal of the fourth RS flip-flop, the control terminal of the buck signal generation module, and the input terminal of the buck enhancement shutdown module are coupled to the ninth node; the buck enhancement shutdown module is configured to reset the buck control module when it is determined that the working time of the buck control module has reached the preset buck duration, so as to stop the discharge operation of the first node.

[0017] Optionally, the boost signal generation module includes a fourth inverter, the input of which is coupled to the eighth node, and the output of which is coupled to the control terminal of the boost drive module; and / or, the buck signal generation module includes a buffer, the input of which is coupled to the ninth node, and the output of which is coupled to the control terminal of the buck drive module.

[0018] Optionally, the boost enhancement shutdown module includes a first timer, the input of which is coupled to the eighth node, and the output of which is coupled to the second input of the boost control module. The first timer is configured to reset and start timing when the voltage of the eighth node is high, and to reset the boost control module to stop charging the first node when the timing duration reaches the preset boost duration. And / or, the buck enhancement shutdown module includes a second timer, the input of which is coupled to the ninth node, and the output of which is coupled to the second input of the buck control module. The second timer is configured to reset and start timing when the voltage of the ninth node is high, and to reset the buck control module to stop discharging the first node when the timing duration reaches the preset buck duration.

[0019] Optionally, the boost drive module includes a fifth MOS transistor, the gate of which is coupled to the output terminal of the boost signal generation module, the source / drain of which is coupled to a first power supply, and the drain / source of which is coupled to the first node; and / or, the buck drive module includes a sixth MOS transistor, the gate of which is coupled to the output terminal of the buck signal generation module, the source / drain of which is coupled to the first node, and the drain / source of which is coupled to reference ground.

[0020] To achieve the above objectives, the present invention also provides a method for enhancing the rapid voltage switching of a DC-DC circuit. The method includes: receiving a DVS signal from the DC-DC circuit and determining the switching mode of the output voltage of the DC-DC circuit based on the DVS signal; if the switching mode is switching from low voltage to high voltage, charging the voltage output terminal of the DC-DC circuit; if the switching mode is switching from high voltage to low voltage, discharging the voltage output terminal of the DC-DC circuit; determining whether the charging / discharging operation of the voltage output terminal of the DC-DC circuit meets the enhancement shutdown preset condition, and if so, stopping the charging / discharging operation of the voltage output terminal of the DC-DC circuit.

[0021] To achieve the above objectives, the present invention also provides a DC-DC power supply, wherein the DC-DC power supply includes a DC-DC circuit and a voltage fast switching enhancement circuit as described in any of the above claims, wherein the input terminal of the voltage fast switching enhancement circuit receives the DVS signal of the DC-DC circuit, and the output terminal of the voltage fast switching enhancement circuit is coupled to the voltage output terminal of the DC-DC circuit.

[0022] Optionally, the output terminal or reference voltage input terminal of the error amplifier of the DC-DC circuit is coupled to the input terminal of the DVS enhancement trigger module to receive the DVS signal.

[0023] To achieve the above objectives, the present invention also provides a chip, wherein the chip integrates the voltage fast switching enhancement circuit or the DC-DC power supply described in any of the above claims.

[0024] To achieve the above objectives, the present invention also provides an electronic device, which includes the voltage fast switching enhancement circuit described in any of the above claims, or the DC-DC power supply described in any of the above claims, or the chip described in the above claims.

[0025] Compared with existing technologies, the voltage fast switching enhancement circuit, method, DC-DC power supply, chip, and device provided by this invention have the following advantages: The voltage fast switching enhancement circuit provided by this invention can obtain the switching mode of the output voltage of the DC-DC circuit through the DVS enhancement trigger module, and the DVS enhancement trigger module can trigger the boost enhancement sub-circuit to work when the switching mode is from low voltage to high voltage, thereby charging the voltage output terminal of the DC-DC circuit, and trigger the buck enhancement sub-circuit to work when the switching mode is from high voltage to low voltage, thereby discharging the voltage output terminal of the DC-DC circuit. Thus, through the boost enhancement sub-circuit and... The buck-enhancing subcircuit accelerates the charging and discharging operations at the voltage output terminal of the DC-DC circuit, thereby significantly increasing the rate of change of the output voltage during DVS switching and thus greatly shortening the DVS switching time. Furthermore, the DVS enhancement shutdown subcircuit can reset the boost-enhancing subcircuit / buck-enhancing subcircuit when the charging / discharging at the voltage output terminal of the DC-DC circuit meets the enhancement shutdown preset conditions, thereby stopping the charging / discharging operations at the voltage output terminal of the DC-DC circuit. This effectively avoids overcharging or over-discharging of the DC-DC circuit's voltage output terminal, greatly improving the reliability of the DC-DC circuit. In summary, this invention can significantly shorten the DVS switching time of the DC-DC circuit, thereby meeting the timing requirements of the communication system and ensuring communication quality.

[0026] Furthermore, since the voltage fast switching enhancement method, DC-DC power supply, chip, and electronic device provided by this invention belong to the same inventive concept as the voltage fast switching enhancement circuit provided by this invention, the voltage fast switching enhancement method, DC-DC power supply, chip, and electronic device provided by this invention have at least all the advantages of the voltage fast switching enhancement circuit provided by this invention. For details on the beneficial effects of the voltage fast switching enhancement method, DC-DC power supply, chip, and electronic device provided by this invention, please refer to the above description of the beneficial effects of the voltage fast switching enhancement circuit provided by this invention, which will not be repeated here. Attached Figure Description

[0027] Figure 1 This is a block diagram of the voltage fast switching enhancement circuit provided in Embodiment 1 of the present invention.

[0028] Figure 2 This is a structural block diagram of a specific example of the voltage fast switching enhancement circuit provided in Embodiment 1 of the present invention.

[0029] Figure 3 This is a schematic diagram of the topology of the voltage fast switching enhancement circuit provided in the first embodiment of the present invention.

[0030] Figure 4 This is a schematic diagram of the topology of the voltage fast switching enhancement circuit provided in the second embodiment of the first embodiment of the present invention.

[0031] Figure 5 The waveforms of the input and output related signals of the DVS enhancement trigger module during normal operation of the DC-DC circuit are shown.

[0032] Figure 6 The waveform diagram shows the input and output related signals of the DVS enhancement trigger module when the output voltage of the DC-DC circuit switches from low voltage to high voltage.

[0033] Figure 7 The waveform diagram shows the input and output related signals of the DVS enhancement trigger module when the output voltage of the DC-DC circuit switches from high voltage to low voltage.

[0034] Figure 8 This is a schematic diagram of the topology of the sampling unit in one specific example of the voltage fast switching enhancement circuit provided in Embodiment 1 of the present invention.

[0035] Figure 9 for Figure 8 A timing diagram of the input and output signals of the sampling unit.

[0036] Figure 10 This is a schematic diagram of the topology of the voltage fast switching enhancement circuit provided in the third embodiment of the first embodiment of the present invention.

[0037] Figure 11 This is a schematic diagram of the topology of the voltage fast switching enhancement circuit provided in the fourth embodiment of the present invention.

[0038] Figure 12 This is a schematic diagram of the topology of the voltage fast switching enhancement circuit provided in the fifth embodiment of the first embodiment of the present invention.

[0039] Figure 13 This is a schematic diagram of the overall process of the voltage fast switching enhancement method for DC-DC circuits provided in Embodiment 2 of the present invention.

[0040] Figure 14 This is a structural block diagram of a DC-DC power supply provided in Embodiment 3 of the present invention.

[0041] Figure 15 This is a schematic diagram of the circuit topology of a DC-DC power supply provided in one embodiment of the third embodiment of the present invention.

[0042] Figure 16This is a schematic diagram illustrating the enhanced simulation effect of the DC-DC power supply in this embodiment during the switching from low voltage to high voltage (DVS Up).

[0043] Figure 17 This is a schematic diagram illustrating the enhanced simulation effect of the DC-DC power supply during the switching from high voltage to low voltage (DVS Down) provided in this embodiment. Detailed Implementation

[0044] The following detailed description, in conjunction with the accompanying drawings, provides a further detailed explanation of the voltage fast switching enhancement circuit, method, DC-DC power supply, chip, and device proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of this invention. Please refer to the drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this invention. Any modifications to the structure, changes in proportions, or adjustments to the size, provided that the effects and objectives achieved by this invention are the same or similar, should still fall within the scope of the technical content disclosed in this invention. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items, so once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0045] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The singular forms “a,” “an,” and “the” include plural objects. The term “or” is generally used to mean “and / or,” the term “several” is generally used to mean “at least one,” and the term “at least two” is generally used to mean “two or more.” Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0046] It should be understood that when a component is referred to as "connected," "connected to," or "coupled to" other components, it may be directly connected to other components, or there may be intermediary components. Conversely, when a component is referred to as "directly connected" or "directly connected to" other components, there are no intermediary components.

[0047] The purpose of this invention is to provide a voltage fast switching enhancement circuit, method, DC-DC power supply, chip, and device. This invention can significantly shorten the DVS switching time of the DC-DC circuit, thereby meeting the timing requirements of the communication system and ensuring the quality of communication.

[0048] It should be noted that the voltage fast switching enhancement circuit and method provided by this invention can be applied to the DC-DC power supply provided by this invention. The voltage fast switching enhancement circuit, method, DC-DC power supply, and chip provided by this invention can be applied to the electronic devices provided by this invention. It should be noted that the voltage fast switching enhancement circuit and DC-DC power supply provided by this invention are particularly suitable for the radio frequency module of mobile communication terminals. The mobile communication terminal referred to herein is an electronic device that can be used in a mobile environment and supports one or more communication standards, including but not limited to GSM, EDGE, TD-SCDMA, TDD-LTE, and FDD-LTE. For example, the electronic devices described herein include, but are not limited to, mobile phones, laptops, tablets, and in-vehicle computers.

[0049] Example 1

[0050] To achieve the above-mentioned goals, this embodiment provides a voltage fast switching enhancement circuit for DC-DC circuits. For an example, please refer to... Figure 1 , Figure 1 This is a block diagram of the voltage fast switching enhancement circuit provided in this embodiment. From... Figure 1 As can be seen, the voltage fast switching enhancement circuit includes a DVS enhancement trigger module 100, a boost enhancement sub-circuit 200, a buck enhancement sub-circuit 300, and a DVS enhancement shutdown sub-circuit 400; the DVS enhancement trigger module 100 receives the DVS signal, and its first and second output terminals are respectively coupled to the control terminals of the boost enhancement sub-circuit 200 and the buck enhancement sub-circuit 300. The output terminals of the boost enhancement sub-circuit 200, the buck enhancement sub-circuit 300, and the input terminal of the DVS enhancement shutdown sub-circuit 400 are connected to the DC-DC circuit (…). Figure 1 The voltage output terminal (not shown) is coupled to the first node N1. Further, the DVS enhancement trigger module 100 is configured to obtain the switching mode of the output voltage of the DC-DC circuit based on the DVS signal, and trigger the boost enhancement sub-circuit 200 to operate to charge the first node N1 when the switching mode is from low voltage to high voltage (DVS Up); and trigger the buck enhancement sub-circuit 300 to operate to discharge the first node N1 when the switching mode is from high voltage to low voltage (DVS Down); the DVS enhancement shutdown sub-circuit 400 is configured to determine whether the charging / discharging of the first node N1 meets the enhancement shutdown preset condition, and if so, reset the boost enhancement sub-circuit 200 / the buck enhancement sub-circuit 300 to stop the charging / discharging operation of the first node N1.

[0051] The voltage fast switching enhancement circuit provided by this invention can obtain the switching mode of the output voltage Vout of the DC-DC circuit through the DVS enhancement trigger module 100. The DVS enhancement trigger module 100 can trigger the boost enhancement sub-circuit 200 to operate when the switching mode is from low voltage to high voltage, thereby charging the voltage output terminal of the DC-DC circuit (denoted as the first node N1 in this document), and trigger the buck enhancement sub-circuit 300 to operate when the switching mode is from high voltage to low voltage, thereby discharging the voltage output terminal of the DC-DC circuit. Thus, the boost enhancement sub-circuit 200 and the buck enhancement sub-circuit 300 accelerate the switching of the DC-DC circuit. The charging and discharging operations at the voltage output terminal of the DC circuit significantly improve the rate of change of the output voltage of the DCDC circuit during DVS switching, thereby greatly shortening the DVS switching time of the DCDC circuit. Furthermore, the DVS enhancement shutdown sub-circuit 400 can reset the boost enhancement sub-circuit 200 / buck enhancement sub-circuit 300 when the charging / discharging at the voltage output terminal of the DCDC circuit (in this document, designated as the first node N1) meets the enhancement shutdown preset conditions, thus stopping the charging / discharging operations at the voltage output terminal of the DCDC circuit. This effectively avoids overcharging or over-discharging of the voltage output terminal of the DCDC circuit, greatly improving the reliability of the DCDC circuit. In summary, this invention can significantly shorten the DVS switching time of the DCDC circuit, thereby meeting the timing requirements of the communication system and ensuring communication quality.

[0052] Please continue reading Figure 1 Next, combined with Figure 1The working principle of this invention is briefly described as follows: When the DVS signal generated by the system where the DCDC circuit is located (such as an APT power supply) switches the output voltage Vout from low voltage to high voltage, the DVS enhancement trigger module 100 will collect the DVS signal and generate a positive acceleration switching trigger signal to trigger the boost enhancement sub-circuit 200 to work, thereby generating a certain amount of drive current to charge the voltage output terminal of the DCDC circuit, thereby accelerating the DVS switching; the DVS enhancement shutdown sub-circuit 400 detects the circuit state during transient switching in real time, and when the voltage at the voltage output terminal of the DCDC circuit is about to reach the target voltage value, it generates a trigger signal to trigger the boost enhancement sub-circuit 200 to stop working and end the charging operation on the voltage output terminal of the DCDC circuit. Similarly, when the DVS signal generated by the system containing the DC-DC circuit (such as an APT power supply) indicates that the output voltage is switching from high to low, the DVS enhancement trigger module 100 will collect the DVS signal and generate a negative acceleration switching trigger signal to trigger the buck enhancement sub-circuit 300 to work, thereby discharging the voltage output terminal of the DC-DC circuit and accelerating the DVS switching; the DVS enhancement shutdown sub-circuit 400 will detect the circuit state during transient switching in real time, and when the voltage at the voltage output terminal of the DC-DC circuit is about to reach the target voltage value, it will generate a trigger signal to trigger the buck enhancement sub-circuit 300 to stop working and end the discharge operation on the voltage output terminal of the DC-DC circuit.

[0053] For example, in a specific example of applying the voltage fast switching enhancement circuit provided by the present invention (the DC-DC circuit is an APT power supply), with an output load of 3Ω (typically, the load is much smaller than 3Ω), the output voltage can be switched from 0.5V to 90% of 3.4V within 5µs (the time will be even shorter when the load is less than 3Ω); with an unloaded output load (typically, the load is greater than 0Ω), the output voltage can be switched from 3.4V to 0.5V within 5µs (the time will be even shorter when the load is greater than 0Ω).

[0054] For example, in some exemplary embodiments, please refer to Figure 2 , Figure 2 This is a structural block diagram of a specific example of the voltage fast switching enhancement circuit provided in Embodiment 1 of the present invention. (See diagram below.) Figure 2As shown, the first input terminal of the DVS enhancement trigger module 100 receives the DVS signal (such as the output voltage or reference voltage of the error amplifier of the DC-DC circuit). The second and third input terminals of the DVS enhancement trigger module 100 receive a preset reference high voltage VrefH and a preset reference low voltage VrefL, respectively, wherein the preset reference high voltage VrefH is greater than the preset reference low voltage VrefL. Further, the DVS enhancement trigger module 100 is configured such that when the DVS signal is greater than the preset reference high voltage VrefH, it determines that the switching mode is a switch from low voltage to high voltage and triggers the boost enhancement sub-circuit 200 to operate; when the DVS signal is less than the preset reference low voltage VrefL, it determines that the switching mode is a switch from high voltage to low voltage and triggers the buck enhancement sub-circuit 300 to operate.

[0055] Therefore, the voltage fast switching enhancement circuit provided by the present invention enables the DVS enhancement trigger module 100 to determine the switching mode of the output voltage of the DC-DC circuit based on the DVS signal, the preset reference high voltage VrefH and the preset reference low voltage VrefL. The circuit structure is simple and easy to implement.

[0056] It should be noted that the above is only an exemplary description of preferred embodiments and not a limitation of the present invention. For example, in some other embodiments, the DVS enhancement trigger module 100 may also directly receive the signal from the system where the DCDC circuit is located (such as the radio frequency front end). For example, when the DVS signal is a rising edge, it indicates that the switching mode is switching from low voltage to high voltage; when the DVS signal is a falling edge, it indicates that the switching mode is switching from high voltage to low voltage.

[0057] For example, please see Figure 3 or Figure 4 ,in, Figure 3 This is a schematic diagram of the topology of the voltage fast switching enhancement circuit provided in the first embodiment of this invention; Figure 4 This is a schematic diagram of the topology of the voltage fast switching enhancement circuit provided in the second embodiment of this invention. From... Figure 3 or Figure 4 As can be seen, the DVS enhancement trigger module 100 includes a first comparator 101, a second comparator 102, an AND gate 103, and a first NOR gate 104; the negative input terminal of the first comparator 101 receives the preset reference high voltage VrefH, and the positive input terminals of the first comparator 101 and the second comparator 102 are coupled to the output terminal of the error amplifier of the DCDC circuit. Figure 3 and Figure 4 (See diagram of the output voltage VEA of the error amplifier) ​​or the reference voltage input terminal ( Figure 3 and Figure 4 (Illustration of the reference voltage Vref of the error amplifier in the diagram). The negative input terminal of the second comparator 102 receives the preset reference low voltage VrefL. The output terminal of the first comparator 101, the first input terminal of the AND gate 103, and the first input terminal of the first NOR gate 104 are coupled. The output terminal of the second comparator 102, the second input terminal of the AND gate 103, and the second input terminal of the first NOR gate 104 are coupled. The output terminal of the AND gate 103 is coupled to the first input terminal of the boost enhancement sub-circuit 200. Figure 3 and Figure 4 (Illustrated using input signal V103), the output of the first NOR gate 104 is coupled to the first input of the buck enhancement sub-circuit 300. Figure 3 and Figure 4 (Illustration of the use of input signal V104).

[0058] Therefore, the voltage fast switching enhancement circuit provided by the present invention has a DVS enhancement trigger module 100 implemented by a first comparator 101, a second comparator 102, an AND gate 103 and a first NOR gate 104, which is simple in logic and easy to implement.

[0059] It should be noted that the present invention does not impose excessive limitations on the specific values ​​of the preset reference high voltage VrefH and the preset reference low voltage VrefL. Taking the non-inverting input terminal of the first comparator 101 and the non-inverting input terminal of the second comparator 102 coupled to the output terminal or reference voltage input terminal of the error amplifier of the DCDC circuit as an example, in this case, the DVS signal is the output voltage VEA of the error amplifier, the value of the preset reference high voltage VrefH is slightly higher than the output voltage VEA of the error amplifier, and the value of the preset reference low voltage VrefL is slightly lower than the output voltage VEA of the error amplifier. For example, the preset reference high voltage VrefH is 100mV~200mV higher than the output voltage VEA, and the preset reference low voltage VrefL is 100mV~200mV lower than the output voltage VEA.

[0060] Please see Figure 5 , Figure 6 and Figure 7 ,in, Figure 5 The waveforms of the input and output related signals of the DVS enhancement trigger module 100 during normal operation of the DC-DC circuit are shown. Figure 6 The waveform diagram shows the input and output related signals of the DVS enhancement trigger module 100 when the output voltage of the DC-DC circuit switches from low voltage to high voltage. Figure 7The diagram shows the input and output waveforms of the DVS enhancement trigger module 100 when the output voltage of the DCDC circuit switches from high to low voltage. Next, taking the example of the non-inverting input terminals of the first comparator 101 and the second comparator 102 of the DVS enhancement trigger module 100 being coupled to the output of the error amplifier of the DCDC circuit, the following analysis is conducted. Figure 3 and Figure 5 , Figure 6 as well as Figure 7 The working principle of the DVS enhancement trigger module 100 of the voltage fast switching enhancement circuit provided by the present invention is briefly described below.

[0061] Please continue reading Figure 3 or Figure 4 ,Depend on Figure 3 or Figure 4It can be seen that: when VEA < VrefL < VrefH, the first comparator 101 and the second comparator 102 generate comparison judgment signals. The output signal V101 of the first comparator 101 is a low-level signal, i.e., 0. At this time, the output signal V102 of the second comparator 102 is also a low-level signal, i.e., 0. When VrefL < VEA < VrefH, the first comparator 101 and the second comparator 102 generate comparison judgment signals. The output signal V101 of the first comparator 101 is a low-level signal, i.e., 0. At this time, the output signal V102 of the second comparator 102 is a high-level signal, i.e., 1. When VrefL < VrefH < VEA, the first comparator 101 and the second comparator 102 generate comparison judgment signals. The output signal V101 of the first comparator 101 is a high-level signal, i.e., 1. At this time, the output signal V102 of the second comparator 102 is also a high-level signal, i.e., 1. Furthermore, when both the output signal V101 of the first comparator 101 and the output signal V102 of the second comparator 102 are low-level signals (i.e., 0), the output signal V103 of the AND gate 103 (i.e., the signal output from the first output terminal of the DVS enhancement trigger module 100) is low-level (i.e., 0), and the output signal V104 of the first NOR gate 104 (i.e., the signal output from the second output terminal of the DVS enhancement trigger module 100) is high-level (i.e., 1). When the output signal V101 of the first comparator 101 is low-level (i.e., 0) and the output signal V102 of the second comparator 102 is high-level (i.e., 1), the output signal V103 of the AND gate 103 (i.e., the signal output from the second output terminal of the DVS enhancement trigger module 100) is high-level (i.e., 1). When the output signal V103 of the first output terminal is low (i.e., 0), the output signal V104 of the first NOR gate 104 (i.e., the output signal of the second output terminal of the DVS enhancement trigger module 100) is low (i.e., 0). When the output signal V101 of the first comparator 101 is high (i.e., 1), and the output signal V102 of the second comparator 102 is also high (i.e., 1), the output signal V103 of the AND gate 103 (i.e., the output signal of the first output terminal of the DVS enhancement trigger module 100) is high (i.e., 1), and the output signal V104 of the first NOR gate 104 (i.e., the output signal of the second output terminal of the DVS enhancement trigger module 100) is low (i.e., 0). The logical relationship is shown in Table 1 below.

[0062] Table 1: Logical Truth Table of DVS Enhanced Trigger Module 100

[0063]

[0064] For example, please continue to see Figure 2 as well as Figure 3 (or Figure 4 ),like Figure 2 and Figure 3 (or Figure 4 As shown in the diagram, the boost enhancement sub-circuit 200 includes a boost control module 210, a boost signal generation module 220, and a boost drive module 230 connected in sequence. The buck enhancement sub-circuit 300 includes a buck control module 310, a buck signal generation module 320, and a buck drive module 330 connected in sequence. The DVS enhancement shutdown sub-circuit 400 includes a boost enhancement shutdown module 410 and a buck enhancement shutdown module 420. The first and second input terminals of the boost control module 210 are respectively coupled to the first output terminal of the DVS enhancement trigger module 100 and the output terminal of the boost enhancement shutdown module 410. The first and second input terminals of the buck control module 310 are respectively coupled to the second output terminal of the DVS enhancement trigger module 100 and the second output terminal of the DVS enhancement shutdown sub-circuit 400. The output terminals of the boost drive module 230 and the buck drive module 330 are coupled to the first node N1. In some embodiments ( Figure 2 The diagram is illustrated with red dashed lines. For detailed implementation instructions, please refer to [link / reference]. Figure 3 In one embodiment, the input terminal of the boost enhancement shutdown module 410 is coupled to the boost signal generation module 220 at the second node N2, and the input terminal of the buck enhancement shutdown module 420 is coupled to the buck signal generation module 320 at the third node N3; in other embodiments ( Figure 2 The diagram uses blue dashed lines for illustration. For detailed implementation methods, please refer to [link / reference]. Figure 4 In the above, the input terminal of the boost enhancement shutdown module 410 and the input terminal of the buck enhancement shutdown module 420 are coupled to the first node N1.

[0065] Therefore, the voltage fast switching enhancement circuit provided by the present invention employs a boost control module 210, a boost signal generation module 220, and a boost drive module 230 in its enhanced shutdown sub-circuit; a buck enhancement sub-circuit 300 employs a buck control module 310, a buck signal generation module 320, and a buck drive module 330; and a DVS enhancement shutdown sub-circuit 400 employs a boost enhancement shutdown module 410 and a buck enhancement shutdown module 420. This design not only facilitates control and effectively avoids signal crosstalk, but also provides clear logic and ease of implementation.

[0066] It should be understood that, as described above: the boost control module 210 is configured to trigger the boost signal generation module 220 to operate when the switching mode is from low voltage to high voltage (DVS Up), so as to drive the boost drive module 230 to charge the voltage output terminal of the DC-DC circuit; the buck control module 310 is configured to trigger the buck signal generation module 320 to operate when the switching mode is from high voltage to low voltage (DVS Down), so as to drive the buck drive module to discharge the voltage output terminal of the DC-DC circuit.

[0067] For example, please continue to see Figure 3 or Figure 4 ,like Figure 3 or Figure 4 As shown, in some exemplary embodiments, the boost control module 210 includes a first sampling module 211, a first RS flip-flop 212, and a first inverter 213; the input of the first sampling module 211 is coupled to the first output of the DVS enhancement trigger module 100. Figure 3 (Using output signal V103 as an illustration) The output terminal of the first sampling module 211 is coupled to the set terminal S of the first RS flip-flop 212, the reset terminal R of the first RS flip-flop 212 is coupled to the output terminal of the boost enhancement shutdown module 410, the output terminal Q of the first RS flip-flop 212 and the input terminal of the first inverter 213 are coupled to the first control terminal of the boost signal generation module 220 at the fourth node N4, and the output terminal of the first inverter 213 is coupled to the second control terminal of the boost signal generation module 220 at the fifth node N5; the boost enhancement shutdown module 410 is configured to reset the boost control module 210 to stop the charging operation of the first node N1 when it is determined that the voltage of the first node N1 is greater than or equal to the boost enhancement preset value; the boost enhancement preset value is less than the target high voltage value of the voltage switching of the DC-DC circuit.

[0068] Therefore, the voltage fast switching enhancement circuit provided by the present invention adopts a design of first sampling module 211, first RS flip-flop 212 and first inverter 213 in the buck control module 310 of the boost enhancement sub-circuit 200, which is logically clear and easy to implement. Furthermore, when the boost enhancement shutdown module 410 determines that the voltage of the first node N1 is greater than or equal to the boost enhancement preset value, it can reset the boost control module 210 to stop the charging operation of the first node N1 (i.e. the voltage output terminal of the DC-DC circuit), thereby avoiding overcharging and effectively ensuring the reliability of the DC-DC circuit.

[0069] It should be noted that the present invention does not impose too many restrictions on the specific value of the boost enhancement preset value. Preferably, the boost enhancement preset value should be close to the target high voltage value of the voltage switching of the DC-DC circuit. For example, the boost enhancement preset value can be, but is not limited to, 90% or 85% of the target high voltage value.

[0070] For example, please continue to see Figure 3 or Figure 4 ,like Figure 3 or Figure 4 As shown, in some exemplary embodiments, the buck control module 310 includes a second sampling module 311, a second RS flip-flop 312, and a second inverter 313. The input of the second sampling module 311 is coupled to the second output of the DVS enhancement trigger module 100, the output of the second sampling module 311 is coupled to the set terminal S of the second RS flip-flop 312, the reset terminal R of the second RS flip-flop 312 is coupled to the output of the buck enhancement shutdown module 420, and the output Q of the second RS flip-flop 312 and the second inverter 313 are also connected. The input terminal is coupled to the first control terminal of the buck signal generation module 320 at the sixth node N6, and the output terminal of the second inverter 313 is coupled to the second control terminal of the buck signal generation module 320 at the seventh node N7; the buck enhancement shutdown module 420 is configured to reset the buck control module 310 when it is determined that the voltage of the first node N1 is less than or equal to the buck enhancement preset value, so as to stop the discharge operation of the first node N1 (i.e., the voltage output terminal of the DC-DC circuit); the buck enhancement preset value is greater than the target low voltage value of the voltage switching of the DC-DC circuit.

[0071] Therefore, the voltage fast switching enhancement circuit provided by the present invention adopts a design of a second sampling module 311, a second RS flip-flop 312, and a second inverter 313 in its buck control module 310. The logic is clear and easy to implement. Furthermore, when the buck enhancement shutdown module 420 determines that the voltage of the first node N1 is less than or equal to the buck enhancement preset value, it can reset the buck control module 310 to stop the discharge operation on the first node N1. This can avoid over-discharge and effectively ensure the reliability of the DC-DC circuit.

[0072] It should be noted that the present invention does not impose too many restrictions on the specific value of the step-down enhancement preset value. Preferably, the step-down enhancement preset value should be close to the target low voltage value of the voltage switching of the DC-DC circuit. For example, the boost enhancement preset value can be, but is not limited to, 110% or 105% of the target low voltage value.

[0073] It should be noted that, although Figure 3 and Figure 4 The boost control module 210 includes a first sampling module 211, a first RS flip-flop 212, and a first inverter 213. The buck control module 310 is exemplified by a symmetrical design using a second sampling module 311, a second RS flip-flop 312, and a second inverter 313. However, this is not a limitation of the present invention. The present invention does not impose excessive restrictions on the specific implementation of the boost control module 210 and the buck control module 310, as long as the boost control module 210 can trigger the boost signal generation module 220 to work when the output voltage of the DC-DC circuit switches from low voltage to high voltage and can trigger the boost signal generation module 220 to stop working under the drive of the boost enhancement shutdown module 410, and the buck control module 310 can trigger the buck signal generation module 320 to work when the output voltage of the DC-DC circuit switches from high voltage to low voltage and can trigger the buck signal generation module 320 to stop working under the drive of the buck enhancement shutdown module 420.

[0074] It should be noted that the present invention does not impose excessive limitations on the specific implementation of the first sampling module 211 and the second sampling module 311. Preferably, the first sampling module 211 and the second sampling module 311 have the same structure. For example, please refer to [link to relevant documentation]. Figure 8 , Figure 8 This is a schematic diagram of the topology of the sampling unit in one specific example of the voltage fast switching enhancement circuit provided in this embodiment. Figure 8 As shown, in some exemplary embodiments, the sampling unit includes a delay unit 201, a third inverter 202, and a second NOR gate 203. The input terminals of the delay unit 201 and the third inverter 202 share a common connection point to form the input terminal of the sampling unit. The output terminals of the delay unit 201 and the third inverter 202 are respectively coupled to the first and second input terminals of the second NOR gate 203. The output terminal of the second NOR gate 203 forms the output terminal of the sampling unit.

[0075] Please see Figure 9 , Figure 9 for Figure 8 A timing diagram of the input and output signals of the sampling unit. (See diagram below.) Figure 9 As shown, delay unit 201 delays the input signal VIN to obtain signal VA, third inverter 202 inverts the input signal VIN to obtain signal VB, and second NOR gate 203 performs logic processing on signals VA and VB to obtain signal Vo, thereby completing the rising edge picking operation of input signal VIN.

[0076] For example, please continue to see Figure 3 or Figure 4 ,like Figure 3 or Figure 4 As shown, in some preferred embodiments, the boost signal generation module 220 includes a first switch S1 to a fourth switch S4, a first MOSFET M1, a first capacitor C1, a first current source I1, and a second current source I2; the control terminals of the first switch S1 and the fourth switch S4 are coupled to the fifth node N5, the control terminals of the second switch S2 and the third switch S3 are coupled to the fourth node N4, the first terminal of the first switch S1, the first terminal of the second switch S2, the gate of the first MOSFET M1, and the first terminal of the first capacitor C1 are coupled, and the second terminal of the first switch S1, the second terminal of the first capacitor C1, and the first MOSFET M1 (… Figure 3 and Figure 4 (Taking the first MOS transistor M1 as an example of a PMOS transistor) source / drain, Figure 3 (Example of a PMOS transistor with its drain grounded) Coupled to reference ground, the second terminal of the second switch S2 is coupled to the output terminal of the first current source I1, and the output terminal of the second current source I2 and the drain / source of the first MOS transistor M1 ( Figure 3 and Figure 4 (Example: the source of a PMOS transistor) and the first terminal of the third switch S3 are coupled to the second node N2. The input terminals of the first current source I1, the second current source I2, and the first terminal of the fourth switch S4 are coupled to the first power supply VDD1. The second terminals of the third switch S3 and the second terminals of the fourth switch S4 are coupled to the control terminal of the boost drive module 230.

[0077] It should be noted that the present invention does not impose too many limitations on the first MOS transistor M1. In some exemplary embodiments, the first MOS transistor M1 can be an NMOS transistor; in other embodiments, the first MOS transistor M1 can also be a PMOS transistor.

[0078] For example, please continue to see Figure 3 or Figure 4 ,like Figure 3 or Figure 4As shown, in some preferred embodiments, the step-down signal generation module 320 includes a fifth switch S5 to an eighth switch S8, a second MOSFET M2, a second capacitor C2, a third current source I3, and a fourth current source I4; the control terminals of the fifth switch S5 and the eighth switch S8 are coupled to the seventh node N7, the control terminals of the sixth switch S6 and the seventh switch S7 are coupled to the sixth node N6, the first terminal of the fifth switch S5, the first terminal of the sixth switch S6, the gate of the second MOSFET M2, and the first terminal of the second capacitor C2 are coupled, and the second terminal of the fifth switch S5, the second terminal of the second capacitor C2, and the second MOSFET M2 ( Figure 3 and Figure 4 The source / drain of the second MOS transistor M2 as an example of an NMOS transistor (using M2 as an example of an NMOS transistor). Figure 3 and Figure 4 (The middle part is a schematic diagram of the drain of the NMOS transistor) is coupled to the second power supply VDD2. The second terminal of the sixth switch S6 is coupled to the input terminal of the third current source I3. The input terminal of the fourth current source I4 and the drain / source of the second MOS transistor M2 ( Figure 3 and Figure 4 (Example: the source of an NMOS transistor) and the first terminal of the seventh switch S7 are coupled to the third node N3. The output terminal of the third current source I3, the output terminal of the fourth current source I4, and the first terminal of the eighth switch S8 are coupled to reference ground. The second terminal of the seventh switch S7 and the second terminal of the eighth switch S8 are coupled to the control terminal of the buck drive module 330.

[0079] It should be noted that the present invention does not impose any limitation on the specific values ​​of the power supply voltages provided by the first power supply VDD1 and the second power supply VDD2. The power supply voltages of the two can be the same or different.

[0080] For example, please continue to see Figure 3 or Figure 4 ,like Figure 3 or Figure 4 As shown, in some exemplary embodiments, the boost enhancement shutdown module 410 includes a third sampling module 411 and a third comparator 412. The output of the third sampling module 411 is coupled to the second input of the boost control module 210, and the input of the third sampling module 411 is coupled to the output of the third comparator 412. Figure 3 In the first embodiment shown, the non-inverting input of the third comparator 412 is coupled to the second node N2; Figure 4In the second embodiment shown, the positive input of the third comparator 412 is coupled to the first node N1. The negative input of the third comparator 412 receives the first reference voltage Vref1.

[0081] For example, please continue to see Figure 3 or Figure 4 ,like Figure 3 or Figure 4 As shown, in some exemplary embodiments, the buck-boost shutdown module 420 includes a fourth sampling module 421 and a fourth comparator 422. The output of the fourth sampling module 421 is coupled to the second input of the buck control module 310, and the input of the fourth sampling module 421 is coupled to the output of the fourth comparator 422. The non-inverting input of the fourth comparator 422 receives a second reference voltage Vref2. Figure 3 In the first embodiment shown, the negative inverting input of the fourth comparator 422 is coupled to the third node N3; Figure 4 In the second embodiment shown, the negative phase input of the fourth comparator 422 is coupled to the first node N1.

[0082] For more detailed information about the third sampling module 411 and the fourth sampling module 421, please refer to [link / reference]. Figure 8 and Figure 9 The relevant explanations regarding the first sampling module 211 and the second sampling module 311 mentioned above are for illustrative purposes and will not be elaborated upon here.

[0083] For example, please continue to see Figure 3 or Figure 4 ,like Figure 3 or Figure 4 As shown, in some exemplary embodiments, the boost drive module 230 includes a fifth MOS transistor M5, the gate of which is coupled to the output of the boost signal generation module. Figure 3 The fifth MOS transistor, M5, is used as the source / drain of the PMOS transistor. Figure 3 and Figure 4 (Example: The source of a PMOS transistor is coupled to the first power supply VDD1, and the drain / source of the fifth MOS transistor M5 is coupled to the first node N1.)

[0084] Therefore, by using the fifth MOSFET M5 to implement the boost drive module 230, it is possible not only to effectively charge the voltage output terminal of the DC-DC circuit, but also to achieve simple logic and easy implementation.

[0085] For example, please continue to see Figure 3 or Figure 4 ,like Figure 3 or Figure 4 As shown, in some exemplary embodiments, the buck drive module 330 includes a sixth MOS transistor M6, the gate of which is coupled to the output of the buck signal generation module 320, and the sixth MOS transistor M5 ( Figure 3 and Figure 4 The source / drain of the sixth MOS transistor M6 (as an example of an NMOS transistor) Figure 3 and Figure 4 (Using an example of an NMOS transistor drain) is coupled to the first node N1, and the drain / source of the sixth MOS transistor M6 is coupled to reference ground.

[0086] Therefore, by using the sixth MOSFET M6 to implement the buck drive module 330, it is possible not only to effectively discharge the voltage output terminal of the DC-DC circuit, but also to achieve simple logic and easy implementation.

[0087] Next, with Figure 3 Taking the first embodiment shown as an example, the working principle of the voltage fast switching enhancement circuit provided by the present invention is explained as follows.

[0088] When the DC-DC circuit is working normally, such as Figure 5 As shown, the voltage VEA of the internal nodes of the DCDC circuit (such as the output voltage of the error amplifier) ​​and the ramp voltage Vramp must have an intersection point, thereby generating a specific duty cycle signal to control the output voltage of the DCDC circuit. At this time, VrefL < VEA < VrefH. As analyzed above, the output signal V101 of the first comparator 101 is 0, the output signal V102 of the second comparator 102 is 1, the output signal V103 of the AND gate 103 (i.e., the output signal of the first output terminal of the DVS enhancement trigger module 100) is 0, and the output signal V104 of the first NOR gate 104 (i.e., the output signal of the second output terminal of the DVS enhancement trigger module 100) is also 0. Since the output signals V103 and V104 of the first and second output terminals of the DVS enhancement trigger module 100 are both 0, the boost enhancement sub-circuit 200 and the buck enhancement sub-circuit 300 are not working. When the switching mode of the output voltage of the DCDC circuit is from low voltage to high voltage, as... Figure 6As shown, VEA will suddenly rise, exceeding the preset reference high voltage VrefH, i.e., satisfying VrefL < VrefH < VEA. As analyzed above, the output signal V101 of the first comparator 101 changes from 0 to 1, while the output signal V102 of the second comparator 102 remains unchanged at 1. At this time, the output signal V103 of the AND gate 103 (i.e., the output signal of the first output terminal of the DVS enhancement trigger module 100) changes from 0 to 1, and the output signal V104 of the first NOR gate 104 (i.e., the output signal of the second output terminal of the DVS enhancement trigger module 100) remains unchanged at 0. Since the output signal V103 of the first output terminal of the DVS enhancement trigger module 100 is 1 and the output signal V104 of the second output terminal is 0, the boost enhancement sub-circuit 200 (in this case, the signal V103 received by the first sampling module 211 of the boost control module 210 changes from 0 to 1) works while the buck enhancement sub-circuit 300 does not work. When the switching mode of the output voltage of the DCDC circuit is from high voltage to low voltage, as shown in the figure... Figure 7 As shown, VEA will suddenly drop, falling below the preset reference low voltage VrefL, i.e., satisfying VEA < VrefL < VrefH. As analyzed above, the output signal V101 of the first comparator 101 remains unchanged at 0, while the output signal V102 of the second comparator 102 changes from 1 to 0. At this time, the output signal V103 of the AND gate 103 (i.e., the output signal of the first output terminal of the DVS enhancement trigger module 100) is 0, and the output signal V104 of the first NOR gate 104 (i.e., the output signal of the second output terminal of the DVS enhancement trigger module 100) changes from 0 to 1. Since the output signal V103 of the first output terminal of the DVS enhancement trigger module 100 is 0 and the output signal V104 of the second output terminal is 1, the boost enhancement sub-circuit 200 does not work, while the buck enhancement sub-circuit 300 (in this case, the signal V104 received by the second sampling module 311 of the buck control module 310 changes from 0 to 1) works.

[0089] When the DC-DC circuit is working normally or the DC-DC circuit's output voltage switching mode is from low voltage to high voltage, since the signal V103 received by the first sampling module 211 of the boost control module 210 is in a state of 0, it will not trigger the first RS flip-flop 212 of the boost control module 210 after passing through the first sampling module 211. That is, the first RS flip-flop 212 is in a reset state, which means the boost control module 210 is in a reset state. The output signal V202 of the output port Q of the first RS flip-flop 212 is in a state of 0. The output signal V203 after passing through the first inverter 213 will be in a state of 1. Signals V202 and V203 are a pair of inverted signals and are output to the boost signal generation module 220 together. They will not drive the boost signal generation module 220 to work. When the output voltage switching mode of the DC-DC circuit is from low voltage to high voltage, the signal V103 received by the first sampling module 211 of the boost control module 210 changes from 0 to 1. This signal is then converted into a pulse signal V201 by the first sampling module 211 (rising edge sampling circuit). This pulse signal V201 triggers the first RS flip-flop 212 of the boost control module 210, thereby setting the output signal V202 at the output port Q of the first RS flip-flop 212 from 0 to 1. After passing through the first inverter 213, the output signal V203 changes from 1 to 0. Signals V202 and V203 are an inverted pair. When the output voltage switching mode of the DC-DC circuit is from low voltage to high voltage, signal V202 is in the state of 1, and signal V203 is in the state of 0. Both are output to the boost signal generation module 220, driving the boost signal generation module 220 to operate.

[0090] Furthermore, when the DC-DC circuit is operating normally or the switching mode of the DC-DC circuit's output voltage is from high voltage to low voltage, that is, when the boost control module 210 is in a reset state (i.e., signal V202 is 0, signal V203 is 1), the boost signal generation module 220 receives signals V202 and V203 from the boost control module 210. Signal V202 controls the second switch S2 and the third switch S3 to open, and signal V203 controls the first switch S1 and the fourth switch S4 to close. The first capacitor C1 is shorted to ground, and the control terminal of the boost drive module 230 of the boost enhancement sub-circuit 200 ( Figure 3 (In the diagram, signal V303 is used) is shorted to the first power supply VDD1. At this time, the gate of the first MOSFET M1 ( Figure 3 and Figure 4 If the potential of signal V301 (indicated by the signal) is 0, then the source / drain of the first MOS transistor M1 ( Figure 3 and Figure 4The source of the PMOS transistor (as shown in the example) is at a relatively low voltage value, namely Vgsp (gate-source voltage). Meanwhile, the control terminal of the boost drive module 230 (… Figure 3 and Figure 4 (Illustrated by signal V303) is shorted to the power supply. Signal V303 will be sent to the boost drive module 230 (i.e., the fifth MOSFET M5), causing the fifth MOSFET M5 ( Figure 3 and Figure 4 In the example using the fifth MOSFET M5 as a PMOS transistor, the transistor is turned off (not working), thus having no effect on the voltage output of the DC-DC circuit. When the DC-DC circuit's output voltage switching mode is from low voltage to high voltage, i.e., signal V202 is 1 and signal V203 is 0, signal V202 controls the second switch S2 and the third switch S3 to close, and signal V203 controls the first switch S1 and the fourth switch S4 to open. The first capacitor C1 is charged by the first current source I1 with a constant current, thereby affecting the gate of the first MOSFET M1. Figure 3 and Figure 4 A voltage signal with a specific slope is generated on the signal V301 (illustrated). Assuming the charging current is I and the capacitance of the first capacitor C1 is C, the expression for the voltage of signal V301 changing with time t is shown in equation (1) below.

[0091] (1)

[0092] The signal V301 passes through the source / gate of the first MOS transistor M1 ( Figure 3 and Figure 4 (Using the source of a PMOS transistor as an example) the follower effect drives the second node N2, causing the voltage of signal V302 to rise at the same slope. Therefore, the expression for the voltage of signal V302 changing with time t is shown in equation (2) below.

[0093] (2)

[0094] Signal V203 controls the first switch S1 to open. Since the third switch S3 is closed and the fourth switch S4 is open, the second node N2 is connected to the control terminal of the boost drive module 230. Figure 3 and Figure 4 (Using the fifth MOSFET M5 as an example of a PMOS transistor) will be shorted together, so the voltage change of signal V303 is consistent with the voltage change of signal V302. The voltage signal of signal V303 will be supplied to the fifth MOSFET M5, thereby turning on the fifth MOSFET M5; the specific magnitude and slope of signal V302 can control the magnitude of the current flowing through the fifth MOSFET M5, thereby driving the output load and accelerating the response speed of the DC-DC circuit from low voltage to high voltage, that is, improving the switching speed from low voltage to high voltage.

[0095] The boost enhancement shutdown module 410 monitors the changes in the internal signal V302 of the boost signal generation module. When signal V302 rises to a certain voltage value, i.e., exceeds the first reference voltage Vref1, the third comparator 412 of the boost enhancement shutdown module 410 generates a high-level reset signal V401, which is simultaneously sent to the third sampling module 411 (rising edge sampling circuit). The third sampling module 411 converts the reset signal V401 into a reset pulse signal V402 and sends it to the boost control module 210. The boost control module 210 receives the reset pulse signal V402 from the boost enhancement shutdown module 410 (the reset terminal R of the first RS flip-flop 212 receives the reset pulse signal V402), thereby putting the boost control module 210 into a reset state. At this time, the state of signal V202 is reset to 0, and the state of signal V203 is inverted to 1, driving the boost signal generation module 220 to stop working, thereby stopping the charging operation of the voltage output terminal of the DC-DC circuit.

[0096] When the DC-DC circuit is working normally or the DC-DC circuit's output voltage switching mode is from low voltage to high voltage, since the signal V104 received by the second sampling module 311 of the buck control module 310 is in a state of 0, the second RS flip-flop 312 of the buck control module 310 will not be triggered after passing through the second sampling module 311. That is, the second RS flip-flop 312 is in a reset state, which means the buck control module 310 is in a reset state. The output signal V602 of the output port Q of the second RS flip-flop 312 is in a state of 0. The output signal V603 after passing through the second inverter 313 will be in a state of 1. Signals V602 and V603 are a pair of inverted signals and are output to the buck signal generation module 320 together. The buck signal generation module 320 will not be driven to work. When the output voltage switching mode of the DC-DC circuit is from high voltage to low voltage, the signal V104 received by the second sampling module 311 of the buck control module 310 changes from 0 to 1. This signal is then converted into a pulse signal V601 by the second sampling module 311 (rising edge sampling circuit). This pulse signal V601 triggers the second RS flip-flop 312 of the buck control module 310, thereby setting the output signal V602 of the output port Q of the second RS flip-flop 312 from 0 to 1. After passing through the second inverter 313, the output signal V603 changes from 1 to 0. Signals V602 and V603 are an inverted pair. When the output voltage switching mode of the DC-DC circuit is from high voltage to low voltage, signal V602 is in the state of 1, and signal V603 is in the state of 0. Both are output to the buck signal generation module 320, driving the buck signal generation module 320 to operate.

[0097] Furthermore, when the DC-DC circuit is operating normally or the switching mode of the DC-DC circuit's output voltage is from low voltage to high voltage, that is, when the buck control module 310 is in a reset state (i.e., signal V602 is 0, signal V603 is 1), the buck signal generation module 320 receives signals V602 and V603 from the buck module. Signal V602 controls the sixth switch S6 and the seventh switch S7 to open, and signal V603 controls the fifth switch S5 and the eighth switch S8 to close. The second capacitor C2 is shorted to the second power supply VDD2, and the control terminal of the buck drive module 330 of the buck signal generation module 320 is shorted to ground. At this time, the second MOSFET M2 ( Figure 3 and Figure 4 The gate of the second MOS transistor (using the NMOS transistor as an example) Figure 3 If the potential of signal V701 is VDD (taking the supply voltage of the second power supply VDD2 as an example), then the source / drain of the second MOSFET M2 ( Figure 3 and Figure 4 (Using an NMOS transistor as an example) a relatively high voltage value, namely VDD - Vgsn (gate-source voltage). Meanwhile, the control terminal of the buck driver module 330 ( Figure 3 and Figure 4 When signal V703 (illustrated in the diagram) is shorted to ground, signal V703 will be sent to the buck driver module 330 (i.e., the sixth MOS transistor M6), causing the sixth MOS transistor M6 to turn off (not work), thus not affecting the voltage output of the DC-DC circuit. When the switching mode of the DC-DC circuit output voltage is from high voltage to low voltage, that is, signal V602 is 1 and signal V603 is 0, at this time signal V602 controls the sixth switch S6 and the seventh switch S7 to close, and signal V603 controls the fifth switch S5 and the eighth switch S8 to open. The second capacitor C2 is discharged by the third current source I3 with a constant current, thereby generating a voltage signal V701 with a specific slope at the gate of the second MOS transistor M2. Assuming the discharge current is I and the capacitance of the second capacitor C2 is C, the expression for the voltage change of signal V701 with time is shown in formula (3).

[0098] (3)

[0099] The signal V701 passes through the source / gate of the second MOSFET M2 ( Figure 3 and Figure 4 (Example of the source of the NMOS transistor) The follower action drives the third node N3, causing the voltage of signal V702 to decrease at the same slope. Therefore, the expression for the voltage of signal V702 changing with time t is shown in equation (4).

[0100] (4)

[0101] Signal V603 controls the eighth switch S8 to open. Since the seventh switch S7 is closed and the eighth switch S8 is open, the third node N3 is connected to the control terminal of the buck driver module 330. Figure 3 and Figure 4 The signal V703 (as illustrated in the diagram) will be shorted together, therefore the voltage change of signal V703 will be consistent with the voltage change of signal V702. The voltage signal of signal V703 will be supplied to the sixth MOSFET M6 ( Figure 3 and Figure 4 (Using the sixth MOSFET M6 as an NMOS example), the sixth MOSFET M6 is turned on. The specific magnitude and slope of the signal V702 can control the magnitude of the current flowing through the sixth MOSFET M6, thereby driving the output load and accelerating the response speed of the DC-DC circuit from high voltage to low voltage, that is, improving the switching speed from high voltage to low voltage.

[0102] The buck enhancement shutdown module 420 monitors the changes in the internal signal V702 of the buck signal generation module 320. When signal V702 drops to a certain voltage value, i.e., below the second reference voltage Vref2, the fourth comparator 422 of the buck enhancement shutdown module 420 generates a high-level reset signal V801, which is simultaneously sent to the fourth sampling module 421 (rising edge sampling circuit). The fourth sampling module 421 converts the reset signal V801 into a reset pulse V802 and sends it to the reset terminal R of the second RS flip-flop 312, thereby putting the buck control module 310 in a reset state. At this time, the state of signal V602 is 0, and the state of signal V603 is inverted to 1, driving the buck signal generation module 320 to stop working, thereby stopping the discharge operation on the voltage output terminal of the DC-DC circuit.

[0103] As mentioned above, Figure 4 The second embodiment shown is the same as Figure 3 The difference in the first embodiment shown is that, Figure 3 The positive input terminal of the third comparator 412 of the boost enhancement shutdown module 410 is coupled to the second node N2, and the negative input terminal of the fourth comparator 422 of the buck enhancement shutdown module 420 is coupled to the third node N3. Figure 4 The positive input of the third comparator 412 of the boost enhancement shutdown module 410 and the negative input of the fourth comparator 422 of the buck enhancement shutdown module 420 are both coupled to the first node N1. Because... Figure 4 The working principle of the voltage fast switching enhancement circuit provided in the second embodiment shown is the same as... Figure 3 The working principle of the first embodiment shown is the same, and to avoid redundancy, it will not be described again here. Figure 4The working principle of the voltage fast switching enhancement circuit provided in the second embodiment shown will be explained in detail below. Figure 4 The operating principle of the voltage fast switching enhancement circuit provided in the second embodiment shown can be understood by referring to the description above.

[0104] The third embodiment of this invention provides yet another voltage fast switching enhancement circuit. The voltage fast switching enhancement circuit provided in this embodiment differs from the first embodiment in that the implementation of the boost signal generation module 220 and / or the buck signal generation module 320 is different. To avoid redundancy, the following only describes the differences from the first embodiment. For parts not mentioned in this embodiment, please refer to the relevant descriptions above for an adaptive understanding. For example, please refer to... Figure 10 , Figure 10 This is a schematic diagram of the topology of the voltage fast switching enhancement circuit provided in the third embodiment of this invention. From... Figure 10 As can be seen, in this embodiment, the boost signal generation module 220 includes a ninth switch S9 to a twelfth switch S12, a third capacitor C3, and a fifth current source I5; the control terminals of the ninth switch S9 and the twelfth switch S12 are coupled to the fifth node N5, the control terminals of the tenth switch S10 and the eleventh switch S11 are coupled to the fourth node N4, the first terminals of the ninth switch S9, the tenth switch S10, the eleventh switch S11, and the third capacitor C3 are coupled to the second node N2, the second terminals of the ninth switch S9 and the third capacitor C3 are coupled to reference ground, the second terminal of the tenth switch S10 is coupled to the output terminal of the fifth current source I5, the input terminal of the fifth current source I5 and the first terminal of the twelfth switch S12 are coupled to the first power supply VDD1, and the second terminals of the eleventh switch S11 and the twelfth switch S12 are coupled to the control terminal of the boost drive module 230.

[0105] For example, please continue to see Figure 10 ,like Figure 10As shown, in some exemplary embodiments, the buck signal generation module 320 includes thirteenth switches S13 to sixteenth switches S16, a fourth capacitor C4, and a sixth current source I6; the control terminals of the thirteenth switch S13 and the sixteenth switch S16 are coupled to the seventh node N7, the control terminals of the fourteenth switch S14 and the fifteenth switch S15 are coupled to the sixth node N6, the first terminals of the thirteenth switch S13, the fourteenth switch S14, the fifteenth switch S15, and the fourth capacitor C4 are coupled to the third node N3, the second terminal of the thirteenth switch S13 and the second terminal of the fourth capacitor C4 are coupled to the second power supply VDD2, the second terminal of the fourteenth switch S14 is coupled to the input terminal of the sixth current source I6, the output terminal of the sixth current source I6 and the first terminal of the sixteenth switch S16 are coupled to reference ground, and the second terminals of the fifteenth switch S15 and the sixteenth switch S16 are coupled to the control terminal of the buck drive module 330.

[0106] By comparison, it is easy to find that, compared with the voltage fast switching enhancement circuit provided in the first embodiment, the boost signal generation module 220 of this embodiment saves the first MOS transistor M1 and the second current source I2, and the buck signal generation module 320 saves the second MOS transistor M2 and the fourth current source I4.

[0107] The working principle of the boost signal generation module 220 and the buck signal generation module 320 of the voltage fast switching enhancement circuit provided in this embodiment are briefly described below. As mentioned above, for any content not mentioned (such as the case when the boost signal generation module 220 and the buck signal generation module 320 are not working) and the working principle of related modules, please refer to the description above for an adaptive understanding.

[0108] Please continue reading Figure 10 When the DC-DC circuit's output voltage switching mode is from low voltage to high voltage (i.e., signal V202 is 1 and signal V203 is 0), signal V202 controls the 10th switch S10 and the 11th switch S11 to close, and signal V203 controls the 9th switch S9 and the 12th switch S12 to open. When the 11th switch S11 is closed, the second node N2 and the control terminal of the boost drive module 230 ( Figure 10(Signal V303 is used in the diagram) is shorted, so the voltage change of signal V303 is consistent with the voltage change of signal V301. Signal V303 will be supplied to the fifth MOSFET M5, thereby turning on the fifth MOSFET M5 and realizing the charging operation of the voltage output terminal of the DC-DC circuit, thereby accelerating the response speed of the DC-DC circuit from low voltage to high voltage, that is, improving the switching speed from low voltage to high voltage. Similarly, when the switching mode of the output voltage of the DC-DC circuit is from high voltage to low voltage, that is, signal V602 is 1 and signal V603 is 0, at this time signal V602 controls the fourteenth switch S14 and the fifteenth switch S15 to close, and signal V603 controls the thirteenth switch S13 and the sixteenth switch S16 to open. When the fifteenth switch S15 is closed, the third node N3 and the control terminal of the buck driver module 330 ( Figure 10 (In the diagram, signal V703 is shorted, so the voltage change of signal V703 is consistent with the voltage change of signal V701.) The voltage signal of signal V703 is supplied to the sixth MOSFET M6, thereby turning on the sixth MOSFET M6 and realizing the discharge operation of the voltage output terminal of the DC-DC circuit, thus accelerating the response speed of the DC-DC circuit from high voltage to low voltage, that is, improving the switching speed from high voltage to low voltage.

[0109] The fourth embodiment of this invention provides yet another voltage fast switching enhancement circuit. The voltage fast switching enhancement circuit provided in this embodiment differs from the second embodiment in that the implementation of the boost signal generation module 220 and / or the buck signal generation module 320 is different. To avoid redundancy, the following only describes the differences from Embodiment 1. For parts not mentioned in this embodiment, please refer to the relevant descriptions above for an adaptive understanding. For example, please refer to... Figure 11 , Figure 11 This is a schematic diagram of the topology of the voltage fast switching enhancement circuit provided in the fourth embodiment of this invention. From... Figure 11 As can be seen, in this embodiment, the boost signal generation module 220 includes a seventeenth switch S17, an eighteenth switch S18, a seventh current source I7, and a third MOSFET M3. The control terminal of the seventeenth switch S17 is coupled to the fourth node N4. The first terminal of the seventeenth switch S17, the input terminal of the seventh current source I7, and the third MOSFET M3 ( Figure 11 The gate and drain of the third MOS transistor M3 (as an example of a PMOS transistor) are coupled, and the second terminal of the seventeenth switch S17 and the first terminal of the eighteenth switch S18 are coupled to the control terminal of the boost drive module 230. Figure 11(Illustrated by signal V303 in the diagram), the control terminal of the eighteenth switch S18 is coupled to the fifth node N5, the second terminal of the eighteenth switch S18 and the source of the third MOS transistor M3 are coupled to the first power supply VDD1, and the output terminal of the seventh current source I7 is coupled to the reference ground.

[0110] For example, please continue to see Figure 11 ,like Figure 11 As shown, in some exemplary embodiments, the buck signal generation module 320 includes a nineteenth switch S19, a twentieth switch S20, an eighth current source I8, and a fourth MOSFET M4. The control terminal of the nineteenth switch S19 is coupled to the sixth node N6. The first terminal of the nineteenth switch S19, the output terminal of the eighth current source I8, and the fourth MOSFET M4 ( Figure 11 The gate and drain of the fourth MOS transistor M4 (using NMOS as an example) are coupled, and the second terminal of the nineteenth switch S19 and the first terminal of the twentieth switch S20 are coupled to the control terminal of the buck drive module 330. Figure 11 (See diagram of signal V703). The control terminal of the twentieth switch S20 is coupled to the seventh node N7. The second terminal of the twentieth switch S20 and the source of the fourth MOS transistor M4 are coupled to reference ground. The input terminal of the eighth current source I8 is coupled to the second power supply VDD2.

[0111] The working principle of the boost signal generation module 220 and the buck signal generation module 320 of the voltage fast switching enhancement circuit provided in this embodiment are briefly described below. As mentioned above, for any content not mentioned (such as the case when the boost signal generation module 220 and the buck signal generation module 320 are not working) and the working principle of related modules, please refer to the description above for an adaptive understanding.

[0112] Please continue reading Figure 11 When the DC-DC circuit is working normally or the DC-DC circuit's output voltage switching mode is from low voltage to high voltage, that is, when the boost control module 210 is in a reset state (i.e., signal V202 is 0 and signal V203 is 1), the boost signal generation module 220 receives signals V202 and V203 from the boost control module 210. At this time, signal V202 controls the seventeenth switch S17 to open, and signal V203 controls the eighteenth switch S18 to close. The control terminal of the boost drive module 230 ( Figure 11When signal V303 is shorted to the power supply, signal V303 is sent to the boost drive module 230 (i.e., the fifth MOSFET M5), causing the fifth MOSFET M5 to turn off (not work), thus not affecting the voltage output of the DC-DC circuit. When the DC-DC circuit's output voltage switching mode is from low voltage to high voltage, i.e., signal V202 is 1 and signal V203 is 0, when signal V202 is high and signal V203 is low, signal V202 controls the seventeenth switch S17 to close, and signal V203 controls the eighteenth switch S18 to open. At this time, the gate of the third MOSFET M3 ( Figure 11 (Signal V301 is shown in the diagram) and the control terminal of the boost drive module 230 ( Figure 11 (Signal V303 is shown in the diagram) is shorted by the seventeenth switch S17. The sources of the third MOSFET M3 and the fifth MOSFET M5 are connected together, and their gates are also connected together. Therefore, the third MOSFET M3 and the fifth MOSFET M5 form a mirror current source structure. The fifth MOSFET M5 mirrors the current flowing through the seventh current source I7 and the current in the third MOSFET M3. The fifth MOSFET M5 provides a constant current to the voltage output terminal of the DC-DC circuit ( Figure 11 The first node N1 is used for charging, thereby driving the output load to accelerate the response speed of the DC-DC circuit from low voltage to high voltage, that is, to improve the switching speed from low voltage to high voltage.

[0113] When the DC-DC circuit is working normally or the DC-DC circuit's output voltage switching mode is from low voltage to high voltage, that is, when the buck control module 310 is in a reset state (signal V602 is 0, signal V603 is 1), the buck signal generation module 320 receives signals V602 and V603 from the buck control module 310. At this time, signal V602 controls the nineteenth switch S19 to open, and signal V603 controls the twentieth switch S20 to close. The control terminal of the buck drive module 330 ( Figure 11 The signal V703 (illustrated in the diagram) is shorted to ground. This signal V703 is sent to the buck driver module 330 (i.e., the sixth MOSFET M6), causing the sixth MOSFET M6 to turn off (not work), thus not affecting the voltage output of the DC-DC circuit. When the DC-DC circuit's output voltage switching mode is from high voltage to low voltage, i.e., signal V602 is 1 and signal V603 is 0, signal V602 controls the nineteenth switch S19 to close, and signal V603 controls the twentieth switch S20 to open. At this time, the gate of the fourth MOSFET M4 ( Figure 11 (Using signal V701 schematic) and the control terminal of buck drive module 330 ( Figure 11(Signal V703 is used in the diagram) is shorted by the nineteenth switch S19. The sources of the fourth MOSFET M4 and the sixth MOSFET M6 are connected together, and their gates are also connected together. Therefore, the fourth MOSFET M4 and the sixth MOSFET M6 form a mirror current source structure. The current flowing through the eighth current source I8 and the fourth MOSFET M4 in the sixth MOSFET M6 reflects the voltage output terminal of the DC-DC circuit. Figure 11 (Illustrated using the first node N1) discharges with a constant current to drive the output load, thereby accelerating the response speed of the DC-DC circuit from high voltage to low voltage, i.e., improving the switching speed from high voltage to low voltage.

[0114] The fifth embodiment of this example provides yet another voltage fast switching enhancement circuit. The voltage fast switching enhancement circuit provided in this embodiment differs from that in Embodiment 1 in the implementation methods of the boost enhancement sub-circuit 200, the buck enhancement sub-circuit 300, the boost enhancement shutdown module 410, and the buck enhancement shutdown module 420. To avoid redundancy, the following only describes the differences from Embodiment 1. For parts not mentioned in this embodiment, please refer to the relevant descriptions above for an adaptive understanding.

[0115] For example, please see Figure 12 , Figure 12 This is a schematic diagram of the topology of the voltage fast switching enhancement circuit provided in the fifth embodiment of this invention. From... Figure 12 As can be seen, the boost control module 210 includes a fifth sampling module 214 and a third RS flip-flop 215; the input terminal of the fifth sampling module 214 is coupled to the first output terminal of the DVS enhancement trigger module 100, the output terminal of the fifth sampling module 214 is coupled to the set terminal S of the third RS flip-flop 215, the reset terminal R of the third RS flip-flop 215 is coupled to the output terminal of the boost enhancement shutdown module 410, and the output terminal Q of the third RS flip-flop 215, the control terminal of the boost signal generation module 220, and the input terminal of the boost enhancement shutdown module 410 are coupled to the eighth node N8; the boost enhancement shutdown module 410 is configured to reset the boost control module 210 when it is determined that the working time of the boost control module 210 has reached the preset boost time, so as to stop the charging operation of the first node N1.

[0116] For example, please continue to see Figure 12 ,like Figure 12As shown, in some exemplary embodiments, the buck control module 310 includes a sixth sampling module 314 and a fourth RS trigger 315; the input terminal of the sixth sampling module 314 is coupled to the second output terminal of the DVS enhancement trigger module 100, the output terminal of the sixth sampling module 314 is coupled to the set terminal S of the fourth RS trigger 315, the reset terminal R of the fourth RS trigger 315 is coupled to the output terminal of the buck enhancement shutdown module 420, and the output terminal Q of the fourth RS trigger 315, the control terminal of the buck signal generation module 320, and the input terminal of the buck enhancement shutdown module 420 are coupled to the ninth node N9; the buck enhancement shutdown module 420 is configured to reset the buck control module 310 when it is determined that the working time of the buck control module 310 has reached a preset buck duration, so as to stop the discharge operation on the first node N1.

[0117] For example, please continue to see Figure 12 ,like Figure 12 As shown, in some exemplary embodiments, the boost signal generation module 220 includes a fourth inverter 221, the input of which is coupled to the eighth node N8, and the output of which is coupled to the control terminal of the boost drive module 230.

[0118] For example, please continue to see Figure 12 ,like Figure 12 As shown, in some exemplary embodiments, the buck signal generation module 320 includes a buffer 321, the input of which is coupled to the ninth node N9, and the output of which is coupled to the control terminal of the buck drive module 330.

[0119] For example, please continue to see Figure 12 ,like Figure 12 As shown, in some exemplary embodiments, the boost enhancement shutdown module 410 includes a first timer 413, the input of which is coupled to the eighth node N8, and the output of which is coupled to the second input of the boost control module 210. The first timer 413 is configured to reset and start timing when the voltage of the eighth node N8 is high, and to reset the boost control module 210 when the timing duration reaches the preset boost duration, so as to stop the charging operation of the first node N1.

[0120] For example, please continue to see Figure 12 ,like Figure 12As shown, in some exemplary embodiments, the buck enhancement shutdown module 420 includes a second timer 423, the input of which is coupled to the ninth node N9, and the output of which is coupled to the second input of the buck control module 310. The second timer 423 is configured to reset and start timing when the voltage of the ninth node N9 is high, and to reset the buck control module 310 when the timing duration reaches the preset buck duration, so as to stop the discharge operation on the first node N1.

[0121] Therefore, the voltage fast switching enhancement circuit provided in this embodiment has a simpler circuit structure and is easier to implement compared with the first, second, third or fourth embodiments.

[0122] It should be noted that those skilled in the art should understand that the present invention does not limit the specific values ​​of the preset boost duration and the preset deboost duration, and should set them reasonably according to actual needs when implementing the present invention.

[0123] The following combination Figure 12 The working principle of the relevant modules of the voltage fast switching enhancement circuit provided in this embodiment is briefly described below. As mentioned above, the working principle of the relevant modules not mentioned can be found in the description above for an adaptive understanding.

[0124] When the DC-DC circuit is working normally or the output voltage switching mode of the DC-DC circuit is switching from low voltage to high voltage, the boost control module 210 is in a reset state (i.e., signal V202 is 0). The boost signal generation module 220 (i.e., the fourth inverter 221) receives the signal V202 from the boost control module 210. The signal V202 is passed through the fourth inverter 221 to obtain the inverted signal V301 of the signal V202. The signal V301 is at a high level and is sent to the boost drive module 230 (i.e., the fifth MOS transistor M5), causing the fifth MOS transistor M5 to turn off (not work), so that it will not have any impact on the voltage output terminal of the DC-DC circuit. When the output voltage switching mode of the DC-DC circuit is from low voltage to high voltage, that is, signal V202 changes from low level to high level, i.e., from 0 to 1, the boost drive module 230 is the fourth inverter 221. Signal V202 passes through the fourth inverter 221 to obtain signal V301. Signal V301 changes from high level to low level, i.e., from 1 to 0. Signal V303 is sent to the fifth MOSFET M5, thereby strongly turning on the fifth MOSFET M5, realizing the voltage output terminal of the DC-DC circuit. Figure 12The charging operation (illustrated using the first node N1) accelerates the response speed of the DC-DC circuit from low voltage to high voltage, thus improving the switching speed from low voltage to high voltage. Furthermore, signal V202 is simultaneously output to the boost enhancement shutdown module 410 (i.e., the first timer 413). The first timer 413 receives the high-level signal of signal V202 as an enable and starts timing. When the timing duration of the first timer 413 reaches the preset boost duration, a reset pulse signal V402 is generated and sent to the boost control module 210. The reset terminal R of the third RS flip-flop 215 of the boost control module 210 receives the reset pulse signal V402 from the boost enhancement shutdown module 410, thereby putting the boost control module 210 in a reset state. At this time, the state of signal V202 is reset to 0. Signal V202 passes through the fourth inverter 221 to obtain the inverted signal V301 of signal V202. Signal V301 is at a high level and is sent to the boost drive module 230 (i.e., the fifth MOS transistor M5), causing the fifth MOS transistor M5 to turn off (not work), thereby stopping the charging operation of the voltage output terminal of the DC-DC circuit.

[0125] Similarly, when the DC-DC circuit is working normally or the output voltage of the DC-DC circuit is switching from low voltage to high voltage, the buck control module 310 is in a reset state (i.e., signal V602 is 0). The buck signal generation module 320 (i.e., buffer 321) receives signal V602 from the boost control module 210. The signal V701 obtained by the buffer 321 after passing through signal V602 is also at a low level. Signal V701 is sent to the buck drive module 330 (i.e., the sixth MOS transistor M6), causing the sixth MOS transistor M6 to turn off (not work), so that it will not have any effect on the voltage output terminal of the DC-DC circuit. When the output voltage switching mode of the DC-DC circuit is from high voltage to low voltage, that is, when signal V602 changes from low level to high level (from 0 to 1), the signal V701 obtained by the buffer 321 of signal V602 is also high level (1). The voltage signal of signal V701 is given to the sixth MOSFET M6, thereby strongly turning on the sixth MOSFET M6 and discharging the voltage output terminal of the DC-DC circuit, accelerating the response speed of the DC-DC circuit from high voltage to low voltage, that is, improving the switching speed from high voltage to low voltage. Furthermore, signal V602 is simultaneously output to the buck enhancement shutdown module 420 (i.e., the second timer 423). The second timer 423 receives the high-level signal of signal V602 as an enable and starts timing. When the timing duration of the second timer 423 reaches the preset buck duration, a reset pulse signal V802 is generated and sent to the buck control module 310. The reset terminal R of the fourth RS flip-flop 315 of the buck control module 310 receives the reset pulse signal V802 from the buck enhancement shutdown module 420, thereby putting the buck control module 310 into a reset state. At this time, the state of signal V602 is reset to 0. Signal V602 passes through buffer 321 to obtain signal V701, which is also low-level. Signal V701 is sent to the buck drive module 330 (i.e., the sixth MOS transistor M6), causing the sixth MOS transistor M6 to turn off (not work), thereby stopping the discharge operation on the voltage output terminal of the DC-DC circuit.

[0126] It should be noted that the embodiments of the voltage fast switching enhancement circuit described herein are merely preferred examples and not limitations of the present invention. For example, the boost enhancement sub-circuit 200, buck enhancement sub-circuit 300, boost enhancement shutdown module 410, and buck enhancement shutdown module 420 of each embodiment can be interchanged. For instance, the boost enhancement sub-circuit 200 and boost enhancement shutdown module 410 of the first embodiment can be combined with the buck enhancement sub-circuit 300 and buck enhancement shutdown module 420 of the second embodiment to form the voltage fast switching enhancement circuit of the sixth embodiment; further examples will not be provided here. It should also be noted that the first power supply VDD1 and the second power supply VDD2 can be the same power supply or different power supplies; the present invention does not limit this.

[0127] Example 2

[0128] Based on the same inventive concept, this embodiment provides a method for enhancing fast voltage switching in a DC-DC circuit. For example, please refer to... Figure 13 , Figure 13 This is a schematic diagram of the overall flow of the voltage fast switching enhancement method for a DC-DC circuit provided in this embodiment. From... Figure 13 As can be seen, the voltage fast switching enhancement method provided in this embodiment includes the following steps.

[0129] S100: Receive the DVS signal from the DCDC circuit and determine the switching mode of the output voltage of the DCDC circuit based on the DVS signal.

[0130] S200: If the switching mode is from low voltage to high voltage, the voltage output terminal of the DCDC circuit is charged; if the switching mode is from high voltage to low voltage, the voltage output terminal of the DCDC circuit is discharged.

[0131] S300: Determine whether the charging / discharging operation of the voltage output terminal of the DCDC circuit meets the enhanced shutdown preset condition. If so, stop the charging / discharging operation of the voltage output terminal of the DCDC circuit.

[0132] Therefore, the voltage fast switching enhancement method for DC-DC circuits provided by this invention can significantly shorten the DVS switching time of DC-DC circuits, thereby meeting the timing requirements of communication systems and ensuring communication quality.

[0133] Preferably, the voltage fast switching enhancement method for DC-DC circuits provided in this embodiment can be applied to the voltage fast switching enhancement circuit provided by the present invention. The basic principle of the voltage fast switching enhancement method for DC-DC circuits provided in this embodiment is the same as the principle of the voltage fast switching enhancement circuit provided by the present invention. Therefore, the voltage fast switching enhancement method provided by the present invention will not be described in detail here. For more detailed information on the voltage fast switching enhancement method provided by the present invention, please refer to the relevant descriptions of the voltage fast switching enhancement circuit provided by the present invention for an adaptive understanding.

[0134] Example 3

[0135] Based on the same inventive concept, this embodiment provides a DC-DC power supply. For example, please refer to... Figure 14 , Figure 14 This is a block diagram of the DC-DC power supply provided in this embodiment. Figure 14 As shown, the DC-DC power supply provided in this embodiment includes a DC-DC circuit 1 and a voltage fast switching enhancement circuit 2 as described in any embodiment of this document. The input terminal of the voltage fast switching enhancement circuit 2 receives the DVS signal of the DC-DC circuit, and the output terminal of the voltage fast switching enhancement circuit is coupled to the voltage output terminal of the DC-DC circuit.

[0136] Since the DC-DC power supply provided in this embodiment and the voltage fast switching enhancement circuit provided in this invention belong to the same inventive concept, the DC-DC power supply provided in this invention has at least all the advantages of the voltage fast switching enhancement circuit provided in this invention. For details on the beneficial effects of the DC-DC power supply provided in this embodiment, please refer to the above description of the beneficial effects of the voltage fast switching enhancement circuit provided in this invention, which will not be repeated here.

[0137] For example, please see Figure 15 , Figure 15 This is a schematic diagram of the circuit topology of a DC-DC power supply provided in one embodiment of this invention. Figure 15 As shown, in some exemplary embodiments, the output terminal of the error amplifier 11 of the DC-DC circuit 1 ( Figure 15 The output voltage VEA (illustrated) is coupled to the input of the voltage fast switching enhancement circuit 2 to receive the DVS signal. This simplifies circuit wiring and makes implementation easier. In other embodiments, the reference voltage input of the error amplifier 11 of the DC-DC circuit 1 can also be coupled to the input of the voltage fast switching enhancement circuit 2.

[0138] It is understood that the present invention does not limit the source of the DVS signal received by the voltage fast switching enhancement circuit 2. For example, in other embodiments, the DVS signal may also come from the control command of the system in which the DC-DC circuit 1 is located. The control command includes the switching mode of the output voltage of the DC-DC circuit 1. Further, the switching mode may include switching from low voltage to high voltage (DVS Up), switching from high voltage to low voltage (DVS Down), and normal operation mode. The voltage fast switching enhancement circuit 2 only works when the switching mode is switching from low voltage to high voltage (DVS Up) or switching from high voltage to low voltage (DVS Down). Its working principle is roughly as follows: The voltage fast switching enhancement circuit 2 collects the signal changes of the internal node VEA of the DC-DC circuit 1, generates DVS UP / DVS DOWN acceleration signals, and acts on the output voltage Vout of the power supply system, thereby accelerating the change of the output voltage Vout.

[0139] For more detailed information on DC-DC circuit 1, please refer to the relevant technical adaptations of buck circuits known to those skilled in the art; due to space limitations, this will not be elaborated upon further here.

[0140] It should be noted that, although Figure 15 The DC-DC circuit 1 is used as an example of a Buck circuit system, but obviously this is not a limitation of the present invention. The DC-DC circuit 1 can also be other DC-DC circuit topologies, including but not limited to Boost, Buck-Boost, etc.

[0141] For example, please see Figure 16 , Figure 16 This is a schematic diagram illustrating the enhanced simulation effect of the DC-DC power supply during low-voltage to high-voltage switching (DVS Up) provided in this embodiment. Specifically, Figure 16 The waveform of the output voltage of DC-DC circuit 1 when switching from 0.5V to 3.4V is shown, with a load resistance of 3 ohms. The dashed line represents the switching waveform when the voltage fast switching enhancement circuit 2 is not enabled. In this case, the time for the output voltage to reach 97% (3.3V) of the target voltage when switching from 0.5V to 3.4V is approximately 7.01µs. The solid line represents the switching waveform when the voltage fast switching enhancement circuit 2 is enabled. In this case, the time for the output voltage to reach 97% (3.3V) of the target voltage when switching from 0.5V to 3.4V is 4.55µs, which is 35% shorter than when the boost enhancement (DVS UP) function is disabled. This demonstrates that the voltage fast switching enhancement circuit 2 can significantly shorten the switching time of the output voltage from low to high, thereby ensuring the performance of the system communication.

[0142] For example, please see Figure 17 , Figure 17 This is a schematic diagram illustrating the enhanced simulation effect of the DC-DC power supply during high-voltage to low-voltage switching (DVS Down) provided in this embodiment. Specifically, Figure 17 The waveforms of the DC-DC circuit 1 when its output voltage switches from 3.4V to 0.5V are shown, with the load unloaded. The dashed line represents the switching voltage waveform when the voltage fast switching enhancement circuit 2 is not enabled; in this case, the time for the output voltage to switch from 3.4V to 0.5V and reach 0.6V is approximately 12.81µs. The solid line represents the switching waveform when the voltage fast switching enhancement circuit 2 is enabled; in this case, the time for the output voltage to switch from 3.4V to 0.5V and reach 0.6V is approximately 3.78µs, a 70% reduction in switching time compared to when the DVS Down function is disabled. Therefore, it is evident that the voltage fast switching enhancement circuit 2 can significantly improve the switching time from high to low voltage, thereby ensuring the system's communication performance.

[0143] Example 4

[0144] This embodiment provides a chip. In some embodiments, the chip integrates the voltage fast switching enhancement circuit described in any embodiment of Embodiment 1 of this document; in other embodiments, the chip integrates the DC-DC power supply described in Embodiment 3 of this document.

[0145] Example 5

[0146] This embodiment provides an electronic device. In some embodiments, the electronic device includes the voltage fast switching enhancement circuit described in any embodiment of Embodiment 1 of this document; in other embodiments, the electronic device includes the DC-DC power supply described in any embodiment of Embodiment 3 of this document; and in still other embodiments, the electronic device includes the chip described in any embodiment of Embodiment 4 of this document.

[0147] Since the electronic device provided by this invention belongs to the same inventive concept as the voltage fast switching enhancement circuit, DC-DC power supply, or chip provided by this invention, and the DC-DC power supply and chip provided by this invention belong to the same inventive concept as the voltage fast switching enhancement circuit provided by this invention, the electronic device provided by this invention has at least all the advantages of the voltage fast switching enhancement circuit provided by this invention. For details on the beneficial effects of the electronic device provided by this invention, please refer to the above description of the beneficial effects of the voltage fast switching enhancement circuit provided by this invention, which will not be repeated here.

[0148] More specifically, the electronic device provided in this embodiment, in addition to at least a processor and a memory, may further include display components, communication components, sensor components, power supply components, multimedia components, and input / output interfaces, etc., as needed. The display components, memory, communication components, sensor components, power supply components, multimedia components, and input / output interfaces are all connected to the processor. The memory can be static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, etc. The processor can be a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processing (DSP) chip, etc. Other communication components, sensor components, power supply components, multimedia components, etc., can all be implemented using general-purpose components; due to space limitations, they will not be described in detail here. For more detailed information, please refer to the relevant technical adaptation understanding known to those skilled in the art.

[0149] It should be noted that the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0150] Compared with the prior art, the voltage fast switching enhancement circuit, method, DC-DC power supply, chip and device provided by the present invention have the following advantages: The present invention can significantly shorten the DVS switching time of the DC-DC circuit, thereby meeting the timing requirements of the communication system and ensuring the quality of communication.

[0151] The above description is merely a preferred embodiment of the voltage fast switching enhancement circuit, method, DC-DC power supply, chip, and device provided by the present invention, and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A voltage fast switching enhancement circuit for DC-DC circuits, characterized in that, The voltage fast switching enhancement circuit includes a DVS enhancement trigger module, a boost enhancement sub-circuit, a buck enhancement sub-circuit, and a DVS enhancement shutdown sub-circuit. The DVS enhancement trigger module receives a DVS signal. The first and second output terminals of the DVS enhancement trigger module are respectively coupled to the control terminals of the boost enhancement sub-circuit and the buck enhancement sub-circuit. The output terminals of the boost enhancement sub-circuit, the buck enhancement sub-circuit, and the input terminal of the DVS enhancement shutdown sub-circuit are coupled to the voltage output terminal of the DC-DC circuit at a first node. The DVS enhancement trigger module is configured to obtain the switching mode of the output voltage of the DCDC circuit according to the DVS signal, and trigger the boost enhancement sub-circuit to work to charge the first node when the switching mode is switching from low voltage to high voltage; and trigger the buck enhancement sub-circuit to work to discharge the first node when the switching mode is switching from high voltage to low voltage. The DVS enhanced shutdown sub-circuit is configured to determine whether the charging / discharging of the first node meets the enhanced shutdown preset conditions. If so, the boost enhancement sub-circuit / the buck enhancement sub-circuit is reset to stop the charging / discharging operation of the first node. The boost enhancement sub-circuit includes a boost control module, a boost signal generation module, and a boost drive module connected in sequence; the buck enhancement sub-circuit includes a buck control module, a buck signal generation module, and a buck drive module connected in sequence; and the DVS enhancement shutdown sub-circuit includes a boost enhancement shutdown module and a buck enhancement shutdown module. The first and second input terminals of the boost control module are respectively coupled to the first output terminal of the DVS enhancement trigger module and the output terminal of the boost enhancement shutdown module; the first and second input terminals of the buck control module are respectively coupled to the second output terminal of the DVS enhancement trigger module and the second output terminal of the DVS enhancement shutdown sub-circuit; the output terminals of the boost drive module and the buck drive module are coupled to the first node. The input terminal of the boost enhancement shutdown module is coupled to the boost signal generation module at the second node or to the first node, and the input terminal of the buck enhancement shutdown module is coupled to the buck signal generation module at the third node or to the first node. The boost drive module includes a fifth MOS transistor, the gate of which is coupled to the output of the boost signal generation module, the source / drain of which is coupled to a first power supply, and the drain / source of which is coupled to the first node; and / or, the buck drive module includes a sixth MOS transistor, the gate of which is coupled to the output of the buck signal generation module, the source / drain of which is coupled to the first node, and the drain / source of which is coupled to a reference ground.

2. The voltage fast switching enhancement circuit according to claim 1, characterized in that, The first input terminal of the DVS enhancement trigger module receives the DVS signal, and the second and third input terminals of the DVS enhancement trigger module respectively receive a preset reference high voltage and a preset reference low voltage, wherein the preset reference high voltage is greater than the preset reference low voltage; The DVS enhancement trigger module is configured to determine that the switching mode is switching from low voltage to high voltage and trigger the boost enhancement sub-circuit to work when the DVS signal is greater than the preset reference high voltage. When the DVS signal is less than the preset reference low voltage, the switching mode is determined to be a switch from high voltage to low voltage and the buck enhancement sub-circuit is triggered to work.

3. The voltage fast switching enhancement circuit according to claim 2, characterized in that, The DVS enhancement trigger module includes a first comparator, a second comparator, an AND gate, and a first NOR gate. The negative input of the first comparator receives the preset reference high voltage. The positive inputs of the first and second comparators are coupled to the output of the error amplifier or the reference voltage input of the DCDC circuit. The negative input of the second comparator receives the preset reference low voltage. The output of the first comparator, the first input of the AND gate, and the first input of the first NOR gate are coupled. The output of the second comparator, the second input of the AND gate, and the second input of the first NOR gate are coupled. The output of the AND gate is coupled to the first input of the boost enhancement sub-circuit. The output of the first NOR gate is coupled to the first input of the buck enhancement sub-circuit.

4. The voltage fast switching enhancement circuit according to claim 1, characterized in that, The boost control module includes a first sampling module, a first RS flip-flop, and a first inverter; the input terminal of the first sampling module is coupled to the first output terminal of the DVS enhancement trigger module, the output terminal of the first sampling module is coupled to the set terminal of the first RS flip-flop, the reset terminal of the first RS flip-flop is coupled to the output terminal of the boost enhancement shutdown module, the output terminal of the first RS flip-flop and the input terminal of the first inverter are coupled to the first control terminal of the boost signal generation module at a fourth node, and the output terminal of the first inverter is coupled to the second control terminal of the boost signal generation module at a fifth node; The boost enhancement shutdown module is configured to reset the boost control module to stop charging the first node when it is determined that the voltage of the first node is greater than or equal to the boost enhancement preset value; the boost enhancement preset value is less than the target high voltage value for voltage switching of the DC-DC circuit. And / or, The buck control module includes a second sampling module, a second RS flip-flop, and a second inverter. The input of the second sampling module is coupled to the second output of the DVS enhancement trigger module, the output of the second sampling module is coupled to the set input of the second RS flip-flop, the reset input of the second RS flip-flop is coupled to the output of the buck enhancement shutdown module, the output of the second RS flip-flop and the input of the second inverter are coupled to the first control terminal of the buck signal generation module at a sixth node, and the output of the second inverter is coupled to the second control terminal of the buck signal generation module at a seventh node. The buck enhancement shutdown module is configured to reset the buck control module to stop the discharge operation on the first node when it is determined that the voltage of the first node is less than or equal to the buck enhancement preset value. The buck enhancement preset value is greater than the target low voltage value of the voltage switching of the DCDC circuit.

5. The voltage fast switching enhancement circuit according to claim 4, characterized in that, The first sampling module and / or the second sampling module are sampling units. The sampling unit includes a delay, a third inverter, and a second NOR gate. The input terminal of the delay and the input terminal of the third inverter share a common connection point to form the input terminal of the sampling unit. The output terminal of the delay and the output terminal of the third inverter are respectively coupled to the first input terminal and the second input terminal of the second NOR gate. The output terminal of the second NOR gate forms the output terminal of the sampling unit.

6. The voltage fast switching enhancement circuit according to claim 4, characterized in that, The boost signal generation module includes a first switch to a fourth switch, a first MOSFET, a first capacitor, a first current source, and a second current source. The control terminals of the first switch and the fourth switch are coupled to the fifth node, the control terminals of the second switch and the third switch are coupled to the fourth node, the first terminal of the first switch, the first terminal of the second switch, the gate of the first MOSFET, and the first terminal of the first capacitor are coupled, the second terminal of the first switch, the second terminal of the first capacitor, and the source / drain of the first MOSFET are coupled to a reference ground, the second terminal of the second switch is coupled to the output terminal of the first current source, the output terminal of the second current source, the drain / source of the first MOSFET, and the first terminal of the third switch are coupled to the second node, the input terminals of the first current source, the input terminals of the second current source, and the first terminal of the fourth switch are coupled to a first power supply, and the second terminals of the third switch and the second terminals of the fourth switch are coupled to the control terminal of the boost drive module. And / or, The buck signal generation module includes a fifth to an eighth switch, a second MOSFET, a second capacitor, a third current source, and a fourth current source. The control terminals of the fifth and eighth switches are coupled to the seventh node, and the control terminals of the sixth and seventh switches are coupled to the sixth node. The first terminal of the fifth switch, the first terminal of the sixth switch, the gate of the second MOSFET, and the first terminal of the second capacitor are coupled. The second terminal of the fifth switch, the second terminal of the second capacitor, and the source / drain of the second MOSFET are coupled to a second power supply. The second terminal of the sixth switch is coupled to the input terminal of the third current source. The input terminal of the fourth current source, the drain / source of the second MOSFET, and the first terminal of the seventh switch are coupled to the third node. The output terminals of the third and fourth current sources and the first terminal of the eighth switch are coupled to a reference ground. The second terminals of the seventh and eighth switches are coupled to the control terminal of the buck drive module.

7. The voltage fast switching enhancement circuit according to claim 4, characterized in that, The boost signal generation module includes a ninth to a twelfth switch, a third capacitor, and a fifth current source; the control terminals of the ninth and twelfth switches are coupled to the fifth node, the control terminals of the tenth and eleventh switches are coupled to the fourth node, the first terminals of the ninth, tenth, and eleventh switches and the first terminal of the third capacitor are coupled to the second node, the second terminal of the ninth switch and the second terminal of the third capacitor are coupled to a reference ground, the second terminal of the tenth switch is coupled to the output terminal of the fifth current source, the input terminal of the fifth current source and the first terminal of the twelfth switch are coupled to a first power supply, and the second terminals of the eleventh and twelfth switches are coupled to the control terminal of the boost drive module. And / or, The step-down signal generation module includes switches 13 to 16, a fourth capacitor, and a sixth current source. The control terminals of the 13th and 16th switches are coupled to the seventh node, the control terminals of the 14th and 15th switches are coupled to the sixth node, the first terminals of the 13th, 14th, and 15th switches and the first terminal of the fourth capacitor are coupled to the third node, the second terminal of the 13th switch and the second terminal of the fourth capacitor are coupled to a second power supply, the second terminal of the 14th switch is coupled to the input terminal of the sixth current source, the output terminal of the sixth current source and the first terminal of the 16th switch are coupled to a reference ground, and the second terminals of the 15th and 16th switches are coupled to the control terminal of the step-down drive module.

8. The voltage fast switching enhancement circuit according to claim 4, characterized in that, The boost signal generation module includes a seventeenth switch, an eighteenth switch, a seventh current source, and a third MOSFET. The control terminal of the seventeenth switch is coupled to the fourth node. The first terminal of the seventeenth switch, the input terminal of the seventh current source, and the gate and drain of the third MOSFET are coupled together. The second terminal of the seventeenth switch and the first terminal of the eighteenth switch are coupled to the control terminal of the boost drive module. The control terminal of the eighteenth switch is coupled to the fifth node. The second terminal of the eighteenth switch and the source of the third MOSFET are coupled to a first power supply. The output terminal of the seventh current source is coupled to a reference ground. And / or, The buck signal generation module includes a nineteenth switch, a twentieth switch, an eighth current source, and a fourth MOSFET. The control terminal of the nineteenth switch is coupled to the sixth node. The first terminal of the nineteenth switch, the output terminal of the eighth current source, and the gate and drain of the fourth MOSFET are coupled. The second terminal of the nineteenth switch and the first terminal of the twentieth switch are coupled to the control terminal of the buck drive module. The control terminal of the twentieth switch is coupled to the seventh node. The second terminal of the twentieth switch and the source of the fourth MOSFET are coupled to a reference ground. The input terminal of the eighth current source is coupled to a second power supply.

9. The voltage fast switching enhancement circuit according to claim 4, characterized in that, The boost enhancement shutdown module includes a third sampling module and a third comparator. The output of the third sampling module is coupled to the second input of the boost control module, the input of the third sampling module is coupled to the output of the third comparator, the positive input of the third comparator is coupled to the first node or the second node, and the negative input of the third comparator receives a first reference voltage. And / or, The buck enhancement shutdown module includes a fourth sampling module and a fourth comparator. The output of the fourth sampling module is coupled to the second input of the buck control module, the input of the fourth sampling module is coupled to the output of the fourth comparator, the positive input of the fourth comparator receives a second reference voltage, and the negative input of the fourth comparator is coupled to the first node or the third node.

10. The voltage fast switching enhancement circuit according to claim 1, characterized in that, The boost control module includes a fifth sampling module and a third RS flip-flop; the input of the fifth sampling module is coupled to the first output of the DVS enhancement trigger module, the output of the fifth sampling module is coupled to the set terminal of the third RS flip-flop, the reset terminal of the third RS flip-flop is coupled to the output of the boost enhancement shutdown module, and the output of the third RS flip-flop, the control terminal of the boost signal generation module, and the input of the boost enhancement shutdown module are coupled to the eighth node; the boost enhancement shutdown module is configured to reset the boost control module when it is determined that the working time of the boost control module has reached a preset boost time, so as to stop the charging operation of the first node; And / or, The buck control module includes a sixth sampling module and a fourth RS flip-flop; the input of the sixth sampling module is coupled to the second output of the DVS enhancement trigger module, the output of the sixth sampling module is coupled to the set terminal of the fourth RS flip-flop, the reset terminal of the fourth RS flip-flop is coupled to the output of the buck enhancement shutdown module, and the output of the fourth RS flip-flop, the control terminal of the buck signal generation module, and the input of the buck enhancement shutdown module are coupled to the ninth node; the buck enhancement shutdown module is configured to reset the buck control module when it is determined that the working time of the buck control module has reached the preset buck duration, so as to stop the discharge operation of the first node.

11. The voltage fast switching enhancement circuit according to claim 10, characterized in that, The boost signal generation module includes a fourth inverter, the input of which is coupled to the eighth node, and the output of which is coupled to the control terminal of the boost drive module. And / or, The buck signal generation module includes a buffer, the input of which is coupled to the ninth node, and the output of which is coupled to the control terminal of the buck drive module.

12. The voltage fast switching enhancement circuit according to claim 10, characterized in that, The boost enhancement shutdown module includes a first timer, the input of which is coupled to the eighth node, and the output of which is coupled to the second input of the boost control module. The first timer is configured to reset and start timing when the voltage of the eighth node is high, and to reset the boost control module to stop charging the first node when the timing duration reaches the preset boost duration. And / or, The buck enhancement shutdown module includes a second timer. The input of the second timer is coupled to the ninth node, and the output of the second timer is coupled to the second input of the buck control module. The second timer is configured to reset and start timing when the voltage of the ninth node is high, and to reset the buck control module when the timing duration reaches the preset buck duration, so as to stop the discharge operation on the first node.

13. A method for enhancing fast voltage switching in a DC-DC circuit, characterized in that, The method is applied to the voltage fast switching enhancement circuit as described in any one of claims 1 to 12, the method comprising: Receive the DVS signal from the DC-DC circuit, and determine the switching mode of the output voltage of the DC-DC circuit based on the DVS signal; If the switching mode is from low voltage to high voltage, the voltage output terminal of the DC-DC circuit is charged; if the switching mode is from high voltage to low voltage, the voltage output terminal of the DC-DC circuit is discharged. Determine whether the charging / discharging operation on the voltage output terminal of the DC-DC circuit meets the enhanced shutdown preset condition. If so, stop the charging / discharging operation on the voltage output terminal of the DC-DC circuit.

14. A DC-DC power supply, characterized in that, The device includes a DC-DC circuit and a voltage fast switching enhancement circuit as described in any one of claims 1 to 12, wherein the input terminal of the voltage fast switching enhancement circuit receives the DVS signal of the DC-DC circuit, and the output terminal of the voltage fast switching enhancement circuit is coupled to the voltage output terminal of the DC-DC circuit.

15. The DC-DC power supply according to claim 14, characterized in that, The output or reference voltage input of the error amplifier in the DC-DC circuit is coupled to the input of the DVS enhancement trigger module to receive the DVS signal.

16. A chip, characterized in that, It integrates a voltage fast switching enhancement circuit as described in any one of claims 1 to 12 or a DC-DC power supply as described in any one of claims 14 to 15.

17. An electronic device, characterized in that, This includes the voltage fast switching enhancement circuit as described in any one of claims 1 to 12, or the DC-DC power supply as described in any one of claims 14 to 15, or the chip as described in claim 16.

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