Power-on reset circuit and chip

Abstract

The application belongs to the technical field of electronic circuits and provides a power-on reset circuit and a chip. The power-on reset circuit comprises a first logic module, a second logic module, a third logic module and a switch module. The second logic module is connected with the third logic module and the switch module respectively. The switch module is connected with the first logic module and the third logic module respectively. The first logic module and the second logic module both receive a power supply voltage. When the power supply voltage is less than a first threshold voltage, which indicates that the power supply voltage is less than the threshold voltage of an NMOS transistor, the first logic module outputs a first logic signal to control the switch module to be turned on. After the switch module is turned on, the first node and the second node are pulled down to a low level, so that the third logic module locks a power-on reset signal to a low level, thereby ensuring that the chip is in a reset state. The problem that the output of the traditional power-on reset circuit is in an uncertain state when the power supply voltage is lower than the threshold voltage of the NMOS transistor, thereby causing the abnormal reset state of the chip, is solved.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a power-on reset circuit and chip. Background Technology

[0002] The power-on reset circuit controls the chip to enter its initial operating state by detecting changes in the power supply voltage. Before the power supply voltage rises to the normal operating voltage, the power-on reset circuit generates a low-level power-on reset signal to put the chip in a reset state, preventing the chip from being affected by abnormal operation. After the power supply voltage rises to the normal operating voltage, the power-on reset circuit outputs a high-level signal to ensure that the chip is in a normal operating state.

[0003] However, when the power supply voltage is lower than the threshold voltage of the NMOS transistor, the output of the traditional power-on reset circuit is indeterminate, which leads to abnormal chip reset state. Summary of the Invention

[0004] This application provides a power-on reset circuit and chip, which can solve the problem that the output of a traditional power-on reset circuit is uncertain when the power supply voltage is lower than the threshold voltage of the NMOS transistor, resulting in an abnormal chip reset state.

[0005] In a first aspect, embodiments of this application provide a power-on reset circuit, including a first logic module, a second logic module, a third logic module, and a switch module. The second logic module is connected to the third logic module and the switch module respectively. The common terminal of the second logic module, the third logic module, and the switch module is called a first node. The switch module is connected to the first logic module and the third logic module respectively. The common terminal of the switch module and the third logic module is called a second node, which is used to output a power-on reset signal. Both the first logic module and the second logic module are used to receive power supply voltage.

[0006] When the power supply voltage is less than the first threshold voltage, the first logic module is used to output a first logic signal; the switch module is used to turn on according to the first logic signal and pull down the first node and the second node to a low level, thereby causing the third logic module to lock the power-on reset signal to a low level;

[0007] When the power supply voltage is greater than the first threshold voltage, the first logic module outputs a second logic signal; the switch module disconnects according to the second logic signal. When the power supply voltage is greater than the first threshold voltage and less than the second threshold voltage, the second logic module outputs a third logic signal; the third logic module outputs a low-level power-on reset signal according to the third logic signal. When the power supply voltage is greater than the second threshold voltage, the second logic module outputs a fourth logic signal; the third logic module outputs a high-level power-on reset signal according to the fourth logic signal.

[0008] In one possible implementation of the first aspect, the first logic module includes a first logic unit, a second logic unit, and a third logic unit, the second logic unit is connected to the first logic unit and the third logic unit respectively, the third logic unit is connected to the switch module, and both the first logic unit and the second logic unit are used to receive power supply voltage.

[0009] When the power supply voltage is less than the first threshold voltage, the first logic unit is used to output a fifth logic signal; the second logic unit is used to output a sixth logic signal according to the fifth logic signal and the power supply voltage; and the third logic unit is used to output a first logic signal according to the sixth logic signal.

[0010] When the power supply voltage is greater than the first threshold voltage, the first logic unit is used to output a seventh logic signal; the second logic unit is used to output an eighth logic signal according to the seventh logic signal and the power supply voltage; and the third logic unit is used to output a second logic signal according to the eighth logic signal.

[0011] In one possible implementation of the first aspect, the first logic unit includes a first capacitor and a first transistor, a first terminal of the first capacitor is used to receive a power supply voltage, a second terminal of the first capacitor is connected to the gate of the first transistor, the drain of the first transistor and the second logic unit, respectively, and the source of the first transistor is grounded.

[0012] In one possible implementation of the first aspect, the second logic unit includes a second transistor and a third transistor, the source of the second transistor is used to receive a power supply voltage, the gate of the second transistor is connected to the gate of the third transistor and the first logic unit respectively, the drain of the second transistor is connected to the drain of the third transistor and the third logic unit respectively, and the source of the third transistor is grounded; wherein, the third transistor is a low threshold voltage transistor.

[0013] In one possible implementation of the first aspect, the third logic unit includes a first inverter, the input of which is connected to the second logic unit, and the output of which is connected to the switching module.

[0014] In one possible implementation of the first aspect, the switching module includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is connected to the gate of the fifth transistor and the first logic module, the drain of the fourth transistor is connected to the second logic module and the third logic module, the drain of the fifth transistor is connected to the third logic module, and the sources of the fourth transistor and the fifth transistor are both grounded.

[0015] In one possible implementation of the first aspect, the third logic module includes a second inverter and a third inverter, the input of the second inverter is connected to the second logic module and the switch module respectively, the output of the second inverter is connected to the input of the third inverter, and the output of the third inverter is connected to the switch module.

[0016] In one possible implementation of the first aspect, the second logic module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first resistor, and a second resistor. The first terminal of the first resistor, the source of the ninth transistor, and the source of the tenth transistor are all used to receive a power supply voltage. The second terminal of the first resistor is connected to the drain, gate, seventh transistor, and eighth transistor, respectively. The drain of the seventh transistor is connected to the drain, gate, and tenth transistor, respectively. The drain of the tenth transistor is connected to the drain of the eighth transistor, the input terminal of the second inverter, and the switching module, respectively. The source of the eighth transistor is connected to the first terminal of the second resistor. The sources of the sixth transistor, the seventh transistor, and the second terminal of the second resistor are all grounded.

[0017] In one possible implementation of the first aspect, the second logic module further includes an eleventh transistor and a third resistor. The gate of the eleventh transistor is connected to the output terminal of the second inverter and the input terminal of the third inverter, respectively. The drain of the eleventh transistor is connected to the first terminal of the third resistor and the second terminal of the second resistor, respectively. The source of the eleventh transistor and the second terminal of the third resistor are both grounded.

[0018] Secondly, embodiments of this application provide a chip including the power-on reset circuit described in any one of the first aspects.

[0019] Thirdly, embodiments of this application provide an electronic device including the chip described in any one of the second aspects.

[0020] The beneficial effects of the embodiments in this application compared with the prior art are:

[0021] This application provides a power-on reset circuit, including a first logic module, a second logic module, a third logic module, and a switch module. The second logic module is connected to the third logic module and the switch module. The common terminal of the second logic module, the third logic module, and the switch module is called a first node. The switch module is connected to the first logic module and the third logic module. The common terminal of the switch module and the third logic module is called a second node, which is used to output a power-on reset signal. Both the first logic module and the second logic module are used to receive power supply voltage.

[0022] When the power supply voltage is less than the first threshold voltage, indicating that the power supply voltage is less than the threshold voltage of the NMOS transistor, the output of the second logic module is in an uncertain state. The first logic module outputs a first logic signal to control the switch module to turn on. After the switch module turns on, it pulls the first node and the second node down to a low level, thereby causing the third logic module to lock the power-on reset signal to a low level to ensure that the chip is in a reset state. This solves the problem that the traditional power-on reset circuit has an uncertain output when the power supply voltage is lower than the threshold voltage of the NMOS transistor, which leads to an abnormal chip reset state.

[0023] When the power supply voltage is greater than the first threshold voltage, the second logic module can output normally. At this time, the first logic module outputs the second logic signal to control the switch module to open. After the switch module is opened, the level state of the first node is determined by the output of the second logic module, and the level state of the second node is determined by the output of the third logic module. Specifically, when the power supply voltage is greater than the first threshold voltage and less than the second threshold voltage, it indicates that the power supply voltage is greater than the threshold voltage of the NMOS transistor and the power supply voltage has not yet risen to the normal operating voltage. At this time, the second logic module is used to output the third logic signal. The third logic module outputs a low-level power-on reset signal according to the third logic signal to ensure that the chip is in the reset state.

[0024] When the power supply voltage is greater than the second threshold voltage, it indicates that the power supply voltage has risen to the normal operating voltage. At this time, the second logic module outputs the fourth logic signal, and the third logic module outputs a high-level power-on reset signal according to the fourth logic signal to ensure that the chip is in normal operating condition.

[0025] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a power-on reset circuit provided in an embodiment of this application;

[0028] Figure 2 This is a schematic diagram of a power-on reset circuit provided in another embodiment of this application;

[0029] Figure 3 This is a circuit connection diagram of a power-on reset circuit provided in an embodiment of this application;

[0030] Figure 4 This is a circuit connection diagram of a power-on reset circuit provided in another embodiment of this application.

[0031] In the diagram: 10, Power-on reset circuit; 101, First logic module; 1011, First logic unit; 1012, Second logic unit; 1013, Third logic unit; 102, Second logic module; 103, Third logic module; 104, Switch module. Detailed Implementation

[0032] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0033] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0034] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0035] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0036] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0037] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0038] To address the problem that traditional power-on reset circuits produce an uncertain output state when the power supply voltage is lower than the threshold voltage of the NMOS transistor, leading to abnormal chip reset status, this application provides a power-on reset circuit, including a first logic module, a second logic module, a third logic module, and a switch module. The second logic module is connected to both the third logic module and the switch module. The common terminal of the second logic module, the third logic module, and the switch module is called the first node. The switch module is connected to both the first logic module and the third logic module. The common terminal of the switch module and the third logic module is called the second node, which is used to output a power-on reset signal. Both the first logic module and the second logic module are used to receive the power supply voltage.

[0039] When the power supply voltage is less than the first threshold voltage, indicating that the power supply voltage is less than the threshold voltage of the NMOS transistor, the output of the second logic module is in an uncertain state. The first logic module outputs a first logic signal to control the switch module to turn on. After the switch module turns on, it pulls the first node and the second node down to a low level, thereby causing the third logic module to lock the power-on reset signal to a low level to ensure that the chip is in a reset state. This solves the problem that the traditional power-on reset circuit has an uncertain output when the power supply voltage is lower than the threshold voltage of the NMOS transistor, which leads to an abnormal chip reset state.

[0040] When the power supply voltage is greater than the first threshold voltage, the second logic module can output normally. At this time, the first logic module outputs the second logic signal to control the switch module to open. After the switch module is opened, the level state of the first node is determined by the output of the second logic module, and the level state of the second node is determined by the output of the third logic module. Specifically, when the power supply voltage is greater than the first threshold voltage and less than the second threshold voltage, it indicates that the power supply voltage is greater than the threshold voltage of the NMOS transistor and the power supply voltage has not yet risen to the normal operating voltage. At this time, the second logic module is used to output the third logic signal. The third logic module outputs a low-level power-on reset signal according to the third logic signal to ensure that the chip is in the reset state.

[0041] When the power supply voltage is greater than the second threshold voltage, it indicates that the power supply voltage has risen to the normal operating voltage. At this time, the second logic module outputs the fourth logic signal, and the third logic module outputs a high-level power-on reset signal according to the fourth logic signal to ensure that the chip is in normal operating condition.

[0042] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0043] Figure 1 A schematic diagram of the power-on reset circuit provided in an embodiment of this application is shown. Figure 1 As shown, the power-on reset circuit 10 includes a first logic module 101, a second logic module 102, a third logic module 103, and a switch module 104. The second logic module 102 is connected to the third logic module 103 and the switch module 104. The common terminal of the second logic module 102, the third logic module 103, and the switch module 104 is called the first node A1. The switch module 104 is connected to the first logic module 101 and the third logic module 103. The common terminal of the switch module 104 and the third logic module 103 is called the second node A2, which is used to output the power-on reset signal POR. Both the first logic module 101 and the second logic module 102 are used to receive the power supply voltage VCC.

[0044] Specifically, when the power supply voltage VCC is less than the first threshold voltage, indicating that VCC is less than the threshold voltage of the NMOS transistor, the output of the second logic module 102 is in an uncertain state. The first logic module 101 is used to output a first logic signal, which is a high-level signal in this embodiment. The switching module 104 is used to turn on according to the first logic signal and pull down the first node A1 and the second node A2 to a low level, thereby causing the third logic module 103 to lock the power-on reset signal POR to a low level, ensuring that the chip is in a reset state. This solves the problem that the output of the traditional power-on reset circuit is in an uncertain state when the power supply voltage VCC is lower than the threshold voltage of the NMOS transistor, resulting in an abnormal chip reset state.

[0045] When the power supply voltage VCC is greater than the first threshold voltage, the second logic module 102 can output normally. At this time, the first logic module 101 outputs the second logic signal, which is a low-level signal in this embodiment. The switch module 104 is used to disconnect according to the second logic signal. After the switch module 104 is disconnected, the level state of the first node A1 is determined by the output of the second logic module 102, and the level state of the second node A2 is determined by the output of the third logic module 103. Specifically, when the power supply voltage VCC is greater than the first threshold voltage and less than the second threshold voltage, it indicates that the power supply voltage VCC is greater than the threshold voltage of the NMOS transistor and the power supply voltage VCC has not yet risen to the normal operating voltage. At this time, the second logic module 102 outputs the third logic signal, that is, the signal at the first node A1 is the third logic signal, which is a low-level signal in this embodiment. The third logic module 103 outputs a low-level power-on reset signal POR according to the third logic signal to ensure that the chip is in a reset state.

[0046] When the power supply voltage VCC is greater than the second threshold voltage, it indicates that the power supply voltage VCC has risen to the normal operating voltage. At this time, the second logic module 102 outputs a fourth logic signal, which in this embodiment is a high-level signal. The third logic module 103 outputs a high-level power-on reset signal POR based on the fourth logic signal to ensure that the chip is in a normal operating state.

[0047] In one embodiment of this application, such as Figure 2 As shown, the first logic module 101 includes a first logic unit 1011, a second logic unit 1012 and a third logic unit 1013. The second logic unit 1012 is connected to the first logic unit 1011 and the third logic unit 1013 respectively. The third logic unit 1013 is connected to the switch module 104. The first logic unit 1011 and the second logic unit 1012 are both used to receive the power supply voltage VCC.

[0048] Specifically, when the power supply voltage VCC is less than the first threshold voltage, indicating that the power supply voltage VCC is less than the threshold voltage of the NMOS transistor, the output of the second logic module 102 is in an uncertain state; the first logic unit 1011 is used to output a fifth logic signal, which in this embodiment is the power supply voltage VCC. The second logic unit 1012 is used to output a sixth logic signal based on the fifth logic signal and the power supply voltage VCC, which in this embodiment is a low-level signal. The third logic unit 1013 is used to output a first logic signal based on the sixth logic signal.

[0049] When the power supply voltage VCC is greater than the first threshold voltage, indicating that VCC is greater than the threshold voltage of the NMOS transistor, the second logic module 102 can output normally. At this time, the first logic unit 1011 outputs the seventh logic signal, which is a low-level signal in this embodiment. The second logic unit 1012 outputs the eighth logic signal based on the seventh logic signal and the power supply voltage VCC, which is a high-level signal in this embodiment. The third logic unit 1013 outputs the second logic signal based on the eighth logic signal.

[0050] In one embodiment of this application, such as Figure 3 As shown, the first logic unit 1011 includes a first capacitor C1 and a first transistor M1. The first terminal of the first capacitor C1 is used to receive the power supply voltage VCC. The second terminal of the first capacitor C1 is connected to the gate of the first transistor M1, the drain of the first transistor M1, and the second logic unit 1012. The common terminal of the first capacitor C1, the first transistor M1, and the second logic unit 1012 is called the third node A3. The source of the first transistor M1 is grounded. The first transistor M1 is an NMOS transistor.

[0051] Specifically, when the power supply voltage VCC is less than the first threshold voltage, it indicates that the power supply voltage VCC is less than the threshold voltage of the NMOS transistor, and the output of the second logic module 102 is in an uncertain state. At this time, since the power supply voltage VCC is less than the threshold voltage of the NMOS transistor, the first transistor M1 is turned off, and the voltage at the third node A3 is the power supply voltage VCC, which is also the fifth logic signal.

[0052] When the power supply voltage VCC is greater than the first threshold voltage, it indicates that the power supply voltage VCC is greater than the threshold voltage of the NMOS transistor, and the second logic module 102 can output normally. At this time, since the power supply voltage VCC is greater than the threshold voltage of the NMOS transistor, the first transistor M1 is turned on. After the first transistor M1 is turned on, the third node A3 is pulled down to a low level, that is, the seventh logic signal output to the second logic unit 1012 is a low level signal.

[0053] In one embodiment of this application, such as Figure 3As shown, the second logic unit 1012 includes a second transistor M2 and a third transistor M3. The source of the second transistor M2 is used to receive the power supply voltage VCC. The gate of the second transistor M2 is connected to the gate of the third transistor M3 and the first logic unit 1011. The drain of the second transistor M2 is connected to the drain of the third transistor M3 and the third logic unit 1013. The common terminal of the second transistor M2, the third transistor M3 and the third logic unit 1013 is called the fourth node A4. The source of the third transistor M3 is grounded. The second transistor M2 is a PMOS transistor, and the third transistor M3 is an NMOS transistor and a low threshold voltage transistor (i.e., an LVT transistor).

[0054] Specifically, when the power supply voltage VCC is less than the first threshold voltage, indicating that the power supply voltage VCC is less than the threshold voltage of the NMOS transistor, the output of the second logic module 102 is in an uncertain state. At this time, since the power supply voltage VCC is less than the threshold voltage of the NMOS transistor, the first transistor M1 is turned off, and the voltage at the third node A3 is the power supply voltage VCC, which is also the fifth logic signal. The third transistor M3 is an LVT transistor, which turns on according to the power supply voltage VCC. After the third transistor M3 turns on, it pulls the fourth node A4 down to a low level, that is, the sixth logic signal output to the third logic unit 1013 is a low-level signal.

[0055] When the power supply voltage VCC is greater than the first threshold voltage, indicating that VCC is greater than the threshold voltage of the NMOS transistor, the second logic module 102 can output normally. At this time, because VCC is greater than the threshold voltage of the NMOS transistor, the first transistor M1 is turned on. After M1 is turned on, it pulls the third node A3 down to a low level, meaning the seventh logic signal is a low-level signal. Since the seventh logic signal is low, the third transistor M3 is turned off, and the second transistor M2 is turned on. After M2 is turned on, it pulls the fourth node A4 up to a high level, meaning the eighth logic signal output to the third logic unit 1013 is a high-level signal.

[0056] In one embodiment of this application, such as Figure 3 As shown, the third logic unit 1013 includes a first inverter INV1. The input terminal of the first inverter INV1 is connected to the second logic unit 1012, and the output terminal of the first inverter INV1 is connected to the switch module 104. The first inverter INV1 is a Schmitt trigger inverter.

[0057] Specifically, when the power supply voltage VCC is less than the first threshold voltage, indicating that VCC is less than the threshold voltage of the NMOS transistor, the output of the second logic module 102 is in an uncertain state. Since VCC is less than the threshold voltage of the NMOS transistor, the first transistor M1 is turned off, and the voltage at the third node A3 is the power supply voltage VCC, which is the fifth logic signal. The third transistor M3 is an LVT, and it turns on according to the power supply voltage VCC. After turning on, the third transistor M3 pulls the fourth node A4 down to a low level, meaning the sixth logic signal is a low-level signal. The first inverter INV1 inverts the sixth logic signal, outputting the first logic signal, which is a high-level signal.

[0058] When the power supply voltage VCC is greater than the first threshold voltage, indicating that VCC is greater than the threshold voltage of the NMOS transistor, the second logic module 102 can output normally. At this time, because VCC is greater than the threshold voltage of the NMOS transistor, the first transistor M1 is turned on. After M1 is turned on, it pulls the third node A3 down to a low level, meaning the seventh logic signal output to the second logic unit 1012 is a low-level signal. Since the seventh logic signal is low, the third transistor M3 is turned off, and the second transistor M2 is turned on. After M2 is turned on, it pulls the fourth node A4 up to a high level, meaning the eighth logic signal is a high-level signal. The first inverter INV1 inverts the eighth logic signal, outputting the second logic signal, which is a low-level signal.

[0059] In one embodiment of this application, such as Figure 3 As shown, the switching module 104 includes a fourth transistor M4 and a fifth transistor M5. The gate of the fourth transistor M4 is connected to the gate of the fifth transistor M5 and the first logic module 101. The common terminal of the fourth transistor M4, the fifth transistor M5, and the first logic module 101 is called the fifth node A5. The drain of the fourth transistor M4 is connected to the second logic module 102 and the third logic module 103, i.e., connected to the first node A1. The drain of the fifth transistor M5 is connected to the third logic module 103, i.e., connected to the second node A2. The sources of the fourth transistor M4 and the fifth transistor M5 are both grounded. Both the fourth transistor M4 and the fifth transistor M5 are NMOS transistors.

[0060] Specifically, when the power supply voltage VCC is less than the first threshold voltage, indicating that VCC is less than the threshold voltage of the NMOS transistor, the output of the second logic module 102 is in an uncertain state. Since VCC is less than the threshold voltage of the NMOS transistor, the first transistor M1 is turned off, and the voltage at the third node A3 is the power supply voltage VCC, which is the fifth logic signal. The third transistor M3 is an LVT, and it turns on according to the power supply voltage VCC. After turning on, the third transistor M3 pulls the fourth node A4 down to a low level, meaning the sixth logic signal is a low-level signal. The first inverter INV1 inverts the sixth logic signal, outputting the first logic signal, which is the signal at the fifth node A5. Since the first logic signal is a high-level signal, both the fourth transistor M4 and the fifth transistor M5 will turn on, thereby pulling the first node A1 and the second node A2 down to a low level. This causes the third logic module 103 to lock the power-on reset signal POR to a low level, ensuring the chip is in a reset state.

[0061] When the power supply voltage VCC is greater than the first threshold voltage, indicating that VCC is greater than the threshold voltage of the NMOS transistor, the second logic module 102 can output normally. At this time, because VCC is greater than the threshold voltage of the NMOS transistor, the first transistor M1 is turned on. After M1 is turned on, it pulls the third node A3 down to a low level, meaning the seventh logic signal output to the second logic unit 1012 is a low-level signal. Since the seventh logic signal is low, the third transistor M3 is turned off, and the second transistor M2 is turned on. After M2 is turned on, it pulls the fourth node A4 up to a high level, meaning the eighth logic signal is a high-level signal. The first inverter INV1 inverts the eighth logic signal, outputting the second logic signal, which is the signal at the fifth node A5. Since the second logic signal is low, both the fourth transistor M4 and the fifth transistor M5 are turned off. Therefore, the level state of the first node A1 is determined by the output of the second logic module 102, and the level state of the second node A2 is determined by the output of the third logic module 103.

[0062] In one embodiment of this application, such as Figure 3As shown, the third logic module 103 includes a second inverter INV2 and a third inverter INV3. The input terminals of the second inverter INV2 are connected to the second logic module 102 and the switch module 104, respectively. The common terminal of the second inverter INV2, the second logic module 102, and the switch module 104 is called the first node A1. The output terminal of the second inverter INV2 is connected to the input terminal of the third inverter INV3, and the output terminal of the third inverter INV3 is connected to the switch module 104. The common terminal of the third inverter INV3 and the switch module 104 is called the second node A2. Both the second inverter INV2 and the third inverter INV3 are Schmitt trigger inverters.

[0063] Specifically, when the power supply voltage VCC is less than the first threshold voltage, indicating that VCC is less than the threshold voltage of the NMOS transistor, the output of the second logic module 102 is in an uncertain state. Since VCC is less than the threshold voltage of the NMOS transistor, the first transistor M1 is turned off, and the voltage at the third node A3 is the power supply voltage VCC, which is the fifth logic signal. The third transistor M3 is an LVT, and it turns on according to the power supply voltage VCC. After turning on, the third transistor M3 pulls the fourth node A4 down to a low level, meaning the sixth logic signal is a low-level signal. The first inverter INV1 inverts the sixth logic signal, outputting the first logic signal, which is the signal at the fifth node A5. Since the first logic signal is a high-level signal, both the fourth transistor M4 and the fifth transistor M5 will turn on, thereby pulling the first node A1 and the second node A2 down to a low level. This causes the second inverter INV2 and the third inverter INV3 to lock the power-on reset signal POR to a low level, ensuring the chip is in a reset state.

[0064] When the power supply voltage VCC is greater than the first threshold voltage, indicating that VCC is greater than the threshold voltage of the NMOS transistor, the second logic module 102 can output normally. At this time, because VCC is greater than the threshold voltage of the NMOS transistor, the first transistor M1 is turned on. After M1 is turned on, it pulls the third node A3 down to a low level, meaning the seventh logic signal output to the second logic unit 1012 is a low-level signal. Since the seventh logic signal is low, the third transistor M3 is turned off, and the second transistor M2 is turned on. After M2 is turned on, it pulls the fourth node A4 up to a high level, meaning the eighth logic signal is a high-level signal. The first inverter INV1 inverts the eighth logic signal, outputting the second logic signal, which is the signal at the fifth node A5. Since the second logic signal is low, both the fourth transistor M4 and the fifth transistor M5 are turned off. Therefore, the level state of the first node A1 is determined by the output of the second logic module 102, and the level state of the second node A2 is determined by the output of the third logic module 103. Specifically, when the power supply voltage VCC is greater than the first threshold voltage and less than the second threshold voltage, indicating that the power supply voltage VCC is greater than the threshold voltage of the NMOS transistor but has not yet risen to the normal operating voltage, the second logic module 102 outputs a third logic signal, that is, the signal at the first node A1 is the third logic signal. In this embodiment, the third logic signal is a low-level signal. The second inverter INV2 inverts the third logic signal and outputs a high-level signal; the third inverter INV inverts the high-level signal and outputs a low-level power-on reset signal POR, ensuring that the chip is in a reset state.

[0065] When the power supply voltage VCC is greater than the second threshold voltage, it indicates that the power supply voltage VCC has risen to the normal operating voltage. At this time, the second logic module 102 outputs the fourth logic signal, which is a high-level signal in this embodiment. The second inverter INV2 inverts the fourth logic signal and outputs a low-level signal; the third inverter INV inverts the low-level signal and outputs a high-level power-on reset signal POR to ensure that the chip is in normal operating condition.

[0066] In one embodiment of this application, such as Figure 3As shown, the second logic module 102 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a first resistor R1, and a second resistor R2. The first terminal of the first resistor R1, the source of the ninth transistor M9, and the source of the tenth transistor M10 are all used to receive the power supply voltage VCC. The second terminal of the first resistor R1 is connected to the drain and gate of the sixth transistor M6, the gate of the seventh transistor M7, and the gate of the eighth transistor M8, respectively. The drain of the seventh transistor M7 is connected to the drain and gate of the ninth transistor M9, the gate of the ninth transistor M9, and the gate of the tenth transistor M10, respectively. The drain of the tenth transistor M10 is connected to the drain of the eighth transistor M8, the input terminal of the second inverter INV2, and the switch module 104, respectively. The source of the eighth transistor M8 is connected to the first terminal of the second resistor R2. The sources of the sixth transistor M6, the seventh transistor M7, and the second terminal of the second resistor R2 are all grounded. The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are NMOS transistors. The ninth transistor M9 and the tenth transistor M10 are PMOS transistors.

[0067] Specifically, when the power supply voltage VCC is less than the first threshold voltage, indicating that VCC is less than the threshold voltage of the NMOS transistor, the output of the second logic module 102 is in an uncertain state. Since VCC is less than the threshold voltage of the NMOS transistor, the first transistor M1 is turned off, and the voltage at the third node A3 is the power supply voltage VCC, which is the fifth logic signal. The third transistor M3 is an LVT, and it turns on according to the power supply voltage VCC. After turning on, the third transistor M3 pulls the fourth node A4 down to a low level, meaning the sixth logic signal is a low-level signal. The first inverter INV1 inverts the sixth logic signal, outputting the first logic signal, which is the signal at the fifth node A5. Since the first logic signal is a high-level signal, both the fourth transistor M4 and the fifth transistor M5 will turn on, thereby pulling the first node A1 and the second node A2 down to a low level. This causes the second inverter INV2 and the third inverter INV3 to lock the power-on reset signal POR to a low level, ensuring the chip is in a reset state.

[0068] When the power supply voltage VCC is greater than the first threshold voltage, indicating that VCC is greater than the threshold voltage of the NMOS transistor, the second logic module 102 can output normally. At this time, because VCC is greater than the threshold voltage of the NMOS transistor, the first transistor M1 is turned on. After M1 is turned on, it pulls the third node A3 down to a low level, meaning the seventh logic signal output to the second logic unit 1012 is a low-level signal. Since the seventh logic signal is low, the third transistor M3 is turned off, and the second transistor M2 is turned on. After M2 is turned on, it pulls the fourth node A4 up to a high level, meaning the eighth logic signal is a high-level signal. The first inverter INV1 inverts the eighth logic signal, outputting the second logic signal, which is the signal at the fifth node A5. Since the second logic signal is low, both the fourth transistor M4 and the fifth transistor M5 are turned off. Therefore, the level state of the first node A1 is determined by the output of the second logic module 102, and the level state of the second node A2 is determined by the output of the third logic module 103. Specifically: When the power supply voltage VCC is greater than the first threshold voltage and less than the second threshold voltage, indicating that the power supply voltage VCC is greater than the threshold voltage of the NMOS transistor but has not yet risen to the normal operating voltage, the current flowing through the first resistor R1 is mirrored to the branch containing the seventh transistor M7 through the current mirror formed by the sixth transistor M6 and the seventh transistor M7, and then mirrored to the branch containing the eighth transistor M8 through the current mirror formed by the ninth transistor M9 and the tenth transistor M10. Since the power supply voltage VCC has not yet risen to the normal operating voltage, the current flowing through the first resistor R1 is relatively small, which in turn makes the pull-up current of the tenth transistor M10 relatively small. Therefore, the level of the first node A1 is pulled down to a low level by the eighth transistor M8, that is, the third logic signal is a low level signal. The second inverter INV2 inverts the third logic signal and outputs a high level signal; the third inverter INV inverts the high level signal and outputs a low level power-on reset signal POR, ensuring that the chip is in a reset state.

[0069] When the power supply voltage VCC exceeds the second threshold voltage, it indicates that the power supply voltage VCC has risen to the normal operating voltage. Because the power supply voltage VCC has risen to the normal operating voltage, the current flowing through the first resistor R1 is relatively large, which in turn causes a relatively large pull-up current in the tenth transistor M10. Therefore, the level of the first node A1 is pulled up to a high level by the tenth transistor M10, meaning the fourth logic signal is a high-level signal. The second inverter INV2 inverts the fourth logic signal, outputting a low-level signal; the third inverter INV inverts the low-level signal, outputting a high-level power-on reset signal POR, ensuring the chip is in normal operating condition.

[0070] In one embodiment of this application, such as Figure 4As shown, the second logic module 102 also includes an eleventh transistor M11 and a third resistor R3. The gate of the eleventh transistor M11 is connected to the output terminal of the second inverter INV2 and the input terminal of the third inverter INV3, respectively. The common terminal of the eleventh transistor M11, the second inverter INV2, and the third inverter INV3 is called the sixth node A6. The drain of the eleventh transistor M11 is connected to the first terminal of the third resistor R3 and the second terminal of the second resistor R2, respectively. The source of the eleventh transistor M11 and the second terminal of the third resistor R3 are both grounded. The eleventh transistor M11 is an NMOS transistor.

[0071] Specifically, to improve the circuit's anti-interference performance, the switching point of the second logic module 102 is changed by altering the resistance at the source of the eighth transistor M8, thereby achieving a hysteresis effect. Specifically: when the power-on reset signal POR is low, the level of the sixth node A6 is high, the eleventh transistor M11 is turned on, shorting the third resistor R3, and the resistance at the source of the eighth transistor M8 becomes the second resistor R2. When the power-on reset signal POR becomes high, the level of the sixth node A6 is low, the eleventh transistor M11 is turned off, the third resistor R3 is connected, and the resistance at the source of the eighth transistor M8 becomes the resistance of the second resistor R2 and the third resistor R3 connected in series. The hysteresis effect occurs during the power-on process of the power supply voltage VCC. When the power-on reset signal POR changes from low to high, the resistance at the source of the eighth transistor M8 switches from the second resistor R2 to the resistance formed by the series connection of the second resistor R2 and the third resistor R3. This creates a difference between the switching point when the power supply voltage VCC rises and the switching point when it falls; this difference is the hysteresis window. If external interference voltage fluctuates within this window, the output of the second logic module 102 will not erroneously flip, thus improving anti-interference performance.

[0072] In summary, the power-on reset circuit 10 provided in this application, when the power supply voltage VCC is less than the first threshold voltage, outputs a first logic signal from the first logic module 101 to control the switch module 104 to turn on. After the switch module 104 turns on, it pulls down the first node A1 and the second node A2 to a low level, thereby causing the third logic module 103 to lock the power-on reset signal POR to a low level, ensuring that the chip is in a reset state. This circuit solves the problem that the output of the traditional power-on reset circuit is uncertain when the power supply voltage is lower than the threshold voltage of the NMOS transistor, leading to an abnormal chip reset state.

[0073] This application also provides a chip including the power-on reset circuit described above. Since the chip provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0074] This application also provides an electronic device including the chip described above. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0075] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0076] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A power-on reset circuit, characterized in that, It includes a first logic module, a second logic module, a third logic module, and a switch module. The second logic module is connected to the third logic module and the switch module respectively. The common terminal of the second logic module, the third logic module, and the switch module is called the first node. The switch module is connected to the first logic module and the third logic module respectively. The common terminal of the switch module and the third logic module is called the second node, which is used to output a power-on reset signal. The first logic module and the second logic module are both used to receive power supply voltage. When the power supply voltage is less than the first threshold voltage, the first logic module is used to output a first logic signal; the switch module is used to turn on according to the first logic signal and pull down the first node and the second node to a low level, thereby causing the third logic module to lock the power-on reset signal to a low level; When the power supply voltage is greater than the first threshold voltage, the first logic module outputs a second logic signal; the switch module disconnects according to the second logic signal. When the power supply voltage is greater than the first threshold voltage and less than the second threshold voltage, the second logic module outputs a third logic signal; the third logic module outputs a low-level power-on reset signal according to the third logic signal. When the power supply voltage is greater than the second threshold voltage, the second logic module outputs a fourth logic signal; the third logic module outputs a high-level power-on reset signal according to the fourth logic signal.

2. The power-on reset circuit according to claim 1, characterized in that, The first logic module includes a first logic unit, a second logic unit, and a third logic unit. The second logic unit is connected to the first logic unit and the third logic unit, respectively. The third logic unit is connected to the switch module. Both the first logic unit and the second logic unit are used to receive power supply voltage. When the power supply voltage is less than the first threshold voltage, the first logic unit is used to output a fifth logic signal; the second logic unit is used to output a sixth logic signal according to the fifth logic signal and the power supply voltage; and the third logic unit is used to output a first logic signal according to the sixth logic signal. When the power supply voltage is greater than the first threshold voltage, the first logic unit is used to output a seventh logic signal; the second logic unit is used to output an eighth logic signal according to the seventh logic signal and the power supply voltage; and the third logic unit is used to output a second logic signal according to the eighth logic signal.

3. The power-on reset circuit according to claim 2, characterized in that, The first logic unit includes a first capacitor and a first transistor. The first terminal of the first capacitor is used to receive the power supply voltage. The second terminal of the first capacitor is connected to the gate of the first transistor, the drain of the first transistor, and the second logic unit. The source of the first transistor is grounded.

4. The power-on reset circuit according to claim 2, characterized in that, The second logic unit includes a second transistor and a third transistor. The source of the second transistor is used to receive the power supply voltage. The gate of the second transistor is connected to the gate of the third transistor and the first logic unit, respectively. The drain of the second transistor is connected to the drain of the third transistor and the third logic unit, respectively. The source of the third transistor is grounded. The third transistor is a low threshold voltage transistor.

5. The power-on reset circuit according to claim 2, characterized in that, The third logic unit includes a first inverter, the input of which is connected to the second logic unit, and the output of which is connected to the switch module.

6. The power-on reset circuit according to claim 1 or 2, characterized in that, The switching module includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is connected to the gate of the fifth transistor and the first logic module, respectively. The drain of the fourth transistor is connected to the second logic module and the third logic module, respectively. The drain of the fifth transistor is connected to the third logic module. The sources of the fourth transistor and the fifth transistor are both grounded.

7. The power-on reset circuit according to claim 1 or 2, characterized in that, The third logic module includes a second inverter and a third inverter. The input terminal of the second inverter is connected to the second logic module and the switch module, respectively. The output terminal of the second inverter is connected to the input terminal of the third inverter, and the output terminal of the third inverter is connected to the switch module.

8. The power-on reset circuit according to claim 7, characterized in that, The second logic module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first resistor, and a second resistor. The first terminal of the first resistor, the source of the ninth transistor, and the source of the tenth transistor are all used to receive power supply voltage. The second terminal of the first resistor is connected to the drain, gate, seventh transistor, and eighth transistor, respectively. The drain of the seventh transistor is connected to the drain, gate, and tenth transistor, respectively. The drain of the tenth transistor is connected to the drain of the eighth transistor, the input terminal of the second inverter, and the switching module, respectively. The source of the eighth transistor is connected to the first terminal of the second resistor. The sources of the sixth transistor, the seventh transistor, and the second terminal of the second resistor are all grounded.

9. The power-on reset circuit according to claim 8, characterized in that, The second logic module further includes an eleventh transistor and a third resistor. The gate of the eleventh transistor is connected to the output terminal of the second inverter and the input terminal of the third inverter, respectively. The drain of the eleventh transistor is connected to the first terminal of the third resistor and the second terminal of the second resistor, respectively. The source of the eleventh transistor and the second terminal of the third resistor are both grounded.

10. A chip, characterized in that, Includes the power-on reset circuit as described in any one of claims 1-9.

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