Power-on reset circuit based on resistance voltage division detection

Abstract

The application discloses a power-on reset circuit based on resistance voltage division detection, comprising: a first detection unit, which detects an input first bias signal to obtain a first detection voltage; a second detection unit, which detects an input second bias signal to obtain a second detection voltage; a logic comparison unit, which comprises a NAND gate, a first input end of the NAND gate being connected with the first detection unit, a second input end of the NAND gate being connected with the second detection unit, and the NAND gate outputting a corresponding reset signal according to the first detection voltage and the second detection voltage; so that the power-on speed is fast and the overall circuit area is reduced.

Description

Technical Field

[0001] This invention relates to the field of reset circuit technology, and in particular to a power-on reset circuit based on resistor voltage divider detection. Background Technology

[0002] In related technologies, existing power-on reset circuits require waiting for Pbias and Nbias to start during power-on. After startup, the circuit uses a comparator COMP to compare the voltages and uses the output as the power-on reset signal. This approach requires strict timing control between the circuit startup time (the stabilization timing of PBIAS and NBIA voltages) and the detection and sampling time of voltages IP and IN (the stabilization speed of R1 and R2). Otherwise, the comparator output will be incorrect, and the power-on reset will fail. In addition, the comparator's own offset makes the timing control of the overall circuit difficult, resulting in a more complex circuit implementation. Summary of the Invention

[0003] The present invention aims to at least partially solve one of the technical problems in the aforementioned technologies. To this end, one objective of the present invention is to propose a power-on reset circuit based on resistor voltage divider detection. Voltage detection is performed using a resistor voltage divider, and the detection result is passed through a NAND gate instead of a comparator, thereby resulting in faster power-on speed and a smaller overall circuit area.

[0004] To achieve the above objectives, this invention proposes a power-on reset circuit based on resistor voltage divider detection, comprising: a first detection unit, which detects an input first bias signal to obtain a first detection voltage; a second detection unit, which detects an input second bias signal to obtain a second detection voltage; and a logic comparison unit, which includes a NAND gate, wherein the first input terminal of the NAND gate is connected to the first detection unit, the second input terminal of the NAND gate is connected to the second detection unit, and the NAND gate outputs a corresponding reset signal based on the first detection voltage and the second detection voltage; thereby achieving fast power-on speed and reduced overall circuit area.

[0005] In addition, the power-on reset circuit based on resistor voltage divider detection proposed in the embodiments of the present invention may also have the following additional technical features:

[0006] Optionally, the first detection unit includes: a first resistor voltage divider unit, which performs voltage division sampling on the input power supply to obtain a first initial detection voltage; a first start control unit, which is connected to the first resistor voltage divider unit to be turned on according to the first initial detection voltage; and a first charge / discharge unit, which is connected to the first start control unit, and which obtains the corresponding first detection voltage according to the first bias signal after the first start control unit is turned on.

[0007] Furthermore, the first resistor voltage divider unit includes: a first resistor, one end of which is grounded; and a second resistor, one end of which is connected to the other end of the first resistor, and the other end of which is connected to a power supply.

[0008] Furthermore, the first start-up control unit includes: a first capacitor, one end of which is connected between the first resistor and the second resistor, and the other end of which is grounded; and a first MOSFET, the gate of which is connected between the first resistor and the second resistor, and the source of which is connected to ground.

[0009] Further, the first charging and discharging unit includes: a second MOSFET, the gate of which is connected to a startup and bias circuit generator unit to receive a first bias signal, the source of which is connected to a power supply, and the drain of which is connected to the drain of the first MOSFET; and a second capacitor, one end of which is connected to the power supply, and the other end of which is connected between the drain of the second MOSFET and the drain of the first MOSFET.

[0010] Optionally, the second detection unit includes: a second resistor voltage divider unit, which performs voltage division sampling on the input power supply to obtain a second initial detection voltage; a second start control unit, which is connected to the second resistor voltage divider unit to conduct according to the second initial detection voltage; and a second charge / discharge unit, which is connected to the second start control unit, and obtains the corresponding second detection voltage according to the second bias signal after the second start control unit is turned on.

[0011] Furthermore, the second resistor voltage divider unit includes: a third resistor, one end of which is grounded; and a fourth resistor, one end of which is connected to the other end of the third resistor, and the other end of which is connected to a power supply.

[0012] Furthermore, the second startup control unit includes: a third capacitor, one end of which is connected between the third resistor and the fourth resistor, and the other end of which is connected to a power supply; and a third MOSFET, the gate of which is connected between the third resistor and the fourth resistor, and the source of which is connected to a power supply.

[0013] Further, the second charging and discharging unit includes: a fourth MOS transistor, the gate of which is connected to the startup and bias circuit generator unit to receive a second bias signal, the source of which is connected to ground, and the drain of which is connected to the drain of the third MOS transistor; and a fourth capacitor, one end of which is connected to ground, and the other end of which is connected between the drain of the fourth MOS transistor and the drain of the third MOS transistor.

[0014] Optionally, the logic comparison unit further includes a first inverter, a second inverter, and a third inverter. The input terminal of the first inverter is connected to the output terminal of the first detection unit, the output terminal of the first inverter is connected to the first input terminal of the NAND gate, the input terminal of the second inverter is connected to the output terminal of the second detection unit, the output terminal of the second inverter is connected to the input terminal of the third inverter, and the output terminal of the third inverter is connected to the second input terminal of the NAND gate. Attached Figure Description

[0015] Figure 1 The circuit schematic of an existing power-on reset circuit;

[0016] Figure 2 This is a circuit diagram of a power-on reset circuit based on resistor voltage divider detection according to an embodiment of the present invention. Detailed Implementation

[0017] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0018] In related technologies, such as Figure 1As shown, in the prior art, the POR startup circuit requires a comparator for voltage detection. The timing error between the signals generated by the startup circuit and the Biasgen circuit, as well as the offset of the comparator itself, are difficult to eliminate, resulting in a relatively complex circuit implementation. To address this, this application proposes a power-on reset circuit based on resistor voltage divider detection. By using resistor voltage divider detection, the power-on speed of the circuit is improved. The logic NAND gate replaces the comparator circuit, eliminating the timing error in the circuit and the influence of the comparator offset, making the power-on reset safer. The overall circuit structure is simple and easy to implement, thereby reducing the area.

[0019] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0020] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0021] The power-on reset circuit based on resistor voltage divider detection according to an embodiment of the present invention will now be described with reference to the accompanying drawings.

[0022] refer to Figure 2 As shown, the power-on reset circuit based on resistor voltage divider detection proposed in this embodiment of the invention includes a first detection unit 100, a second detection unit 200, and a logic comparison unit 300.

[0023] The first detection unit 100 detects the input first bias signal Pbias to obtain the first detection voltage IPP.

[0024] As one embodiment, the first detection unit 100 includes a first resistor voltage divider unit, a first start control unit, and a first charge / discharge unit. The first resistor voltage divider unit performs voltage division sampling on the input power supply to obtain a first initial detection voltage. The first start control unit is connected to the first resistor voltage divider unit to conduct according to the first initial detection voltage. The first charge / discharge unit is connected to the first start control unit, and after the first start control unit is turned on, the first charge / discharge unit obtains the corresponding first detection voltage according to the first bias signal.

[0025] Specifically, the first resistor voltage divider unit includes a first resistor R1 and a second resistor R2; one end of the first resistor R1 is grounded; one end of the second resistor R2 is connected to the other end of the first resistor R1, and the other end of the second resistor R2 is connected to the power supply.

[0026] Specifically, the first start-up control unit includes a first capacitor C1 and a first MOSFET NM1; one end of the first capacitor C1 is connected between a first resistor R1 and a second resistor R2, and the other end of the first capacitor C1 is grounded; the gate of the first MOSFET NM1 is connected between the first resistor R1 and the second resistor R2, and the source of the first MOSFET NM1 is connected to ground.

[0027] In other words, during the power supply VDD power-on process, voltage sampling is performed through resistors, and the first capacitor C1 is charged so that the first MOSFET NM1 is turned on by the first initial detection voltage IP.

[0028] Specifically, the first charging and discharging unit includes a second MOSFET PM1 and a second capacitor C2; the gate of the second MOSFET PM1 is connected to the startup and bias circuit generator unit to receive the first bias signal Pbias, the source of the second MOSFET PM1 is connected to the power supply, and the drain of the second MOSFET PM1 is connected to the drain of the first MOSFET NM1; one end of the second capacitor C2 is connected to the power supply, and the other end of the second capacitor C2 is connected between the drain of the second MOSFET PM1 and the drain of the first MOSFET NM1.

[0029] The second detection unit 200 detects the input second bias signal Nbias to obtain the second detection voltage INN.

[0030] As one embodiment, the second detection unit 200 includes a second resistor voltage divider unit, a second start control unit, and a second charge / discharge unit. The second resistor voltage divider unit performs voltage division sampling on the input power supply to obtain a second initial detection voltage. The second start control unit is connected to the second resistor voltage divider unit to conduct according to the second initial detection voltage. The second charge / discharge unit is connected to the second start control unit, and after the second start control unit is turned on, the second charge / discharge unit obtains the corresponding second detection voltage according to the second bias signal.

[0031] Specifically, the second resistor voltage divider unit includes a third resistor R3 and a fourth resistor R4; one end of the third resistor R3 is grounded; one end of the fourth resistor R4 is connected to the other end of the third resistor R3, and the other end of the fourth resistor R4 is connected to the power supply.

[0032] Specifically, the second start-up control unit includes a third capacitor C3 and a third MOSFET PM2; one end of the third capacitor C3 is connected between the third resistor R3 and the fourth resistor R4, and the other end of the third capacitor C3 is connected to the power supply; the gate of the third MOSFET PM2 is connected between the third resistor R3 and the fourth resistor R4, and the source of the third MOSFET PM2 is connected to the power supply.

[0033] In other words, during the power supply VDD power-on process, voltage sampling is performed through resistors, and the third capacitor C3 is charged so that the third MOSFET PM2 is turned on by the second initial detection voltage IN.

[0034] Specifically, the second charging and discharging unit includes a fourth MOSFET NM2 and a fourth capacitor C4; the gate of the fourth MOSFET NM2 is connected to the startup and bias circuit generator unit to receive the second bias signal Nbias, the source of the fourth MOSFET NM2 is connected to ground, and the drain of the fourth MOSFET NM2 is connected to the drain of the third MOSFET PM2; one end of the fourth capacitor C4 is connected to ground, and the other end of the fourth capacitor C4 is connected between the drain of the fourth MOSFET NM2 and the drain of the third MOSFET PM2.

[0035] In other words, after the first MOSFET NM1 and the third MOSFET PM2 are turned on, the bias circuit generator Biasgen and the start-up circuit are activated. After the first bias signal Pbias and the second bias signal Nbias arrive, IPP and INN are charged through the second capacitor C2 and the fourth capacitor C4.

[0036] Specifically, when the first MOSFET NM1 is turned on, the second capacitor C2 discharges, and when the first MOSFET NM1 is not turned on, the second capacitor C2 charges; when the third MOSFET PM2 is turned on, the fourth capacitor C4 charges, and when the third MOSFET PM2 is not turned on, the fourth capacitor C4 discharges.

[0037] The logic comparison unit 300 includes a NAND gate N1. The first input terminal of the NAND gate N1 is connected to the first detection unit 100, and the second input terminal of the NAND gate N1 is connected to the second detection unit 200. The NAND gate N1 outputs a corresponding reset signal according to the first detection voltage IPP and the second detection voltage INN.

[0038] In other words, the first detection voltage IPP and the second detection voltage INN are compared by the NAND gate N1 of the logic comparison unit 300, and the POR is successfully powered on.

[0039] As an embodiment, the logic comparison unit 300 further includes a first inverter 10, a second inverter 20, and a third inverter 30. The input terminal of the first inverter 10 is connected to the output terminal of the first detection unit 100, and the output terminal of the first inverter 10 is connected to the first input terminal of the NAND gate N1. The input terminal of the second inverter 20 is connected to the output terminal of the second detection unit 200, and the output terminal of the second inverter 20 is connected to the input terminal of the third inverter 30. The output terminal of the third inverter 30 is connected to the second input terminal of the NAND gate N1.

[0040] It should be noted that the inverter ensures that the signal input to the NAND gate N1 is time-matched, eliminates glitches or unstable states, and converts the analog voltage signal generated by capacitor charging and discharging into a steep digital logic level, thus meeting the logic threshold requirements of the NAND gate N1 for the input signal.

[0041] In summary, the power-on reset circuit based on resistor voltage divider detection proposed in this embodiment of the invention detects the first input bias signal through a first detection unit to obtain a first detection voltage; the second detection unit detects the second input bias signal to obtain a second detection voltage; the logic comparison unit includes a NAND gate, the first input terminal of which is connected to the first detection unit, and the second input terminal of which is connected to the second detection unit. The NAND gate outputs a corresponding reset signal based on the first and second detection voltages. Thus, voltage detection is performed through resistor voltage divider, and the detection result is replaced by a comparator through a NAND logic gate, thereby resulting in faster power-on speed and a smaller overall circuit area.

[0042] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0044] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0045] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0046] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0047] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A power-on reset circuit based on resistive voltage divider detection, characterized in that, include: The first detection unit detects the input first bias signal to obtain the first detection voltage; The second detection unit detects the input second bias signal to obtain the second detection voltage; The logic comparison unit includes a NAND gate, the first input terminal of which is connected to the first detection unit, the second input terminal of which is connected to the second detection unit, and the NAND gate outputs a corresponding reset signal based on the first detection voltage and the second detection voltage. The first detection unit includes: The first resistor voltage divider unit performs voltage division sampling on the input power supply to obtain the first initial detection voltage; A first start-up control unit is connected to the first resistor voltage divider unit to be turned on according to the first initial detection voltage; The first charging and discharging unit is connected to the first start control unit. After the first start control unit is turned on, the first charging and discharging unit obtains the corresponding first detection voltage according to the first bias signal. The first resistor voltage divider unit includes: The first resistor has one end grounded. A second resistor, one end of which is connected to the other end of the first resistor, and the other end of which is connected to a power source; The first start-up control unit includes: A first capacitor, one end of which is connected between the first resistor and the second resistor, and the other end of which is grounded; The first MOSFET has its gate connected between the first resistor and the second resistor, and its source connected to ground. The first charging and discharging unit includes: The second MOSFET has its gate connected to the startup and bias circuit generator unit to receive the first bias signal, its source connected to the power supply, and its drain connected to the drain of the first MOSFET. The second capacitor has one end connected to the power supply and the other end connected between the drain of the second MOSFET and the drain of the first MOSFET.

2. The power-on reset circuit based on resistor voltage divider detection according to claim 1, characterized in that, The second detection unit includes: The second resistor voltage divider unit performs voltage division sampling on the input power supply to obtain the second initial detection voltage; The second start control unit is connected to the second resistor voltage divider unit to be turned on according to the second initial detection voltage; The second charging and discharging unit is connected to the second start control unit. After the second start control unit is turned on, the second charging and discharging unit obtains the corresponding second detection voltage according to the second bias signal.

3. The power-on reset circuit based on resistor voltage divider detection according to claim 2, characterized in that, The second resistor voltage divider unit includes: The third resistor, one end of which is grounded; A fourth resistor, one end of which is connected to the other end of the third resistor, and the other end of which is connected to a power source.

4. The power-on reset circuit based on resistor voltage divider detection according to claim 3, characterized in that, The second start control unit includes: The third capacitor has one end connected between the third resistor and the fourth resistor, and the other end connected to the power supply. The third MOS transistor has its gate connected between the third resistor and the fourth resistor, and its source connected to the power supply.

5. The power-on reset circuit based on resistor voltage divider detection according to claim 4, characterized in that, The second charge / discharge unit includes: The fourth MOS transistor has its gate connected to the startup and bias circuit generator unit to receive the second bias signal, its source connected to ground, and its drain connected to the drain of the third MOS transistor. A fourth capacitor, one end of which is connected to ground, and the other end of which is connected between the drain of the fourth MOS transistor and the drain of the third MOS transistor.

6. The power-on reset circuit based on resistor voltage divider detection according to claim 1, characterized in that, The logic comparison unit further includes a first inverter, a second inverter, and a third inverter. The input terminal of the first inverter is connected to the output terminal of the first detection unit, and the output terminal of the first inverter is connected to the first input terminal of the NAND gate. The input terminal of the second inverter is connected to the output terminal of the second detection unit, and the output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the second input terminal of the NAND gate.

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