Multifunctional in-memory computing circuit and chip based on 9T1C-SRAM cell

Abstract

This invention relates to an in-memory computing circuit in the field of integrated circuits, and particularly to a multifunctional in-memory computing circuit and chip based on a 9T1C-SRAM cell. The multifunctional in-memory computing circuit includes five NMOS transistors N1-N5, four PMOS transistors P1-P4, and a capacitor C0. P1, P2, N1, and N2 form a latch structure; N3 controls row-direction read / write operations via word line WL and bit line BL; P3, P4, N4, and N5 are used to implement Boolean logic write-back, row-direction read / write, and multiply-accumulate functions. This invention's multifunctional in-memory computing circuit simultaneously supports Boolean logic write-back, signed multiply-accumulate (MAC) operations, and bidirectional row and column read / write, achieving deep integration of logical operations, arithmetic operations, and data movement within the same memory cell.

Description

Technical Field

[0001] This invention relates to an in-memory computing circuit in the field of integrated circuit technology, and in particular to a multifunctional in-memory computing circuit and chip based on a 9T1C-SRAM cell, which integrates Boolean logic write-back, bidirectional read-write and multiply-accumulate calculation functions. Background Technology

[0002] In recent years, the rapid development of artificial intelligence and big data algorithms has led to a sharp increase in the demand for high-speed processing of massive amounts of data. However, traditional data processing platforms based on the von Neumann architecture, due to the physical separation of computing and storage modules, require frequent large-scale data migrations. With the widespread application of computationally intensive tasks such as deep learning, the growth rate of computing power in computing units far exceeds the growth rate of on-chip storage bandwidth, resulting in a severe bandwidth bottleneck between the two.

[0003] To address this issue, scientists in the fields of computer science and big data are increasingly focusing their efforts on research projects aimed at breaking through the von Neumann architecture. Currently, computing in memory (CIM) is attracting widespread attention as one of the effective strategies for overcoming the von Neumann architecture.

[0004] Some mainstream in-memory computing research focuses on Boolean logic write-back (such as AND logic judgment). This type of technology performs logical operations such as AND, OR, IMP, and XOR directly within the memory cell and writes the result back to the target cell in place, avoiding the frequent data movement in traditional architectures and offering significant advantages in energy efficiency and throughput. However, current mainstream circuits for implementing Boolean logic operations typically require 10 or more transistors, leading to increased power consumption during circuit operations and reduced circuit area utilization efficiency. Summary of the Invention

[0005] (1) Technical problems to be solved To address the technical problems of high power consumption and low area efficiency in in-memory computing circuits during Boolean logic write-back operations, this invention provides a multifunctional in-memory computing circuit and chip based on 9T1C.

[0006] (2) Technical solution The first aspect of this invention provides a multifunctional in-memory computing circuit based on a 9T1C-SRAM cell, comprising five NMOS transistors N1~N5, four PMOS transistors P1~P4, and a capacitor C0; the gates of P2, N2, and N4 are connected to the drains of P1, N1, N3, and N5 to form a storage node Q; the gates of P1, N1, and P3 are connected to the drains of P2 and N2 to form a storage node QB; the source of P1 is connected to a voltage source VD; the source of P2 is connected to a voltage source VDD; and the source of N1 is connected to a voltage source VDD. The voltage source VS; the source of N2 is connected to the voltage source VSS; the gate of N3 is connected to the word line WL, and the source of N3 is connected to the bit line BL; the drain of N4 and the source of P3 are connected to the bit line IL; the sources of N4 and N5 and the drains of P3 and P4 are connected to C0; C0 is connected to the bit line CBL; the gate of P4 is connected to the word line RWL, and the source of P4 is connected to the bit line RBL; the gate of N5 is connected to the word line WWL; VD and VS are connected to VDD and VSS respectively through the power supply gate signal EN and its inverted signal ENB via MOSFETs. The AND logic judgment performed by the multi-functional in-memory computing circuit is as follows: EN and ENB disconnect the connection between VD and VDD, and the connection between VS and VSS; set bit lines IL, RBL, and word line RWL to low level; when the word line WWL input is 0, set the word line WWL to high level, and write the input 0 to the storage node Q as the AND logic judgment result; when the word line WWL input is 1, set the word line WWL to low level, and keep the original value in the storage node Q unchanged as the AND logic judgment result.

[0007] As a further improvement to the above scheme, the OR logic judgment performed by the multi-functional in-memory computing circuit is as follows: EN and ENB disconnect the connection between VD and VDD, and the connection between VS and VSS; set bit lines IL and RBL to high level; set word line RWL to low level; when word line WWL input is 0, set word line WWL to low level, and the original value in storage node Q remains unchanged as the OR logic judgment result; when word line WWL input is 1, set WWL to high level, and write input 1 to storage node Q for storage as the OR logic judgment result.

[0008] As a further improvement to the above scheme, the implied logic judgment performed by the multi-functional in-memory computing circuit is as follows: EN and ENB disconnect the connection between VD and VDD, and the connection between VS and VSS; set bit lines IL and RBL to high level; set word line RWL to low level; when word line WWL input is 0, set WWL to high level, input 1 and write it to memory node Q for storage, as the implied logic judgment result; when word line WWL input is 1, set word line WWL to low level, the original value in memory node Q remains unchanged, as the implied logic judgment result.

[0009] As a further improvement to the above scheme, P1 and N1 in the multi-functional in-memory computing circuit constitute the first inverter, and P2 and N2 constitute the second inverter; N3 controls the column-direction read and write operations through the word line WL and the bit line BL; P3, P4, N4, and N5 are used to implement row-direction read and write and multiplication-accumulation functions; wherein: The column write operation logic executed by the multi-functional in-memory computing circuit is as follows: First, turn off P3, P4, N4, and N5; set EN to low level and ENB to high level, disconnecting VD and VS from VDD and VSS; set the word line WL to high level; then, input the number to be written to the first inverter through the bit line BL, causing the second inverter to flip; then control EN and ENB to connect VD to VDD and VS to VSS, so that the first inverter and the second inverter form a stable structure.

[0010] As a further improvement to the above scheme, the column read operation logic executed by the multi-functional in-memory computing circuit is as follows: When preparing for row read: N4, N5, P3 and P4 are turned off; EN is set to high level and ENB is set to low level; the bit line BL is precharged to high level; the word line WL is set to low level; When starting row read: by setting the word line WL to high level, the data of the access node Q is transmitted to BL, and then the bit line BL is connected to the OUT terminal of the read amplifier SA. The BOUT terminal of SA is connected to an external voltage source (800mV) to discharge the bit line BL. Then the word line WL is set to low level, and the voltage difference is amplified by SA before reading.

[0011] As a further improvement to the above scheme, the row write operation logic executed by the multi-functional in-memory computing circuit is as follows: set EN to low level and ENB to high level; set word line WL to low level and turn off bit line BL; set word line WWL to high level and word line RWL to low level; then, input the number to be written to inverter one through bit line IL and bit line RBL. When inverter two flips, control the EN and ENB signals to connect VD to VDD and VS to VSS, so that the first inverter and the second inverter form a stable structure.

[0012] As a further improvement to the above scheme, the row read operation logic executed by the multi-functional in-memory computing circuit is as follows: When preparing for row read: set EN to high level and ENB to low level; set word line WL to low level and turn off bit line BL; precharge bit line RBL and word line RWL to high level, and set bit line IL and word line WWL to low level; When starting column read: set word line RWL to low level, connect RBL to the BOUT terminal of SA, and connect the OUT terminal to an external voltage source (800mV). When Q is 1, bit line RBL is discharged through bit line IL, so that the BOUT voltage is lower than OUT, and the output is 1. When Q is 0, RBL remains high level, so that the BOUT voltage is higher than OUT, and the output is 0.

[0013] As a further improvement to the above scheme, the multiply-accumulate operation logic performed by the multi-functional in-memory computing circuit is as follows: (1) Preparation stage: Set EN to high and ENB to low; disconnect bit line BL and set bit line WL and word line WWL to low. (2) Pre-charge stage: Precharge bit lines IL and RBL to VDD / 2, set word line RWL to low level, precharge the upper plate of C0 to VDD / 2, and connect the lower plate of C0 to VSS via bit line CBL. (3) Multiplication stage: Both word line RWL and bit line RBL are set to high level, the PMOS transistor controlled by word line RWL is turned off, and the 5-bit signed input analog voltage is input to the upper plate of C0 via bit line IL; when Q is 1, the input value is transmitted to the upper plate through P3 and N4; when Q is 0, the upper plate is kept at the pre-charged VDD / 2. (4) Accumulation phase: Disconnect bit line CBL from VSS, close the PMOS transistor controlled by word line RWL, set bit lines IL and RBL to high level, charge the upper plate of C0 to VDD through bit lines IL and RBL, and the voltage of the lower plate is equal to VDD minus the input analog level. The formula then accumulates the results of 64 multiplication operations on CBL. ; In the formula, V is the voltage at bit line CBL, which is the voltage at the lower plate; VDD is the voltage of the voltage source; C in the numerator of the fraction is the MOM capacitance of each 9T1C-SRAM cell, and V is the voltage of each cell; C in the denominator of the fraction refers to the total MOM capacitance of the bit line.

[0014] As a further improvement to the above scheme, the multi-functional in-memory computing circuit includes an in-memory computing array module, which is used to perform Boolean logic write-back, signed multiply-accumulate (MAC) operations, and bidirectional row and column read / write operations. The in-memory computing array module includes 64 columns of storage cells, each column of storage cells includes 4 block modules, and each block module is composed of 16 9T1C-SRAM cells connected in columns.

[0015] As a further improvement to the above scheme, the multifunctional computing circuit also includes a row and column SA and precharge module, a logic write-back control module, a row and column read and write control module, as well as a multiply-accumulate input DAC and output ADC and a shift-accumulate adder tree module; the row and column read and write control module, the logic write-back control module, the row and column SA and precharge module, as well as the multiply-accumulate input DAC and output ADC and shift-accumulate adder tree module are all used to cooperate with the in-memory computing array module to complete Boolean logic write-back, bidirectional read and write and multiply-accumulate calculation functions.

[0016] A second aspect of the present invention also provides an in-memory computing chip based on a 9T1C-SRAM cell, which is packaged from any of the above-mentioned multifunctional in-memory computing circuits based on 9T1C-SRAM.

[0017] (3) Beneficial effects 1. Compared to traditional technologies (in-memory computing circuits, by parallelizing the computing module and storage module in a single circuit unit, initially solve the severe bandwidth bottleneck caused by frequent large-scale data transfers; however, existing in-memory computing circuits typically involve increasing the area of ​​the circuit unit to simultaneously achieve storage and multiple computing functions, thus increasing power consumption), the multi-functional in-memory computing circuit of this invention is based on a 9T1C-SRAM cell. It determines whether the unit circuit performs an equivalent operation or a write operation based on the input value and the original value in the storage node Q. Therefore, it can accurately implement Boolean logic write-back operations (i.e., AND logic determination), allowing the multi-functional in-memory computing circuit to increase the types of calculations without increasing the circuit area, thereby enabling calculations on more data. Therefore, the multi-functional in-memory computing circuit based on the 9T1C-SRAM cell can effectively reduce the circuit area and power consumption compared to existing circuit units, thus solving the technical problem of high power consumption and low area efficiency in in-memory computing circuits when performing Boolean logic write-back operations.

[0018] 2. The multifunctional in-memory computing circuit of this invention integrates row and column read / write functions into a single unit circuit and sets up two sets of inverters. When performing row and column read / write operations, after data is input to the storage node, the second inverter flips, thereby releasing or storing the data. On the one hand, row and column read / write can share a single reference voltage, saving circuit area; on the other hand, it can isolate the interference of the read process to the storage node, improve read noise tolerance, and avoid read corruption. This solves the problems of existing SRAM cells being unable to achieve bidirectional row and column read / write, having low read noise tolerance, and being prone to read corruption during in-memory computing.

[0019] 3. The multifunctional in-memory computing circuit of this invention simultaneously supports Boolean logic write-back, signed multiply-accumulate (MAC) operations, and bidirectional row and column read / write, achieving deep integration of logical operations, arithmetic operations, and data movement within the same storage unit. This structure breaks the limitations of traditional in-memory computing architectures, which suffer from "dispersed implementation of logical functions and numerical calculations, data needing to be moved across arrays, and complex write-back paths." It enables Boolean operations, multiply-accumulate calculations, and in-array data rearrangement to be completed collaboratively in a single cycle, in-situ, and with high parallelism, significantly reducing energy consumption and latency while improving array-level throughput and functional density. Due to its ability to simultaneously support high-precision numerical calculations and large-scale logical processing, and its flexible row / column data flow scheduling, this unit has broad application prospects in scenarios such as edge AI inference, encryption algorithms (such as AES), binary and low-bit neural networks, reconfigurable processors, dataflow accelerators, and efficient on-chip machine learning systems. It provides a key foundational unit for building a highly versatile, energy-efficient, and programmable next-generation in-memory computing architecture. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a multi-functional in-memory computing circuit based on a 9T1C-SRAM cell provided in an embodiment of the present invention; Figure 2 This is a circuit diagram of the BLOCK module provided in Embodiment 1 of the present invention; Figure 3 The circuit diagram of the 9T1C-SRAM cell provided in Embodiment 1 of the present invention; Figure 4 This is a signal state diagram of the logical decision-making process in Boolean logic decision-making provided in Embodiment 1 of the present invention; Figure 5 is a signal state diagram of Boolean logic determination and OR logic determination provided in Embodiment 1 of the present invention. Figure 6 This is a signal state diagram of the Boolean logic decision provided in Embodiment 1 of the present invention when the logic decision is implied. Figure 7 This is a signal state diagram of the column write operation in the bidirectional read / write operation provided in Embodiment 2 of the present invention; Figure 8 This is a signal state diagram during column read operations in the bidirectional read / write operation provided in Embodiment 2 of the present invention; Figure 9 This is a signal state diagram during a row write operation in the bidirectional read / write operation provided in Embodiment 2 of the present invention; Figure 10 This is a signal state diagram of the row read operation in the bidirectional read / write operation provided in Embodiment 2 of the present invention; Figure 11 This is a signal state diagram of the multiply-accumulate operation provided in Embodiment 3 of the present invention. Detailed Implementation

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0024] Example 1 This embodiment introduces an in-memory computing chip based on 9T1C-SRAM cells, used to perform calculation, storage, or transmission operations on externally transmitted electrical signals, thereby realizing information processing. The in-memory computing chip based on 9T1C-SRAM cells can be packaged into one or more sets of multifunctional in-memory computing circuits based on 9T1C-SRAM.

[0025] A multi-functional in-memory computing circuit based on 9T1C-SRAM is used to implement Boolean logic write-back, bidirectional row and column read / write, and signed multiply-accumulate (MAC) operations. This multi-functional in-memory computing circuit based on 9T1C-SRAM may include an in-memory computing array module, a logic write-back control module, row and column SA and precharge modules, a row and column read / write control module, a multiply-accumulate input DAC and output ADC, and a shift-accumulate adder tree module, such as... Figure 1As shown. The in-memory computing array module is used to perform calculations and store externally transmitted electrical signals according to the set circuit units, thereby completing Boolean logic write-back, signed multiply-accumulate (MAC) operations, and bidirectional row-column read / write operations. The logic write-back control module is used to cooperate with the in-memory computing array module to complete the Boolean logic write-back operation. It may include logic control circuits set in the row and column directions of the in-memory computing array module; wherein, the logic control circuit in the row direction controls the type of Boolean logic performed, and the logic control circuit in the column direction controls the timing of the Boolean logic write-back. The row-column SA and precharge module is used to precharge the data bit lines in the in-memory computing array module to an accurate voltage (such as VDD, VDD / 2), then read the data stored in the in-memory computing array module, amplify the small voltage difference between the two complementary bit lines, and then output the digital signal. The row-column read / write control module is used to cooperate with the in-memory computing array module to complete the bidirectional read / write operation. It includes read / write control circuits set in the row and column directions of the in-memory computing array module. The multiply-accumulate input DAC, output ADC, and shift-accumulate adder tree module are used in conjunction with the in-memory computing array module to complete signed multiply-accumulate (MAC) operations.

[0026] The in-memory computing array module may include 64 columns of storage cells (or 32 columns of storage cells, or 128 columns of storage cells, etc.). n Column storage unit (n is a positive integer). Each column storage unit can be composed of 4 block modules, and each block module can be composed of 16 9T1C-SRAM cells connected in columns. The voltage sources VD and VS of the 16 9T1C-SRAM cells are connected together, and connected to voltage sources VDD and VSS through a MOSFET via the power gating signal EN and its inverted signal ENB. EN and ENB are used as global control lines connected to the read / write and logic control circuits, such as... Figure 2 As shown.

[0027] Please see Figure 3The circuit layout of the 9T1C-SRAM cell is as follows: it includes 5 NMOS transistors N1~N5, 4 PMOS transistors P1~P4 and capacitor C0. The gates of P2, N2, and N4 are connected to the drains of P1, N1, N3, and N5 to form memory node Q; the gates of P1, N1, and P3 are connected to the drains of P2 and N2 to form memory node QB; the source of P1 is connected to voltage source VD; the source of P2 is connected to voltage source VDD; the source of N1 is connected to voltage source VS; the source of N2 is connected to voltage source VSS; the gate of N3 is connected to word line WL, and the source of N3 is connected to bit line BL; the drain of N4 and the source of P3 are connected to bit line IL; the sources of N4 and N5, and the drains of P3 and P4 are connected to C0; C0 is connected to bit line CBL; the gate of P4 is connected to word line RWL, and the source of P4 is connected to bit line RBL; the gate of N5 is connected to word line WWL; VD and VS are connected to VDD and VSS respectively through power gating signal EN and its inverted signal ENB via MOSFETs. In the circuit, P1 and N1 form the first inverter, and P2 and N2 form the second inverter.

[0028] Please see Figures 4 to 6 The Boolean logic decision performed by the 9T1C-SRAM cell is as follows: (1) AND logic determination: EN and ENB disconnect VD from VDD and VS from VSS; set bit line IL, RBL and word line RWL to low level; when word line WWL input is 0, set word line WWL to high level, input 0 and write to storage node Q to save as AND logic determination result; when word line WWL input is 1, set word line WWL to low level, the original value in storage node Q remains unchanged as AND logic determination result.

[0029] (2) OR logic determination: The OR logic determination performed by the multi-functional in-memory computing circuit is as follows: EN and ENB disconnect the connection between VD and VDD, and the connection between VS and VSS; set the bit lines IL and RBL to high level; set the word line RWL to low level; when the word line WWL input is 0, set the word line WWL to low level, and the original value in the storage node Q remains unchanged as the OR logic determination result; when the word line WWL input is 1, set WWL to high level, and write the input 1 to the storage node Q for storage as the OR logic determination result.

[0030] (3) Implied logic determination: The implied logic determination performed by the multi-functional in-memory computing circuit is as follows: EN and ENB disconnect the connection between VD and VDD, and the connection between VS and VSS; set bit lines IL and RBL to high level; set word line RWL to low level; when word line WWL input is 0, set WWL to high level, input 1 and write it to storage node Q for storage, as the result of implied logic determination; when word line WWL input is 1, set word line WWL to low level, the original value in storage node Q remains unchanged, as the result of implied logic determination.

[0031] (4) Other determinations: Since AES encryption involves a large number of XOR and XNOR operations, in order to adapt to more operations, based on the formula, an XOR operation is completed in two cycles through two parallel AND operations and one OR operation (the XNOR operation result is stored by the QB node). In the formula, A and B are the calculation results obtained after logic calculation by the 9T1C-SRAM cell; The reverse result of A (if) If A is 1, then A is 0). The reverse result of B (if) If B is 1, then B is 0.

[0032] In this invention, four Boolean logic write-back operations are completed using only a single 9T1C-SRAM cell, saving circuit area. Furthermore, due to the mapping relationship of this invention, the power consumption of operations where the input is 1 and the write operation is 1, and operations where the input is 0 and the write operation is 0, are extremely low in the calculation process of each Boolean logic (AND, OR, and implied). Only operations where the input is 0 and the write operation is 1, or operations where the input is 1 and the write operation is 0, have relatively high power consumption. When the probability of the four input and storage conditions is considered equal, the computational efficiency can be significantly improved.

[0033] The detailed Boolean logic write-back flowchart and truth table are shown in Table 1. The middle section of the table shows the three logical operations in the Boolean logic write-back: AND, OR, and implication. The flowchart on the left shows the excitation signals of the lines involved in the operations during the three Boolean logic write-back operations. The truth table on the right shows the fundamental principle of Boolean logic write-back, mapping the three operations to write as 1, write as 0, and hold.

[0034] In summary, the multi-functional in-memory computing circuit based on the 9T1C-SRAM cell can perform four Boolean logic write-back operations, effectively improving computing efficiency while keeping the circuit area unchanged.

[0035] Example 2 Based on the multi-functional in-memory computing circuit based on the 9T1C-SRAM cell provided in Embodiment 1, this embodiment further provides bidirectional read / write operations for the 9T1C-SRAM cell in the multi-functional in-memory computing circuit. Please refer to... Figures 7 to 10 The bidirectional read / write operation logic performed by the 9T1C-SRAM cell is as follows: (1) Column write operation: First, turn off P3, P4, N4, and N5; set EN to low level and ENB to high level, and disconnect VD and VS from VDD and VSS; set word line WL to high level; then, input the number to be written into the first inverter through bit line BL, so that the second inverter flips, and then control EN and ENB to connect VD to VDD and VS to VSS, so that the first inverter and the second inverter form a stable structure.

[0036] (2) Column read operation: When preparing for row read: turn off N4, N5, P3 and P4; set EN to high level and ENB to low level; first precharge the bit line BL to high level; set the word line WL to low level; when starting row read: by setting the word line WL to high level, the data of the access node Q is transmitted to BL, then the bit line BL is connected to the OUT terminal of the read amplifier SA, and the BOUT terminal of SA is connected to an external voltage source (800mV) to speed up the read speed, discharge the bit line BL, and then set the word line WL to low level. After the voltage difference is amplified by SA, the data is read.

[0037] (3) Row write operation: Set EN to low level and ENB to high level; set word line WL to low level and turn off bit line BL; set word line WWL to high level and word line RWL to low level. Then, input the number to be written to inverter one through bit line IL and bit line RBL. When inverter two flips, control the EN and ENB signals to make VD connected to VDD and VS connected to VSS, so that the first inverter and the second inverter form a steady-state structure.

[0038] (4) Row read operation: When preparing for row read: set EN to high level and ENB to low level; set word line WL to low level and turn off bit line BL; precharge bit line RBL and word line RWL to high level, and set bit line IL and word line WWL to low level; When starting column read: set word line RWL to low level, connect RBL to the BOUT terminal of SA, and connect the OUT terminal to an external voltage source (800mV) to amplify the voltage difference and speed up the read speed. When Q is 1, bit line RBL is discharged through bit line IL, so that the BOUT voltage is lower than OUT and the output is 1. When Q is 0, RBL is kept high level, so that the BOUT voltage is higher than OUT and the output is 0.

[0039] In summary, the multi-functional in-memory computing circuit based on the 9T1C-SRAM cell has the function of bidirectional reading and writing of rows and columns. By setting two sets of inverters, the inverter is turned on during writing and turned off after writing, and the data is stored in the storage node Q. On the one hand, it can share a reference voltage with column reading and writing to save circuit area. On the other hand, it can isolate the interference of the reading process to the storage node, improve the reading noise tolerance and avoid reading damage.

[0040] Example 3 Based on the multi-functional in-memory computing circuit based on 9T1C-SRAM cells provided in Embodiment 1, this embodiment further provides the operation of multiplication-accumulation in the 9T1C-SRAM cells within the multi-functional in-memory computing circuit. Please refer to... Figure 11 The logic for the multiply-accumulate operation performed by the 9T1C-SRAM cell is as follows: (1) Preparation stage: Set EN to high and ENB to low; disconnect bit line BL and set bit line WL and word line WWL to low. (2) Pre-charge stage: Precharge bit lines IL and RBL to VDD / 2, set word line RWL to low level, precharge the upper plate of C0 to VDD / 2, and connect the lower plate of C0 to VSS via bit line CBL. (3) Multiplication stage: Both word line RWL and bit line RBL are set to high level, the PMOS transistor controlled by word line RWL is turned off, and the 5-bit signed input analog voltage is input to the upper plate of C0 via bit line IL; when Q is 1, the input value is transmitted to the upper plate through P3 and N4; when Q is 0, the upper plate is kept at the pre-charged VDD / 2. (4) Accumulation phase: Disconnect bit line CBL from VSS, close the PMOS transistor controlled by word line RWL, set bit lines IL and RBL to high level, and charge the upper plate of C0 to VDD through bit lines IL and RBL. Since the voltage drop of C0 remains unchanged, the voltage of the lower plate of C0 becomes VDD minus the input analog level. Then, the formula can be obtained by applying the superposition theorem. ; In the formula, V is the voltage at bit line CBL, which is the voltage at the lower plate; VDD is the voltage of the voltage source; C in the numerator of the fraction is the MOM capacitance of each 9T1C-SRAM cell, and V is the voltage of each cell; C in the denominator of the fraction refers to the total MOM capacitance of the bit line.

[0041] In this process, the DAC in the horizontal direction converts the 5-bit signed input into an analog level according to the correspondence in Table 2, and then inputs it into the IL unit for multiplication and accumulation calculation. The ADC converts the analog level generated by multiplying the 64 5-bit inputs on CBL with the 1-bit weight into a 5-bit signed output. Then, it performs shift accumulation in groups of four through an addition tree to complete the weighting, and outputs the 5-bit signed input multiplied and accumulated result with the 5-bit weight in parallel.

[0042] In detail, Table 2 shows the correspondence between the input 5-bit signed number and the analog level, as well as the multiplication-accumulation flowchart. The correspondence on the left shows how the DAC converts the input binary number into an analog level input, and the flowchart on the right shows how each stage is operated.

[0043] In summary, based on the analog input levels in Table 2, and... Figure 11 The circuit state information in the three stages of pre-charging, calculation and holding converts the analog level into a 5-bit signed output result. Then, the output is shifted and accumulated in groups of four through an adder tree. Therefore, the multi-functional in-memory calculation circuit based on the 9T1C-SRAM cell has the function of realizing multiplication and accumulation operations.

[0044] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0045] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A multi-functional in-memory computing circuit based on a 9T1C-SRAM cell, characterized in that, This includes a 9T1C-SRAM cell, comprising 5 NMOS transistors N1~N5, 4 PMOS transistors P1~P4, and capacitor C0; the gates of P2, N2, and N4 are connected to the drains of P1, N1, N3, and N5 to form storage node Q; the gates of P1, N1, and P3 are connected to the drains of P2 and N2 to form storage node QB; the source of P1 is connected to voltage source VD; the source of P2 is connected to voltage source VDD; the source of N1 is connected to voltage source VS; and the source of N2 is connected to... Voltage source VSS; gate of N3 connected to word line WL, source of N3 connected to bit line BL; drain of N4 and source of P3 connected to bit line IL; sources of N4 and N5 and drains of P3 and P4 connected to C0; C0 connected to bit line CBL; gate of P4 connected to word line RWL, source of P4 connected to bit line RBL; gate of N5 connected to word line WWL; VD and VS are connected to VDD and VSS respectively through power gate signal EN and its inverted signal ENB via MOSFETs. The in-memory computing circuit performs the following AND logic judgment: EN and ENB disconnect the connection between VD and VDD, and the connection between VS and VSS; set bit lines IL, RBL and word line RWL to low level; when word line WWL input is 0, set word line WWL to high level, and write the input 0 to memory node Q to save as the AND logic judgment result; When the word line WWL input is 1, the word line WWL is set to low level, and the original value in the storage node Q remains unchanged as the result of the AND logic judgment.

2. The multi-functional in-memory computing circuit based on a 9T1C-SRAM cell according to claim 1, characterized in that, The OR logic decision performed by the multi-functional in-memory computing circuit is as follows: EN and ENB disconnect the connection between VD and VDD, and the connection between VS and VSS; set bit lines IL and RBL to high level; set word line RWL to low level; when word line WWL input is 0, set word line WWL to low level, and the original value in memory node Q remains unchanged as the OR logic decision result; when word line WWL input is 1, set WWL to high level, and write input 1 to memory node Q for storage as the OR logic decision result.

3. The multi-functional in-memory computing circuit based on a 9T1C-SRAM cell according to claim 1, characterized in that, The implied logic judgment performed by the multi-functional in-memory computing circuit is as follows: EN and ENB disconnect the connection between VD and VDD, and the connection between VS and VSS; set bit lines IL and RBL to high level; set word line RWL to low level; when word line WWL input is 0, set WWL to high level, input 1 and write it to memory node Q for storage, as the implied logic judgment result; when word line WWL input is 1, set word line WWL to low level, the original value in memory node Q remains unchanged, as the implied logic judgment result.

4. The multi-functional in-memory computing circuit based on a 9T1C-SRAM cell according to claim 1, characterized in that, In the multi-functional in-memory computing circuit, P1 and N1 form the first inverter, and P2 and N2 form the second inverter; N3 controls the column-direction read / write operations through the word line WL and the bit line BL; P3, P4, N4, and N5 are used to implement row-direction read / write and multiplication / accumulation functions; among them: The column write operation logic executed by the multi-functional in-memory computing circuit is as follows: First, turn off P3, P4, N4, and N5; set EN to low level and ENB to high level, disconnecting VD and VS from VDD and VSS; set the word line WL to high level; then, input the number to be written to the first inverter through the bit line BL, causing the second inverter to flip; then control EN and ENB to connect VD to VDD and VS to VSS, so that the first inverter and the second inverter form a stable structure.

5. The multi-functional in-memory computing circuit based on a 9T1C-SRAM cell according to claim 1, characterized in that, The column read operation logic executed by the multi-functional in-memory computing circuit is as follows: When preparing for row read: N4, N5, P3 and P4 are turned off; EN is set to high level and ENB is set to low level; the bit line BL is precharged to high level; the word line WL is set to low level; When starting row read: by setting the word line WL to high level, the data of the access node Q is transmitted to BL, then the bit line BL is connected to the OUT terminal of the read amplifier SA, the BOUT terminal of SA is connected to the reference voltage Vref=800mV to discharge the bit line BL, and then the word line WL is set to low level. After the voltage difference is amplified by SA, the data is read out.

6. The multi-functional in-memory computing circuit based on a 9T1C-SRAM cell according to claim 1, characterized in that, The row write operation logic executed by the multi-functional in-memory computing circuit is as follows: Set EN to low level and ENB to high level; set word line WL to low level and turn off bit line BL; set word line WWL to high level and word line RWL to low level. Then, input the number to be written to inverter one through bit line IL and bit line RBL. When inverter two flips, control the EN and ENB signals to connect VD to VDD and VS to VSS, so that the first inverter and the second inverter form a stable structure.

7. The multi-functional in-memory computing circuit based on a 9T1C-SRAM cell according to claim 1, characterized in that, The row read operation logic executed by the multi-functional in-memory computing circuit is as follows: When preparing for row read: EN is set to high level and ENB is set to low level; word line WL is set to low level and bit line BL is turned off; bit line RBL and word line RWL are precharged to high level, and bit line IL and word line WWL are set to low level; When starting column read: word line RWL is set to low level, bit line RBL is connected to the BOUT terminal of SA, and the OUT terminal is connected to the reference voltage Vref=800mV. When Q is 1, bit line RBL is discharged through bit line IL, so that the BOUT voltage is lower than OUT, and the output is 1. When Q is 0, RBL is kept high level, so that the BOUT voltage is higher than OUT, and the output is 0.

8. The multi-functional in-memory computing circuit based on a 9T1C-SRAM cell according to claim 1, characterized in that, The logic for the multiply-accumulate operation performed by the multi-function in-memory computing circuit is as follows: (1) Preparation stage: Set EN to high and ENB to low; disconnect bit line BL and set bit line WL and word line WWL to low. (2) Pre-charge stage: Precharge bit lines IL and RBL to VDD / 2, set word line RWL to low level, precharge the upper plate of C0 to VDD / 2, and connect the lower plate of C0 to VSS via bit line CBL. (3) Multiplication stage: Both word line RWL and bit line RBL are set to high level, the PMOS transistor controlled by word line RWL is turned off, and the 5-bit signed input analog voltage is input to the upper plate of C0 via bit line IL; when Q is 1, the input value is transmitted to the upper plate through P3 and N4. When Q is 0, the upper plate maintains a pre-charged VDD / 2; (4) Accumulation phase: Disconnect bit line CBL from VSS, close the PMOS transistor controlled by word line RWL, set bit lines IL and RBL to high level, charge the upper plate of C0 to VDD through bit lines IL and RBL, and the voltage of the lower plate is equal to VDD minus the input analog level. The formula then accumulates the results of 64 multiplication operations on CBL. ； In the formula, V is the voltage at bit line CBL, which is the voltage at the lower plate; VDD is the voltage of the voltage source; C in the numerator of the fraction is the MOM capacitance of each 9T1C-SRAM cell, and V is the voltage of each cell; C in the denominator of the fraction refers to the total MOM capacitance of the bit line.

9. The multi-functional in-memory computing circuit based on a 9T1C-SRAM cell according to claim 1, characterized in that, The multi-functional in-memory computing circuit includes an in-memory computing array module for performing Boolean logic write-back, signed multiply-accumulate (MAC) operations, and bidirectional row and column read / write operations. The in-memory computing array module includes 64 columns of storage units, each column of storage units includes 4 Block modules, and each Block module is composed of 16 9T1C-SRAM units connected in columns. Furthermore / or, the multi-functional computing circuit also includes a row and column SA and a pre-charge module, a logic write-back control module, a row and column read and write control module, as well as a multiply-accumulate input DAC and output ADC and a shift-accumulate adder tree module; the row and column read and write control module, the logic write-back control module, the row and column SA and the pre-charge module, as well as the multiply-accumulate input DAC and output ADC and shift-accumulate adder tree module are all used to cooperate with the in-memory computing array module to complete Boolean logic write-back, bidirectional read and write, and multiply-accumulate calculation functions.

10. An in-memory computing chip based on 9T1C-SRAM cells, characterized in that, It is packaged from a multi-functional in-memory computing circuit based on 9T1C-SRAM as described in any one of claims 1 to 9.

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