An analog-to-digital converter for voltage-mode RRAM memory circuits
By using power supply LDO- and power supply LDO+ to provide quantization reference potentials in the analog-to-digital converter, the area and power consumption problems of existing analog-to-digital converters when expanding the quantization bit width are solved, and a more efficient circuit design is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING INST OF INTELLIGENT TECH INST OF MICROELECTRONICS OF THE CHINESE ACAD OF
- Filing Date
- 2022-12-29
- Publication Date
- 2026-05-26
AI Technical Summary
Existing analog-to-digital converters (ADCs) face significant area and power consumption issues when expanding the quantization bit width, especially in Flash ADC, SAR ADC, and Pipelined ADC structures where the increased number of comparators and capacitor DAC arrays lead to excessive circuit area and dynamic power consumption.
Power supplies LDO- and LDO+ are used to provide quantization reference potentials that are high and low compared to the initialization reference voltage for the first and second quantization circuits. The quantization reference potentials provided by power supplies LDO- and LDO+ are directly compared with the sampling potential of capacitor CC in the sampling module, reducing the need for external signal control and avoiding the need to increase the number of comparators and capacitor arrays.
Expanding the quantization bit width reduces circuit area and power consumption, optimizes circuit design complexity, and achieves more efficient analog-to-digital conversion.
Smart Images
Figure CN115833838B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an analog-to-digital converter for voltage-mode RRAM storage circuits, belonging to the field of analog-to-digital converter technology. Background Technology
[0002] Current analog-to-digital converters (ADCs) mainly consist of Flash ADCs, SAR ADCs, and Pipelined ADCs. As accuracy increases, the number of comparators used in Flash ADCs increases exponentially, resulting in significant power consumption and area increases. SAR ADCs require a capacitor DAC array for successive weighted comparison quantization, and the large number of capacitors not only increases the circuit area but also generates significant dynamic power consumption during capacitor charging and discharging. Pipelined ADCs have a more complex structure and are more difficult to design. Summary of the Invention
[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide an analog-to-digital converter for voltage-mode RRAM memory circuits, which solves the problem of large area and power consumption caused by the current analog-to-digital converter structure when expanding the quantization bit width.
[0004] To achieve the above objectives / to solve the above technical problems, the present invention is implemented using the following technical solution:
[0005] An analog-to-digital converter for voltage-mode RRAM memory circuitry, including a source line SL i The components include: sampling module, error amplifier A, first quantization circuit, second quantization circuit, buffer BU, power supply LDO- and power supply LDO+;
[0006] The source line SL i Connected to the sampling module, the sampling module is used to sample the source line SL. i Perform potential sampling;
[0007] The inverting input of the error amplifier A is connected to the sampling module, and the non-inverting input is connected to a capacitor C. C The capacitor C C The lower plate is grounded; the non-inverting and inverting input terminals of the error amplifier A have an initialization reference voltage V. ref ;
[0008] The output signal of the error amplifier A is V. F The output terminal of the error amplifier A is connected to the first quantization circuit and the second quantization circuit; the output terminals of the first quantization circuit and the second quantization circuit are connected to the buffer BU.
[0009] The capacitor C CThe upper plates are connected to the output terminals of power supply LDO- and power supply LDO+, respectively; power supply LDO- and power supply LDO+ are used to provide reference potentials of various amplitudes.
[0010] The power supply LDO- has a start-up terminal PD-, which is connected to the output terminal of the second quantization circuit; the power supply LDO+ has a start-up terminal PD+, which is connected to the output terminal of the second quantization circuit; the second quantization circuit is used to control the start and stop of the power supplies LDO- and LDO+.
[0011] Optionally, the sampling module includes a capacitor C. S and switch S i The switch S i One end is connected to the source line SL i Connected, the switch S i The other end is connected to capacitor C. S The upper plate of the capacitor is connected to the inverting input terminal of error amplifier A, and the capacitor C is connected to the upper plate of the capacitor. S The lower electrode plate is grounded.
[0012] Optionally, the second quantization circuit includes a switch S. s0- Switch S s19 Inverters INV2 and INV3; the switch S s0- One end of the switch is connected to the output of error amplifier A, and the switch S s0- The other end is connected to the input of inverter INV2; the output of inverter INV2 is connected to the input of inverter INV3, and the output signal of inverter INV2 is Vos. - The output terminal of the inverter INV3 is connected to the switch S. s19 One end of the switch S is connected to the switch. s19 The other end is connected to the input of the buffer BU; the output signal of the buffer BU is V0; the output signal of the inverter INV3 is Vos.
[0013] Optionally, the first quantization circuit includes a switch S. s0 Switch S s5- Switch S s5 Switch S s18 Inverters INV0 and INV1; the switch S s0 One end of the switch is connected to the output of error amplifier A, and the switch S s0 The other end is connected to the input terminal of inverter INV0; the output terminal of inverter INV0 is connected to switch S. s5- One end of the inverter is connected to the input terminal of the inverter INV1; the output terminal of the inverter INV1 is connected to the switch S. s5One end of the switch S is connected; s5- The other end, switch S s5 The other end is connected to switch S s18 One end of the switch S is connected to the switch. s18 The other end is connected to the input of the buffer BU, and the switch S s18 Follow switch S s0 Simultaneously closed or opened; when Vos - When the level is high "1", the switch S s5- When closed, the switch S s5 Disconnect; when Vos is high level "1", the switch S s5 When closed, the switch S s5- disconnect.
[0014] Optionally, the power supply LDO includes a reference potential V. F0- Reference potential V F1- Reference potential V F2- Reference potential V F3- The circuit includes a first potential path, a second potential path, a third potential path, and a fourth potential path; the first potential path includes a switch S. s1 and switch S s6 The switch S s1 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s1 The other end is connected to switch S s6 One end of the switch S is connected to the switch. s6 The other end is connected to the reference potential V F0- Connected; the second potential path includes switch S s2 and switch S s7 The switch S s2 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s2 The other end is connected to switch S s7 One end of the switch S is connected to the switch. s7 The other end is connected to the reference potential V F1- Connected; the third potential path includes switch S s3 and switch S s8 The switch S s3 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s3 The other end is connected to switch S s8 One end of the switch S is connected to the switch. s8 The other end is connected to the reference potential V F2- Connected; the fourth potential path includes switch S s4 and switch S s9The switch S s4 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s4 The other end is connected to switch S s9 One end of the switch S is connected to the switch. s9 The other end is connected to the reference potential V F3- Connected; when Vos is high ("1"), the LDO power supply is activated, and switch S... s6 Switch S s9 closure.
[0015] Optionally, the power supply LDO+ includes a reference potential V. F0+ Reference potential V F1+ Reference potential V F2+ Reference potential V F3+ The fifth potential path, the sixth potential path, the seventh potential path, and the eighth potential path; the fifth potential path includes switch S. s10 and switch S s14 The switch S s10 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s10 The other end is connected to switch S s14 One end of the switch S is connected to the switch. s14 The other end is connected to the reference potential V F0+ Connected; the sixth potential path includes switch S s11 and switch S s15 The switch S s11 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s11 The other end is connected to switch S s15 One end of the switch S is connected to the switch. s15 The other end is connected to the reference potential V F1+ Connected; the seventh potential path includes switch S s12 and switch S s16 The switch S s12 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s12 The other end is connected to switch S s16 One end of the switch S is connected to the switch. s16 The other end is connected to the reference potential V F2+ Connected; the eighth potential path includes switch S s13 and switch S s17 The switch S s13 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s13 The other end is connected to switch S s17One end of the switch S is connected to the switch. s17 The other end is connected to the reference potential V F3+ Connected; when Vos is low "0", the LDO+ power supply starts, and switch S... s14 Switch S s17 closure.
[0016] Optionally, the reference potential V F0- Reference potential V F1- Reference potential V F2- and reference potential V F3- The voltage increases sequentially but remains less than the initial reference voltage V. ref The reference potential V F3+ Reference potential V F2+ Reference potential V F1+ and reference potential V F0+ The voltage decreases sequentially and is greater than the initial reference voltage V. ref .
[0017] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:
[0018] 1. This invention provides the first and second quantization circuits with high and low initialization reference voltages V by setting power supplies LDO- and LDO+. ref The quantization reference potentials are used to determine the positive or negative value of the quantized value, without the need for external signal control. Since the quantization reference potentials are directly provided by the power supply LDO- and LDO+, when expanding the quantization bit width, it is only necessary to change the number of quantization potentials provided by the power supply, without exponentially increasing the number of comparators or setting up a DAC capacitor array. This greatly reduces the circuit area and power consumption, solving the problem of large area and power consumption caused by the current analog-to-digital converter structure when expanding the quantization bit width.
[0019] 2. This invention directly provides the quantization reference potential and the sampling module's capacitor C through power supply LDO- and power supply LDO+. C The sampling potentials are directly compared, without complex logic control structures, thus reducing the difficulty of circuit design. Attached Figure Description
[0020] Figure 1 A schematic diagram of an analog-to-digital converter for a voltage-mode RRAM memory circuit provided in an embodiment of the present invention;
[0021] Figure 2 A circuit diagram of an analog-to-digital converter for a voltage-mode RRAM storage circuit provided in an embodiment of the present invention;
[0022] Figure 3This is a schematic diagram illustrating the connection between an analog-to-digital converter and an RRAM array for a voltage-mode RRAM memory circuit, provided as an embodiment of the present invention. Detailed Implementation
[0023] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.
[0024] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances. Example
[0026] like Figure 1 As shown, an analog-to-digital converter for voltage-mode RRAM memory circuitry includes a source line SL. i The system includes a sampling module, an error amplifier A, a first quantization circuit, a second quantization circuit, a buffer BU, and power supplies LDO- and LDO+; the source line SL... i Connected to the sampling module, the sampling module is used to sample the source line SL. i Potential sampling is performed; the inverting input of the error amplifier A is connected to the sampling module, and the non-inverting input is connected to a capacitor C. C The capacitor C C The lower plate is grounded; the non-inverting and inverting input terminals of the error amplifier A have an initial reference voltage V. ref The output signal of the error amplifier A is V. F The output of the error amplifier A is connected to the first quantization circuit and the second quantization circuit; the outputs of the first quantization circuit and the second quantization circuit are respectively connected to the buffer BU; the capacitor C CThe upper plates are connected to the output terminals of power supplies LDO- and LDO+, respectively; power supplies LDO- and LDO+ are used to provide reference potentials of various amplitudes; power supply LDO- has a start-up terminal PD-, which is connected to the output terminal of the second quantization circuit; power supply LDO+ has a start-up terminal PD+, which is connected to the output terminal of the second quantization circuit; the second quantization circuit is used to control the start and stop of power supplies LDO- and LDO+.
[0027] like Figure 2 As shown, the sampling module includes capacitor C. S and switch S i The switch S i One end is connected to the source line SL i Connected, the switch S i The other end is connected to capacitor C. S The upper plate of the capacitor is connected to the inverting input terminal of error amplifier A, and the capacitor C is connected to the upper plate of the capacitor. S The lower electrode plate is grounded;
[0028] like Figure 2 As shown, the second quantization circuit includes a switch S. s0- Switch S s19 Inverters INV2 and INV3; the switch S s0- One end of the switch is connected to the output of error amplifier A, and the switch S s0- The other end is connected to the input of inverter INV2; the output of inverter INV2 is connected to the input of inverter INV3, and the output signal of inverter INV2 is Vos. - The output terminal of the inverter INV3 is connected to the switch S. s19 One end of the switch S is connected to the switch. s19 The other end is connected to the input of the buffer BU; the output signal of the buffer BU is V0; the output signal of the inverter INV3 is Vos.
[0029] like Figure 2 As shown, the first quantization circuit includes a switch S. s0 Switch S s5- Switch S s5 Switch S s18 Inverters INV0 and INV1; the switch S s0 One end of the switch is connected to the output of error amplifier A, and the switch S s0 The other end is connected to the input terminal of inverter INV0; the output terminal of inverter INV0 is connected to switch S. s5- One end of the inverter is connected to the input terminal of the inverter INV1; the output terminal of the inverter INV1 is connected to the switch S.s5 One end of the switch S is connected; s5- The other end, switch S s5 The other end is connected to switch S s18 One end of the switch S is connected to the switch. s18 The other end is connected to the input of the buffer BU, and the switch S s18 Follow switch S s0 Simultaneously closed or opened; when Vos - When the level is high "1", the switch S s5- When closed, the switch S s5 Disconnect; when Vos is high level "1", the switch S s5 When closed, the switch S s5- disconnect.
[0030] like Figure 2 As shown, the power supply LDO includes a reference potential V. F0- Reference potential V F1- Reference potential V F2- Reference potential V F3- The circuit includes a first potential path, a second potential path, a third potential path, and a fourth potential path; the first potential path includes a switch S. s1 and switch S s6 The switch S s1 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s1 The other end is connected to switch S s6 One end of the switch S is connected to the switch. s6 The other end is connected to the reference potential V F0- Connected; the second potential path includes switch S s2 and switch S s7 The switch S s2 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s2 The other end is connected to switch S s7 One end of the switch S is connected to the switch. s7 The other end is connected to the reference potential V F1- Connected; the third potential path includes switch S s3 and switch S s8 The switch S s3 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s3 The other end is connected to switch S s8 One end of the switch S is connected to the switch. s8 The other end is connected to the reference potential V F2- Connected; the fourth potential path includes switch S s4and switch S s9 The switch S s4 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s4 The other end is connected to switch S s9 One end of the switch S is connected to the switch. s9 The other end is connected to the reference potential V F3- Connected; the starting terminal PD- is connected to the output terminal of inverter INV3. When Vos is high level "1", the power supply LDO- is started, and switch S... s6 Switch S s9 closure.
[0031] like Figure 2 As shown, the power supply LDO+ includes a reference potential V. F0+ Reference potential V F1+ Reference potential V F2+ Reference potential V F3+ The fifth potential path, the sixth potential path, the seventh potential path, and the eighth potential path; the fifth potential path includes switch S. s10 and switch S s14 The switch S s10 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s10 The other end is connected to switch S s14 One end of the switch S is connected to the switch. s14 The other end is connected to the reference potential V F0+ Connected; the sixth potential path includes switch S s11 and switch S s15 The switch S s11 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s11 The other end is connected to switch S s15 One end of the switch S is connected to the switch. s15 The other end is connected to the reference potential V F1+ Connected; the seventh potential path includes switch S s12 and switch S s16 The switch S s12 One end is connected to capacitor C C The upper electrode plate is connected, and the switch S s12 The other end is connected to switch S s16 One end of the switch S is connected to the switch. s16 The other end is connected to the reference potential V F2+ Connected; the eighth potential path includes switch S s13 and switch S s17 The switch S s13 One end is connected to capacitor CC The upper electrode plate is connected, and the switch S s13 The other end is connected to switch S s17 One end of the switch S is connected to the switch. s17 The other end is connected to the reference potential V F3+ The power supply LDO+ is connected to the output terminal of the inverter INV3. When Vos is low ("0"), the power supply LDO+ starts, and the switch S... s14 Switch S s17 closure;
[0032] like Figure 2 As shown, the reference potential V F0- Reference potential V F1- Reference potential V F2- and reference potential V F3- The voltage increases sequentially but remains less than the initial reference voltage V. ref The reference potential V F3+ Reference potential V F2+ Reference potential V F1+ and reference potential V F0+ The voltage decreases sequentially and is greater than the initial reference voltage V. ref Specifically, the reference potential V F1- =2V F0- Reference potential V F2- =4V F0- Reference potential V F3- =8V F0- Reference potential V F1+ =2V F0+ Reference potential V F2+ =4V F0+ Reference potential V F3+ =8V F0+ .
[0033] like Figure 2 and Figure 3 As shown, before performing analog-to-digital signal conversion, the non-inverting and inverting input terminals of error amplifier A are initialized, such that capacitor C... S The capacitor C at the non-inverting input terminal of error amplifier A C The upper plates are all at the initial reference voltage V ref ;
[0034] If the result of the RRAM array operation makes the source line SL i The voltage on is less than the initial reference voltage V ref Then switch S i After opening, capacitor C S via source line SL i Discharge causes capacitor CS The amount of charge stored in the capacitor decreases, causing the capacitor C to... S The potential of the upper plate drops to less than the initial reference potential V. ref ,Right now:
[0035] V cs =V ref -ΔV<V ref
[0036] Where ΔV is the capacitance C S via source line SL i The amount of charge lost during discharge is related to the capacitance C. S The ratio of capacitance values; capacitor C C The upper plate potential remains at the initial reference potential V. ref Therefore, at this time, the differential input of error amplifier A is misaligned, and the potential at the non-inverting input is higher than that at the inverting input. Therefore, the output level V of the error amplifier is... F High level "1"; waiting potential V F After stabilization, close switch S. s0- and S s19 Disconnect switch S s0 and S s18 (Switch S) s0- and S s19 Switch S is closed only when determining the sign bit; it is closed when determining the amplitude bit. s0 and S s18 Disconnect switch S s0- and S s19 Then the potential V F After being inverted by inverter INV2, it becomes a low level "0" (Vos). - The signal is then inverted by inverter INV3 to a high level "1" (Vos), and output through buffer BU. The first bit of the analog-to-digital converter is the sign bit, represented by a high level "1", indicating that the data quantized by the analog-to-digital converter is a negative number. Since Vos is a high level "1", the LDO- power supply is activated, the LDO+ power supply is not activated, and switch S... s6 ~S s9 Turn on, switch S s14 ~S s17 Disconnect, awaiting reference potential V F0- After stabilization, close switch S. s1 Due to the reference potential V F0- Reference potential V F1- Reference potential V F2- and reference potential V F3- The potentials are all less than the initial reference voltage V. ref At this time, capacitor C C Through switch S s1The potential path where it is located discharges, causing the potential of its upper plate to decrease, until the capacitor C... C After the upper plate potential stabilizes, read the potential V. F At this time, V F The amplitude value is the highest bit, if capacitor C C The upper plate potential is higher than that of capacitor C. S If the upper plate potential is V, then F If the capacitor C is at a high level "1", then... C The upper plate potential is lower than that of capacitor C. S If the upper plate potential is V, then F When the voltage level is low ("0"), switch S is closed. s0 and S s18 Since V OS The voltage level is high "1", therefore switch S s5 Closed, S s5- Disconnect, V F After being inverted by inverters INV0 and INV1, the original potential is maintained, and the voltage is then passed through switch S. s5 and S s18 Transmit to buffer BU output; disconnect switch S s1 Close switch S s2 Due to capacitor C C The upper plate potential is different from the reference potential V. F1- Small, power supply LDO - via switch S s2 The potential path is related to capacitor C C Charging, waiting for capacitor C C After the upper plate potential stabilizes, the potential V is then read. F V at this time F The amplitude value is the second highest bit, if capacitor C C The upper plate potential is higher than that of capacitor C. S If the upper plate potential is V, then F If the capacitor C is at a high level "1", then... C The upper plate potential is lower than that of capacitor C. S If the upper plate potential is V, then F The voltage level is low ("0"), then switch S is closed. s0 and S s18 Since V OS The voltage level is high ("1"), so switch S... s5 Closed, S s5- Disconnect, V F After being inverted by inverters INV0 and INV1, the original potential is maintained, and the voltage is then passed through switch S. s5 and S s18 Transmit to buffer BU output; disconnect switch S s2 Close switch S s3 Due to capacitor C CThe upper plate potential is different from the reference potential V. F2 -Small, power supply LDO-via switch S s3 The potential path located on capacitor C C Charging, waiting for capacitor C C After the upper plate potential stabilizes, the potential V is then read. F V at this time F The amplitude value is the second lowest bit, if capacitor C C The upper plate potential is higher than that of capacitor C. S If the upper plate potential is V, then F If the capacitor C is at a high level "1", then... C The upper plate potential is lower than that of capacitor C. S If the upper plate potential is V, then F When the voltage level is low ("0"), switch S is closed. s0 and S s18 Because of V OS The voltage level is high "1", therefore switch S s5 Closed, S s5- Disconnect, V F After being inverted by inverters INV0 and INV1, the original potential is maintained, and the voltage is then passed through switch S. s5 and S s18 Transmit to buffer BU output; disconnect switch S s3 Close switch S s4 Due to capacitor C C The upper plate potential is different from the reference potential V. F3- Small, power supply LDO - via switch S s4 The potential path is related to capacitor C C Charging, waiting for capacitor C C After the upper plate potential stabilizes, the potential V is then read. F V at this time F The amplitude value is the least significant bit, if capacitor C C The upper plate potential is higher than that of capacitor C. S If the upper plate potential is V, then F If the capacitor C is at a high level "1", then... C The upper plate potential is lower than that of capacitor C. S If the upper plate potential is V, then F The voltage level is low ("0"), then switch S is closed. s0 and S s18 Because of V OS The voltage level is high ("1"), so switch S... s5 Closed, S s5- Disconnect, V F After being inverted by inverters INV0 and INV1, the original potential is maintained, and the voltage is then passed through switch S. s5 and S s18Transmitted to the output of buffer BU.
[0037] If the result of the RRAM array operation makes the source line SL i The voltage on is greater than the initial reference voltage V. ref Then switch S i After opening, capacitor C S via source line SL i Charging causes capacitor C to... S The amount of charge stored in it increases, causing the capacitor C to... S The potential of the upper plate rises to a level greater than the initial reference potential V. ref ,Right now:
[0038] V cs =V ref +ΔV>V ref
[0039] Where ΔV is the capacitance C S From source line SL i The sampled charge quantity and capacitance C S The ratio of capacitance values; while the capacitance C C The upper plate potential remains at the initial reference potential V. ref At this time, the differential input of error amplifier A is misaligned, and the potential at the non-inverting input is lower than that at the inverting input. Therefore, the output level V of error amplifier A is... F The voltage level is low "0", and the potential V is waiting to be reached. F After stabilization, close switch S. s0_ and S s19 Disconnect switch S s0 and S s18 (Switch S) s0_ and S s19 Switch S is closed only when determining the sign bit; it is closed when determining the amplitude bit. s0 and S s18 Disconnect switch S s0_ and S s19 Then the potential V F After being inverted by inverter INV2, it becomes a high level "1" (V). OS_ Then, after being inverted by inverter INV3, it becomes a low level "0" (V). OS The output is through the buffer BU; the first bit of the analog-to-digital converter is the sign bit, represented by a low level "0", indicating that the data quantized by the analog-to-digital converter is a positive number; due to V OS The voltage level is low ("0"), so the LDO+ power supply is activated, the LDO- power supply is deactivated, and switch S... s14 ~S s17 Turn on, switch S s6 ~S s9 Disconnect, awaiting reference potential VF0+ After stabilization, close switch S. s10 Due to the reference potential V F0+ Reference potential V F1+ Reference potential V F2+ and reference potential V F3+ The potentials of all are greater than the initial reference voltage V. ref At this time, capacitor C C Just by using switch S s10 The potential path where it is located is charged, causing the potential of its upper plate to rise, until the capacitor C C After the upper plate potential stabilizes, read the potential V. F V at this time F The amplitude value is the highest bit, if capacitor C C The upper plate potential is higher than that of capacitor C. S If the upper plate potential is V, then F If the capacitor C is at a high level "1", then... C The upper plate potential is lower than that of capacitor C. S If the upper plate potential is V, then F When the voltage level is low ("0"), switch S is closed. s0 and S s18 Because of V OS_ The voltage level is high ("1"), so switch S... s5_ Closed, S s5 Disconnect, V F After being inverted by inverter INV0, and then passed through switch S... s5_ and S s18 Transmit to buffer BU output; disconnect switch S s10 Close switch S s11 Due to capacitor C C The upper plate potential is different from the reference potential V. F1+ Large, power supply LDO+ via switch S s11 The potential path located on capacitor C C Discharge, waiting for capacitor C C After the upper plate potential stabilizes, the potential V is then read. F V at this time F The amplitude value is the second highest bit, if capacitor C C The upper plate potential is higher than that of capacitor C. S If the upper plate potential is V, then F If the capacitor C is at a high level "1", then... C The upper plate potential is lower than that of capacitor C. S If the upper plate potential is V, then F The voltage level is low ("0"), then switch S is closed. s0 and S s18 Because of V OS_ When the voltage level is high ("1"), switch Ss5_ Open, S s5 Off, V F After being inverted by inverter INV0, and then passed through switch S... s5_ and S s18 The data is transmitted to the output of buffer BU; then switch S is turned off. s11 Close switch S s12 At this time, due to capacitor C C The upper plate potential is different from the reference potential V. F2+ Large, so the power supply LDO+ is connected to switch S s12 The potential path located on capacitor C C Discharge, waiting for capacitor C C After the upper plate potential stabilizes, the potential V is then read. F At this time, V F The amplitude value is the second lowest bit, if capacitor C C The upper plate potential is higher than that of capacitor C. S If the upper plate potential is V, then F If the capacitor C is at a high level "1", then... C The upper plate potential is lower than that of capacitor C. S If the upper plate potential is V, then F The voltage level is low ("0"), then switch S is closed. s0 and switch S s18 Since V OS_ When the voltage level is high ("1"), switch S s5_ Closed, S s5 Disconnect, V F After being inverted by inverter INV0, and then passed through switch S... s5_ and switch S s18 Transmit to buffer BU output; disconnect switch S s12 Close switch S s13 Due to capacitor C C The upper plate potential is different from the reference potential V. F3+ Large, power supply LDO+ via switch S s13 The potential path located on capacitor C C Discharge, waiting for capacitor C C After the upper plate potential stabilizes, the potential V is then read. F V at this time F If the amplitude value is the least significant bit, and the capacitor C C The upper plate potential is higher than that of capacitor C. S If the upper plate potential is V, then F If the capacitor C is at a high level "1", then... C The upper plate potential is lower than that of capacitor C. S If the upper plate potential is V, then F The voltage level is low ("0"), then switch S is closed.s0 and S s18 Since V OS_ The voltage level is high ("1"), so switch S... s5_ Closed, S s5 Disconnect, V F After being inverted by inverter INV0, and then passed through switch S... s5_ and S s18 Transmitted to the output of buffer BU.
[0040] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. An analog-to-digital converter for a voltage-mode RRAM computing-in-memory circuit, characterized in that comprises a source line SL i , a sampling module, an error amplifier A, a first quantization circuit, a second quantization circuit, a buffer BU, a power supply LDO- and a power supply LDO+; The source line SL i Connected with the sampling module, the sampling module is used for potential sampling of the source line SL i ; The inverting input terminal of the error amplifier A is connected to the sampling module, and a capacitor C is connected to the non-inverting input terminal C , and the lower plate of the capacitor C C is grounded; the non-inverting input terminal and the inverting input terminal of the error amplifier A have an initial reference voltage V ref ; The output signal of the error amplifier A is V F , the output terminal of the error amplifier A is respectively connected to the first quantization circuit and the second quantization circuit; the output terminals of the first quantization circuit and the second quantization circuit are respectively connected to the buffer BU; The capacitor C C has its upper plate connected to the output terminals of the power supplies LDO- and LDO+; the power supplies LDO- and LDO+ are used to provide reference potentials with various different amplitudes; The power supply LDO- has a start-up terminal PD-, and the start-up terminal PD- is connected to the output terminal of the second quantization circuit; the power supply LDO+ has a start-up terminal PD+, and the start-up terminal PD+ is connected to the output terminal of the second quantization circuit; the second quantization circuit is used to control the start and stop of the power supply LDO- and the power supply LDO+.
2. The analog-to-digital converter for a voltage-mode RRAM arithmetic circuit according to claim 1, wherein The sampling module includes a capacitor C S and a switch S i ; One end of the switch S i is connected to the source line SL i ; The other end of the switch S i is connected to the upper plate of the capacitor C S and the inverting input terminal of the error amplifier A. The lower plate of the capacitor C S is grounded.
3. The analog-to-digital converter for a voltage-mode RRAM arithmetic circuit according to claim 1, wherein The second quantization circuit includes a switch S s0- , a switch S s19 , an inverter INV2 and an inverter INV3; one end of the switch S s0- is connected to the output end of the error amplifier A, and the other end of the switch S s0- is connected to the input end of the inverter INV2; the output end of the inverter INV2 is connected to the input end of the inverter INV3, and the output signal of the inverter INV2 is Vos - ; the output end of the inverter INV3 is connected to one end of the switch S s19 , and the other end of the switch S s19 is connected to the input end of the buffer BU; the output signal of the buffer BU is V0; the output signal of the inverter INV3 is Vos.
4. The analog-to-digital converter for a voltage-mode RRAM computing-in-memory circuit according to claim 3, wherein The first quantization circuit includes switches S s0 , switch S s5- , switch S s5 , switch S s18 , inverter INV0 and inverter INV1; One end of the switch S s0 is connected to the output end of the error amplifier A, and the other end of the switch S s0 is connected to the input end of the inverter INV0; The output end of the inverter INV0 is connected to one end of the switch S s5- and the input end of the inverter INV1; The output end of the inverter INV1 is connected to one end of the switch S s5 ; The other ends of the switch S s5- and the other end of the switch S s5 are both connected to one end of the switch S s18 , and the other end of the switch S s18 is connected to the input end of the buffer BU, and the switch S s18 closes or opens simultaneously with the switch S s0 ; When Vos - is at the high level "1", the switch S s5- closes and the switch S s5 opens; When Vos is at the high level "1", the switch S s5 closes and the switch S s5- opens.
5. The analog-to-digital converter for a voltage-mode RRAM computing-in-memory circuit according to claim 3, wherein The power supply LDO includes a reference potential V F0- , a reference potential V F1- , a reference potential V F2- , a reference potential V F3- , a first potential path, a second potential path, a third potential path, and a fourth potential path; the first potential path includes switches S s1 and S s6 ; one end of the switch S s1 is connected to the upper plate of the capacitor C C , the other end of the switch S s1 is connected to one end of the switch S s6 , and the other end of the switch S s6 is connected to the reference potential V F0- ; the second potential path includes switches S s2 and S s7 ; one end of the switch S s2 is connected to the upper plate of the capacitor C C , the other end of the switch S s2 is connected to one end of the switch S s7 , and the other end of the switch S s7 is connected to the reference potential V F1- ; the third potential path includes switches S s3 and S s8 ; one end of the switch S s3 is connected to the upper plate of the capacitor C C , the other end of the switch S s3 is connected to one end of the switch S s8 , and the other end of the switch S s8 is connected to the reference potential V F2- ; the fourth potential path includes switches S s4 and S s9 ; one end of the switch S s4 is connected to the upper plate of the capacitor C C , the other end of the switch S s4 is connected to one end of the switch S s9 , and the other end of the switch S s9 is connected to the reference potential V F3- ; when Vos is at the high level "1", the power supply LDO starts, and the switches S s6 to S s9 close.
6. The analog-to-digital converter for a voltage-mode RRAM computing-in-memory circuit according to claim 5, wherein The power supply LDO+ includes a reference potential V F0+ , a reference potential V F1+ , a reference potential V F2+ , a reference potential V F3+ , a fifth potential path, a sixth potential path, a seventh potential path, and an eighth potential path; The fifth potential path includes switch S s10 and switch S s14 ; One end of the switch S s10 is connected to the upper plate of the capacitor C C , the other end of the switch S s10 is connected to one end of the switch S s14 , and the other end of the switch S s14 is connected to the reference potential V F0+ ; The sixth potential path includes switch S s11 and switch S s15 ; One end of the switch S s11 is connected to the upper plate of the capacitor C C , the other end of the switch S s11 is connected to one end of the switch S s15 , and the other end of the switch S s15 is connected to the reference potential V F1+ ; The seventh potential path includes switch S s12 and switch S s16 ; One end of the switch S s12 is connected to the upper plate of the capacitor C C , the other end of the switch S s12 is connected to one end of the switch S s16 , and the other end of the switch S s16 is connected to the reference potential V F2+ ; The eighth potential path includes switch S s13 and switch S s17 ; One end of the switch S s13 is connected to the upper plate of the capacitor C C , the other end of the switch S s13 is connected to one end of the switch S s17 , and the other end of the switch S s17 is connected to the reference potential V F3+ ; When Vos is at a low level of "0", the power supply LDO+ starts, and the switches S s14 ~S s17 close. 7. The analog-to-digital converter for a voltage-mode RRAM computing-in-memory circuit according to claim 6, wherein The reference potential V F0- , the reference potential V F1- , the reference potential V F2- and the reference potential V F3- increase in sequence and are less than the initialization reference voltage V ref ; the reference potential V F3+ , the reference potential V F2+ , the reference potential V F1+ and the reference potential V F0+ decrease in sequence and are greater than the initialization reference voltage V ref .