Power-on reset circuit, system reset method and electronic equipment

Abstract

The invention relates to the technical field of integrated circuits, and discloses a power-on reset circuit, which comprises a starting circuit, a reference current circuit, a current comparison circuit and a reset signal generation circuit, and is characterized in that the starting circuit is configured to provide starting current for a control node at the initial stage of power supply voltage power-on so as to force the reference current circuit to be separated from a zero current state; the reference current circuit is configured to generate a reference current with a temperature compensation characteristic after being separated from a zero current state; the current comparison circuit is configured to generate a detection current and generate an overturning signal at a comparison node by comparing the reference current and the detection current; the reset signal generation circuit is configured to generate a system reset signal having a determined pulse width in response to the flipping signal. The release point of the system reset signal is determined by the magnitude relation of the two currents, so that the reset action threshold value is kept stable at different temperatures, and the reliability of the power-on reset circuit is improved. The invention further discloses a system reset method and electronic equipment.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, such as a power-on reset circuit, a system reset method, and an electronic device. Background Technology

[0002] Digital systems and mixed-signal systems integrate numerous critical functional units such as status registers, control registers, and counters. If these units are in a random and uncertain electrical state at the initial power-on, it can easily lead to unexpected system behavior or functional malfunctions, and even permanent hardware damage. To ensure that the system reliably and controllably enters a preset stable operating state from the moment power is applied, a power-on reset (POR) circuit must be introduced. This circuit generates and maintains a valid reset signal before the power supply voltage reaches a safe and stable operating level, thereby initializing the system. Currently, in the field of integrated circuit technology, widely used POR circuits generally employ a simple structure based on the RC time constant. They utilize resistors to charge capacitors and determine whether to release the reset state by monitoring whether the capacitor voltage reaches the toggling threshold of subsequent logic gates (such as inverters or Schmitt triggers).

[0003] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art: In existing POR circuits, the reset threshold depends entirely on the switching voltage of the logic gate. The switching voltage threshold is greatly affected by temperature, resulting in significant differences in the reset point at different temperatures, leading to low reliability of the POR circuit.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0006] This disclosure provides a power-on reset circuit, a system reset method, and an electronic device to improve the reliability of the power-on reset circuit.

[0007] In some embodiments, the power-on reset circuit includes a startup circuit, a reference current circuit, a current comparison circuit, and a reset signal generation circuit, wherein: the input terminal of the startup circuit is connected to the power supply voltage, and the output terminal is connected to the control node of the reference current circuit, and is configured to provide a startup current to the control node in the initial stage of power-on to force the reference current circuit to leave the zero-current state; the input terminal of the reference current circuit is connected to the power supply voltage, and is configured to generate a reference current with temperature compensation characteristics after leaving the zero-current state; the current comparison circuit is connected to the power supply voltage and the reference current circuit, and is configured to generate a detection current, and generate a flip signal at the comparison node by comparing the magnitude of the reference current and the detection current; the input terminal of the reset signal generation circuit is connected to the comparison node of the current comparison circuit, and is configured to generate a system reset signal with a defined pulse width in response to the flip signal.

[0008] Optionally, the reference current circuit includes: a Wilson current mirror, comprising a PMOS current mirror and an NMOS current mirror connected in series, configured to generate a reference current; and a temperature compensation resistor, connected in series in the current path of the Wilson current mirror, configured to provide temperature compensation for the reference current.

[0009] Optionally, the reference current circuit further includes: a trimming switch, connected in parallel with the temperature compensation resistor, configured to adjust the current flowing through the temperature compensation circuit by changing the on state of the trimming switch, so as to trim the magnitude of the reference current.

[0010] Optionally, the current comparison circuit includes: a detection branch connected to the power supply voltage, wherein the current in the detection branch changes with the power supply voltage; and a load branch connected to the reference current circuit, wherein the current in the load branch is mirrored from the reference current; wherein the current comparison circuit is configured to generate a flip signal at the comparison node by comparing the magnitude of the current in the detection branch with the magnitude of the current in the load branch.

[0011] Optionally, the current comparison circuit further includes a hysteresis branch, with its input connected to the comparison node and its output connected to the load branch, configured to adjust the current drive capability of the load branch after the level of the comparison node flips, so that the power supply voltage threshold required for the current in the detection branch and the current in the load branch to reach a new balance changes.

[0012] Optionally, the hysteresis branch includes a first transistor and a second transistor, wherein: the gate of the first transistor is connected to the comparator node, and the source is grounded; the drain of the second transistor is connected to the current input terminal of the load branch, the gate receives a fixed bias voltage, and the source is connected to the drain of the first transistor; wherein, after the level of the comparator node flips, the first transistor turns on and pulls the source potential of the second transistor low to adjust the current driving capability of the load branch.

[0013] Optionally, the current comparison circuit further includes a coupling capacitor, with one end connected to the power supply voltage and the other end connected to the critical bias node of the reference current circuit, configured to couple a fast positive transient of the power supply voltage to the critical bias node to instantaneously change the current balance between the detection branch and the load branch, triggering a flip signal.

[0014] Optionally, the reset signal generation circuit includes: a POR pulse width adjustment circuit, with its input connected to a comparator node, configured to delay the edge of the flip signal to generate an intermediate signal with a defined width; and a Schmitt trigger, with its input connected to the output of the POR pulse width adjustment circuit, configured to hysteresis-shape the intermediate signal and output a system reset signal with a steep edge.

[0015] In some embodiments, the system reset method based on the power-on reset circuit includes: at the initial stage of power-on, providing a starting current to the reference current circuit through a startup circuit to cause the reference current circuit to leave the zero-current state; after the reference current circuit leaves the zero-current state, generating a reference current with temperature compensation characteristics using the reference current circuit, and generating a detection current that varies with the power supply voltage using a current comparison circuit; generating a flip signal at the comparison node by comparing the magnitudes of the reference current and the detection current; and generating a system reset signal with a defined pulse width in response to the flip signal.

[0016] In some embodiments, the electronic device includes: an electronic device body, including a power module and a functional circuit module; and the aforementioned power-on reset circuit, connected to the power module and the functional circuit module.

[0017] The power-on reset circuit, system reset method, and electronic device provided in this disclosure can achieve the following technical effects: In this disclosed technical solution, the power-on reset circuit includes a startup circuit, a reference current circuit, a current comparison circuit, and a reset signal generation circuit. During the initial power-on phase, the startup circuit provides a startup current to the control node to force the reference current circuit out of the zero-current state. After leaving the zero-current state, the reference current circuit generates a reference current with temperature compensation characteristics. The current comparison circuit generates a detection current and, by comparing the magnitudes of the reference current and the detection current, generates a flip-flop signal at the comparison node. The reset signal generation circuit responds to the flip-flop signal to generate a system reset signal with a defined pulse width. Thus, a stable reference current insensitive to temperature changes is generated by the reference current circuit, while a detection current that increases with the power supply voltage is generated by the current comparison circuit. When the power supply voltage rises to a safe level, the detection current exceeds the reference current, triggering the flip-flop signal. Therefore, the release point of the system reset signal is determined by the relationship between the magnitudes of the two currents (rather than the temperature-sensitive logic gate threshold voltage). This ensures that the reset action threshold remains stable at different temperatures, avoiding false triggering or delays, improving the reliability of the power-on reset circuit, and ensuring the determinism and consistency of system power-on initialization.

[0018] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of a power-on reset circuit provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of another power-on reset circuit provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of another power-on reset circuit provided in an embodiment of this disclosure; Figure 4 This is a schematic flowchart of a system reset method based on a power-on reset circuit provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of a system reset device based on a power-on reset circuit provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0020] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0021] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0022] Unless otherwise stated, the term "multiple" means two or more. In embodiments of this disclosure, the character " / " indicates that the preceding and following objects are in an "OR" relationship. For example, A / B means: A or B. The term "and / or" describes an association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B. The term "correspondence" can refer to an association or binding relationship; A corresponding to B means that there is an association or binding relationship between A and B.

[0023] Combination Figure 1 As shown, this embodiment of the present disclosure provides a power-on reset circuit 100, including a startup circuit 110, a reference current circuit 120, a current comparison circuit 130, and a reset signal generation circuit 140. The startup circuit 110 has its input terminal connected to a power supply voltage and its output terminal connected to a control node of the reference current circuit 120. It is configured to provide a startup current to the control node during the initial power-on phase of the power supply voltage, thereby forcing the reference current circuit 120 out of the zero-current state. The reference current circuit 120 has its input terminal connected to the power supply voltage and is configured to generate a reference current with temperature compensation characteristics after leaving the zero-current state. The current comparison circuit 130 is connected to the power supply voltage and the reference current circuit 120 and is configured to generate a detection current. By comparing the magnitudes of the reference current and the detection current, a flip signal is generated at the comparison node. The reset signal generation circuit 140 has its input terminal connected to the comparison node of the current comparison circuit 130 and is configured to generate a system reset signal with a defined pulse width in response to the flip signal.

[0024] Optionally, combined Figure 3As shown, the startup circuit 110 includes transistors M1, M2, M3, and M4, wherein M1, M2, and M3 are connected in series, the gate terminals of M1 and M2 are connected to GND, the gate terminal of M3 is connected to NBIAS, the gate terminal of M4 is connected to the drain terminal of M3, and the drain terminal of M4 is connected to the gate terminal of M5. M1, M2, and M3 are NMOS transistors, and M4 is a PMOS transistor.

[0025] In practical applications, M1, M2, and M3 are connected in series between VDD and ground, forming a high-resistance voltage divider path. Initially, the NBIAS node voltage is 0, and the gate of M4 is pulled to an intermediate potential by this voltage divider network, thus turning on M4. When M4 is on, it pumps the charge from VDD into the core node of the reference current circuit 120 (connected to the gate of M5), giving this node an initial voltage disturbance and forcing the reference current circuit 120 out of its zero-current deadlock state. Once the reference current circuit 120 starts working, the NBIAS voltage is established, M3 turns off, and subsequently M4 also turns off. The startup circuit 110 completes its mission and automatically exits, no longer affecting the operation of the reference current circuit 120.

[0026] Optionally, combined Figure 2 As shown, the reference current circuit 120 includes: a Wilson current mirror 121, comprising a PMOS current mirror and an NMOS current mirror connected in series, configured to generate a reference current; and a temperature compensation resistor R, connected in series in the current path of the Wilson current mirror 121, configured to perform temperature compensation on the reference current.

[0027] In some possible implementations, combining Figure 3 As shown, the reference current circuit 120 includes a PMOS current mirror and an NMOS current mirror connected in series. Transistors M5 and M6 form the PMOS current mirror, and transistors M7 and M8 form the NMOS current mirror. M5 and M7 are connected in series, with their gate and drain terminals connected. M6 and M8 are connected in series, with their gate and drain terminals connected. M5 and M6 are PMOS transistors, and M7 and M8 are NMOS transistors. The temperature compensation resistor R includes resistors R1, R2, and R3 connected in series.

[0028] The Wilson current mirror 121 and the temperature compensation resistor R together form a Wilson current mirror self-biased structure, generating a reference current that is insensitive to changes in the power supply voltage and relatively stable in temperature due to the temperature compensation design. The PMOS current mirror is responsible for mirroring and transferring current, while the NMOS current mirror and the PMOS mirror together form a closed negative feedback loop to stabilize the operating point. The temperature compensation resistors R1, R2, and R3 are connected in series with M7 and are crucial for current-to-voltage conversion. The positive temperature coefficient of the temperature compensation resistor R is used to offset the negative temperature coefficient of the transistor threshold voltage.

[0029] By employing a high-precision, high-output-impedance Wilson current mirror structure to generate and mirror the reference current, current stability and strong suppression of power supply voltage variations are ensured. Simultaneously, a designed temperature-compensated resistor network is connected in series in the current path of the current mirror. Utilizing the resistors themselves and the positive and negative temperature characteristics of the transistors, the reference current's variation with temperature can be effectively offset, resulting in a highly stable reference current across the entire temperature range. This stable reference current serves as a comparison benchmark, fundamentally ensuring that the judgment threshold of the current comparison circuit 130 does not drift with temperature. This makes the final system reset signal release point accurate and reliable, greatly improving the overall performance of the power-on reset circuit 100.

[0030] Optionally, combined Figure 2 As shown, the reference current circuit 120 further includes: a trimming switch S, connected in parallel with the temperature compensation resistor R, configured to adjust the current flowing through the temperature compensation circuit by changing the on state of the trimming switch S, so as to trim the magnitude of the reference current.

[0031] In some possible implementations, combining Figure 3 As shown, the trim switch S includes trim switches S1 and S2. S1 is connected in parallel with R2, and S2 is connected in parallel with R3. Trim switches S1 and S2 change the resistance value of the circuit (short-circuiting R2 or R3) by means of laser melting, thereby fine-tuning the reference current and calibrating the flip-voltage threshold error caused by manufacturing process deviation.

[0032] By connecting a programmable adjustment switch S in parallel across the temperature compensation resistor R, the effective resistance value of the temperature compensation network can be dynamically changed by selectively turning these switches on or off during chip testing or use, thereby finely adjusting the reference current flowing through the Wilson current mirror 121. This design effectively compensates for systematic errors in the absolute resistance value and transistor parameters caused by variations in semiconductor manufacturing processes. This allows the reference current value to be calibrated to a precise target value across multiple chip samples or under different operating conditions, significantly improving the consistency and repeatability of the critical threshold of the power-on reset circuit 100 across the entire temperature range, and enhancing product yield and reliability.

[0033] Optionally, combined Figure 2 As shown, the current comparison circuit 130 includes: a detection branch 131 connected to the power supply voltage, the detection branch current changing with the power supply voltage; and a load branch 132 connected to the reference current circuit 120, the load branch current mirroring the reference current; wherein, the current comparison circuit 130 is configured to generate a flip signal at the comparison node by comparing the magnitude of the detection branch current and the load branch current.

[0034] In some possible implementations, combining Figure 3As shown, the current comparison circuit 130 includes transistors M9, M10, M11, M12, M13, M14, M15, M16, and M17, coupling capacitor C1, and inverter INV1. M9, M11, M12, M13, M14, M16, and M17 are NMOS transistors, while M10 and M15 are PMOS transistors. M13 has its gate and drain connected, and the gate and drain terminals of M13 and M14 are connected to NBIAS. M11 and M9 are connected in parallel and their gates and drains are connected. M11 and M9 are connected in series with M14. M10 and M12 are connected in parallel and in series with M15 and M16. The gate terminals of M10 and M12 are connected to the drain terminal of M14 (A). The drain terminal of M15 is connected to the input of INV1 (B). The gate terminal of M17 is connected to the output of INV1 (C). The drain terminal of M17 is connected to the source terminal of M15. One end of C1 is connected to VCC, and the other end is connected to NBIAS.

[0035] The detection branch 131 includes transistors M9, M11, M13, and M14. The sources of M9 and M11 are connected to the power supply voltage VCC. The gates and drains of M9 and M11 are shorted together and connected to detection node A. Detection node A is connected to the drain of M14. The source of M14 is grounded, and its gate receives the critical bias voltage NBIAS from the reference current circuit 120. The drain and gate of M13 are shorted (diode connected) and connected to the NBIAS node, and its source is grounded.

[0036] The detection branch 131 forms a current path from VCC through M9 / M11, then through M14 to ground. The magnitude of the detection current is determined by the gate-source voltage Vgs of M9 / M11 (approximately equal to VCC - VA) and the conduction state of M14. M14 is controlled by NBIAS, acting as a controlled current valve. Therefore, the detection current ultimately changes sensitively with the power supply voltage VCC and is output to point A.

[0037] The load branch 132 includes transistors M10, M12, M15, M16, and M17; the sources of M10 and M12 are connected to the power supply voltage VCC, their gates are connected to the detection node A of the detection branch 131, and their drains are connected to the comparator node B; the source of M15 is connected to the power supply voltage VCC, its gate receives a fixed bias voltage from the reference current circuit 120, and its drain is connected to the comparator node B; the drain of M16 is connected to the source of M15 (i.e., the VCC side), its gate receives a fixed bias voltage, and its source is connected to the drain of M17; the source of M17 is grounded, and its gate is connected to the output terminal C of the inverter INV1.

[0038] When the current in the sensing branch is small (VCC is low), the voltage at point A is low, causing M10 / M12 to conduct and pull node B up to VCC (reset effective); when the current in the sensing branch increases to a level sufficient to exceed the pull-up capability of M10 / M12 and reaches a balance with the load branch current, the voltage at node B begins to flip.

[0039] The current comparison circuit 130 includes a current mirror that compares the reference current (mirrored by M15) with the detection current (flowing through M9) reflecting the power supply voltage, thereby controlling the switching voltage of the comparison node B. M9 is a critical detection transistor; the detection current flowing through M9 is strongly dependent on its source voltage (≈VDD) and gate voltage (VA). As VDD increases, its current increases. M10 and M15 form a PMOS current mirror. M10 is responsible for charging and pulling up point B when VDD is low, while M15 mirrors the reference current to discharge and pull down point B, thus determining the potential of point B. M11 and M12 are trimmable current mirror devices. By switching them on or off, the equivalent width-to-length ratio of the detection branch 131 or the load branch 132 can be adjusted, thereby fine-tuning the balance point of the current comparison. M13 provides a fast discharge path for the NBIAS node and acts as a voltage clamp during power-down. The gate of M14 is controlled by NBIAS and acts as a common-source amplifier, converting the voltage change of NBIAS into a change in the current at point A.

[0040] Optionally, combined Figure 2 As shown, the current comparison circuit 130 further includes a hysteresis branch 133, with its input connected to the comparison node and its output connected to the load branch 132. It is configured to adjust the current driving capability of the load branch 132 after the level of the comparison node flips, so that the power supply voltage threshold required for the detection branch current and the load branch current to reach a new balance changes.

[0041] In some possible implementations, combining Figure 3 As shown, the hysteresis branch 133 includes a first transistor M17 and a second transistor M16, wherein: the gate of the first transistor M17 is connected to the comparator node, and the source is grounded; the drain of the second transistor M16 is connected to the current input terminal of the load branch 132, the gate receives a fixed bias voltage, and the source is connected to the drain of the first transistor M17; wherein, after the level of the comparator node flips, the first transistor M17 turns on and pulls the source potential of the second transistor M16 low, so as to adjust the current driving capability of the load branch 132.

[0042] M17 is controlled by the output (point C) of inverter INV1. When the comparator node (point B) flips low and point C is high, M17 turns on. After M17 turns on, it pulls the source of M16 low, effectively enhancing the pull-down capability of M15. This means that during power-down, a lower VDD is required for the current of M9 to be less than the current of M15, thus creating a hysteresis window to prevent false triggering caused by power supply noise.

[0043] Optionally, combined Figure 3 As shown, the current comparison circuit 130 also includes a coupling capacitor C1, with its first end connected to the power supply voltage VDD and its second end connected to the critical bias node of the reference current circuit 120. It is configured to couple the fast positive transient of the power supply voltage to the critical bias node to instantaneously change the current balance state between the detection branch 131 and the load branch 132, triggering a flip signal.

[0044] In practical applications, under normal steady-state conditions, C1 is fully charged, and there is a DC voltage difference across its terminals, which does not affect the DC operating point. When VDD experiences a rapid positive step (upward jump), since the voltage across capacitor C1 cannot change abruptly, the instantaneous rise in VDD will almost entirely couple to the other end of C1, namely the critical bias node NBIAS, causing the NBIAS voltage to rise instantaneously. This instantaneous rise in NBIAS causes a sharp increase in the gate-source voltage Vgs of M14, resulting in a sudden increase in the current of M14. At this time, the pull-down capability of M14 at point A is much stronger than that of M9 (the Vgs of M9 changes relatively slowly), causing the voltage VA at point A to be rapidly pulled down. The drop in point A causes M10 to conduct, rapidly pulling up the potential at point B, thereby immediately generating a reset pulse and triggering the flip signal.

[0045] By adding a coupling capacitor between the power supply and the critical bias node of the reference current, a fast response path is constructed for rapid positive transients in the power supply (such as voltage spikes or rapid power-up): when VDD rises rapidly, the change is directly coupled to the critical bias node through capacitor C1, instantaneously altering the current balance between the detection branch 131 and the load branch 132 in the comparator circuit, thereby immediately triggering a flip-flop signal and generating a reset pulse. This effectively avoids state uncertainties or logic errors that may be caused by power supply voltage transients, enhances the circuit's monitoring capability for power supply noise and rapid power-up processes, and enables the system to obtain reliable and timely reset protection even in complex power supply environments, further improving overall robustness.

[0046] Optionally, combined Figure 2As shown, the reset signal generation circuit 140 includes: a POR pulse width adjustment circuit 141, whose input is connected to a comparator node and is configured to delay the edge of the flip signal to generate an intermediate signal with a defined width; and a Schmitt trigger 142, whose input is connected to the output of the POR pulse width adjustment circuit 141 and is configured to hysteresis-shape the intermediate signal and output a system reset signal with a steep edge.

[0047] In some possible implementations, combining Figure 3 As shown, the POR pulse width adjustment circuit 141 includes transistors M18, M19, M20, M21, M22, M23, and M24, an inverter INV2, and a capacitor C2. M18, M20, M21, M22, M23, and M24 are PMOS transistors, and M19 is an NMOS transistor. M18, M19, and M20 are connected in series, as are M21, M22, and M23. The gate terminals of M18 and M20 are connected to capacitor C, the gate terminal of M19 is connected to capacitor D, and the gate terminals of M21, M22, and M23 are connected to node D. The input terminal of INV2 is connected to capacitor C, and its output terminal is connected to capacitor E. The gate terminal of M24 is connected to capacitor E, its drain terminal is connected to capacitor F, and it is connected to the input terminal of Schmitt trigger 142. One end of capacitor C2 is connected to capacitor F, and the other end is connected to GND.

[0048] M18, M20, M21, M22, and M23 are inverting ratio transistors, designed to be long and narrow with extremely high on-resistance. When a reset pulse is needed (point C goes high, point D goes low), these three transistors connected in series form a slow charge pump, charging capacitor C2 with a very small current, causing the voltage at point F to rise slowly. C2 and the inverting ratio transistors together determine the RC charging time constant, directly controlling the width of the reset pulse. In the non-reset state (point D is high), M19 clamps the voltage at the intermediate node D to a level close to VDD-Vth, ensuring that transistors such as M18 are completely turned off. M24 acts as a fast discharge switch; when an immediate reset signal is needed (point E goes low), M24 turns on instantaneously, quickly pulling the voltage at point F down to VDD, triggering the Schmitt trigger 142. The Schmitt trigger 142 shapes the slowly rising / falling voltage at point F and outputs a clean, steep digital level POR signal. The Schmitt trigger 142 itself also has hysteresis characteristics, which can further suppress residual noise at point F.

[0049] In practical applications, when a reset signal is required, the preceding stage sets node C to a high level; after being inverted by INV2, node E is set to a low level, turning on M24 and quickly pulling the output node F up to VCC (high level). This high level, after passing through Schmitt trigger 142, generates a valid reset signal; C being high turns off M18 and M20. When the reset is required, the front-end determines that the power supply voltage is within the acceptable range, and node C flips to a low level. After inversion by INV2, point E becomes high, causing M24 to turn off and disconnecting the fast pull-up path from VCC to point F. M18 and M20 turn on. Since point D is low at this time, M19 also turns on, thus forming a strong pull-up path from VCC through M18-M19-M20 to point D, quickly charging point D to a high level (approximately VCC - Vth). After point D goes high, M21, M22, and M23 turn on. Since these three PMOS transistors are designed as inverting ratio transistors, they form a high-resistance charging path, starting to charge capacitor C2 with a very small current, causing the voltage at point F to slowly decrease from VCC. The rate at which the voltage at point F slowly decreases (i.e., the delay time) is determined by the product of the equivalent resistance of the high-impedance path (M21-M23) and capacitor C2 (RC time constant). By precisely designing the dimensions of these three transistors and the value of C2, a reset pulse of a certain width can be obtained. When the voltage at point F drops to the low-level threshold of Schmitt trigger 142, the final POR reset signal flips, and the system reset is released. If the power supply becomes abnormal again during this period (such as a rapid drop), point C in the preceding stage will quickly flip back to a high level; the high C level will immediately cut off M18 / M20, and through INV2, make point E low, turning on M24 again, thereby instantly pulling point F back up to VCC, immediately generating a reset signal, ensuring the circuit's rapid response capability to power supply transient abnormalities.

[0050] By precisely delaying the toggle signal using a specific POR pulse width adjustment circuit 141, an intermediate signal with a defined and sufficiently wide width is generated, ensuring that the reset pulse reliably covers the initialization time required by each unit in the system. Subsequently, the intermediate signal is shaped using the hysteresis characteristic of the Schmitt trigger 142, effectively suppressing glitches that may be introduced by power supply noise or residual jitter of the comparator node, and generating a system reset signal with steep edges and clean levels. The combination of these two stages of processing not only ensures the stability and consistency of the reset signal duration but also enhances its anti-interference capability and the reliability of driving subsequent logic, thereby comprehensively improving the success rate and robustness of system power-on initialization.

[0051] The power-on reset circuit provided in this embodiment includes a startup circuit, a reference current circuit, a current comparison circuit, and a reset signal generation circuit. During the initial power-on phase, the startup circuit provides a startup current to the control node to force the reference current circuit out of the zero-current state. After leaving the zero-current state, the reference current circuit generates a reference current with temperature compensation characteristics. The current comparison circuit generates a detection current and, by comparing the magnitudes of the reference current and the detection current, generates a flip-flop signal at the comparison node. The reset signal generation circuit responds to the flip-flop signal to generate a system reset signal with a defined pulse width. Thus, a stable reference current insensitive to temperature changes is generated by the reference current circuit, while a detection current that increases with the power supply voltage is generated by the current comparison circuit. When the power supply voltage rises to a safe level, the detection current exceeds the reference current, triggering the flip-flop signal. Therefore, the release point of the reset signal is determined by the relationship between the magnitudes of the two currents (rather than the temperature-sensitive logic gate threshold voltage). This ensures that the reset action threshold remains stable at different temperatures, avoiding false triggering or delays, improving the reliability of the power-on reset circuit, and ensuring the determinism and consistency of system power-on initialization.

[0052] The following combination Figure 3 This further explains the working principle of the power-on reset circuit under slow power-on / off, rapid power-on / off, and rapid voltage jump states: When the power supply voltage is slowly increasing or decreasing: When the system begins to power on slowly, the power supply voltage VDD gradually increases but has not yet reached the normal operating voltage of the reference current circuit (approximately the sum of the transistor threshold voltage and overdrive voltage). At this time, the startup circuit composed of transistors M1, M2, M3, and M4 will cause the reference current circuit to break away from its initial zero steady state, causing the node NBIAS voltage to rise and putting transistor M14 into a subthreshold conducting state. By designing the size of transistor M9, the potential at point A can be maintained at a low level close to 0, thereby turning on transistor M10 and charging node B to the VDD level. Simultaneously, the potential at point F remains low, keeping the output signal of the Schmitt trigger high.

[0053] As the power supply voltage VDD continues to rise, the reference current generated by the reference current circuit... It will remain essentially unchanged, and its value will be approximately:

[0054] in, Indicates the carrier mobility of an NMOS transistor. This represents the capacitance per unit area of ​​the gate oxide layer. R represents the width-to-length ratio of transistor M8, R represents the resistance from the source terminal of transistor M7 to ground, and K represents the ratio of the width-to-length ratio of transistors M7 and M8.

[0055] As the power-up process continues, the potential at point NBIAS will remain essentially constant. However, the potential at point A, due to its relationship with the diode-connected transistor M9, will gradually increase as VDD rises. When the potential at point A rises to a certain level, causing the potential at point B to reach half of VDD, this power supply voltage is considered the threshold voltage of the POR circuit. The reference current flowing through node NBIAS Satisfy the following formula:

[0056]

[0057] According to the aforementioned formula, we can obtain: The approximate calculation formula is:

[0058] in, Indicates the carrier mobility of an NMOS transistor. express The equivalent width-to-length ratio of the NMOS transistor through which the current flows. express The equivalent width-to-length ratio of the PMOS transistor through which the current flows. This represents the threshold voltage of an NMOS transistor. This represents the threshold voltage of the PMOS transistor.

[0059] According to the above formula, the threshold voltage of the POR circuit is... Temperature stability depends primarily on two key factors: reference current. and the threshold voltage of MOS transistors .in, From the reference current Obtained by mirroring, and using the reference current. A positive temperature coefficient can be achieved by using an NPOLY resistor. Therefore, by properly designing the resistor value and the size of the MOS transistor, a transistor that is insensitive to temperature can be obtained. .

[0060] As the power supply voltage continues to rise, the potential at point B will change from high to low, and the potential at point F will change from low to high. This causes the output signal of the Schmitt trigger to flip, and the circuit begins to operate normally.

[0061] To further enhance the circuit's anti-interference capability, a hysteresis circuit is introduced. Transistors M16 and M17 form a hysteresis circuit; when the potential at point C becomes high, M17 will conduct, causing... The equivalent width-to-length ratio in the approximate calculation formula This will increase. This change will lead to an increase in the POR threshold voltage. Drop to a lower low voltage reset voltage This significantly improves the circuit's resistance to power supply noise.

[0062] When the power supply voltage VDD begins to slowly decrease and is less than When node B and E become high, transistor M24 pulls down the potential of point F, and the Schmitt trigger generates a high-level reset signal.

[0063] because The threshold voltage of the transistor in the approximate calculation formula varies greatly with the manufacturing process. Therefore, switches S1 and S2, and transistors M11 and M12 are added. Adjustments are needed. When the switch is closed or transistor M12 is connected to the circuit, Increase; when the switch is off or transistor M11 is connected to the circuit, It gets smaller.

[0064] Under conditions of rapid power-on and power-off: Assume the power supply voltage VCC rises from 0V to VCC within 1µs. While the potential at point B initially follows the change in VCC, it quickly drops to a low level as the reference current circuit stabilizes. Simultaneously, the potentials at points D and E will also remain low. However, due to the influence of transistor M19 connected in diode form, the potential at point D will approximately remain around the threshold voltage of the MOSFET. Next, inverting transistors M21, M22, and M23 charge capacitor C2, causing the voltage at node F to rise slowly. When the voltage at point F rises to the threshold voltage of the Schmitt trigger, the POR signal flips, and the circuit enters normal operation. By adjusting the values ​​of transistors M21, M22, and M23 and capacitor C2 in the POR pulse width adjustment circuit, the width of the reset signal is controlled, allowing the circuit to respond correctly to the reset signal.

[0065] Assume the power supply voltage VCC drops from VCC to 0V within 1µs. Due to the presence of capacitor C1, the node voltage at point NBIAS follows VCC's drop, while transistor M13, connected as a diode, clamps the node voltage to approximately one MOSFET threshold voltage lower than ground. The potential at point A discharges through transistor M9 to approximately one threshold voltage higher than VCC, while the potential at point B remains unchanged. At this point, the POR circuit does not generate a reset signal. Once the power supply voltage stabilizes, node NBIAS is charged by transistor M6. When the NBIAS potential turns on transistor M14, the potential at point A decreases, and the potential at point B increases. At this time, the potential at point F is quickly pulled down to ground by transistor M24, and the Schmitt trigger generates a high-level reset signal POR.

[0066] Under conditions of rapid power supply voltage increase: Assume the initial voltage of the power supply is V1, and V1 is greater than... When the power supply voltage rises from V1 to V2 within 10ns, the NBIAS voltage will rise along with VDD due to the presence of capacitor C1. Therefore, the voltage VA at node A will remain approximately constant due to the path formed by transistors M9 and M14 (the currents of both M9 and M14 increase). As the power supply voltage VDD rises, the current of transistor M10 will be greater than the current of M15, causing the potentials of nodes B, D, and E to rise. Simultaneously, the voltage at point F is quickly pulled down to ground by transistor M24, triggering a Schmitt trigger to generate a high-level reset signal POR.

[0067] Once the circuit stabilizes, the voltage at point NBIAS drops, causing the voltage at point A to rise. The voltages at nodes B, D, and E drop to low levels again, charging capacitor C2 through inverting transistors M21-M23. When the voltage at point F rises to the threshold voltage of the Schmitt trigger, the POR signal flips, and the circuit enters its normal operating phase.

[0068] Combination Figure 3 It can be known that:

[0069] Based on the aforementioned formula, the approximate calculation formula for V2 can be obtained as follows:

[0070] Among them, V A This represents the voltage at node A when the power supply voltage is V1.

[0071] Combination Figure 3 The power-on reset circuit structure shown is reasonably designed and integrated into the chip, with a default Trim setting configured via the chip port. Under different temperatures, 10ms slow power-on, 1us fast power-on, 10ms slow power-off, and 1us fast power-off were performed, and the voltage at which the POR signal toggled was measured. When VCC exceeded the POR detection voltage, a rapid jump was observed, and the presence of a POR pulse signal was measured. Multiple tests verified that the circuit effectively implemented the power-on reset function and the rapid VCC jump detection function.

[0072] In some embodiments, combined with Figure 4 As shown, a system reset method based on a power-on reset circuit is provided, including the following steps: S401, in the initial stage of power supply voltage, provides starting current to the reference current circuit through the starting circuit, so that the reference current circuit is removed from the zero current state.

[0073] In some possible implementations, the startup circuit can be a MOSFET operating in the weak inversion region or a large-value resistor, connected between the supply voltage and the core node of the reference current circuit (such as the amplifier input node of a bandgap reference or the gate of a current mirror). During initial power-up, the MOSFET or resistor injects a small startup current into the node, disrupting any degeneracy points (such as zero-current states) that may exist in the circuit. This forces the core transistor of the reference current circuit out of its cutoff region and into its normal operating region, thus initiating the entire reference generation process.

[0074] S402, after the reference current circuit leaves the zero current state, it generates a reference current with temperature compensation characteristics and generates a detection current that changes with the power supply voltage using the current comparison circuit.

[0075] In some possible implementations, the reference current is typically generated based on the bandgap reference principle, by superimposing two voltages with opposite temperature coefficients across a resistor to produce a current independent of absolute temperature (zero temperature coefficient). The sense current is generated by a component directly connected to the supply voltage, for example, by converting the supply voltage into current through a resistor, or by using a MOSFET operating in the deep linear region as a controllable resistor, whose generated current is directly and almost proportional to the supply voltage.

[0076] S403 generates a flip signal at the comparison node by comparing the magnitude of the reference current and the detected current.

[0077] In some possible implementations, the reference current and the sense current are mirrored into a pair of matched transistors and flow into a common comparator node (e.g., the connection point of a common load transistor or resistor). When the mirrored value of the sense current, which rises with the supply voltage, is less than the mirrored value of the stable reference current, the comparator node is pulled to a certain level (e.g., low); when the sense current exceeds the reference current, the potential of the comparator node flips (e.g., goes high), and this potential change serves as the flip signal.

[0078] S404, in response to the toggle signal, generates a system reset signal with a defined pulse width.

[0079] In some possible implementations, the transition edge (e.g., rising edge) of the toggle signal triggers a monostable circuit or a simple RC delay chain. For example, the toggle signal is delayed by an inverter chain or by charging / discharging a capacitor, and then the original transition is combined with the delayed signal by logic gates (e.g., AND gates or OR gates) to generate a system reset signal that starts from the toggle moment and whose duration (pulse width) is determined by the RC time constant or the gate delay.

[0080] The system reset method based on a power-on reset circuit provided in this disclosure ensures the reliable establishment of the reference current by introducing a startup circuit. By comparing the reference current with temperature compensation characteristics with the detection current related to the power supply voltage, the release point of the system reset signal is determined by a stable current ratio, rather than an absolute voltage threshold that is easily affected by temperature and process. This fundamentally overcomes the defect of large reset threshold drift in traditional circuits, thereby providing accurate and consistent power-on reset voltage threshold and stable reset signal pulse width under different temperatures and process angles, greatly improving the reliability of system initialization.

[0081] Combination Figure 5 The present disclosure provides a system reset device 500 based on a power-on reset circuit, including a processor 50 and a memory 51, and may also include a communication interface 52 and a bus 53. The processor 50, communication interface 52, and memory 51 can communicate with each other via the bus 53. The communication interface 52 can be used for information transmission. The processor 50 can call logic instructions in the memory 51 to execute the system reset method based on the power-on reset circuit described in the above embodiment.

[0082] Furthermore, the logic instructions in the aforementioned memory 51 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0083] The memory 51, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 50 executes functional applications and data processing by running the program instructions / modules stored in the memory 51, that is, it implements the system reset method based on the power-on reset circuit in the above method embodiments.

[0084] The memory 51 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 51 may include high-speed random access memory and may also include non-volatile memory.

[0085] Processor 50 is a circuit with signal processing capabilities. In one implementation, processor 50 can be a circuit with instruction read and execute capabilities, such as a central processing unit (CPU), microprocessor, graphics processing unit (GPU) (which can be understood as a type of microprocessor), or digital signal processor (DSP). In another implementation, processor 50 can implement certain functions through the logical relationships of hardware circuits. These logical relationships of hardware circuits are fixed or reconfigurable. For example, processor 50 can be a hardware circuit implemented as an ASIC or a programmable logic device (PLD), such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above modules. Furthermore, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), tensor processing unit (TPU), or deep learning processing unit (DPU). The processor 50 is used to execute related programs to implement the functions required by the units in the system reset device based on the power-on reset circuit in the embodiments of this application, or to execute the system reset method based on the power-on reset circuit in the method embodiments of this application.

[0086] As can be seen, each module in the above device can be one or more processors (or processing circuits) configured to implement the above methods, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor types.

[0087] Furthermore, the modules in the above devices can be integrated in whole or in part, or they can be implemented independently. In one implementation, these modules are integrated together as a system-on-a-chip (SOC). The SOC may include at least one processor for implementing any of the above methods or for implementing the functions of the modules of the device. The at least one processor may be of different types, such as CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0088] In some embodiments, combined with Figure 6As shown, the electronic device 600 includes an electronic device body 610 and a power-on reset circuit 100, wherein: the electronic device body 610 includes a power module 611 and a functional circuit module 612; the power-on reset circuit 100 connects the power module 611 and the functional circuit module 612. The power-on reset circuit 100 can be installed on the electronic device body 610.

[0089] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to execute the aforementioned system reset method based on a power-on reset circuit.

[0090] This disclosure provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions that, when executed by a computer, cause the computer to perform the aforementioned system reset method based on a power-on reset circuit.

[0091] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0092] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0093] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. The scope of the embodiments of this disclosure includes the entire scope of the claims and all available equivalents of the claims. While the terms “first,” “second,” etc., may be used in this application to describe elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be called a second element without changing the meaning of the description, and similarly, a second element may be called a first element, provided that all occurrences of “first element” are consistently renamed and all occurrences of “second element” are consistently renamed. First and second elements are both elements, but may not be the same element. Moreover, the terminology used in this application is only for describing embodiments and is not intended to limit the claims. As used in the description of the embodiments and claims, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. Similarly, the term “and / or” as used herein means including one or more of the associated listed any and all possible combinations. Additionally, when used herein, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase “comprising an…” does not exclude the presence of additional identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0094] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0095] The methods and products disclosed in the embodiments herein (including but not limited to devices and equipment) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0096] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A power-on reset circuit, characterized in that, It includes a startup circuit, a reference current circuit, a current comparison circuit, and a reset signal generation circuit, wherein: The input of the startup circuit is connected to the power supply voltage, and the output is connected to the control node of the reference current circuit. It is configured to provide a startup current to the control node in the early stage of power supply voltage on-time, so as to force the reference current circuit out of the zero current state. The input terminal of the reference current circuit is connected to the power supply voltage. After being configured to leave the zero current state, it generates a reference current with temperature compensation characteristics. The current comparison circuit is connected to the power supply voltage and the reference current circuit. It is configured to generate a detection current and generate a flip signal at the comparison node by comparing the magnitudes of the reference current and the detection current. The input of the reset signal generation circuit is connected to the comparison node of the current comparison circuit and is configured to generate a system reset signal with a defined pulse width in response to a toggle signal.

2. The power-on reset circuit according to claim 1, characterized in that, The reference current circuit includes: Wilson current mirrors, including a PMOS current mirror and an NMOS current mirror connected in series, are configured to generate a reference current; A temperature compensation resistor, connected in series in the current path of the Wilson current mirror, is configured to provide temperature compensation for the reference current.

3. The power-on reset circuit according to claim 2, characterized in that, The reference current circuit also includes: The adjustment switch, connected in parallel with the temperature compensation resistor, is configured to adjust the current flowing through the temperature compensation circuit by changing the on state of the adjustment switch, thereby adjusting the magnitude of the reference current.

4. The power-on reset circuit according to claim 1, characterized in that, The current comparison circuit includes: The test branch is connected to a power supply voltage, and the test branch current changes with the power supply voltage. The load branch is connected to the reference current circuit, and the load branch current is a mirror image of the reference current. The current comparison circuit is configured to generate a flip signal at the comparison node by comparing the magnitude of the current in the detection branch with that in the load branch.

5. The power-on reset circuit according to claim 4, characterized in that, The current comparison circuit also includes: The hysteresis branch, with its input connected to the comparator node and its output connected to the load branch, is configured to adjust the current drive capability of the load branch after the level of the comparator node flips, so that the power supply voltage threshold required for the current in the detection branch to rebalance with the current in the load branch changes.

6. The power-on reset circuit according to claim 5, characterized in that, The hysteresis branch includes a first transistor and a second transistor, wherein: The gate of the first transistor is connected to the comparator node, and its source is grounded. The drain of the second transistor is connected to the current input terminal of the load branch, the gate receives a fixed bias voltage, and the source is connected to the drain of the first transistor. When the level of the comparison node flips, the first transistor turns on and pulls the source potential of the second transistor low to adjust the current driving capability of the load branch.

7. The power-on reset circuit according to claim 4, characterized in that, The current comparison circuit also includes: The coupling capacitor, with its first end connected to the power supply voltage and its second end connected to the critical bias node of the reference current circuit, is configured to couple a fast positive transient change in the power supply voltage to the critical bias node, thereby instantaneously changing the current balance between the detection branch and the load branch and triggering a switching signal.

8. The power-on reset circuit according to any one of claims 1 to 7, characterized in that, The reset signal generation circuit includes: The POR pulse width adjustment circuit, with its input connected to a comparator node, is configured to delay the edge of the flip signal to generate an intermediate signal with a defined width. The Schmitt trigger, with its input connected to the output of the POR pulse width adjustment circuit, is configured to hysteresis-shape the intermediate signal and output a system reset signal with steep edges.

9. A system reset method based on the power-on reset circuit as described in any one of claims 1 to 8, characterized in that, include: In the initial stage of power supply voltage, the starting circuit provides starting current to the reference current circuit, so that the reference current circuit is removed from the zero current state. After the reference current circuit leaves the zero current state, a reference current with temperature compensation characteristics is generated using the reference current circuit, and a detection current that changes with the power supply voltage is generated using the current comparison circuit. A flip signal is generated at the comparison node by comparing the magnitudes of the reference current and the detected current. In response to the flip signal, a system reset signal with a defined pulse width is generated.

10. An electronic device, characterized in that, include: The main body of the electronic device includes a power supply module and a functional circuit module; The power-on reset circuit as described in any one of claims 1 to 8 connects the power supply module and the functional circuit module.

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